2 * Copyright (c) 2002-2007 Neterion, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #ifndef XGE_HAL_DEVICE_H
30 #define XGE_HAL_DEVICE_H
32 #include <dev/nxge/include/xge-os-pal.h>
33 #include <dev/nxge/include/xge-queue.h>
34 #include <dev/nxge/include/xgehal-event.h>
35 #include <dev/nxge/include/xgehal-config.h>
36 #include <dev/nxge/include/xgehal-regs.h>
37 #include <dev/nxge/include/xgehal-channel.h>
38 #include <dev/nxge/include/xgehal-stats.h>
39 #include <dev/nxge/include/xgehal-ring.h>
43 #define XGE_HAL_VPD_LENGTH 80
44 #define XGE_HAL_CARD_XENA_VPD_ADDR 0x50
45 #define XGE_HAL_CARD_HERC_VPD_ADDR 0x80
46 #define XGE_HAL_VPD_READ_COMPLETE 0x80
47 #define XGE_HAL_VPD_BUFFER_SIZE 128
48 #define XGE_HAL_DEVICE_XMSI_WAIT_MAX_MILLIS 500
49 #define XGE_HAL_DEVICE_CMDMEM_WAIT_MAX_MILLIS 500
50 #define XGE_HAL_DEVICE_QUIESCENT_WAIT_MAX_MILLIS 500
51 #define XGE_HAL_DEVICE_FAULT_WAIT_MAX_MILLIS 50
52 #define XGE_HAL_DEVICE_RESET_WAIT_MAX_MILLIS 250
53 #define XGE_HAL_DEVICE_SPDM_READY_WAIT_MAX_MILLIS 250 /* TODO */
55 #define XGE_HAL_MAGIC 0x12345678
56 #define XGE_HAL_DEAD 0xDEADDEAD
57 #define XGE_HAL_DUMP_BUF_SIZE 0x4000
59 #define XGE_HAL_LRO_MAX_BUCKETS 32
62 * enum xge_hal_card_e - Xframe adapter type.
63 * @XGE_HAL_CARD_UNKNOWN: Unknown device.
64 * @XGE_HAL_CARD_XENA: Xframe I device.
65 * @XGE_HAL_CARD_HERC: Xframe II (PCI-266Mhz) device.
66 * @XGE_HAL_CARD_TITAN: Xframe ER (PCI-266Mhz) device.
68 * Enumerates Xframe adapter types. The corresponding PCI device
69 * IDs are listed in the file xgehal-defs.h.
70 * (See XGE_PCI_DEVICE_ID_XENA_1, etc.)
72 * See also: xge_hal_device_check_id().
74 typedef enum xge_hal_card_e {
75 XGE_HAL_CARD_UNKNOWN = 0,
76 XGE_HAL_CARD_XENA = 1,
77 XGE_HAL_CARD_HERC = 2,
78 XGE_HAL_CARD_TITAN = 3,
82 * struct xge_hal_device_attr_t - Device memory spaces.
83 * @regh0: BAR0 mapped memory handle (Solaris), or simply PCI device @pdev
84 * (Linux and the rest.)
85 * @regh1: BAR1 mapped memory handle. Same comment as above.
86 * @bar0: BAR0 virtual address.
87 * @bar1: BAR1 virtual address.
88 * @irqh: IRQ handle (Solaris).
89 * @cfgh: Configuration space handle (Solaris), or PCI device @pdev (Linux).
90 * @pdev: PCI device object.
92 * Device memory spaces. Includes configuration, BAR0, BAR1, etc. per device
93 * mapped memories. Also, includes a pointer to OS-specific PCI device object.
95 typedef struct xge_hal_device_attr_t {
105 } xge_hal_device_attr_t;
108 * enum xge_hal_device_link_state_e - Link state enumeration.
109 * @XGE_HAL_LINK_NONE: Invalid link state.
110 * @XGE_HAL_LINK_DOWN: Link is down.
111 * @XGE_HAL_LINK_UP: Link is up.
114 typedef enum xge_hal_device_link_state_e {
118 } xge_hal_device_link_state_e;
122 * enum xge_hal_pci_mode_e - PIC bus speed and mode specific enumeration.
123 * @XGE_HAL_PCI_33MHZ_MODE: 33 MHZ pci mode.
124 * @XGE_HAL_PCI_66MHZ_MODE: 66 MHZ pci mode.
125 * @XGE_HAL_PCIX_M1_66MHZ_MODE: PCIX M1 66MHZ mode.
126 * @XGE_HAL_PCIX_M1_100MHZ_MODE: PCIX M1 100MHZ mode.
127 * @XGE_HAL_PCIX_M1_133MHZ_MODE: PCIX M1 133MHZ mode.
128 * @XGE_HAL_PCIX_M2_66MHZ_MODE: PCIX M2 66MHZ mode.
129 * @XGE_HAL_PCIX_M2_100MHZ_MODE: PCIX M2 100MHZ mode.
130 * @XGE_HAL_PCIX_M2_133MHZ_MODE: PCIX M3 133MHZ mode.
131 * @XGE_HAL_PCIX_M1_RESERVED: PCIX M1 reserved mode.
132 * @XGE_HAL_PCIX_M1_66MHZ_NS: PCIX M1 66MHZ mode not supported.
133 * @XGE_HAL_PCIX_M1_100MHZ_NS: PCIX M1 100MHZ mode not supported.
134 * @XGE_HAL_PCIX_M1_133MHZ_NS: PCIX M1 133MHZ not supported.
135 * @XGE_HAL_PCIX_M2_RESERVED: PCIX M2 reserved.
136 * @XGE_HAL_PCIX_533_RESERVED: PCIX 533 reserved.
137 * @XGE_HAL_PCI_BASIC_MODE: PCI basic mode, XENA specific value.
138 * @XGE_HAL_PCIX_BASIC_MODE: PCIX basic mode, XENA specific value.
139 * @XGE_HAL_PCI_INVALID_MODE: Invalid PCI or PCIX mode.
142 typedef enum xge_hal_pci_mode_e {
143 XGE_HAL_PCI_33MHZ_MODE = 0x0,
144 XGE_HAL_PCI_66MHZ_MODE = 0x1,
145 XGE_HAL_PCIX_M1_66MHZ_MODE = 0x2,
146 XGE_HAL_PCIX_M1_100MHZ_MODE = 0x3,
147 XGE_HAL_PCIX_M1_133MHZ_MODE = 0x4,
148 XGE_HAL_PCIX_M2_66MHZ_MODE = 0x5,
149 XGE_HAL_PCIX_M2_100MHZ_MODE = 0x6,
150 XGE_HAL_PCIX_M2_133MHZ_MODE = 0x7,
151 XGE_HAL_PCIX_M1_RESERVED = 0x8,
152 XGE_HAL_PCIX_M1_66MHZ_NS = 0xA,
153 XGE_HAL_PCIX_M1_100MHZ_NS = 0xB,
154 XGE_HAL_PCIX_M1_133MHZ_NS = 0xC,
155 XGE_HAL_PCIX_M2_RESERVED = 0xD,
156 XGE_HAL_PCIX_533_RESERVED = 0xE,
157 XGE_HAL_PCI_BASIC_MODE = 0x10,
158 XGE_HAL_PCIX_BASIC_MODE = 0x11,
159 XGE_HAL_PCI_INVALID_MODE = 0x12,
160 } xge_hal_pci_mode_e;
163 * enum xge_hal_pci_bus_frequency_e - PCI bus frequency enumeration.
164 * @XGE_HAL_PCI_BUS_FREQUENCY_33MHZ: PCI bus frequency 33MHZ
165 * @XGE_HAL_PCI_BUS_FREQUENCY_66MHZ: PCI bus frequency 66MHZ
166 * @XGE_HAL_PCI_BUS_FREQUENCY_100MHZ: PCI bus frequency 100MHZ
167 * @XGE_HAL_PCI_BUS_FREQUENCY_133MHZ: PCI bus frequency 133MHZ
168 * @XGE_HAL_PCI_BUS_FREQUENCY_200MHZ: PCI bus frequency 200MHZ
169 * @XGE_HAL_PCI_BUS_FREQUENCY_250MHZ: PCI bus frequency 250MHZ
170 * @XGE_HAL_PCI_BUS_FREQUENCY_266MHZ: PCI bus frequency 266MHZ
171 * @XGE_HAL_PCI_BUS_FREQUENCY_UNKNOWN: Unrecognized PCI bus frequency value.
174 typedef enum xge_hal_pci_bus_frequency_e {
175 XGE_HAL_PCI_BUS_FREQUENCY_33MHZ = 33,
176 XGE_HAL_PCI_BUS_FREQUENCY_66MHZ = 66,
177 XGE_HAL_PCI_BUS_FREQUENCY_100MHZ = 100,
178 XGE_HAL_PCI_BUS_FREQUENCY_133MHZ = 133,
179 XGE_HAL_PCI_BUS_FREQUENCY_200MHZ = 200,
180 XGE_HAL_PCI_BUS_FREQUENCY_250MHZ = 250,
181 XGE_HAL_PCI_BUS_FREQUENCY_266MHZ = 266,
182 XGE_HAL_PCI_BUS_FREQUENCY_UNKNOWN = 0
183 } xge_hal_pci_bus_frequency_e;
186 * enum xge_hal_pci_bus_width_e - PCI bus width enumeration.
187 * @XGE_HAL_PCI_BUS_WIDTH_64BIT: 64 bit bus width.
188 * @XGE_HAL_PCI_BUS_WIDTH_32BIT: 32 bit bus width.
189 * @XGE_HAL_PCI_BUS_WIDTH_UNKNOWN: unknown bus width.
192 typedef enum xge_hal_pci_bus_width_e {
193 XGE_HAL_PCI_BUS_WIDTH_64BIT = 0,
194 XGE_HAL_PCI_BUS_WIDTH_32BIT = 1,
195 XGE_HAL_PCI_BUS_WIDTH_UNKNOWN = 2,
196 } xge_hal_pci_bus_width_e;
198 #if defined (XGE_HAL_CONFIG_LRO)
200 #define IP_TOTAL_LENGTH_OFFSET 2
201 #define IP_FAST_PATH_HDR_MASK 0x45
202 #define TCP_FAST_PATH_HDR_MASK1 0x50
203 #define TCP_FAST_PATH_HDR_MASK2 0x10
204 #define TCP_FAST_PATH_HDR_MASK3 0x18
205 #define IP_SOURCE_ADDRESS_OFFSET 12
206 #define IP_DESTINATION_ADDRESS_OFFSET 16
207 #define TCP_DESTINATION_PORT_OFFSET 2
208 #define TCP_SOURCE_PORT_OFFSET 0
209 #define TCP_DATA_OFFSET_OFFSET 12
210 #define TCP_WINDOW_OFFSET 14
211 #define TCP_SEQUENCE_NUMBER_OFFSET 4
212 #define TCP_ACKNOWLEDGEMENT_NUMBER_OFFSET 8
214 typedef struct tcplro {
226 typedef struct iplro {
237 /*The options start here. */
241 * LRO object, one per each LRO session.
244 /* non-linear: contains scatter-gather list of
245 xframe-mapped received buffers */
246 OS_NETSTACK_BUF os_buf;
247 OS_NETSTACK_BUF os_buf_end;
249 /* link layer header of the first frame;
250 remains intack throughout the processing */
253 /* IP header - gets _collapsed_ */
256 /* transport header - gets _collapsed_ */
259 /* Next tcp sequence number */
260 u32 tcp_next_seq_num;
261 /* Current tcp seq & ack */
265 /* total number of accumulated (so far) frames */
268 /* total data length */
271 /* receive side hash value, available from Hercules */
277 /* Total length of the fragments clubbed with the inital frame */
280 /* LRO frame contains time stamp, if (ts_off != -1) */
287 * xge_hal_spdm_entry_t
289 * Represents a single spdm entry in the SPDM table.
291 typedef struct xge_hal_spdm_entry_t {
292 xge_hal_ipaddr_t src_ip;
293 xge_hal_ipaddr_t dst_ip;
302 } xge_hal_spdm_entry_t;
304 #if defined(XGE_HAL_CONFIG_LRO)
306 lro_t lro_pool[XGE_HAL_LRO_MAX_BUCKETS];
309 } xge_hal_lro_desc_t;
314 * Represents vpd capabilty structure
316 typedef struct xge_hal_vpd_data_t {
317 u8 product_name[XGE_HAL_VPD_LENGTH];
318 u8 serial_num[XGE_HAL_VPD_LENGTH];
319 } xge_hal_vpd_data_t;
324 * HAL device object. Represents Xframe.
338 xge_hal_pci_config_t pci_config_space;
339 xge_hal_pci_config_t pci_config_space_bios;
340 xge_hal_device_config_t config;
341 xge_list_t free_channels;
342 xge_list_t fifo_channels;
343 xge_list_t ring_channels;
344 volatile int is_initialized;
345 volatile int terminating;
346 xge_hal_stats_t stats;
347 macaddr_t macaddr[1];
349 volatile int mcast_refcnt;
351 volatile xge_hal_device_link_state_e link_state;
352 void *upper_layer_info;
353 xge_hal_device_attr_t orig_attr;
357 int hw_is_initialized;
361 int inject_bad_tcode_for_chan_type;
362 int reset_needed_after_close;
364 xge_hal_tti_config_t bimodal_tti[XGE_HAL_MAX_RING_NUM];
365 int bimodal_timer_val_us;
366 int bimodal_urange_a_en;
367 int bimodal_intr_cnt;
369 u16 spdm_max_entries;
370 xge_hal_spdm_entry_t **spdm_table;
371 spinlock_t spdm_lock;
372 #if defined(XGE_HAL_CONFIG_LRO)
373 xge_hal_lro_desc_t lro_desc[XGE_HAL_MAX_RING_NUM];
375 spinlock_t xena_post_lock;
377 /* bimodal workload stats */
378 int irq_workload_rxd[XGE_HAL_MAX_RING_NUM];
379 int irq_workload_rxcnt[XGE_HAL_MAX_RING_NUM];
380 int irq_workload_rxlen[XGE_HAL_MAX_RING_NUM];
381 int irq_workload_txd[XGE_HAL_MAX_FIFO_NUM];
382 int irq_workload_txcnt[XGE_HAL_MAX_FIFO_NUM];
383 int irq_workload_txlen[XGE_HAL_MAX_FIFO_NUM];
385 int mtu_first_time_set;
387 u64 rxufca_lbolt_time;
388 u64 rxufca_intr_thres;
390 xge_hal_pci_mode_e pci_mode;
391 xge_hal_pci_bus_frequency_e bus_frequency;
392 xge_hal_pci_bus_width_e bus_width;
393 xge_hal_vpd_data_t vpd_data;
394 volatile int in_poll;
395 u64 msix_vector_table[XGE_HAL_MAX_MSIX_MESSAGES_WITH_ADDR];
399 /* ========================== PRIVATE API ================================= */
402 __hal_device_event_queued(void *data, int event_type);
405 __hal_device_set_swapper(xge_hal_device_t *hldev);
408 __hal_device_rth_it_configure(xge_hal_device_t *hldev);
411 __hal_device_rth_spdm_configure(xge_hal_device_t *hldev);
414 __hal_verify_pcc_idle(xge_hal_device_t *hldev, u64 adp_status);
417 __hal_device_handle_pic(xge_hal_device_t *hldev, u64 reason);
420 __hal_read_spdm_entry_line(xge_hal_device_t *hldev, u8 spdm_line,
421 u16 spdm_entry, u64 *spdm_line_val);
423 void __hal_pio_mem_write32_upper(pci_dev_h pdev, pci_reg_h regh, u32 val,
426 void __hal_pio_mem_write32_lower(pci_dev_h pdev, pci_reg_h regh, u32 val,
428 void __hal_device_get_vpd_data(xge_hal_device_t *hldev);
431 __hal_device_handle_txpic(xge_hal_device_t *hldev, u64 reason);
434 __hal_device_handle_txdma(xge_hal_device_t *hldev, u64 reason);
437 __hal_device_handle_txmac(xge_hal_device_t *hldev, u64 reason);
440 __hal_device_handle_txxgxs(xge_hal_device_t *hldev, u64 reason);
443 __hal_device_handle_rxpic(xge_hal_device_t *hldev, u64 reason);
446 __hal_device_handle_rxdma(xge_hal_device_t *hldev, u64 reason);
449 __hal_device_handle_rxmac(xge_hal_device_t *hldev, u64 reason);
452 __hal_device_handle_rxxgxs(xge_hal_device_t *hldev, u64 reason);
455 __hal_device_handle_mc(xge_hal_device_t *hldev, u64 reason);
458 __hal_device_register_poll(xge_hal_device_t *hldev, u64 *reg, int op, u64 mask,
461 __hal_device_rts_mac_configure(xge_hal_device_t *hldev);
464 __hal_device_rts_qos_configure(xge_hal_device_t *hldev);
467 __hal_device_rts_port_configure(xge_hal_device_t *hldev);
470 __hal_device_rti_configure(xge_hal_device_t *hldev, int runtime);
473 __hal_device_msi_intr_endis(xge_hal_device_t *hldev, int flag);
476 __hal_device_msix_intr_endis(xge_hal_device_t *hldev,
477 xge_hal_channel_t *channel, int flag);
479 /* =========================== PUBLIC API ================================= */
482 __hal_fix_time_ival_herc(xge_hal_device_t *hldev,
483 unsigned int time_ival);
485 xge_hal_rts_rth_itable_set(xge_hal_device_t *hldev, u8 *itable,
489 xge_hal_rts_rth_set(xge_hal_device_t *hldev, u8 def_q, u64 hash_type,
493 xge_hal_rts_rth_init(xge_hal_device_t *hldev);
496 xge_hal_rts_rth_clr(xge_hal_device_t *hldev);
499 xge_hal_rts_rth_start(xge_hal_device_t *hldev);
502 xge_hal_rts_rth_stop(xge_hal_device_t *hldev);
505 xge_hal_device_rts_rth_key_set(xge_hal_device_t *hldev, u8 KeySize, u8 *Key);
508 xge_hal_device_rts_mac_enable(xge_hal_device_h devh, int index, macaddr_t macaddr);
511 xge_hal_device_rts_mac_disable(xge_hal_device_h devh, int index);
513 int xge_hal_reinitialize_hw(xge_hal_device_t * hldev);
515 xge_hal_status_e xge_hal_fix_rldram_ecc_error(xge_hal_device_t * hldev);
517 * xge_hal_device_rti_reconfigure
520 static inline xge_hal_status_e
521 xge_hal_device_rti_reconfigure(xge_hal_device_t *hldev)
523 return __hal_device_rti_configure(hldev, 1);
527 * xge_hal_device_rts_port_reconfigure
530 static inline xge_hal_status_e
531 xge_hal_device_rts_port_reconfigure(xge_hal_device_t *hldev)
533 return __hal_device_rts_port_configure(hldev);
537 * xge_hal_device_is_initialized - Returns 0 if device is not
538 * initialized, non-zero otherwise.
539 * @devh: HAL device handle.
541 * Returns 0 if device is not initialized, non-zero otherwise.
544 xge_hal_device_is_initialized(xge_hal_device_h devh)
546 return ((xge_hal_device_t*)devh)->is_initialized;
551 * xge_hal_device_in_poll - non-zero, if xge_hal_device_poll() is executing.
552 * @devh: HAL device handle.
554 * Returns non-zero if xge_hal_device_poll() is executing, and 0 - otherwise.
557 xge_hal_device_in_poll(xge_hal_device_h devh)
559 return ((xge_hal_device_t*)devh)->in_poll;
564 * xge_hal_device_inject_ecc - Inject ECC error.
565 * @devh: HAL device, pointer to xge_hal_device_t structure.
566 * @err_reg: Contains the error register.
568 * This function is used to inject ECC error into the driver flow.
569 * This facility can be used to test the driver flow in the
570 * case of ECC error is reported by the firmware.
573 * See also: xge_hal_device_inject_serr(),
574 * xge_hal_device_inject_bad_tcode()
577 xge_hal_device_inject_ecc(xge_hal_device_h devh, u64 err_reg)
579 ((xge_hal_device_t*)devh)->inject_ecc = err_reg;
584 * xge_hal_device_inject_serr - Inject SERR error.
585 * @devh: HAL device, pointer to xge_hal_device_t structure.
586 * @err_reg: Contains the error register.
588 * This function is used to inject SERR error into the driver flow.
589 * This facility can be used to test the driver flow in the
590 * case of SERR error is reported by firmware.
593 * See also: xge_hal_device_inject_ecc(),
594 * xge_hal_device_inject_bad_tcode()
597 xge_hal_device_inject_serr(xge_hal_device_h devh, u64 err_reg)
599 ((xge_hal_device_t*)devh)->inject_serr = err_reg;
604 * xge_hal_device_inject_bad_tcode - Inject Bad transfer code.
605 * @devh: HAL device, pointer to xge_hal_device_t structure.
606 * @chan_type: Channel type (fifo/ring).
607 * @t_code: Transfer code.
609 * This function is used to inject bad (Tx/Rx Data)transfer code
610 * into the driver flow.
612 * This facility can be used to test the driver flow in the
613 * case of bad transfer code reported by firmware for a Tx/Rx data
617 * See also: xge_hal_device_inject_ecc(), xge_hal_device_inject_serr()
620 xge_hal_device_inject_bad_tcode(xge_hal_device_h devh, int chan_type, u8 t_code)
622 ((xge_hal_device_t*)devh)->inject_bad_tcode_for_chan_type = chan_type;
623 ((xge_hal_device_t*)devh)->inject_bad_tcode = t_code;
626 void xge_hal_device_msi_enable(xge_hal_device_h devh);
629 * xge_hal_device_msi_mode - Is MSI enabled?
630 * @devh: HAL device handle.
632 * Returns 0 if MSI is enabled for the specified device,
633 * non-zero otherwise.
636 xge_hal_device_msi_mode(xge_hal_device_h devh)
638 return ((xge_hal_device_t*)devh)->msi_enabled;
642 * xge_hal_device_queue - Get per-device event queue.
643 * @devh: HAL device handle.
645 * Returns: event queue associated with the specified HAL device.
647 static inline xge_queue_h
648 xge_hal_device_queue (xge_hal_device_h devh)
650 return ((xge_hal_device_t*)devh)->queueh;
654 * xge_hal_device_attr - Get original (user-specified) device
656 * @devh: HAL device handle.
658 * Returns: original (user-specified) device attributes.
660 static inline xge_hal_device_attr_t*
661 xge_hal_device_attr(xge_hal_device_h devh)
663 return &((xge_hal_device_t*)devh)->orig_attr;
667 * xge_hal_device_private_set - Set ULD context.
668 * @devh: HAL device handle.
669 * @data: pointer to ULD context
671 * Use HAL device to set upper-layer driver (ULD) context.
673 * See also: xge_hal_device_from_private(), xge_hal_device_private()
676 xge_hal_device_private_set(xge_hal_device_h devh, void *data)
678 ((xge_hal_device_t*)devh)->upper_layer_info = data;
682 * xge_hal_device_private - Get ULD context.
683 * @devh: HAL device handle.
685 * Use HAL device to get upper-layer driver (ULD) context.
687 * Returns: ULD context.
689 * See also: xge_hal_device_from_private(), xge_hal_device_private_set()
692 xge_hal_device_private(xge_hal_device_h devh)
694 return ((xge_hal_device_t*)devh)->upper_layer_info;
698 * xge_hal_device_from_private - Get HAL device object from private.
699 * @info_ptr: ULD context.
701 * Use ULD context to get HAL device.
703 * Returns: Device handle.
705 * See also: xge_hal_device_private(), xge_hal_device_private_set()
707 static inline xge_hal_device_h
708 xge_hal_device_from_private(void *info_ptr)
710 return xge_container_of((void ** ) info_ptr, xge_hal_device_t,
715 * xge_hal_device_mtu_check - check MTU value for ranges
717 * @new_mtu: new MTU value to check
719 * Will do sanity check for new MTU value.
721 * Returns: XGE_HAL_OK - success.
722 * XGE_HAL_ERR_INVALID_MTU_SIZE - MTU is invalid.
724 * See also: xge_hal_device_mtu_set()
726 static inline xge_hal_status_e
727 xge_hal_device_mtu_check(xge_hal_device_t *hldev, int new_mtu)
729 if ((new_mtu < XGE_HAL_MIN_MTU) || (new_mtu > XGE_HAL_MAX_MTU)) {
730 return XGE_HAL_ERR_INVALID_MTU_SIZE;
736 void xge_hal_device_bcast_enable(xge_hal_device_h devh);
738 void xge_hal_device_bcast_disable(xge_hal_device_h devh);
740 void xge_hal_device_terminating(xge_hal_device_h devh);
742 xge_hal_status_e xge_hal_device_initialize(xge_hal_device_t *hldev,
743 xge_hal_device_attr_t *attr, xge_hal_device_config_t *config);
745 void xge_hal_device_terminate(xge_hal_device_t *hldev);
747 xge_hal_status_e xge_hal_device_reset(xge_hal_device_t *hldev);
749 xge_hal_status_e xge_hal_device_macaddr_get(xge_hal_device_t *hldev,
750 int index, macaddr_t *macaddr);
752 xge_hal_status_e xge_hal_device_macaddr_set(xge_hal_device_t *hldev,
753 int index, macaddr_t macaddr);
755 xge_hal_status_e xge_hal_device_macaddr_clear(xge_hal_device_t *hldev,
758 int xge_hal_device_macaddr_find(xge_hal_device_t *hldev, macaddr_t wanted);
760 xge_hal_status_e xge_hal_device_mtu_set(xge_hal_device_t *hldev, int new_mtu);
762 xge_hal_status_e xge_hal_device_status(xge_hal_device_t *hldev, u64 *hw_status);
764 void xge_hal_device_intr_enable(xge_hal_device_t *hldev);
766 void xge_hal_device_intr_disable(xge_hal_device_t *hldev);
768 xge_hal_status_e xge_hal_device_mcast_enable(xge_hal_device_t *hldev);
770 xge_hal_status_e xge_hal_device_mcast_disable(xge_hal_device_t *hldev);
772 void xge_hal_device_promisc_enable(xge_hal_device_t *hldev);
774 void xge_hal_device_promisc_disable(xge_hal_device_t *hldev);
776 xge_hal_status_e xge_hal_device_disable(xge_hal_device_t *hldev);
778 xge_hal_status_e xge_hal_device_enable(xge_hal_device_t *hldev);
780 xge_hal_status_e xge_hal_device_handle_tcode(xge_hal_channel_h channelh,
784 xge_hal_status_e xge_hal_device_link_state(xge_hal_device_h devh,
785 xge_hal_device_link_state_e *ls);
787 void xge_hal_device_sched_timer(xge_hal_device_h devh, int interval_us,
790 void xge_hal_device_poll(xge_hal_device_h devh);
792 xge_hal_card_e xge_hal_device_check_id(xge_hal_device_h devh);
794 int xge_hal_device_is_slot_freeze(xge_hal_device_h devh);
797 xge_hal_device_pci_info_get(xge_hal_device_h devh, xge_hal_pci_mode_e *pci_mode,
798 xge_hal_pci_bus_frequency_e *bus_frequency,
799 xge_hal_pci_bus_width_e *bus_width);
802 xge_hal_spdm_entry_add(xge_hal_device_h devh, xge_hal_ipaddr_t *src_ip,
803 xge_hal_ipaddr_t *dst_ip, u16 l4_sp, u16 l4_dp,
804 u8 is_tcp, u8 is_ipv4, u8 tgt_queue);
807 xge_hal_spdm_entry_remove(xge_hal_device_h devh, xge_hal_ipaddr_t *src_ip,
808 xge_hal_ipaddr_t *dst_ip, u16 l4_sp, u16 l4_dp,
809 u8 is_tcp, u8 is_ipv4);
812 xge_hal_device_rts_section_enable(xge_hal_device_h devh, int index);
815 xge_hal_device_is_closed (xge_hal_device_h devh);
817 /* private functions, don't use them in ULD */
819 void __hal_serial_mem_write64(xge_hal_device_t *hldev, u64 value, u64 *reg);
821 u64 __hal_serial_mem_read64(xge_hal_device_t *hldev, u64 *reg);
824 /* Some function protoypes for MSI implementation. */
826 xge_hal_channel_msi_set (xge_hal_channel_h channelh, int msi,
829 xge_hal_mask_msi(xge_hal_device_t *hldev);
832 xge_hal_unmask_msi(xge_hal_channel_h channelh);
835 xge_hal_channel_msix_set(xge_hal_channel_h channelh, int msix_idx);
838 xge_hal_mask_msix(xge_hal_device_h devh, int msi_id);
841 xge_hal_unmask_msix(xge_hal_device_h devh, int msi_id);
843 #if defined(XGE_HAL_CONFIG_LRO)
845 xge_hal_lro_init(u32 lro_scale, xge_hal_device_t *hldev);
848 xge_hal_lro_terminate(u32 lro_scale, xge_hal_device_t *hldev);
851 #if defined(XGE_DEBUG_FP) && (XGE_DEBUG_FP & XGE_DEBUG_FP_DEVICE)
852 #define __HAL_STATIC_DEVICE
853 #define __HAL_INLINE_DEVICE
855 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE int
856 xge_hal_device_rev(xge_hal_device_t *hldev);
858 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
859 xge_hal_device_begin_irq(xge_hal_device_t *hldev, u64 *reason);
861 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
862 xge_hal_device_clear_rx(xge_hal_device_t *hldev);
864 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
865 xge_hal_device_clear_tx(xge_hal_device_t *hldev);
867 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
868 xge_hal_device_continue_irq(xge_hal_device_t *hldev);
870 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
871 xge_hal_device_handle_irq(xge_hal_device_t *hldev);
873 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE char *
874 xge_hal_device_bar0(xge_hal_device_t *hldev);
876 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE char *
877 xge_hal_device_isrbar0(xge_hal_device_t *hldev);
879 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE char *
880 xge_hal_device_bar1(xge_hal_device_t *hldev);
882 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
883 xge_hal_device_bar0_set(xge_hal_device_t *hldev, char *bar0);
885 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
886 xge_hal_device_isrbar0_set(xge_hal_device_t *hldev, char *isrbar0);
888 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
889 xge_hal_device_bar1_set(xge_hal_device_t *hldev, xge_hal_channel_h channelh,
892 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
893 xge_hal_device_mask_tx(xge_hal_device_t *hldev);
895 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
896 xge_hal_device_mask_rx(xge_hal_device_t *hldev);
898 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
899 xge_hal_device_mask_all(xge_hal_device_t *hldev);
901 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
902 xge_hal_device_unmask_tx(xge_hal_device_t *hldev);
904 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
905 xge_hal_device_unmask_rx(xge_hal_device_t *hldev);
907 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE void
908 xge_hal_device_unmask_all(xge_hal_device_t *hldev);
910 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
911 xge_hal_device_poll_tx_channels(xge_hal_device_t *hldev, int *got_tx);
913 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
914 xge_hal_device_poll_rx_channels(xge_hal_device_t *hldev, int *got_rx);
916 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
917 xge_hal_device_poll_rx_channel(xge_hal_channel_t *channel, int *got_rx);
919 __HAL_STATIC_DEVICE __HAL_INLINE_DEVICE xge_hal_status_e
920 xge_hal_device_poll_tx_channel(xge_hal_channel_t *channel, int *got_tx);
922 #if defined (XGE_HAL_CONFIG_LRO)
923 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u8
924 __hal_header_parse_token_u8(u8 *string,u16 offset);
926 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u16
927 __hal_header_parse_token_u16(u8 *string,u16 offset);
929 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u32
930 __hal_header_parse_token_u32(u8 *string,u16 offset);
932 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
933 __hal_header_update_u8(u8 *string, u16 offset, u8 val);
935 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
936 __hal_header_update_u16(u8 *string, u16 offset, u16 val);
938 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
939 __hal_header_update_u32(u8 *string, u16 offset, u32 val);
941 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL u16
942 __hal_tcp_seg_len(iplro_t *ip, tcplro_t *tcp);
944 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
945 __hal_ip_lro_capable(iplro_t *ip, xge_hal_dtr_info_t *ext_info);
947 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
948 __hal_tcp_lro_capable(iplro_t *ip, tcplro_t *tcp, lro_t *lro, int *ts_off);
950 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
951 __hal_lro_capable(u8 *buffer, iplro_t **ip, tcplro_t **tcp,
952 xge_hal_dtr_info_t *ext_info);
954 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
955 __hal_get_lro_session(u8 *eth_hdr, iplro_t *ip, tcplro_t *tcp, lro_t **lro,
956 xge_hal_dtr_info_t *ext_info, xge_hal_device_t *hldev,
957 xge_hal_lro_desc_t *ring_lro, lro_t **lro_end3);
959 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
960 __hal_lro_under_optimal_thresh(iplro_t *ip, tcplro_t *tcp, lro_t *lro,
961 xge_hal_device_t *hldev);
963 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
964 __hal_collapse_ip_hdr(iplro_t *ip, tcplro_t *tcp, lro_t *lro,
965 xge_hal_device_t *hldev);
967 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
968 __hal_collapse_tcp_hdr(iplro_t *ip, tcplro_t *tcp, lro_t *lro,
969 xge_hal_device_t *hldev);
971 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
972 __hal_append_lro(iplro_t *ip, tcplro_t **tcp, u32 *seg_len, lro_t *lro,
973 xge_hal_device_t *hldev);
975 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
976 xge_hal_lro_process_rx(int ring, u8 *eth_hdr, u8 *ip_hdr, tcplro_t **tcp,
977 u32 *seglen, lro_t **p_lro,
978 xge_hal_dtr_info_t *ext_info, xge_hal_device_t *hldev,
981 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL xge_hal_status_e
982 xge_hal_accumulate_large_rx(u8 *buffer, tcplro_t **tcp, u32 *seglen,
983 lro_t **lro, xge_hal_dtr_info_t *ext_info,
984 xge_hal_device_t *hldev, lro_t **lro_end3);
986 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL lro_t *
987 xge_hal_lro_next_session (xge_hal_device_t *hldev, int ring);
989 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL lro_t *
990 xge_hal_lro_get_next_session(xge_hal_device_t *hldev);
992 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL void
993 __hal_open_lro_session (u8 *buffer, iplro_t *ip, tcplro_t *tcp, lro_t **lro,
994 xge_hal_device_t *hldev, xge_hal_lro_desc_t *ring_lro,
995 int slot, u32 tcp_seg_len, int ts_off);
997 __HAL_STATIC_CHANNEL __HAL_INLINE_CHANNEL int
998 __hal_lro_get_free_slot (xge_hal_lro_desc_t *ring_lro);
1001 #else /* XGE_FASTPATH_EXTERN */
1002 #define __HAL_STATIC_DEVICE static
1003 #define __HAL_INLINE_DEVICE inline
1004 #include <dev/nxge/xgehal/xgehal-device-fp.c>
1005 #endif /* XGE_FASTPATH_INLINE */
1010 #endif /* XGE_HAL_DEVICE_H */