2 * Copyright (C) 2012 Emulex
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of the Emulex Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
31 * Contact Information:
32 * freebsd-drivers@emulex.com
36 * Costa Mesa, CA 92626
45 extern uint32_t sfp_vpd_dump_buffer[TRANSCEIVER_DATA_NUM_ELE];
48 * @brief Reset (firmware) common function
49 * @param sc software handle to the device
50 * @returns 0 on success, ETIMEDOUT on failure
53 oce_reset_fun(POCE_SOFTC sc)
57 struct ioctl_common_function_reset *fwcmd;
60 if (sc->flags & OCE_FLAGS_FUNCRESET_RQD) {
61 mb = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx);
63 bzero(mbx, sizeof(struct oce_mbx));
65 fwcmd = (struct ioctl_common_function_reset *)&mbx->payload;
66 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
68 OPCODE_COMMON_FUNCTION_RESET,
69 10, /* MBX_TIMEOUT_SEC */
71 ioctl_common_function_reset),
74 mbx->u0.s.embedded = 1;
76 sizeof(struct ioctl_common_function_reset);
78 rc = oce_mbox_dispatch(sc, 2);
86 * @brief This funtions tells firmware we are
88 * @param sc software handle to the device
89 * @returns 0 on success, ETIMEDOUT on failure
92 oce_fw_clean(POCE_SOFTC sc)
98 mbx = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx);
99 ptr = (uint8_t *) &mbx->mbx;
101 /* Endian Signature */
111 ret = oce_mbox_dispatch(sc, 2);
118 * @brief Mailbox wait
119 * @param sc software handle to the device
120 * @param tmo_sec timeout in seconds
123 oce_mbox_wait(POCE_SOFTC sc, uint32_t tmo_sec)
126 pd_mpu_mbox_db_t mbox_db;
134 mbox_db.dw0 = OCE_READ_REG32(sc, db, PD_MPU_MBOX_DB);
136 if (mbox_db.bits.ready)
142 device_printf(sc->dev, "Mailbox timed out\n");
149 * @brief Mailbox dispatch
150 * @param sc software handle to the device
151 * @param tmo_sec timeout in seconds
154 oce_mbox_dispatch(POCE_SOFTC sc, uint32_t tmo_sec)
156 pd_mpu_mbox_db_t mbox_db;
160 oce_dma_sync(&sc->bsmbx, BUS_DMASYNC_PREWRITE);
161 pa = (uint32_t) ((uint64_t) sc->bsmbx.paddr >> 34);
162 bzero(&mbox_db, sizeof(pd_mpu_mbox_db_t));
163 mbox_db.bits.ready = 0;
165 mbox_db.bits.address = pa;
167 rc = oce_mbox_wait(sc, tmo_sec);
169 OCE_WRITE_REG32(sc, db, PD_MPU_MBOX_DB, mbox_db.dw0);
171 pa = (uint32_t) ((uint64_t) sc->bsmbx.paddr >> 4) & 0x3fffffff;
172 mbox_db.bits.ready = 0;
174 mbox_db.bits.address = pa;
176 rc = oce_mbox_wait(sc, tmo_sec);
179 OCE_WRITE_REG32(sc, db, PD_MPU_MBOX_DB, mbox_db.dw0);
181 rc = oce_mbox_wait(sc, tmo_sec);
183 oce_dma_sync(&sc->bsmbx, BUS_DMASYNC_POSTWRITE);
193 * @brief Mailbox common request header initialization
194 * @param hdr mailbox header
197 * @param subsys subsystem
198 * @param opcode opcode
199 * @param timeout timeout
200 * @param pyld_len payload length
203 mbx_common_req_hdr_init(struct mbx_hdr *hdr,
204 uint8_t dom, uint8_t port,
205 uint8_t subsys, uint8_t opcode,
206 uint32_t timeout, uint32_t pyld_len,
209 hdr->u0.req.opcode = opcode;
210 hdr->u0.req.subsystem = subsys;
211 hdr->u0.req.port_number = port;
212 hdr->u0.req.domain = dom;
214 hdr->u0.req.timeout = timeout;
215 hdr->u0.req.request_length = pyld_len - sizeof(struct mbx_hdr);
216 hdr->u0.req.version = version;
222 * @brief Function to initialize the hw with host endian information
223 * @param sc software handle to the device
224 * @returns 0 on success, ETIMEDOUT on failure
227 oce_mbox_init(POCE_SOFTC sc)
229 struct oce_bmbx *mbx;
233 if (sc->flags & OCE_FLAGS_MBOX_ENDIAN_RQD) {
234 mbx = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx);
235 ptr = (uint8_t *) &mbx->mbx;
237 /* Endian Signature */
247 ret = oce_mbox_dispatch(sc, 0);
255 * @brief Function to get the firmware version
256 * @param sc software handle to the device
257 * @returns 0 on success, EIO on failure
260 oce_get_fw_version(POCE_SOFTC sc)
263 struct mbx_get_common_fw_version *fwcmd;
266 bzero(&mbx, sizeof(struct oce_mbx));
268 fwcmd = (struct mbx_get_common_fw_version *)&mbx.payload;
269 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
270 MBX_SUBSYSTEM_COMMON,
271 OPCODE_COMMON_GET_FW_VERSION,
273 sizeof(struct mbx_get_common_fw_version),
276 mbx.u0.s.embedded = 1;
277 mbx.payload_length = sizeof(struct mbx_get_common_fw_version);
278 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
280 ret = oce_mbox_post(sc, &mbx, NULL);
282 ret = fwcmd->hdr.u0.rsp.status;
284 device_printf(sc->dev,"%s failed - cmd status: %d\n",
289 bcopy(fwcmd->params.rsp.fw_ver_str, sc->fw_version, 32);
296 * @brief Firmware will send gracious notifications during
297 * attach only after sending first mcc commnad. We
298 * use MCC queue only for getting async and mailbox
299 * for sending cmds. So to get gracious notifications
300 * atleast send one dummy command on mcc.
303 oce_first_mcc_cmd(POCE_SOFTC sc)
306 struct oce_mq *mq = sc->mq;
307 struct mbx_get_common_fw_version *fwcmd;
310 mbx = RING_GET_PRODUCER_ITEM_VA(mq->ring, struct oce_mbx);
311 bzero(mbx, sizeof(struct oce_mbx));
313 fwcmd = (struct mbx_get_common_fw_version *)&mbx->payload;
314 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
315 MBX_SUBSYSTEM_COMMON,
316 OPCODE_COMMON_GET_FW_VERSION,
318 sizeof(struct mbx_get_common_fw_version),
320 mbx->u0.s.embedded = 1;
321 mbx->payload_length = sizeof(struct mbx_get_common_fw_version);
322 bus_dmamap_sync(mq->ring->dma.tag, mq->ring->dma.map,
323 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
324 RING_PUT(mq->ring, 1);
325 reg_value = (1 << 16) | mq->mq_id;
326 OCE_WRITE_REG32(sc, db, PD_MQ_DB, reg_value);
332 * @brief Function to post a MBX to the mbox
333 * @param sc software handle to the device
334 * @param mbx pointer to the MBX to send
335 * @param mbxctx pointer to the mbx context structure
336 * @returns 0 on success, error on failure
339 oce_mbox_post(POCE_SOFTC sc, struct oce_mbx *mbx, struct oce_mbx_ctx *mbxctx)
341 struct oce_mbx *mb_mbx = NULL;
342 struct oce_mq_cqe *mb_cqe = NULL;
343 struct oce_bmbx *mb = NULL;
346 uint32_t cstatus = 0;
347 uint32_t xstatus = 0;
349 LOCK(&sc->bmbx_lock);
351 mb = OCE_DMAPTR(&sc->bsmbx, struct oce_bmbx);
358 /* copy mbx into mbox */
359 bcopy(mbx, mb_mbx, sizeof(struct oce_mbx));
362 rc = oce_mbox_dispatch(sc, tmo);
365 * the command completed successfully. Now get the
366 * completion queue entry
369 DW_SWAP(u32ptr(&mb_cqe->u0.dw[0]), sizeof(struct oce_mq_cqe));
371 /* copy mbox mbx back */
372 bcopy(mb_mbx, mbx, sizeof(struct oce_mbx));
374 /* pick up the mailbox status */
375 cstatus = mb_cqe->u0.s.completion_status;
376 xstatus = mb_cqe->u0.s.extended_status;
379 * store the mbx context in the cqe tag section so that
380 * the upper layer handling the cqe can associate the mbx
383 if (cstatus == 0 && mbxctx) {
385 mbxctx->mbx = mb_mbx;
386 bcopy(&mbxctx, mb_cqe->u0.s.mq_tag,
387 sizeof(struct oce_mbx_ctx *));
391 UNLOCK(&sc->bmbx_lock);
397 * @brief Function to read the mac address associated with an interface
398 * @param sc software handle to the device
399 * @param if_id interface id to read the address from
400 * @param perm set to 1 if reading the factory mac address.
401 * In this case if_id is ignored
402 * @param type type of the mac address, whether network or storage
403 * @param[out] mac [OUTPUT] pointer to a buffer containing the
404 * mac address when the command succeeds.
405 * @returns 0 on success, EIO on failure
408 oce_read_mac_addr(POCE_SOFTC sc, uint32_t if_id,
409 uint8_t perm, uint8_t type, struct mac_address_format *mac)
412 struct mbx_query_common_iface_mac *fwcmd;
415 bzero(&mbx, sizeof(struct oce_mbx));
417 fwcmd = (struct mbx_query_common_iface_mac *)&mbx.payload;
418 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
419 MBX_SUBSYSTEM_COMMON,
420 OPCODE_COMMON_QUERY_IFACE_MAC,
422 sizeof(struct mbx_query_common_iface_mac),
425 fwcmd->params.req.permanent = perm;
427 fwcmd->params.req.if_id = (uint16_t) if_id;
429 fwcmd->params.req.if_id = 0;
431 fwcmd->params.req.type = type;
433 mbx.u0.s.embedded = 1;
434 mbx.payload_length = sizeof(struct mbx_query_common_iface_mac);
435 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
437 ret = oce_mbox_post(sc, &mbx, NULL);
439 ret = fwcmd->hdr.u0.rsp.status;
441 device_printf(sc->dev,"%s failed - cmd status: %d\n",
446 /* copy the mac addres in the output parameter */
447 mac->size_of_struct = fwcmd->params.rsp.mac.size_of_struct;
448 bcopy(&fwcmd->params.rsp.mac.mac_addr[0], &mac->mac_addr[0],
449 mac->size_of_struct);
455 * @brief Function to query the fw attributes from the hw
456 * @param sc software handle to the device
457 * @returns 0 on success, EIO on failure
460 oce_get_fw_config(POCE_SOFTC sc)
463 struct mbx_common_query_fw_config *fwcmd;
466 bzero(&mbx, sizeof(struct oce_mbx));
468 fwcmd = (struct mbx_common_query_fw_config *)&mbx.payload;
469 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
470 MBX_SUBSYSTEM_COMMON,
471 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG,
473 sizeof(struct mbx_common_query_fw_config),
476 mbx.u0.s.embedded = 1;
477 mbx.payload_length = sizeof(struct mbx_common_query_fw_config);
478 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
480 ret = oce_mbox_post(sc, &mbx, NULL);
482 ret = fwcmd->hdr.u0.rsp.status;
484 device_printf(sc->dev,"%s failed - cmd status: %d\n",
489 DW_SWAP(u32ptr(fwcmd), sizeof(struct mbx_common_query_fw_config));
491 sc->config_number = fwcmd->params.rsp.config_number;
492 sc->asic_revision = fwcmd->params.rsp.asic_revision;
493 sc->port_id = fwcmd->params.rsp.port_id;
494 sc->function_mode = fwcmd->params.rsp.function_mode;
495 sc->function_caps = fwcmd->params.rsp.function_caps;
497 if (fwcmd->params.rsp.ulp[0].ulp_mode & ULP_NIC_MODE) {
498 sc->max_tx_rings = fwcmd->params.rsp.ulp[0].nic_wq_tot;
499 sc->max_rx_rings = fwcmd->params.rsp.ulp[0].lro_rqid_tot;
501 sc->max_tx_rings = fwcmd->params.rsp.ulp[1].nic_wq_tot;
502 sc->max_rx_rings = fwcmd->params.rsp.ulp[1].lro_rqid_tot;
512 * @brief function to create a device interface
513 * @param sc software handle to the device
514 * @param cap_flags capability flags
515 * @param en_flags enable capability flags
516 * @param vlan_tag optional vlan tag to associate with the if
517 * @param mac_addr pointer to a buffer containing the mac address
518 * @param[out] if_id [OUTPUT] pointer to an integer to hold the ID of the
520 * @returns 0 on success, EIO on failure
523 oce_if_create(POCE_SOFTC sc,
531 struct mbx_create_common_iface *fwcmd;
534 bzero(&mbx, sizeof(struct oce_mbx));
536 fwcmd = (struct mbx_create_common_iface *)&mbx.payload;
537 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
538 MBX_SUBSYSTEM_COMMON,
539 OPCODE_COMMON_CREATE_IFACE,
541 sizeof(struct mbx_create_common_iface),
543 DW_SWAP(u32ptr(&fwcmd->hdr), sizeof(struct mbx_hdr));
545 fwcmd->params.req.version = 0;
546 fwcmd->params.req.cap_flags = LE_32(cap_flags);
547 fwcmd->params.req.enable_flags = LE_32(en_flags);
548 if (mac_addr != NULL) {
549 bcopy(mac_addr, &fwcmd->params.req.mac_addr[0], 6);
550 fwcmd->params.req.vlan_tag.u0.normal.vtag = LE_16(vlan_tag);
551 fwcmd->params.req.mac_invalid = 0;
553 fwcmd->params.req.mac_invalid = 1;
556 mbx.u0.s.embedded = 1;
557 mbx.payload_length = sizeof(struct mbx_create_common_iface);
558 DW_SWAP(u32ptr(&mbx), OCE_BMBX_RHDR_SZ);
560 rc = oce_mbox_post(sc, &mbx, NULL);
562 rc = fwcmd->hdr.u0.rsp.status;
564 device_printf(sc->dev,"%s failed - cmd status: %d\n",
569 *if_id = LE_32(fwcmd->params.rsp.if_id);
571 if (mac_addr != NULL)
572 sc->pmac_id = LE_32(fwcmd->params.rsp.pmac_id);
578 * @brief Function to delete an interface
579 * @param sc software handle to the device
580 * @param if_id ID of the interface to delete
581 * @returns 0 on success, EIO on failure
584 oce_if_del(POCE_SOFTC sc, uint32_t if_id)
587 struct mbx_destroy_common_iface *fwcmd;
590 bzero(&mbx, sizeof(struct oce_mbx));
592 fwcmd = (struct mbx_destroy_common_iface *)&mbx.payload;
593 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
594 MBX_SUBSYSTEM_COMMON,
595 OPCODE_COMMON_DESTROY_IFACE,
597 sizeof(struct mbx_destroy_common_iface),
600 fwcmd->params.req.if_id = if_id;
602 mbx.u0.s.embedded = 1;
603 mbx.payload_length = sizeof(struct mbx_destroy_common_iface);
604 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
606 rc = oce_mbox_post(sc, &mbx, NULL);
608 rc = fwcmd->hdr.u0.rsp.status;
610 device_printf(sc->dev,"%s failed - cmd status: %d\n",
616 * @brief Function to send the mbx command to configure vlan
617 * @param sc software handle to the device
618 * @param if_id interface identifier index
619 * @param vtag_arr array of vlan tags
620 * @param vtag_cnt number of elements in array
621 * @param untagged boolean TRUE/FLASE
622 * @param enable_promisc flag to enable/disable VLAN promiscuous mode
623 * @returns 0 on success, EIO on failure
626 oce_config_vlan(POCE_SOFTC sc,
628 struct normal_vlan *vtag_arr,
629 uint8_t vtag_cnt, uint32_t untagged, uint32_t enable_promisc)
632 struct mbx_common_config_vlan *fwcmd;
635 bzero(&mbx, sizeof(struct oce_mbx));
636 fwcmd = (struct mbx_common_config_vlan *)&mbx.payload;
638 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
639 MBX_SUBSYSTEM_COMMON,
640 OPCODE_COMMON_CONFIG_IFACE_VLAN,
642 sizeof(struct mbx_common_config_vlan),
645 fwcmd->params.req.if_id = (uint8_t) if_id;
646 fwcmd->params.req.promisc = (uint8_t) enable_promisc;
647 fwcmd->params.req.untagged = (uint8_t) untagged;
648 fwcmd->params.req.num_vlans = vtag_cnt;
650 if (!enable_promisc) {
651 bcopy(vtag_arr, fwcmd->params.req.tags.normal_vlans,
652 vtag_cnt * sizeof(struct normal_vlan));
654 mbx.u0.s.embedded = 1;
655 mbx.payload_length = sizeof(struct mbx_common_config_vlan);
656 DW_SWAP(u32ptr(&mbx), (OCE_BMBX_RHDR_SZ + mbx.payload_length));
658 rc = oce_mbox_post(sc, &mbx, NULL);
660 rc = fwcmd->hdr.u0.rsp.status;
662 device_printf(sc->dev,"%s failed - cmd status: %d\n",
669 * @brief Function to set flow control capability in the hardware
670 * @param sc software handle to the device
671 * @param flow_control flow control flags to set
672 * @returns 0 on success, EIO on failure
675 oce_set_flow_control(POCE_SOFTC sc, uint32_t flow_control)
678 struct mbx_common_get_set_flow_control *fwcmd =
679 (struct mbx_common_get_set_flow_control *)&mbx.payload;
682 bzero(&mbx, sizeof(struct oce_mbx));
684 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
685 MBX_SUBSYSTEM_COMMON,
686 OPCODE_COMMON_SET_FLOW_CONTROL,
688 sizeof(struct mbx_common_get_set_flow_control),
691 if (flow_control & OCE_FC_TX)
692 fwcmd->tx_flow_control = 1;
694 if (flow_control & OCE_FC_RX)
695 fwcmd->rx_flow_control = 1;
697 mbx.u0.s.embedded = 1;
698 mbx.payload_length = sizeof(struct mbx_common_get_set_flow_control);
699 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
701 rc = oce_mbox_post(sc, &mbx, NULL);
703 rc = fwcmd->hdr.u0.rsp.status;
705 device_printf(sc->dev,"%s failed - cmd status: %d\n",
711 * @brief Initialize the RSS CPU indirection table
713 * The table is used to choose the queue to place the incomming packets.
714 * Incomming packets are hashed. The lowest bits in the hash result
715 * are used as the index into the CPU indirection table.
716 * Each entry in the table contains the RSS CPU-ID returned by the NIC
717 * create. Based on the CPU ID, the receive completion is routed to
718 * the corresponding RSS CQs. (Non-RSS packets are always completed
719 * on the default (0) CQ).
721 * @param sc software handle to the device
722 * @param *fwcmd pointer to the rss mbox command
726 oce_rss_itbl_init(POCE_SOFTC sc, struct mbx_config_nic_rss *fwcmd)
728 int i = 0, j = 0, rc = 0;
729 uint8_t *tbl = fwcmd->params.req.cputable;
732 for (j = 0; j < sc->nrqs; j++) {
733 if (sc->rq[j]->cfg.is_rss_queue) {
734 tbl[i] = sc->rq[j]->rss_cpuid;
739 device_printf(sc->dev, "error: Invalid number of RSS RQ's\n");
744 /* fill log2 value indicating the size of the CPU table */
746 fwcmd->params.req.cpu_tbl_sz_log2 = LE_16(OCE_LOG2(i));
752 * @brief Function to set flow control capability in the hardware
753 * @param sc software handle to the device
754 * @param if_id interface id to read the address from
755 * @param enable_rss 0=disable, RSS_ENABLE_xxx flags otherwise
756 * @returns 0 on success, EIO on failure
759 oce_config_nic_rss(POCE_SOFTC sc, uint32_t if_id, uint16_t enable_rss)
763 struct mbx_config_nic_rss *fwcmd =
764 (struct mbx_config_nic_rss *)&mbx.payload;
767 bzero(&mbx, sizeof(struct oce_mbx));
770 version = OCE_MBX_VER_V1;
771 fwcmd->params.req.enable_rss = RSS_ENABLE_UDP_IPV4 |
774 version = OCE_MBX_VER_V0;
776 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
780 sizeof(struct mbx_config_nic_rss),
783 fwcmd->params.req.enable_rss |= (RSS_ENABLE_IPV4 |
784 RSS_ENABLE_TCP_IPV4 |
786 RSS_ENABLE_TCP_IPV6);
787 fwcmd->params.req.flush = OCE_FLUSH;
788 fwcmd->params.req.if_id = LE_32(if_id);
790 srandom(arc4random()); /* random entropy seed */
791 read_random(fwcmd->params.req.hash, sizeof(fwcmd->params.req.hash));
793 rc = oce_rss_itbl_init(sc, fwcmd);
795 mbx.u0.s.embedded = 1;
796 mbx.payload_length = sizeof(struct mbx_config_nic_rss);
797 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
799 rc = oce_mbox_post(sc, &mbx, NULL);
801 rc = fwcmd->hdr.u0.rsp.status;
803 device_printf(sc->dev,"%s failed - cmd status: %d\n",
810 * @brief RXF function to enable/disable device promiscuous mode
811 * @param sc software handle to the device
812 * @param enable enable/disable flag
813 * @returns 0 on success, EIO on failure
815 * The NIC_CONFIG_PROMISCUOUS command deprecated for Lancer.
816 * This function uses the COMMON_SET_IFACE_RX_FILTER command instead.
819 oce_rxf_set_promiscuous(POCE_SOFTC sc, uint32_t enable)
821 struct mbx_set_common_iface_rx_filter *fwcmd;
822 int sz = sizeof(struct mbx_set_common_iface_rx_filter);
823 iface_rx_filter_ctx_t *req;
827 /* allocate mbx payload's dma scatter/gather memory */
828 rc = oce_dma_alloc(sc, sz, &sgl, 0);
832 fwcmd = OCE_DMAPTR(&sgl, struct mbx_set_common_iface_rx_filter);
834 req = &fwcmd->params.req;
835 req->iface_flags_mask = MBX_RX_IFACE_FLAGS_PROMISCUOUS |
836 MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS;
838 req->iface_flags = MBX_RX_IFACE_FLAGS_PROMISCUOUS |
839 MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS;
841 req->if_id = sc->if_id;
843 rc = oce_set_common_iface_rx_filter(sc, &sgl);
844 oce_dma_free(sc, &sgl);
851 * @brief Function modify and select rx filter options
852 * @param sc software handle to the device
853 * @param sgl scatter/gather request/response
854 * @returns 0 on success, error code on failure
857 oce_set_common_iface_rx_filter(POCE_SOFTC sc, POCE_DMA_MEM sgl)
860 int mbx_sz = sizeof(struct mbx_set_common_iface_rx_filter);
861 struct mbx_set_common_iface_rx_filter *fwcmd;
864 bzero(&mbx, sizeof(struct oce_mbx));
865 fwcmd = OCE_DMAPTR(sgl, struct mbx_set_common_iface_rx_filter);
867 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
868 MBX_SUBSYSTEM_COMMON,
869 OPCODE_COMMON_SET_IFACE_RX_FILTER,
874 oce_dma_sync(sgl, BUS_DMASYNC_PREWRITE);
875 mbx.u0.s.embedded = 0;
876 mbx.u0.s.sge_count = 1;
877 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(sgl->paddr);
878 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(sgl->paddr);
879 mbx.payload.u0.u1.sgl[0].length = mbx_sz;
880 mbx.payload_length = mbx_sz;
881 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
883 rc = oce_mbox_post(sc, &mbx, NULL);
885 rc = fwcmd->hdr.u0.rsp.status;
887 device_printf(sc->dev,"%s failed - cmd status: %d\n",
893 * @brief Function to query the link status from the hardware
894 * @param sc software handle to the device
895 * @param[out] link pointer to the structure returning link attributes
896 * @returns 0 on success, EIO on failure
899 oce_get_link_status(POCE_SOFTC sc, struct link_status *link)
902 struct mbx_query_common_link_config *fwcmd;
905 bzero(&mbx, sizeof(struct oce_mbx));
907 IS_XE201(sc) ? (version = OCE_MBX_VER_V1) : (version = OCE_MBX_VER_V0);
909 fwcmd = (struct mbx_query_common_link_config *)&mbx.payload;
910 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
911 MBX_SUBSYSTEM_COMMON,
912 OPCODE_COMMON_QUERY_LINK_CONFIG,
914 sizeof(struct mbx_query_common_link_config),
917 mbx.u0.s.embedded = 1;
918 mbx.payload_length = sizeof(struct mbx_query_common_link_config);
919 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
921 rc = oce_mbox_post(sc, &mbx, NULL);
924 rc = fwcmd->hdr.u0.rsp.status;
926 device_printf(sc->dev,"%s failed - cmd status: %d\n",
930 /* interpret response */
931 bcopy(&fwcmd->params.rsp, link, sizeof(struct link_status));
932 link->logical_link_status = LE_32(link->logical_link_status);
933 link->qos_link_speed = LE_16(link->qos_link_speed);
941 oce_mbox_get_nic_stats_v0(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem)
944 struct mbx_get_nic_stats_v0 *fwcmd;
947 bzero(&mbx, sizeof(struct oce_mbx));
949 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_nic_stats_v0);
950 bzero(fwcmd, sizeof(struct mbx_get_nic_stats_v0));
952 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
956 sizeof(struct mbx_get_nic_stats_v0),
959 mbx.u0.s.embedded = 0;
960 mbx.u0.s.sge_count = 1;
962 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE);
964 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr);
965 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr);
966 mbx.payload.u0.u1.sgl[0].length = sizeof(struct mbx_get_nic_stats_v0);
968 mbx.payload_length = sizeof(struct mbx_get_nic_stats_v0);
970 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
972 rc = oce_mbox_post(sc, &mbx, NULL);
974 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE);
977 rc = fwcmd->hdr.u0.rsp.status;
979 device_printf(sc->dev,"%s failed - cmd status: %d\n",
987 * @brief Function to get NIC statistics
988 * @param sc software handle to the device
989 * @param *stats pointer to where to store statistics
990 * @param reset_stats resets statistics of set
991 * @returns 0 on success, EIO on failure
992 * @note command depricated in Lancer
995 oce_mbox_get_nic_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem)
998 struct mbx_get_nic_stats *fwcmd;
1001 bzero(&mbx, sizeof(struct oce_mbx));
1002 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_nic_stats);
1003 bzero(fwcmd, sizeof(struct mbx_get_nic_stats));
1005 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1009 sizeof(struct mbx_get_nic_stats),
1013 mbx.u0.s.embedded = 0; /* stats too large for embedded mbx rsp */
1014 mbx.u0.s.sge_count = 1; /* using scatter gather instead */
1016 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE);
1017 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr);
1018 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr);
1019 mbx.payload.u0.u1.sgl[0].length = sizeof(struct mbx_get_nic_stats);
1021 mbx.payload_length = sizeof(struct mbx_get_nic_stats);
1022 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1024 rc = oce_mbox_post(sc, &mbx, NULL);
1025 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE);
1027 rc = fwcmd->hdr.u0.rsp.status;
1029 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1036 * @brief Function to get pport (physical port) statistics
1037 * @param sc software handle to the device
1038 * @param *stats pointer to where to store statistics
1039 * @param reset_stats resets statistics of set
1040 * @returns 0 on success, EIO on failure
1043 oce_mbox_get_pport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem,
1044 uint32_t reset_stats)
1047 struct mbx_get_pport_stats *fwcmd;
1050 bzero(&mbx, sizeof(struct oce_mbx));
1051 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_pport_stats);
1052 bzero(fwcmd, sizeof(struct mbx_get_pport_stats));
1054 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1056 NIC_GET_PPORT_STATS,
1058 sizeof(struct mbx_get_pport_stats),
1061 fwcmd->params.req.reset_stats = reset_stats;
1062 fwcmd->params.req.port_number = sc->port_id;
1064 mbx.u0.s.embedded = 0; /* stats too large for embedded mbx rsp */
1065 mbx.u0.s.sge_count = 1; /* using scatter gather instead */
1067 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE);
1068 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr);
1069 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr);
1070 mbx.payload.u0.u1.sgl[0].length = sizeof(struct mbx_get_pport_stats);
1072 mbx.payload_length = sizeof(struct mbx_get_pport_stats);
1073 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1075 rc = oce_mbox_post(sc, &mbx, NULL);
1076 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE);
1079 rc = fwcmd->hdr.u0.rsp.status;
1081 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1088 * @brief Function to get vport (virtual port) statistics
1089 * @param sc software handle to the device
1090 * @param *stats pointer to where to store statistics
1091 * @param reset_stats resets statistics of set
1092 * @returns 0 on success, EIO on failure
1095 oce_mbox_get_vport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem,
1096 uint32_t req_size, uint32_t reset_stats)
1099 struct mbx_get_vport_stats *fwcmd;
1102 bzero(&mbx, sizeof(struct oce_mbx));
1104 fwcmd = OCE_DMAPTR(pstats_dma_mem, struct mbx_get_vport_stats);
1105 bzero(fwcmd, sizeof(struct mbx_get_vport_stats));
1107 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1109 NIC_GET_VPORT_STATS,
1111 sizeof(struct mbx_get_vport_stats),
1114 fwcmd->params.req.reset_stats = reset_stats;
1115 fwcmd->params.req.vport_number = sc->if_id;
1117 mbx.u0.s.embedded = 0; /* stats too large for embedded mbx rsp */
1118 mbx.u0.s.sge_count = 1; /* using scatter gather instead */
1120 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_PREWRITE);
1121 mbx.payload.u0.u1.sgl[0].pa_lo = ADDR_LO(pstats_dma_mem->paddr);
1122 mbx.payload.u0.u1.sgl[0].pa_hi = ADDR_HI(pstats_dma_mem->paddr);
1123 mbx.payload.u0.u1.sgl[0].length = sizeof(struct mbx_get_vport_stats);
1125 mbx.payload_length = sizeof(struct mbx_get_vport_stats);
1126 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1128 rc = oce_mbox_post(sc, &mbx, NULL);
1129 oce_dma_sync(pstats_dma_mem, BUS_DMASYNC_POSTWRITE);
1132 rc = fwcmd->hdr.u0.rsp.status;
1134 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1141 * @brief Function to update the muticast filter with
1143 * @param sc software handle to the device
1144 * @param dma_mem pointer to dma memory region
1145 * @returns 0 on success, EIO on failure
1148 oce_update_multicast(POCE_SOFTC sc, POCE_DMA_MEM pdma_mem)
1151 struct oce_mq_sge *sgl;
1152 struct mbx_set_common_iface_multicast *req = NULL;
1155 req = OCE_DMAPTR(pdma_mem, struct mbx_set_common_iface_multicast);
1156 mbx_common_req_hdr_init(&req->hdr, 0, 0,
1157 MBX_SUBSYSTEM_COMMON,
1158 OPCODE_COMMON_SET_IFACE_MULTICAST,
1160 sizeof(struct mbx_set_common_iface_multicast),
1163 bzero(&mbx, sizeof(struct oce_mbx));
1165 mbx.u0.s.embedded = 0; /*Non embeded*/
1166 mbx.payload_length = sizeof(struct mbx_set_common_iface_multicast);
1167 mbx.u0.s.sge_count = 1;
1168 sgl = &mbx.payload.u0.u1.sgl[0];
1169 sgl->pa_hi = htole32(upper_32_bits(pdma_mem->paddr));
1170 sgl->pa_lo = htole32((pdma_mem->paddr) & 0xFFFFFFFF);
1171 sgl->length = htole32(mbx.payload_length);
1173 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1175 rc = oce_mbox_post(sc, &mbx, NULL);
1177 rc = req->hdr.u0.rsp.status;
1179 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1186 * @brief Function to send passthrough Ioctls
1187 * @param sc software handle to the device
1188 * @param dma_mem pointer to dma memory region
1189 * @param req_size size of dma_mem
1190 * @returns 0 on success, EIO on failure
1193 oce_pass_through_mbox(POCE_SOFTC sc, POCE_DMA_MEM dma_mem, uint32_t req_size)
1196 struct oce_mq_sge *sgl;
1199 bzero(&mbx, sizeof(struct oce_mbx));
1201 mbx.u0.s.embedded = 0; /*Non embeded*/
1202 mbx.payload_length = req_size;
1203 mbx.u0.s.sge_count = 1;
1204 sgl = &mbx.payload.u0.u1.sgl[0];
1205 sgl->pa_hi = htole32(upper_32_bits(dma_mem->paddr));
1206 sgl->pa_lo = htole32((dma_mem->paddr) & 0xFFFFFFFF);
1207 sgl->length = htole32(req_size);
1209 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1211 rc = oce_mbox_post(sc, &mbx, NULL);
1217 oce_mbox_macaddr_add(POCE_SOFTC sc, uint8_t *mac_addr,
1218 uint32_t if_id, uint32_t *pmac_id)
1221 struct mbx_add_common_iface_mac *fwcmd;
1224 bzero(&mbx, sizeof(struct oce_mbx));
1226 fwcmd = (struct mbx_add_common_iface_mac *)&mbx.payload;
1227 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1228 MBX_SUBSYSTEM_COMMON,
1229 OPCODE_COMMON_ADD_IFACE_MAC,
1231 sizeof(struct mbx_add_common_iface_mac),
1234 fwcmd->params.req.if_id = (uint16_t) if_id;
1235 bcopy(mac_addr, fwcmd->params.req.mac_address, 6);
1237 mbx.u0.s.embedded = 1;
1238 mbx.payload_length = sizeof(struct mbx_add_common_iface_mac);
1239 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1240 rc = oce_mbox_post(sc, &mbx, NULL);
1242 rc = fwcmd->hdr.u0.rsp.status;
1244 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1248 *pmac_id = fwcmd->params.rsp.pmac_id;
1255 oce_mbox_macaddr_del(POCE_SOFTC sc, uint32_t if_id, uint32_t pmac_id)
1258 struct mbx_del_common_iface_mac *fwcmd;
1261 bzero(&mbx, sizeof(struct oce_mbx));
1263 fwcmd = (struct mbx_del_common_iface_mac *)&mbx.payload;
1264 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1265 MBX_SUBSYSTEM_COMMON,
1266 OPCODE_COMMON_DEL_IFACE_MAC,
1268 sizeof(struct mbx_del_common_iface_mac),
1271 fwcmd->params.req.if_id = (uint16_t)if_id;
1272 fwcmd->params.req.pmac_id = pmac_id;
1274 mbx.u0.s.embedded = 1;
1275 mbx.payload_length = sizeof(struct mbx_del_common_iface_mac);
1276 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1278 rc = oce_mbox_post(sc, &mbx, NULL);
1280 rc = fwcmd->hdr.u0.rsp.status;
1282 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1290 oce_mbox_check_native_mode(POCE_SOFTC sc)
1293 struct mbx_common_set_function_cap *fwcmd;
1296 bzero(&mbx, sizeof(struct oce_mbx));
1298 fwcmd = (struct mbx_common_set_function_cap *)&mbx.payload;
1299 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1300 MBX_SUBSYSTEM_COMMON,
1301 OPCODE_COMMON_SET_FUNCTIONAL_CAPS,
1303 sizeof(struct mbx_common_set_function_cap),
1306 fwcmd->params.req.valid_capability_flags = CAP_SW_TIMESTAMPS |
1307 CAP_BE3_NATIVE_ERX_API;
1309 fwcmd->params.req.capability_flags = CAP_BE3_NATIVE_ERX_API;
1311 mbx.u0.s.embedded = 1;
1312 mbx.payload_length = sizeof(struct mbx_common_set_function_cap);
1313 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1315 rc = oce_mbox_post(sc, &mbx, NULL);
1317 rc = fwcmd->hdr.u0.rsp.status;
1319 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1323 sc->be3_native = fwcmd->params.rsp.capability_flags
1324 & CAP_BE3_NATIVE_ERX_API;
1333 oce_mbox_cmd_set_loopback(POCE_SOFTC sc, uint8_t port_num,
1334 uint8_t loopback_type, uint8_t enable)
1337 struct mbx_lowlevel_set_loopback_mode *fwcmd;
1341 bzero(&mbx, sizeof(struct oce_mbx));
1343 fwcmd = (struct mbx_lowlevel_set_loopback_mode *)&mbx.payload;
1344 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1345 MBX_SUBSYSTEM_LOWLEVEL,
1346 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
1348 sizeof(struct mbx_lowlevel_set_loopback_mode),
1351 fwcmd->params.req.src_port = port_num;
1352 fwcmd->params.req.dest_port = port_num;
1353 fwcmd->params.req.loopback_type = loopback_type;
1354 fwcmd->params.req.loopback_state = enable;
1356 mbx.u0.s.embedded = 1;
1357 mbx.payload_length = sizeof(struct mbx_lowlevel_set_loopback_mode);
1358 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1360 rc = oce_mbox_post(sc, &mbx, NULL);
1362 rc = fwcmd->hdr.u0.rsp.status;
1364 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1372 oce_mbox_cmd_test_loopback(POCE_SOFTC sc, uint32_t port_num,
1373 uint32_t loopback_type, uint32_t pkt_size, uint32_t num_pkts,
1378 struct mbx_lowlevel_test_loopback_mode *fwcmd;
1382 bzero(&mbx, sizeof(struct oce_mbx));
1384 fwcmd = (struct mbx_lowlevel_test_loopback_mode *)&mbx.payload;
1385 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1386 MBX_SUBSYSTEM_LOWLEVEL,
1387 OPCODE_LOWLEVEL_TEST_LOOPBACK,
1389 sizeof(struct mbx_lowlevel_test_loopback_mode),
1392 fwcmd->params.req.pattern = pattern;
1393 fwcmd->params.req.src_port = port_num;
1394 fwcmd->params.req.dest_port = port_num;
1395 fwcmd->params.req.pkt_size = pkt_size;
1396 fwcmd->params.req.num_pkts = num_pkts;
1397 fwcmd->params.req.loopback_type = loopback_type;
1399 mbx.u0.s.embedded = 1;
1400 mbx.payload_length = sizeof(struct mbx_lowlevel_test_loopback_mode);
1401 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1403 rc = oce_mbox_post(sc, &mbx, NULL);
1405 rc = fwcmd->hdr.u0.rsp.status;
1407 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1414 oce_mbox_write_flashrom(POCE_SOFTC sc, uint32_t optype,uint32_t opcode,
1415 POCE_DMA_MEM pdma_mem, uint32_t num_bytes)
1419 struct oce_mq_sge *sgl = NULL;
1420 struct mbx_common_read_write_flashrom *fwcmd = NULL;
1421 int rc = 0, payload_len = 0;
1423 bzero(&mbx, sizeof(struct oce_mbx));
1424 fwcmd = OCE_DMAPTR(pdma_mem, struct mbx_common_read_write_flashrom);
1425 payload_len = sizeof(struct mbx_common_read_write_flashrom) + 32*1024;
1427 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1428 MBX_SUBSYSTEM_COMMON,
1429 OPCODE_COMMON_WRITE_FLASHROM,
1434 fwcmd->flash_op_type = optype;
1435 fwcmd->flash_op_code = opcode;
1436 fwcmd->data_buffer_size = num_bytes;
1438 mbx.u0.s.embedded = 0; /*Non embeded*/
1439 mbx.payload_length = payload_len;
1440 mbx.u0.s.sge_count = 1;
1442 sgl = &mbx.payload.u0.u1.sgl[0];
1443 sgl->pa_hi = upper_32_bits(pdma_mem->paddr);
1444 sgl->pa_lo = pdma_mem->paddr & 0xFFFFFFFF;
1445 sgl->length = payload_len;
1447 /* post the command */
1448 rc = oce_mbox_post(sc, &mbx, NULL);
1450 rc = fwcmd->hdr.u0.rsp.status;
1452 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1460 oce_mbox_get_flashrom_crc(POCE_SOFTC sc, uint8_t *flash_crc,
1461 uint32_t offset, uint32_t optype)
1464 int rc = 0, payload_len = 0;
1466 struct mbx_common_read_write_flashrom *fwcmd;
1468 bzero(&mbx, sizeof(struct oce_mbx));
1470 fwcmd = (struct mbx_common_read_write_flashrom *)&mbx.payload;
1472 /* Firmware requires extra 4 bytes with this ioctl. Since there
1473 is enough room in the mbx payload it should be good enough
1474 Reference: Bug 14853
1476 payload_len = sizeof(struct mbx_common_read_write_flashrom) + 4;
1478 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1479 MBX_SUBSYSTEM_COMMON,
1480 OPCODE_COMMON_READ_FLASHROM,
1485 fwcmd->flash_op_type = optype;
1486 fwcmd->flash_op_code = FLASHROM_OPER_REPORT;
1487 fwcmd->data_offset = offset;
1488 fwcmd->data_buffer_size = 0x4;
1490 mbx.u0.s.embedded = 1;
1491 mbx.payload_length = payload_len;
1493 /* post the command */
1494 rc = oce_mbox_post(sc, &mbx, NULL);
1496 rc = fwcmd->hdr.u0.rsp.status;
1498 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1502 bcopy(fwcmd->data_buffer, flash_crc, 4);
1508 oce_mbox_get_phy_info(POCE_SOFTC sc, struct oce_phy_info *phy_info)
1512 struct mbx_common_phy_info *fwcmd;
1515 bzero(&mbx, sizeof(struct oce_mbx));
1517 fwcmd = (struct mbx_common_phy_info *)&mbx.payload;
1518 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1519 MBX_SUBSYSTEM_COMMON,
1520 OPCODE_COMMON_GET_PHY_CONFIG,
1522 sizeof(struct mbx_common_phy_info),
1525 mbx.u0.s.embedded = 1;
1526 mbx.payload_length = sizeof(struct mbx_common_phy_info);
1528 /* now post the command */
1529 rc = oce_mbox_post(sc, &mbx, NULL);
1531 rc = fwcmd->hdr.u0.rsp.status;
1533 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1537 phy_info->phy_type = fwcmd->params.rsp.phy_info.phy_type;
1538 phy_info->interface_type =
1539 fwcmd->params.rsp.phy_info.interface_type;
1540 phy_info->auto_speeds_supported =
1541 fwcmd->params.rsp.phy_info.auto_speeds_supported;
1542 phy_info->fixed_speeds_supported =
1543 fwcmd->params.rsp.phy_info.fixed_speeds_supported;
1544 phy_info->misc_params =fwcmd->params.rsp.phy_info.misc_params;
1552 oce_mbox_lancer_write_flashrom(POCE_SOFTC sc, uint32_t data_size,
1553 uint32_t data_offset, POCE_DMA_MEM pdma_mem,
1554 uint32_t *written_data, uint32_t *additional_status)
1558 struct mbx_lancer_common_write_object *fwcmd = NULL;
1559 int rc = 0, payload_len = 0;
1561 bzero(&mbx, sizeof(struct oce_mbx));
1562 payload_len = sizeof(struct mbx_lancer_common_write_object);
1564 mbx.u0.s.embedded = 1;/* Embedded */
1565 mbx.payload_length = payload_len;
1566 fwcmd = (struct mbx_lancer_common_write_object *)&mbx.payload;
1568 /* initialize the ioctl header */
1569 mbx_common_req_hdr_init(&fwcmd->params.req.hdr, 0, 0,
1570 MBX_SUBSYSTEM_COMMON,
1571 OPCODE_COMMON_WRITE_OBJECT,
1576 fwcmd->params.req.write_length = data_size;
1578 fwcmd->params.req.eof = 1;
1580 fwcmd->params.req.eof = 0;
1582 strcpy(fwcmd->params.req.object_name, "/prg");
1583 fwcmd->params.req.descriptor_count = 1;
1584 fwcmd->params.req.write_offset = data_offset;
1585 fwcmd->params.req.buffer_length = data_size;
1586 fwcmd->params.req.address_lower = pdma_mem->paddr & 0xFFFFFFFF;
1587 fwcmd->params.req.address_upper = upper_32_bits(pdma_mem->paddr);
1589 /* post the command */
1590 rc = oce_mbox_post(sc, &mbx, NULL);
1592 rc = fwcmd->params.rsp.status;
1594 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1598 *written_data = fwcmd->params.rsp.actual_write_length;
1599 *additional_status = fwcmd->params.rsp.additional_status;
1608 oce_mbox_create_rq(struct oce_rq *rq)
1612 struct mbx_create_nic_rq *fwcmd;
1613 POCE_SOFTC sc = rq->parent;
1614 int rc, num_pages = 0;
1616 if (rq->qstate == QCREATED)
1619 bzero(&mbx, sizeof(struct oce_mbx));
1621 fwcmd = (struct mbx_create_nic_rq *)&mbx.payload;
1622 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1624 NIC_CREATE_RQ, MBX_TIMEOUT_SEC,
1625 sizeof(struct mbx_create_nic_rq),
1628 /* oce_page_list will also prepare pages */
1629 num_pages = oce_page_list(rq->ring, &fwcmd->params.req.pages[0]);
1632 fwcmd->params.req.frag_size = rq->cfg.frag_size/2048;
1633 fwcmd->params.req.page_size = 1;
1634 fwcmd->hdr.u0.req.version = OCE_MBX_VER_V1;
1636 fwcmd->params.req.frag_size = OCE_LOG2(rq->cfg.frag_size);
1637 fwcmd->params.req.num_pages = num_pages;
1638 fwcmd->params.req.cq_id = rq->cq->cq_id;
1639 fwcmd->params.req.if_id = sc->if_id;
1640 fwcmd->params.req.max_frame_size = rq->cfg.mtu;
1641 fwcmd->params.req.is_rss_queue = rq->cfg.is_rss_queue;
1643 mbx.u0.s.embedded = 1;
1644 mbx.payload_length = sizeof(struct mbx_create_nic_rq);
1646 rc = oce_mbox_post(sc, &mbx, NULL);
1648 rc = fwcmd->hdr.u0.rsp.status;
1650 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1654 rq->rq_id = fwcmd->params.rsp.rq_id;
1655 rq->rss_cpuid = fwcmd->params.rsp.rss_cpuid;
1664 oce_mbox_create_wq(struct oce_wq *wq)
1667 struct mbx_create_nic_wq *fwcmd;
1668 POCE_SOFTC sc = wq->parent;
1669 int rc = 0, version, num_pages;
1671 bzero(&mbx, sizeof(struct oce_mbx));
1673 fwcmd = (struct mbx_create_nic_wq *)&mbx.payload;
1675 version = OCE_MBX_VER_V1;
1676 fwcmd->params.req.if_id = sc->if_id;
1678 version = OCE_MBX_VER_V0;
1680 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1682 NIC_CREATE_WQ, MBX_TIMEOUT_SEC,
1683 sizeof(struct mbx_create_nic_wq),
1686 num_pages = oce_page_list(wq->ring, &fwcmd->params.req.pages[0]);
1688 fwcmd->params.req.nic_wq_type = wq->cfg.wq_type;
1689 fwcmd->params.req.num_pages = num_pages;
1690 fwcmd->params.req.wq_size = OCE_LOG2(wq->cfg.q_len) + 1;
1691 fwcmd->params.req.cq_id = wq->cq->cq_id;
1692 fwcmd->params.req.ulp_num = 1;
1694 mbx.u0.s.embedded = 1;
1695 mbx.payload_length = sizeof(struct mbx_create_nic_wq);
1697 rc = oce_mbox_post(sc, &mbx, NULL);
1699 rc = fwcmd->hdr.u0.rsp.status;
1701 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1705 wq->wq_id = LE_16(fwcmd->params.rsp.wq_id);
1714 oce_mbox_create_eq(struct oce_eq *eq)
1717 struct mbx_create_common_eq *fwcmd;
1718 POCE_SOFTC sc = eq->parent;
1722 bzero(&mbx, sizeof(struct oce_mbx));
1724 fwcmd = (struct mbx_create_common_eq *)&mbx.payload;
1726 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1727 MBX_SUBSYSTEM_COMMON,
1728 OPCODE_COMMON_CREATE_EQ, MBX_TIMEOUT_SEC,
1729 sizeof(struct mbx_create_common_eq),
1732 num_pages = oce_page_list(eq->ring, &fwcmd->params.req.pages[0]);
1733 fwcmd->params.req.ctx.num_pages = num_pages;
1734 fwcmd->params.req.ctx.valid = 1;
1735 fwcmd->params.req.ctx.size = (eq->eq_cfg.item_size == 4) ? 0 : 1;
1736 fwcmd->params.req.ctx.count = OCE_LOG2(eq->eq_cfg.q_len / 256);
1737 fwcmd->params.req.ctx.armed = 0;
1738 fwcmd->params.req.ctx.delay_mult = eq->eq_cfg.cur_eqd;
1741 mbx.u0.s.embedded = 1;
1742 mbx.payload_length = sizeof(struct mbx_create_common_eq);
1744 rc = oce_mbox_post(sc, &mbx, NULL);
1746 rc = fwcmd->hdr.u0.rsp.status;
1748 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1752 eq->eq_id = LE_16(fwcmd->params.rsp.eq_id);
1760 oce_mbox_cq_create(struct oce_cq *cq, uint32_t ncoalesce, uint32_t is_eventable)
1763 struct mbx_create_common_cq *fwcmd;
1764 POCE_SOFTC sc = cq->parent;
1767 uint32_t num_pages, page_size;
1771 bzero(&mbx, sizeof(struct oce_mbx));
1773 fwcmd = (struct mbx_create_common_cq *)&mbx.payload;
1776 version = OCE_MBX_VER_V2;
1778 version = OCE_MBX_VER_V0;
1780 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1781 MBX_SUBSYSTEM_COMMON,
1782 OPCODE_COMMON_CREATE_CQ,
1784 sizeof(struct mbx_create_common_cq),
1787 ctx = &fwcmd->params.req.cq_ctx;
1789 num_pages = oce_page_list(cq->ring, &fwcmd->params.req.pages[0]);
1790 page_size = 1; /* 1 for 4K */
1792 if (version == OCE_MBX_VER_V2) {
1793 ctx->v2.num_pages = LE_16(num_pages);
1794 ctx->v2.page_size = page_size;
1795 ctx->v2.eventable = is_eventable;
1797 ctx->v2.count = OCE_LOG2(cq->cq_cfg.q_len / 256);
1798 ctx->v2.nodelay = cq->cq_cfg.nodelay;
1799 ctx->v2.coalesce_wm = ncoalesce;
1801 ctx->v2.eq_id = cq->eq->eq_id;
1802 if (ctx->v2.count == 3) {
1803 if (cq->cq_cfg.q_len > (4*1024)-1)
1804 ctx->v2.cqe_count = (4*1024)-1;
1806 ctx->v2.cqe_count = cq->cq_cfg.q_len;
1809 ctx->v0.num_pages = LE_16(num_pages);
1810 ctx->v0.eventable = is_eventable;
1812 ctx->v0.count = OCE_LOG2(cq->cq_cfg.q_len / 256);
1813 ctx->v0.nodelay = cq->cq_cfg.nodelay;
1814 ctx->v0.coalesce_wm = ncoalesce;
1816 ctx->v0.eq_id = cq->eq->eq_id;
1819 mbx.u0.s.embedded = 1;
1820 mbx.payload_length = sizeof(struct mbx_create_common_cq);
1822 rc = oce_mbox_post(sc, &mbx, NULL);
1824 rc = fwcmd->hdr.u0.rsp.status;
1826 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1830 cq->cq_id = LE_16(fwcmd->params.rsp.cq_id);
1837 oce_mbox_read_transrecv_data(POCE_SOFTC sc, uint32_t page_num)
1841 struct mbx_read_common_transrecv_data *fwcmd;
1842 struct oce_mq_sge *sgl;
1845 /* Allocate DMA mem*/
1846 if (oce_dma_alloc(sc, sizeof(struct mbx_read_common_transrecv_data),
1850 fwcmd = OCE_DMAPTR(&dma, struct mbx_read_common_transrecv_data);
1851 bzero(fwcmd, sizeof(struct mbx_read_common_transrecv_data));
1853 bzero(&mbx, sizeof(struct oce_mbx));
1854 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1855 MBX_SUBSYSTEM_COMMON,
1856 OPCODE_COMMON_READ_TRANSRECEIVER_DATA,
1858 sizeof(struct mbx_read_common_transrecv_data),
1861 /* fill rest of mbx */
1862 mbx.u0.s.embedded = 0;
1863 mbx.payload_length = sizeof(struct mbx_read_common_transrecv_data);
1864 mbx.u0.s.sge_count = 1;
1865 sgl = &mbx.payload.u0.u1.sgl[0];
1866 sgl->pa_hi = htole32(upper_32_bits(dma.paddr));
1867 sgl->pa_lo = htole32((dma.paddr) & 0xFFFFFFFF);
1868 sgl->length = htole32(mbx.payload_length);
1869 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1871 fwcmd->params.req.port = LE_32(sc->port_id);
1872 fwcmd->params.req.page_num = LE_32(page_num);
1875 rc = oce_mbox_post(sc, &mbx, NULL);
1877 rc = fwcmd->hdr.u0.rsp.status;
1879 device_printf(sc->dev,"%s failed - cmd status: %d\n",
1883 if(fwcmd->params.rsp.page_num == PAGE_NUM_A0)
1885 bcopy((char *)fwcmd->params.rsp.page_data,
1886 (char *)&sfp_vpd_dump_buffer[0],
1887 TRANSCEIVER_A0_SIZE);
1890 if(fwcmd->params.rsp.page_num == PAGE_NUM_A2)
1892 bcopy((char *)fwcmd->params.rsp.page_data,
1893 (char *)&sfp_vpd_dump_buffer[32],
1894 TRANSCEIVER_A2_SIZE);
1901 oce_mbox_eqd_modify_periodic(POCE_SOFTC sc, struct oce_set_eqd *set_eqd,
1905 struct mbx_modify_common_eq_delay *fwcmd;
1909 bzero(&mbx, sizeof(struct oce_mbx));
1911 /* Initialize MODIFY_EQ_DELAY ioctl header */
1912 fwcmd = (struct mbx_modify_common_eq_delay *)&mbx.payload;
1913 mbx_common_req_hdr_init(&fwcmd->hdr, 0, 0,
1914 MBX_SUBSYSTEM_COMMON,
1915 OPCODE_COMMON_MODIFY_EQ_DELAY,
1917 sizeof(struct mbx_modify_common_eq_delay),
1919 /* fill rest of mbx */
1920 mbx.u0.s.embedded = 1;
1921 mbx.payload_length = sizeof(struct mbx_modify_common_eq_delay);
1922 DW_SWAP(u32ptr(&mbx), mbx.payload_length + OCE_BMBX_RHDR_SZ);
1924 fwcmd->params.req.num_eq = num;
1925 for (i = 0; i < num; i++) {
1926 fwcmd->params.req.delay[i].eq_id =
1927 htole32(set_eqd[i].eq_id);
1928 fwcmd->params.req.delay[i].phase = 0;
1929 fwcmd->params.req.delay[i].dm =
1930 htole32(set_eqd[i].delay_multiplier);
1935 rc = oce_mbox_post(sc, &mbx, NULL);
1938 rc = fwcmd->hdr.u0.rsp.status;
1940 device_printf(sc->dev,"%s failed - cmd status: %d\n",