2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000, BSDi
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/malloc.h>
37 #include <sys/module.h>
38 #include <sys/linker.h>
39 #include <sys/fcntl.h>
41 #include <sys/kernel.h>
42 #include <sys/queue.h>
43 #include <sys/sysctl.h>
44 #include <sys/endian.h>
48 #include <vm/vm_extern.h>
51 #include <machine/bus.h>
53 #include <machine/resource.h>
54 #include <machine/stdarg.h>
56 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
57 #include <machine/intr_machdep.h>
60 #include <sys/pciio.h>
61 #include <dev/pci/pcireg.h>
62 #include <dev/pci/pcivar.h>
63 #include <dev/pci/pci_private.h>
65 #include <dev/usb/controller/xhcireg.h>
66 #include <dev/usb/controller/ehcireg.h>
67 #include <dev/usb/controller/ohcireg.h>
68 #include <dev/usb/controller/uhcireg.h>
73 #define PCIR_IS_BIOS(cfg, reg) \
74 (((cfg)->hdrtype == PCIM_HDRTYPE_NORMAL && reg == PCIR_BIOS) || \
75 ((cfg)->hdrtype == PCIM_HDRTYPE_BRIDGE && reg == PCIR_BIOS_1))
77 static int pci_has_quirk(uint32_t devid, int quirk);
78 static pci_addr_t pci_mapbase(uint64_t mapreg);
79 static const char *pci_maptype(uint64_t mapreg);
80 static int pci_mapsize(uint64_t testval);
81 static int pci_maprange(uint64_t mapreg);
82 static pci_addr_t pci_rombase(uint64_t mapreg);
83 static int pci_romsize(uint64_t testval);
84 static void pci_fixancient(pcicfgregs *cfg);
85 static int pci_printf(pcicfgregs *cfg, const char *fmt, ...);
87 static int pci_porten(device_t dev);
88 static int pci_memen(device_t dev);
89 static void pci_assign_interrupt(device_t bus, device_t dev,
91 static int pci_add_map(device_t bus, device_t dev, int reg,
92 struct resource_list *rl, int force, int prefetch);
93 static int pci_probe(device_t dev);
94 static int pci_attach(device_t dev);
95 static void pci_load_vendor_data(void);
96 static int pci_describe_parse_line(char **ptr, int *vendor,
97 int *device, char **desc);
98 static char *pci_describe_device(device_t dev);
99 static int pci_modevent(module_t mod, int what, void *arg);
100 static void pci_hdrtypedata(device_t pcib, int b, int s, int f,
102 static void pci_read_cap(device_t pcib, pcicfgregs *cfg);
103 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg,
104 int reg, uint32_t *data);
106 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg,
107 int reg, uint32_t data);
109 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg);
110 static void pci_disable_msi(device_t dev);
111 static void pci_enable_msi(device_t dev, uint64_t address,
113 static void pci_enable_msix(device_t dev, u_int index,
114 uint64_t address, uint32_t data);
115 static void pci_mask_msix(device_t dev, u_int index);
116 static void pci_unmask_msix(device_t dev, u_int index);
117 static int pci_msi_blacklisted(void);
118 static int pci_msix_blacklisted(void);
119 static void pci_resume_msi(device_t dev);
120 static void pci_resume_msix(device_t dev);
121 static int pci_remap_intr_method(device_t bus, device_t dev,
124 static uint16_t pci_get_rid_method(device_t dev, device_t child);
126 static device_method_t pci_methods[] = {
127 /* Device interface */
128 DEVMETHOD(device_probe, pci_probe),
129 DEVMETHOD(device_attach, pci_attach),
130 DEVMETHOD(device_detach, bus_generic_detach),
131 DEVMETHOD(device_shutdown, bus_generic_shutdown),
132 DEVMETHOD(device_suspend, pci_suspend),
133 DEVMETHOD(device_resume, pci_resume),
136 DEVMETHOD(bus_print_child, pci_print_child),
137 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
138 DEVMETHOD(bus_read_ivar, pci_read_ivar),
139 DEVMETHOD(bus_write_ivar, pci_write_ivar),
140 DEVMETHOD(bus_driver_added, pci_driver_added),
141 DEVMETHOD(bus_setup_intr, pci_setup_intr),
142 DEVMETHOD(bus_teardown_intr, pci_teardown_intr),
144 DEVMETHOD(bus_get_dma_tag, pci_get_dma_tag),
145 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
146 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
147 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
148 DEVMETHOD(bus_delete_resource, pci_delete_resource),
149 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
150 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
151 DEVMETHOD(bus_release_resource, pci_release_resource),
152 DEVMETHOD(bus_activate_resource, pci_activate_resource),
153 DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource),
154 DEVMETHOD(bus_child_detached, pci_child_detached),
155 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
156 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
157 DEVMETHOD(bus_remap_intr, pci_remap_intr_method),
160 DEVMETHOD(pci_read_config, pci_read_config_method),
161 DEVMETHOD(pci_write_config, pci_write_config_method),
162 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
163 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
164 DEVMETHOD(pci_enable_io, pci_enable_io_method),
165 DEVMETHOD(pci_disable_io, pci_disable_io_method),
166 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method),
167 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method),
168 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
169 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
170 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
171 DEVMETHOD(pci_find_cap, pci_find_cap_method),
172 DEVMETHOD(pci_find_extcap, pci_find_extcap_method),
173 DEVMETHOD(pci_find_htcap, pci_find_htcap_method),
174 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method),
175 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method),
176 DEVMETHOD(pci_remap_msix, pci_remap_msix_method),
177 DEVMETHOD(pci_release_msi, pci_release_msi_method),
178 DEVMETHOD(pci_msi_count, pci_msi_count_method),
179 DEVMETHOD(pci_msix_count, pci_msix_count_method),
180 DEVMETHOD(pci_get_rid, pci_get_rid_method),
185 DEFINE_CLASS_0(pci, pci_driver, pci_methods, sizeof(struct pci_softc));
187 static devclass_t pci_devclass;
188 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, NULL);
189 MODULE_VERSION(pci, 1);
191 static char *pci_vendordata;
192 static size_t pci_vendordata_size;
195 uint32_t devid; /* Vendor/device of the card */
197 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
198 #define PCI_QUIRK_DISABLE_MSI 2 /* Neither MSI nor MSI-X work */
199 #define PCI_QUIRK_ENABLE_MSI_VM 3 /* Older chipset in VM where MSI works */
200 #define PCI_QUIRK_UNMAP_REG 4 /* Ignore PCI map register */
201 #define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */
202 #define PCI_QUIRK_MSI_INTX_BUG 6 /* PCIM_CMD_INTxDIS disables MSI */
207 static const struct pci_quirk pci_quirks[] = {
208 /* The Intel 82371AB and 82443MX have a map register at offset 0x90. */
209 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
210 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
211 /* As does the Serverworks OSB4 (the SMBus mapping register) */
212 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
215 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
216 * or the CMIC-SL (AKA ServerWorks GC_LE).
218 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
219 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
222 * MSI doesn't work on earlier Intel chipsets including
223 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
225 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
226 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
227 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
228 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
229 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
230 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
231 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
234 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
237 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 },
240 * MSI-X allocation doesn't work properly for devices passed through
241 * by VMware up to at least ESXi 5.1.
243 { 0x079015ad, PCI_QUIRK_DISABLE_MSIX, 0, 0 }, /* PCI/PCI-X */
244 { 0x07a015ad, PCI_QUIRK_DISABLE_MSIX, 0, 0 }, /* PCIe */
247 * Some virtualization environments emulate an older chipset
248 * but support MSI just fine. QEMU uses the Intel 82440.
250 { 0x12378086, PCI_QUIRK_ENABLE_MSI_VM, 0, 0 },
253 * HPET MMIO base address may appear in Bar1 for AMD SB600 SMBus
254 * controller depending on SoftPciRst register (PM_IO 0x55 [7]).
255 * It prevents us from attaching hpet(4) when the bit is unset.
256 * Note this quirk only affects SB600 revision A13 and earlier.
257 * For SB600 A21 and later, firmware must set the bit to hide it.
258 * For SB700 and later, it is unused and hardcoded to zero.
260 { 0x43851002, PCI_QUIRK_UNMAP_REG, 0x14, 0 },
263 * Atheros AR8161/AR8162/E2200 Ethernet controllers have a bug that
264 * MSI interrupt does not assert if PCIM_CMD_INTxDIS bit of the
265 * command register is set.
267 { 0x10911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 },
268 { 0xE0911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 },
269 { 0x10901969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 },
272 * Broadcom BCM5714(S)/BCM5715(S)/BCM5780(S) Ethernet MACs don't
273 * issue MSI interrupts with PCIM_CMD_INTxDIS set either.
275 { 0x166814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714 */
276 { 0x166914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714S */
277 { 0x166a14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780 */
278 { 0x166b14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780S */
279 { 0x167814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715 */
280 { 0x167914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715S */
285 /* map register information */
286 #define PCI_MAPMEM 0x01 /* memory map */
287 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */
288 #define PCI_MAPPORT 0x04 /* port map */
290 struct devlist pci_devq;
291 uint32_t pci_generation;
292 uint32_t pci_numdevs = 0;
293 static int pcie_chipset, pcix_chipset;
296 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters");
298 static int pci_enable_io_modes = 1;
299 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes);
300 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW,
301 &pci_enable_io_modes, 1,
302 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\
303 enable these bits correctly. We'd like to do this all the time, but there\n\
304 are some peripherals that this causes problems with.");
306 static int pci_do_realloc_bars = 0;
307 TUNABLE_INT("hw.pci.realloc_bars", &pci_do_realloc_bars);
308 SYSCTL_INT(_hw_pci, OID_AUTO, realloc_bars, CTLFLAG_RW,
309 &pci_do_realloc_bars, 0,
310 "Attempt to allocate a new range for any BARs whose original firmware-assigned ranges fail to allocate during the initial device scan.");
312 static int pci_do_power_nodriver = 0;
313 TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver);
314 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW,
315 &pci_do_power_nodriver, 0,
316 "Place a function into D3 state when no driver attaches to it. 0 means\n\
317 disable. 1 means conservatively place devices into D3 state. 2 means\n\
318 agressively place devices into D3 state. 3 means put absolutely everything\n\
321 int pci_do_power_resume = 1;
322 TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume);
323 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW,
324 &pci_do_power_resume, 1,
325 "Transition from D3 -> D0 on resume.");
327 int pci_do_power_suspend = 1;
328 TUNABLE_INT("hw.pci.do_power_suspend", &pci_do_power_suspend);
329 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_suspend, CTLFLAG_RW,
330 &pci_do_power_suspend, 1,
331 "Transition from D0 -> D3 on suspend.");
333 static int pci_do_msi = 1;
334 TUNABLE_INT("hw.pci.enable_msi", &pci_do_msi);
335 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RW, &pci_do_msi, 1,
336 "Enable support for MSI interrupts");
338 static int pci_do_msix = 1;
339 TUNABLE_INT("hw.pci.enable_msix", &pci_do_msix);
340 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RW, &pci_do_msix, 1,
341 "Enable support for MSI-X interrupts");
343 static int pci_honor_msi_blacklist = 1;
344 TUNABLE_INT("hw.pci.honor_msi_blacklist", &pci_honor_msi_blacklist);
345 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RD,
346 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI/MSI-X");
348 #if defined(__i386__) || defined(__amd64__)
349 static int pci_usb_takeover = 1;
351 static int pci_usb_takeover = 0;
353 TUNABLE_INT("hw.pci.usb_early_takeover", &pci_usb_takeover);
354 SYSCTL_INT(_hw_pci, OID_AUTO, usb_early_takeover, CTLFLAG_RDTUN,
355 &pci_usb_takeover, 1, "Enable early takeover of USB controllers.\n\
356 Disable this if you depend on BIOS emulation of USB devices, that is\n\
357 you use USB devices (like keyboard or mouse) but do not load USB drivers");
359 static int pci_clear_bars;
360 TUNABLE_INT("hw.pci.clear_bars", &pci_clear_bars);
361 SYSCTL_INT(_hw_pci, OID_AUTO, clear_bars, CTLFLAG_RDTUN, &pci_clear_bars, 0,
362 "Ignore firmware-assigned resources for BARs.");
364 static int pci_enable_ari = 1;
365 TUNABLE_INT("hw.pci.enable_ari", &pci_enable_ari);
366 SYSCTL_INT(_hw_pci, OID_AUTO, enable_ari, CTLFLAG_RDTUN, &pci_enable_ari,
367 0, "Enable support for PCIe Alternative RID Interpretation");
370 pci_has_quirk(uint32_t devid, int quirk)
372 const struct pci_quirk *q;
374 for (q = &pci_quirks[0]; q->devid; q++) {
375 if (q->devid == devid && q->type == quirk)
381 /* Find a device_t by bus/slot/function in domain 0 */
384 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func)
387 return (pci_find_dbsf(0, bus, slot, func));
390 /* Find a device_t by domain/bus/slot/function */
393 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func)
395 struct pci_devinfo *dinfo;
397 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
398 if ((dinfo->cfg.domain == domain) &&
399 (dinfo->cfg.bus == bus) &&
400 (dinfo->cfg.slot == slot) &&
401 (dinfo->cfg.func == func)) {
402 return (dinfo->cfg.dev);
409 /* Find a device_t by vendor/device ID */
412 pci_find_device(uint16_t vendor, uint16_t device)
414 struct pci_devinfo *dinfo;
416 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
417 if ((dinfo->cfg.vendor == vendor) &&
418 (dinfo->cfg.device == device)) {
419 return (dinfo->cfg.dev);
427 pci_find_class(uint8_t class, uint8_t subclass)
429 struct pci_devinfo *dinfo;
431 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
432 if (dinfo->cfg.baseclass == class &&
433 dinfo->cfg.subclass == subclass) {
434 return (dinfo->cfg.dev);
442 pci_printf(pcicfgregs *cfg, const char *fmt, ...)
447 retval = printf("pci%d:%d:%d:%d: ", cfg->domain, cfg->bus, cfg->slot,
450 retval += vprintf(fmt, ap);
455 /* return base address of memory or port map */
458 pci_mapbase(uint64_t mapreg)
461 if (PCI_BAR_MEM(mapreg))
462 return (mapreg & PCIM_BAR_MEM_BASE);
464 return (mapreg & PCIM_BAR_IO_BASE);
467 /* return map type of memory or port map */
470 pci_maptype(uint64_t mapreg)
473 if (PCI_BAR_IO(mapreg))
475 if (mapreg & PCIM_BAR_MEM_PREFETCH)
476 return ("Prefetchable Memory");
480 /* return log2 of map size decoded for memory or port map */
483 pci_mapsize(uint64_t testval)
487 testval = pci_mapbase(testval);
490 while ((testval & 1) == 0)
499 /* return base address of device ROM */
502 pci_rombase(uint64_t mapreg)
505 return (mapreg & PCIM_BIOS_ADDR_MASK);
508 /* return log2 of map size decided for device ROM */
511 pci_romsize(uint64_t testval)
515 testval = pci_rombase(testval);
518 while ((testval & 1) == 0)
527 /* return log2 of address range supported by map register */
530 pci_maprange(uint64_t mapreg)
534 if (PCI_BAR_IO(mapreg))
537 switch (mapreg & PCIM_BAR_MEM_TYPE) {
538 case PCIM_BAR_MEM_32:
541 case PCIM_BAR_MEM_1MB:
544 case PCIM_BAR_MEM_64:
551 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
554 pci_fixancient(pcicfgregs *cfg)
556 if ((cfg->hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL)
559 /* PCI to PCI bridges use header type 1 */
560 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
561 cfg->hdrtype = PCIM_HDRTYPE_BRIDGE;
564 /* extract header type specific config data */
567 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
569 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
570 switch (cfg->hdrtype & PCIM_HDRTYPE) {
571 case PCIM_HDRTYPE_NORMAL:
572 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
573 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
574 cfg->nummaps = PCI_MAXMAPS_0;
576 case PCIM_HDRTYPE_BRIDGE:
577 cfg->nummaps = PCI_MAXMAPS_1;
579 case PCIM_HDRTYPE_CARDBUS:
580 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
581 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
582 cfg->nummaps = PCI_MAXMAPS_2;
588 /* read configuration header into pcicfgregs structure */
590 pci_read_device(device_t pcib, int d, int b, int s, int f, size_t size)
592 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
593 pcicfgregs *cfg = NULL;
594 struct pci_devinfo *devlist_entry;
595 struct devlist *devlist_head;
597 devlist_head = &pci_devq;
599 devlist_entry = NULL;
601 if (REG(PCIR_DEVVENDOR, 4) != 0xfffffffful) {
602 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
603 if (devlist_entry == NULL)
606 cfg = &devlist_entry->cfg;
612 cfg->vendor = REG(PCIR_VENDOR, 2);
613 cfg->device = REG(PCIR_DEVICE, 2);
614 cfg->cmdreg = REG(PCIR_COMMAND, 2);
615 cfg->statreg = REG(PCIR_STATUS, 2);
616 cfg->baseclass = REG(PCIR_CLASS, 1);
617 cfg->subclass = REG(PCIR_SUBCLASS, 1);
618 cfg->progif = REG(PCIR_PROGIF, 1);
619 cfg->revid = REG(PCIR_REVID, 1);
620 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
621 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
622 cfg->lattimer = REG(PCIR_LATTIMER, 1);
623 cfg->intpin = REG(PCIR_INTPIN, 1);
624 cfg->intline = REG(PCIR_INTLINE, 1);
626 cfg->mingnt = REG(PCIR_MINGNT, 1);
627 cfg->maxlat = REG(PCIR_MAXLAT, 1);
629 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
630 cfg->hdrtype &= ~PCIM_MFDEV;
631 STAILQ_INIT(&cfg->maps);
634 pci_hdrtypedata(pcib, b, s, f, cfg);
636 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT)
637 pci_read_cap(pcib, cfg);
639 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
641 devlist_entry->conf.pc_sel.pc_domain = cfg->domain;
642 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
643 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
644 devlist_entry->conf.pc_sel.pc_func = cfg->func;
645 devlist_entry->conf.pc_hdr = cfg->hdrtype;
647 devlist_entry->conf.pc_subvendor = cfg->subvendor;
648 devlist_entry->conf.pc_subdevice = cfg->subdevice;
649 devlist_entry->conf.pc_vendor = cfg->vendor;
650 devlist_entry->conf.pc_device = cfg->device;
652 devlist_entry->conf.pc_class = cfg->baseclass;
653 devlist_entry->conf.pc_subclass = cfg->subclass;
654 devlist_entry->conf.pc_progif = cfg->progif;
655 devlist_entry->conf.pc_revid = cfg->revid;
660 return (devlist_entry);
665 pci_read_cap(device_t pcib, pcicfgregs *cfg)
667 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
668 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w)
669 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
673 int ptr, nextptr, ptrptr;
675 switch (cfg->hdrtype & PCIM_HDRTYPE) {
676 case PCIM_HDRTYPE_NORMAL:
677 case PCIM_HDRTYPE_BRIDGE:
678 ptrptr = PCIR_CAP_PTR;
680 case PCIM_HDRTYPE_CARDBUS:
681 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */
684 return; /* no extended capabilities support */
686 nextptr = REG(ptrptr, 1); /* sanity check? */
689 * Read capability entries.
691 while (nextptr != 0) {
694 printf("illegal PCI extended capability offset %d\n",
698 /* Find the next entry */
700 nextptr = REG(ptr + PCICAP_NEXTPTR, 1);
702 /* Process this entry */
703 switch (REG(ptr + PCICAP_ID, 1)) {
704 case PCIY_PMG: /* PCI power management */
705 if (cfg->pp.pp_cap == 0) {
706 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
707 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS;
708 cfg->pp.pp_bse = ptr + PCIR_POWER_BSE;
709 if ((nextptr - ptr) > PCIR_POWER_DATA)
710 cfg->pp.pp_data = ptr + PCIR_POWER_DATA;
713 case PCIY_HT: /* HyperTransport */
714 /* Determine HT-specific capability type. */
715 val = REG(ptr + PCIR_HT_COMMAND, 2);
717 if ((val & 0xe000) == PCIM_HTCAP_SLAVE)
718 cfg->ht.ht_slave = ptr;
720 #if defined(__i386__) || defined(__amd64__) || defined(__powerpc__)
721 switch (val & PCIM_HTCMD_CAP_MASK) {
722 case PCIM_HTCAP_MSI_MAPPING:
723 if (!(val & PCIM_HTCMD_MSI_FIXED)) {
724 /* Sanity check the mapping window. */
725 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI,
728 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO,
730 if (addr != MSI_INTEL_ADDR_BASE)
732 "HT device at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n",
733 cfg->domain, cfg->bus,
734 cfg->slot, cfg->func,
737 addr = MSI_INTEL_ADDR_BASE;
739 cfg->ht.ht_msimap = ptr;
740 cfg->ht.ht_msictrl = val;
741 cfg->ht.ht_msiaddr = addr;
746 case PCIY_MSI: /* PCI MSI */
747 cfg->msi.msi_location = ptr;
748 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);
749 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl &
750 PCIM_MSICTRL_MMC_MASK)>>1);
752 case PCIY_MSIX: /* PCI MSI-X */
753 cfg->msix.msix_location = ptr;
754 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2);
755 cfg->msix.msix_msgnum = (cfg->msix.msix_ctrl &
756 PCIM_MSIXCTRL_TABLE_SIZE) + 1;
757 val = REG(ptr + PCIR_MSIX_TABLE, 4);
758 cfg->msix.msix_table_bar = PCIR_BAR(val &
760 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK;
761 val = REG(ptr + PCIR_MSIX_PBA, 4);
762 cfg->msix.msix_pba_bar = PCIR_BAR(val &
764 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK;
766 case PCIY_VPD: /* PCI Vital Product Data */
767 cfg->vpd.vpd_reg = ptr;
770 /* Should always be true. */
771 if ((cfg->hdrtype & PCIM_HDRTYPE) ==
772 PCIM_HDRTYPE_BRIDGE) {
773 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4);
774 cfg->subvendor = val & 0xffff;
775 cfg->subdevice = val >> 16;
778 case PCIY_PCIX: /* PCI-X */
780 * Assume we have a PCI-X chipset if we have
781 * at least one PCI-PCI bridge with a PCI-X
782 * capability. Note that some systems with
783 * PCI-express or HT chipsets might match on
784 * this check as well.
786 if ((cfg->hdrtype & PCIM_HDRTYPE) ==
789 cfg->pcix.pcix_location = ptr;
791 case PCIY_EXPRESS: /* PCI-express */
793 * Assume we have a PCI-express chipset if we have
794 * at least one PCI-express device.
797 cfg->pcie.pcie_location = ptr;
798 val = REG(ptr + PCIER_FLAGS, 2);
799 cfg->pcie.pcie_type = val & PCIEM_FLAGS_TYPE;
806 #if defined(__powerpc__)
808 * Enable the MSI mapping window for all HyperTransport
809 * slaves. PCI-PCI bridges have their windows enabled via
812 if (cfg->ht.ht_slave != 0 && cfg->ht.ht_msimap != 0 &&
813 !(cfg->ht.ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) {
815 "Enabling MSI window for HyperTransport slave at pci%d:%d:%d:%d\n",
816 cfg->domain, cfg->bus, cfg->slot, cfg->func);
817 cfg->ht.ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
818 WREG(cfg->ht.ht_msimap + PCIR_HT_COMMAND, cfg->ht.ht_msictrl,
822 /* REG and WREG use carry through to next functions */
826 * PCI Vital Product Data
829 #define PCI_VPD_TIMEOUT 1000000
832 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data)
834 int count = PCI_VPD_TIMEOUT;
836 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
838 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2);
840 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) {
843 DELAY(1); /* limit looping */
845 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4));
852 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data)
854 int count = PCI_VPD_TIMEOUT;
856 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
858 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4);
859 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2);
860 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {
863 DELAY(1); /* limit looping */
870 #undef PCI_VPD_TIMEOUT
872 struct vpd_readstate {
882 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data)
887 if (vrs->bytesinval == 0) {
888 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®))
890 vrs->val = le32toh(reg);
892 byte = vrs->val & 0xff;
895 vrs->val = vrs->val >> 8;
896 byte = vrs->val & 0xff;
906 pci_read_vpd(device_t pcib, pcicfgregs *cfg)
908 struct vpd_readstate vrs;
913 int alloc, off; /* alloc/off for RO/W arrays */
919 /* init vpd reader */
927 name = remain = i = 0; /* shut up stupid gcc */
928 alloc = off = 0; /* shut up stupid gcc */
929 dflen = 0; /* shut up stupid gcc */
932 if (vpd_nextbyte(&vrs, &byte)) {
937 printf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \
938 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val,
939 vrs.off, vrs.bytesinval, byte, state, remain, name, i);
942 case 0: /* item name */
944 if (vpd_nextbyte(&vrs, &byte2)) {
949 if (vpd_nextbyte(&vrs, &byte2)) {
953 remain |= byte2 << 8;
954 if (remain > (0x7f*4 - vrs.off)) {
957 "invalid VPD data, remain %#x\n",
963 name = (byte >> 3) & 0xf;
966 case 0x2: /* String */
967 cfg->vpd.vpd_ident = malloc(remain + 1,
975 case 0x10: /* VPD-R */
978 cfg->vpd.vpd_ros = malloc(alloc *
979 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF,
983 case 0x11: /* VPD-W */
986 cfg->vpd.vpd_w = malloc(alloc *
987 sizeof(*cfg->vpd.vpd_w), M_DEVBUF,
991 default: /* Invalid data, abort */
997 case 1: /* Identifier String */
998 cfg->vpd.vpd_ident[i++] = byte;
1001 cfg->vpd.vpd_ident[i] = '\0';
1006 case 2: /* VPD-R Keyword Header */
1008 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros,
1009 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros),
1010 M_DEVBUF, M_WAITOK | M_ZERO);
1012 cfg->vpd.vpd_ros[off].keyword[0] = byte;
1013 if (vpd_nextbyte(&vrs, &byte2)) {
1017 cfg->vpd.vpd_ros[off].keyword[1] = byte2;
1018 if (vpd_nextbyte(&vrs, &byte2)) {
1022 cfg->vpd.vpd_ros[off].len = dflen = byte2;
1024 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV",
1027 * if this happens, we can't trust the rest
1030 pci_printf(cfg, "bad keyword length: %d\n",
1035 } else if (dflen == 0) {
1036 cfg->vpd.vpd_ros[off].value = malloc(1 *
1037 sizeof(*cfg->vpd.vpd_ros[off].value),
1038 M_DEVBUF, M_WAITOK);
1039 cfg->vpd.vpd_ros[off].value[0] = '\x00';
1041 cfg->vpd.vpd_ros[off].value = malloc(
1043 sizeof(*cfg->vpd.vpd_ros[off].value),
1044 M_DEVBUF, M_WAITOK);
1047 /* keep in sync w/ state 3's transistions */
1048 if (dflen == 0 && remain == 0)
1050 else if (dflen == 0)
1056 case 3: /* VPD-R Keyword Value */
1057 cfg->vpd.vpd_ros[off].value[i++] = byte;
1058 if (strncmp(cfg->vpd.vpd_ros[off].keyword,
1059 "RV", 2) == 0 && cksumvalid == -1) {
1065 "bad VPD cksum, remain %hhu\n",
1074 /* keep in sync w/ state 2's transistions */
1076 cfg->vpd.vpd_ros[off++].value[i++] = '\0';
1077 if (dflen == 0 && remain == 0) {
1078 cfg->vpd.vpd_rocnt = off;
1079 cfg->vpd.vpd_ros = reallocf(cfg->vpd.vpd_ros,
1080 off * sizeof(*cfg->vpd.vpd_ros),
1081 M_DEVBUF, M_WAITOK | M_ZERO);
1083 } else if (dflen == 0)
1093 case 5: /* VPD-W Keyword Header */
1095 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w,
1096 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w),
1097 M_DEVBUF, M_WAITOK | M_ZERO);
1099 cfg->vpd.vpd_w[off].keyword[0] = byte;
1100 if (vpd_nextbyte(&vrs, &byte2)) {
1104 cfg->vpd.vpd_w[off].keyword[1] = byte2;
1105 if (vpd_nextbyte(&vrs, &byte2)) {
1109 cfg->vpd.vpd_w[off].len = dflen = byte2;
1110 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval;
1111 cfg->vpd.vpd_w[off].value = malloc((dflen + 1) *
1112 sizeof(*cfg->vpd.vpd_w[off].value),
1113 M_DEVBUF, M_WAITOK);
1116 /* keep in sync w/ state 6's transistions */
1117 if (dflen == 0 && remain == 0)
1119 else if (dflen == 0)
1125 case 6: /* VPD-W Keyword Value */
1126 cfg->vpd.vpd_w[off].value[i++] = byte;
1129 /* keep in sync w/ state 5's transistions */
1131 cfg->vpd.vpd_w[off++].value[i++] = '\0';
1132 if (dflen == 0 && remain == 0) {
1133 cfg->vpd.vpd_wcnt = off;
1134 cfg->vpd.vpd_w = reallocf(cfg->vpd.vpd_w,
1135 off * sizeof(*cfg->vpd.vpd_w),
1136 M_DEVBUF, M_WAITOK | M_ZERO);
1138 } else if (dflen == 0)
1143 pci_printf(cfg, "invalid state: %d\n", state);
1149 if (cksumvalid == 0 || state < -1) {
1150 /* read-only data bad, clean up */
1151 if (cfg->vpd.vpd_ros != NULL) {
1152 for (off = 0; cfg->vpd.vpd_ros[off].value; off++)
1153 free(cfg->vpd.vpd_ros[off].value, M_DEVBUF);
1154 free(cfg->vpd.vpd_ros, M_DEVBUF);
1155 cfg->vpd.vpd_ros = NULL;
1159 /* I/O error, clean up */
1160 pci_printf(cfg, "failed to read VPD data.\n");
1161 if (cfg->vpd.vpd_ident != NULL) {
1162 free(cfg->vpd.vpd_ident, M_DEVBUF);
1163 cfg->vpd.vpd_ident = NULL;
1165 if (cfg->vpd.vpd_w != NULL) {
1166 for (off = 0; cfg->vpd.vpd_w[off].value; off++)
1167 free(cfg->vpd.vpd_w[off].value, M_DEVBUF);
1168 free(cfg->vpd.vpd_w, M_DEVBUF);
1169 cfg->vpd.vpd_w = NULL;
1172 cfg->vpd.vpd_cached = 1;
1178 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr)
1180 struct pci_devinfo *dinfo = device_get_ivars(child);
1181 pcicfgregs *cfg = &dinfo->cfg;
1183 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1184 pci_read_vpd(device_get_parent(dev), cfg);
1186 *identptr = cfg->vpd.vpd_ident;
1188 if (*identptr == NULL)
1195 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw,
1198 struct pci_devinfo *dinfo = device_get_ivars(child);
1199 pcicfgregs *cfg = &dinfo->cfg;
1202 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1203 pci_read_vpd(device_get_parent(dev), cfg);
1205 for (i = 0; i < cfg->vpd.vpd_rocnt; i++)
1206 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword,
1207 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) {
1208 *vptr = cfg->vpd.vpd_ros[i].value;
1217 pci_fetch_vpd_list(device_t dev)
1219 struct pci_devinfo *dinfo = device_get_ivars(dev);
1220 pcicfgregs *cfg = &dinfo->cfg;
1222 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1223 pci_read_vpd(device_get_parent(device_get_parent(dev)), cfg);
1228 * Find the requested HyperTransport capability and return the offset
1229 * in configuration space via the pointer provided. The function
1230 * returns 0 on success and an error code otherwise.
1233 pci_find_htcap_method(device_t dev, device_t child, int capability, int *capreg)
1238 error = pci_find_cap(child, PCIY_HT, &ptr);
1243 * Traverse the capabilities list checking each HT capability
1244 * to see if it matches the requested HT capability.
1247 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2);
1248 if (capability == PCIM_HTCAP_SLAVE ||
1249 capability == PCIM_HTCAP_HOST)
1252 val &= PCIM_HTCMD_CAP_MASK;
1253 if (val == capability) {
1259 /* Skip to the next HT capability. */
1261 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
1262 if (pci_read_config(child, ptr + PCICAP_ID, 1) ==
1271 * Find the requested capability and return the offset in
1272 * configuration space via the pointer provided. The function returns
1273 * 0 on success and an error code otherwise.
1276 pci_find_cap_method(device_t dev, device_t child, int capability,
1279 struct pci_devinfo *dinfo = device_get_ivars(child);
1280 pcicfgregs *cfg = &dinfo->cfg;
1285 * Check the CAP_LIST bit of the PCI status register first.
1287 status = pci_read_config(child, PCIR_STATUS, 2);
1288 if (!(status & PCIM_STATUS_CAPPRESENT))
1292 * Determine the start pointer of the capabilities list.
1294 switch (cfg->hdrtype & PCIM_HDRTYPE) {
1295 case PCIM_HDRTYPE_NORMAL:
1296 case PCIM_HDRTYPE_BRIDGE:
1299 case PCIM_HDRTYPE_CARDBUS:
1300 ptr = PCIR_CAP_PTR_2;
1304 return (ENXIO); /* no extended capabilities support */
1306 ptr = pci_read_config(child, ptr, 1);
1309 * Traverse the capabilities list.
1312 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) {
1317 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
1324 * Find the requested extended capability and return the offset in
1325 * configuration space via the pointer provided. The function returns
1326 * 0 on success and an error code otherwise.
1329 pci_find_extcap_method(device_t dev, device_t child, int capability,
1332 struct pci_devinfo *dinfo = device_get_ivars(child);
1333 pcicfgregs *cfg = &dinfo->cfg;
1337 /* Only supported for PCI-express devices. */
1338 if (cfg->pcie.pcie_location == 0)
1342 ecap = pci_read_config(child, ptr, 4);
1343 if (ecap == 0xffffffff || ecap == 0)
1346 if (PCI_EXTCAP_ID(ecap) == capability) {
1351 ptr = PCI_EXTCAP_NEXTPTR(ecap);
1354 ecap = pci_read_config(child, ptr, 4);
1361 * Support for MSI-X message interrupts.
1364 pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data)
1366 struct pci_devinfo *dinfo = device_get_ivars(dev);
1367 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1370 KASSERT(msix->msix_table_len > index, ("bogus index"));
1371 offset = msix->msix_table_offset + index * 16;
1372 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff);
1373 bus_write_4(msix->msix_table_res, offset + 4, address >> 32);
1374 bus_write_4(msix->msix_table_res, offset + 8, data);
1376 /* Enable MSI -> HT mapping. */
1377 pci_ht_map_msi(dev, address);
1381 pci_mask_msix(device_t dev, u_int index)
1383 struct pci_devinfo *dinfo = device_get_ivars(dev);
1384 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1385 uint32_t offset, val;
1387 KASSERT(msix->msix_msgnum > index, ("bogus index"));
1388 offset = msix->msix_table_offset + index * 16 + 12;
1389 val = bus_read_4(msix->msix_table_res, offset);
1390 if (!(val & PCIM_MSIX_VCTRL_MASK)) {
1391 val |= PCIM_MSIX_VCTRL_MASK;
1392 bus_write_4(msix->msix_table_res, offset, val);
1397 pci_unmask_msix(device_t dev, u_int index)
1399 struct pci_devinfo *dinfo = device_get_ivars(dev);
1400 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1401 uint32_t offset, val;
1403 KASSERT(msix->msix_table_len > index, ("bogus index"));
1404 offset = msix->msix_table_offset + index * 16 + 12;
1405 val = bus_read_4(msix->msix_table_res, offset);
1406 if (val & PCIM_MSIX_VCTRL_MASK) {
1407 val &= ~PCIM_MSIX_VCTRL_MASK;
1408 bus_write_4(msix->msix_table_res, offset, val);
1413 pci_pending_msix(device_t dev, u_int index)
1415 struct pci_devinfo *dinfo = device_get_ivars(dev);
1416 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1417 uint32_t offset, bit;
1419 KASSERT(msix->msix_table_len > index, ("bogus index"));
1420 offset = msix->msix_pba_offset + (index / 32) * 4;
1421 bit = 1 << index % 32;
1422 return (bus_read_4(msix->msix_pba_res, offset) & bit);
1426 * Restore MSI-X registers and table during resume. If MSI-X is
1427 * enabled then walk the virtual table to restore the actual MSI-X
1431 pci_resume_msix(device_t dev)
1433 struct pci_devinfo *dinfo = device_get_ivars(dev);
1434 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1435 struct msix_table_entry *mte;
1436 struct msix_vector *mv;
1439 if (msix->msix_alloc > 0) {
1440 /* First, mask all vectors. */
1441 for (i = 0; i < msix->msix_msgnum; i++)
1442 pci_mask_msix(dev, i);
1444 /* Second, program any messages with at least one handler. */
1445 for (i = 0; i < msix->msix_table_len; i++) {
1446 mte = &msix->msix_table[i];
1447 if (mte->mte_vector == 0 || mte->mte_handlers == 0)
1449 mv = &msix->msix_vectors[mte->mte_vector - 1];
1450 pci_enable_msix(dev, i, mv->mv_address, mv->mv_data);
1451 pci_unmask_msix(dev, i);
1454 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1455 msix->msix_ctrl, 2);
1459 * Attempt to allocate *count MSI-X messages. The actual number allocated is
1460 * returned in *count. After this function returns, each message will be
1461 * available to the driver as SYS_RES_IRQ resources starting at rid 1.
1464 pci_alloc_msix_method(device_t dev, device_t child, int *count)
1466 struct pci_devinfo *dinfo = device_get_ivars(child);
1467 pcicfgregs *cfg = &dinfo->cfg;
1468 struct resource_list_entry *rle;
1469 int actual, error, i, irq, max;
1471 /* Don't let count == 0 get us into trouble. */
1475 /* If rid 0 is allocated, then fail. */
1476 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1477 if (rle != NULL && rle->res != NULL)
1480 /* Already have allocated messages? */
1481 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1484 /* If MSI-X is blacklisted for this system, fail. */
1485 if (pci_msix_blacklisted())
1488 /* MSI-X capability present? */
1489 if (cfg->msix.msix_location == 0 || !pci_do_msix)
1492 /* Make sure the appropriate BARs are mapped. */
1493 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1494 cfg->msix.msix_table_bar);
1495 if (rle == NULL || rle->res == NULL ||
1496 !(rman_get_flags(rle->res) & RF_ACTIVE))
1498 cfg->msix.msix_table_res = rle->res;
1499 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) {
1500 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1501 cfg->msix.msix_pba_bar);
1502 if (rle == NULL || rle->res == NULL ||
1503 !(rman_get_flags(rle->res) & RF_ACTIVE))
1506 cfg->msix.msix_pba_res = rle->res;
1509 device_printf(child,
1510 "attempting to allocate %d MSI-X vectors (%d supported)\n",
1511 *count, cfg->msix.msix_msgnum);
1512 max = min(*count, cfg->msix.msix_msgnum);
1513 for (i = 0; i < max; i++) {
1514 /* Allocate a message. */
1515 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq);
1521 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1527 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1);
1529 device_printf(child, "using IRQ %lu for MSI-X\n",
1535 * Be fancy and try to print contiguous runs of
1536 * IRQ values as ranges. 'irq' is the previous IRQ.
1537 * 'run' is true if we are in a range.
1539 device_printf(child, "using IRQs %lu", rle->start);
1542 for (i = 1; i < actual; i++) {
1543 rle = resource_list_find(&dinfo->resources,
1544 SYS_RES_IRQ, i + 1);
1546 /* Still in a run? */
1547 if (rle->start == irq + 1) {
1553 /* Finish previous range. */
1559 /* Start new range. */
1560 printf(",%lu", rle->start);
1564 /* Unfinished range? */
1567 printf(" for MSI-X\n");
1571 /* Mask all vectors. */
1572 for (i = 0; i < cfg->msix.msix_msgnum; i++)
1573 pci_mask_msix(child, i);
1575 /* Allocate and initialize vector data and virtual table. */
1576 cfg->msix.msix_vectors = malloc(sizeof(struct msix_vector) * actual,
1577 M_DEVBUF, M_WAITOK | M_ZERO);
1578 cfg->msix.msix_table = malloc(sizeof(struct msix_table_entry) * actual,
1579 M_DEVBUF, M_WAITOK | M_ZERO);
1580 for (i = 0; i < actual; i++) {
1581 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1582 cfg->msix.msix_vectors[i].mv_irq = rle->start;
1583 cfg->msix.msix_table[i].mte_vector = i + 1;
1586 /* Update control register to enable MSI-X. */
1587 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
1588 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL,
1589 cfg->msix.msix_ctrl, 2);
1591 /* Update counts of alloc'd messages. */
1592 cfg->msix.msix_alloc = actual;
1593 cfg->msix.msix_table_len = actual;
1599 * By default, pci_alloc_msix() will assign the allocated IRQ
1600 * resources consecutively to the first N messages in the MSI-X table.
1601 * However, device drivers may want to use different layouts if they
1602 * either receive fewer messages than they asked for, or they wish to
1603 * populate the MSI-X table sparsely. This method allows the driver
1604 * to specify what layout it wants. It must be called after a
1605 * successful pci_alloc_msix() but before any of the associated
1606 * SYS_RES_IRQ resources are allocated via bus_alloc_resource().
1608 * The 'vectors' array contains 'count' message vectors. The array
1609 * maps directly to the MSI-X table in that index 0 in the array
1610 * specifies the vector for the first message in the MSI-X table, etc.
1611 * The vector value in each array index can either be 0 to indicate
1612 * that no vector should be assigned to a message slot, or it can be a
1613 * number from 1 to N (where N is the count returned from a
1614 * succcessful call to pci_alloc_msix()) to indicate which message
1615 * vector (IRQ) to be used for the corresponding message.
1617 * On successful return, each message with a non-zero vector will have
1618 * an associated SYS_RES_IRQ whose rid is equal to the array index +
1619 * 1. Additionally, if any of the IRQs allocated via the previous
1620 * call to pci_alloc_msix() are not used in the mapping, those IRQs
1621 * will be freed back to the system automatically.
1623 * For example, suppose a driver has a MSI-X table with 6 messages and
1624 * asks for 6 messages, but pci_alloc_msix() only returns a count of
1625 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and
1626 * C. After the call to pci_alloc_msix(), the device will be setup to
1627 * have an MSI-X table of ABC--- (where - means no vector assigned).
1628 * If the driver then passes a vector array of { 1, 0, 1, 2, 0, 2 },
1629 * then the MSI-X table will look like A-AB-B, and the 'C' vector will
1630 * be freed back to the system. This device will also have valid
1631 * SYS_RES_IRQ rids of 1, 3, 4, and 6.
1633 * In any case, the SYS_RES_IRQ rid X will always map to the message
1634 * at MSI-X table index X - 1 and will only be valid if a vector is
1635 * assigned to that table entry.
1638 pci_remap_msix_method(device_t dev, device_t child, int count,
1639 const u_int *vectors)
1641 struct pci_devinfo *dinfo = device_get_ivars(child);
1642 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1643 struct resource_list_entry *rle;
1644 int i, irq, j, *used;
1647 * Have to have at least one message in the table but the
1648 * table can't be bigger than the actual MSI-X table in the
1651 if (count == 0 || count > msix->msix_msgnum)
1654 /* Sanity check the vectors. */
1655 for (i = 0; i < count; i++)
1656 if (vectors[i] > msix->msix_alloc)
1660 * Make sure there aren't any holes in the vectors to be used.
1661 * It's a big pain to support it, and it doesn't really make
1662 * sense anyway. Also, at least one vector must be used.
1664 used = malloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK |
1666 for (i = 0; i < count; i++)
1667 if (vectors[i] != 0)
1668 used[vectors[i] - 1] = 1;
1669 for (i = 0; i < msix->msix_alloc - 1; i++)
1670 if (used[i] == 0 && used[i + 1] == 1) {
1671 free(used, M_DEVBUF);
1675 free(used, M_DEVBUF);
1679 /* Make sure none of the resources are allocated. */
1680 for (i = 0; i < msix->msix_table_len; i++) {
1681 if (msix->msix_table[i].mte_vector == 0)
1683 if (msix->msix_table[i].mte_handlers > 0)
1685 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1686 KASSERT(rle != NULL, ("missing resource"));
1687 if (rle->res != NULL)
1691 /* Free the existing resource list entries. */
1692 for (i = 0; i < msix->msix_table_len; i++) {
1693 if (msix->msix_table[i].mte_vector == 0)
1695 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1699 * Build the new virtual table keeping track of which vectors are
1702 free(msix->msix_table, M_DEVBUF);
1703 msix->msix_table = malloc(sizeof(struct msix_table_entry) * count,
1704 M_DEVBUF, M_WAITOK | M_ZERO);
1705 for (i = 0; i < count; i++)
1706 msix->msix_table[i].mte_vector = vectors[i];
1707 msix->msix_table_len = count;
1709 /* Free any unused IRQs and resize the vectors array if necessary. */
1710 j = msix->msix_alloc - 1;
1712 struct msix_vector *vec;
1714 while (used[j] == 0) {
1715 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1716 msix->msix_vectors[j].mv_irq);
1719 vec = malloc(sizeof(struct msix_vector) * (j + 1), M_DEVBUF,
1721 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) *
1723 free(msix->msix_vectors, M_DEVBUF);
1724 msix->msix_vectors = vec;
1725 msix->msix_alloc = j + 1;
1727 free(used, M_DEVBUF);
1729 /* Map the IRQs onto the rids. */
1730 for (i = 0; i < count; i++) {
1731 if (vectors[i] == 0)
1733 irq = msix->msix_vectors[vectors[i]].mv_irq;
1734 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1739 device_printf(child, "Remapped MSI-X IRQs as: ");
1740 for (i = 0; i < count; i++) {
1743 if (vectors[i] == 0)
1747 msix->msix_vectors[vectors[i]].mv_irq);
1756 pci_release_msix(device_t dev, device_t child)
1758 struct pci_devinfo *dinfo = device_get_ivars(child);
1759 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1760 struct resource_list_entry *rle;
1763 /* Do we have any messages to release? */
1764 if (msix->msix_alloc == 0)
1767 /* Make sure none of the resources are allocated. */
1768 for (i = 0; i < msix->msix_table_len; i++) {
1769 if (msix->msix_table[i].mte_vector == 0)
1771 if (msix->msix_table[i].mte_handlers > 0)
1773 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1774 KASSERT(rle != NULL, ("missing resource"));
1775 if (rle->res != NULL)
1779 /* Update control register to disable MSI-X. */
1780 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
1781 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL,
1782 msix->msix_ctrl, 2);
1784 /* Free the resource list entries. */
1785 for (i = 0; i < msix->msix_table_len; i++) {
1786 if (msix->msix_table[i].mte_vector == 0)
1788 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1790 free(msix->msix_table, M_DEVBUF);
1791 msix->msix_table_len = 0;
1793 /* Release the IRQs. */
1794 for (i = 0; i < msix->msix_alloc; i++)
1795 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1796 msix->msix_vectors[i].mv_irq);
1797 free(msix->msix_vectors, M_DEVBUF);
1798 msix->msix_alloc = 0;
1803 * Return the max supported MSI-X messages this device supports.
1804 * Basically, assuming the MD code can alloc messages, this function
1805 * should return the maximum value that pci_alloc_msix() can return.
1806 * Thus, it is subject to the tunables, etc.
1809 pci_msix_count_method(device_t dev, device_t child)
1811 struct pci_devinfo *dinfo = device_get_ivars(child);
1812 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1814 if (pci_do_msix && msix->msix_location != 0)
1815 return (msix->msix_msgnum);
1820 * HyperTransport MSI mapping control
1823 pci_ht_map_msi(device_t dev, uint64_t addr)
1825 struct pci_devinfo *dinfo = device_get_ivars(dev);
1826 struct pcicfg_ht *ht = &dinfo->cfg.ht;
1831 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) &&
1832 ht->ht_msiaddr >> 20 == addr >> 20) {
1833 /* Enable MSI -> HT mapping. */
1834 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
1835 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1839 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) {
1840 /* Disable MSI -> HT mapping. */
1841 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE;
1842 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1848 pci_get_max_read_req(device_t dev)
1850 struct pci_devinfo *dinfo = device_get_ivars(dev);
1854 cap = dinfo->cfg.pcie.pcie_location;
1857 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2);
1858 val &= PCIEM_CTL_MAX_READ_REQUEST;
1860 return (1 << (val + 7));
1864 pci_set_max_read_req(device_t dev, int size)
1866 struct pci_devinfo *dinfo = device_get_ivars(dev);
1870 cap = dinfo->cfg.pcie.pcie_location;
1877 size = (1 << (fls(size) - 1));
1878 val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2);
1879 val &= ~PCIEM_CTL_MAX_READ_REQUEST;
1880 val |= (fls(size) - 8) << 12;
1881 pci_write_config(dev, cap + PCIER_DEVICE_CTL, val, 2);
1886 * Support for MSI message signalled interrupts.
1889 pci_enable_msi(device_t dev, uint64_t address, uint16_t data)
1891 struct pci_devinfo *dinfo = device_get_ivars(dev);
1892 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1894 /* Write data and address values. */
1895 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1896 address & 0xffffffff, 4);
1897 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1898 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR_HIGH,
1900 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA_64BIT,
1903 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, data,
1906 /* Enable MSI in the control register. */
1907 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE;
1908 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1911 /* Enable MSI -> HT mapping. */
1912 pci_ht_map_msi(dev, address);
1916 pci_disable_msi(device_t dev)
1918 struct pci_devinfo *dinfo = device_get_ivars(dev);
1919 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1921 /* Disable MSI -> HT mapping. */
1922 pci_ht_map_msi(dev, 0);
1924 /* Disable MSI in the control register. */
1925 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE;
1926 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1931 * Restore MSI registers during resume. If MSI is enabled then
1932 * restore the data and address registers in addition to the control
1936 pci_resume_msi(device_t dev)
1938 struct pci_devinfo *dinfo = device_get_ivars(dev);
1939 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1943 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) {
1944 address = msi->msi_addr;
1945 data = msi->msi_data;
1946 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1947 address & 0xffffffff, 4);
1948 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1949 pci_write_config(dev, msi->msi_location +
1950 PCIR_MSI_ADDR_HIGH, address >> 32, 4);
1951 pci_write_config(dev, msi->msi_location +
1952 PCIR_MSI_DATA_64BIT, data, 2);
1954 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA,
1957 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1962 pci_remap_intr_method(device_t bus, device_t dev, u_int irq)
1964 struct pci_devinfo *dinfo = device_get_ivars(dev);
1965 pcicfgregs *cfg = &dinfo->cfg;
1966 struct resource_list_entry *rle;
1967 struct msix_table_entry *mte;
1968 struct msix_vector *mv;
1974 * Handle MSI first. We try to find this IRQ among our list
1975 * of MSI IRQs. If we find it, we request updated address and
1976 * data registers and apply the results.
1978 if (cfg->msi.msi_alloc > 0) {
1980 /* If we don't have any active handlers, nothing to do. */
1981 if (cfg->msi.msi_handlers == 0)
1983 for (i = 0; i < cfg->msi.msi_alloc; i++) {
1984 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ,
1986 if (rle->start == irq) {
1987 error = PCIB_MAP_MSI(device_get_parent(bus),
1988 dev, irq, &addr, &data);
1991 pci_disable_msi(dev);
1992 dinfo->cfg.msi.msi_addr = addr;
1993 dinfo->cfg.msi.msi_data = data;
1994 pci_enable_msi(dev, addr, data);
2002 * For MSI-X, we check to see if we have this IRQ. If we do,
2003 * we request the updated mapping info. If that works, we go
2004 * through all the slots that use this IRQ and update them.
2006 if (cfg->msix.msix_alloc > 0) {
2007 for (i = 0; i < cfg->msix.msix_alloc; i++) {
2008 mv = &cfg->msix.msix_vectors[i];
2009 if (mv->mv_irq == irq) {
2010 error = PCIB_MAP_MSI(device_get_parent(bus),
2011 dev, irq, &addr, &data);
2014 mv->mv_address = addr;
2016 for (j = 0; j < cfg->msix.msix_table_len; j++) {
2017 mte = &cfg->msix.msix_table[j];
2018 if (mte->mte_vector != i + 1)
2020 if (mte->mte_handlers == 0)
2022 pci_mask_msix(dev, j);
2023 pci_enable_msix(dev, j, addr, data);
2024 pci_unmask_msix(dev, j);
2035 * Returns true if the specified device is blacklisted because MSI
2039 pci_msi_device_blacklisted(device_t dev)
2042 if (!pci_honor_msi_blacklist)
2045 return (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSI));
2049 * Determine if MSI is blacklisted globally on this system. Currently,
2050 * we just check for blacklisted chipsets as represented by the
2051 * host-PCI bridge at device 0:0:0. In the future, it may become
2052 * necessary to check other system attributes, such as the kenv values
2053 * that give the motherboard manufacturer and model number.
2056 pci_msi_blacklisted(void)
2060 if (!pci_honor_msi_blacklist)
2063 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */
2064 if (!(pcie_chipset || pcix_chipset)) {
2065 if (vm_guest != VM_GUEST_NO) {
2067 * Whitelist older chipsets in virtual
2068 * machines known to support MSI.
2070 dev = pci_find_bsf(0, 0, 0);
2072 return (!pci_has_quirk(pci_get_devid(dev),
2073 PCI_QUIRK_ENABLE_MSI_VM));
2078 dev = pci_find_bsf(0, 0, 0);
2080 return (pci_msi_device_blacklisted(dev));
2085 * Returns true if the specified device is blacklisted because MSI-X
2086 * doesn't work. Note that this assumes that if MSI doesn't work,
2087 * MSI-X doesn't either.
2090 pci_msix_device_blacklisted(device_t dev)
2093 if (!pci_honor_msi_blacklist)
2096 if (pci_has_quirk(pci_get_devid(dev), PCI_QUIRK_DISABLE_MSIX))
2099 return (pci_msi_device_blacklisted(dev));
2103 * Determine if MSI-X is blacklisted globally on this system. If MSI
2104 * is blacklisted, assume that MSI-X is as well. Check for additional
2105 * chipsets where MSI works but MSI-X does not.
2108 pci_msix_blacklisted(void)
2112 if (!pci_honor_msi_blacklist)
2115 dev = pci_find_bsf(0, 0, 0);
2116 if (dev != NULL && pci_has_quirk(pci_get_devid(dev),
2117 PCI_QUIRK_DISABLE_MSIX))
2120 return (pci_msi_blacklisted());
2124 * Attempt to allocate *count MSI messages. The actual number allocated is
2125 * returned in *count. After this function returns, each message will be
2126 * available to the driver as SYS_RES_IRQ resources starting at a rid 1.
2129 pci_alloc_msi_method(device_t dev, device_t child, int *count)
2131 struct pci_devinfo *dinfo = device_get_ivars(child);
2132 pcicfgregs *cfg = &dinfo->cfg;
2133 struct resource_list_entry *rle;
2134 int actual, error, i, irqs[32];
2137 /* Don't let count == 0 get us into trouble. */
2141 /* If rid 0 is allocated, then fail. */
2142 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
2143 if (rle != NULL && rle->res != NULL)
2146 /* Already have allocated messages? */
2147 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
2150 /* If MSI is blacklisted for this system, fail. */
2151 if (pci_msi_blacklisted())
2154 /* MSI capability present? */
2155 if (cfg->msi.msi_location == 0 || !pci_do_msi)
2159 device_printf(child,
2160 "attempting to allocate %d MSI vectors (%d supported)\n",
2161 *count, cfg->msi.msi_msgnum);
2163 /* Don't ask for more than the device supports. */
2164 actual = min(*count, cfg->msi.msi_msgnum);
2166 /* Don't ask for more than 32 messages. */
2167 actual = min(actual, 32);
2169 /* MSI requires power of 2 number of messages. */
2170 if (!powerof2(actual))
2174 /* Try to allocate N messages. */
2175 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual,
2187 * We now have N actual messages mapped onto SYS_RES_IRQ
2188 * resources in the irqs[] array, so add new resources
2189 * starting at rid 1.
2191 for (i = 0; i < actual; i++)
2192 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1,
2193 irqs[i], irqs[i], 1);
2197 device_printf(child, "using IRQ %d for MSI\n", irqs[0]);
2202 * Be fancy and try to print contiguous runs
2203 * of IRQ values as ranges. 'run' is true if
2204 * we are in a range.
2206 device_printf(child, "using IRQs %d", irqs[0]);
2208 for (i = 1; i < actual; i++) {
2210 /* Still in a run? */
2211 if (irqs[i] == irqs[i - 1] + 1) {
2216 /* Finish previous range. */
2218 printf("-%d", irqs[i - 1]);
2222 /* Start new range. */
2223 printf(",%d", irqs[i]);
2226 /* Unfinished range? */
2228 printf("-%d", irqs[actual - 1]);
2229 printf(" for MSI\n");
2233 /* Update control register with actual count. */
2234 ctrl = cfg->msi.msi_ctrl;
2235 ctrl &= ~PCIM_MSICTRL_MME_MASK;
2236 ctrl |= (ffs(actual) - 1) << 4;
2237 cfg->msi.msi_ctrl = ctrl;
2238 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2);
2240 /* Update counts of alloc'd messages. */
2241 cfg->msi.msi_alloc = actual;
2242 cfg->msi.msi_handlers = 0;
2247 /* Release the MSI messages associated with this device. */
2249 pci_release_msi_method(device_t dev, device_t child)
2251 struct pci_devinfo *dinfo = device_get_ivars(child);
2252 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2253 struct resource_list_entry *rle;
2254 int error, i, irqs[32];
2256 /* Try MSI-X first. */
2257 error = pci_release_msix(dev, child);
2258 if (error != ENODEV)
2261 /* Do we have any messages to release? */
2262 if (msi->msi_alloc == 0)
2264 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages"));
2266 /* Make sure none of the resources are allocated. */
2267 if (msi->msi_handlers > 0)
2269 for (i = 0; i < msi->msi_alloc; i++) {
2270 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
2271 KASSERT(rle != NULL, ("missing MSI resource"));
2272 if (rle->res != NULL)
2274 irqs[i] = rle->start;
2277 /* Update control register with 0 count. */
2278 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE),
2279 ("%s: MSI still enabled", __func__));
2280 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK;
2281 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
2284 /* Release the messages. */
2285 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs);
2286 for (i = 0; i < msi->msi_alloc; i++)
2287 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
2289 /* Update alloc count. */
2297 * Return the max supported MSI messages this device supports.
2298 * Basically, assuming the MD code can alloc messages, this function
2299 * should return the maximum value that pci_alloc_msi() can return.
2300 * Thus, it is subject to the tunables, etc.
2303 pci_msi_count_method(device_t dev, device_t child)
2305 struct pci_devinfo *dinfo = device_get_ivars(child);
2306 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2308 if (pci_do_msi && msi->msi_location != 0)
2309 return (msi->msi_msgnum);
2313 /* free pcicfgregs structure and all depending data structures */
2316 pci_freecfg(struct pci_devinfo *dinfo)
2318 struct devlist *devlist_head;
2319 struct pci_map *pm, *next;
2322 devlist_head = &pci_devq;
2324 if (dinfo->cfg.vpd.vpd_reg) {
2325 free(dinfo->cfg.vpd.vpd_ident, M_DEVBUF);
2326 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++)
2327 free(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF);
2328 free(dinfo->cfg.vpd.vpd_ros, M_DEVBUF);
2329 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++)
2330 free(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF);
2331 free(dinfo->cfg.vpd.vpd_w, M_DEVBUF);
2333 STAILQ_FOREACH_SAFE(pm, &dinfo->cfg.maps, pm_link, next) {
2336 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
2337 free(dinfo, M_DEVBUF);
2339 /* increment the generation count */
2342 /* we're losing one device */
2348 * PCI power manangement
2351 pci_set_powerstate_method(device_t dev, device_t child, int state)
2353 struct pci_devinfo *dinfo = device_get_ivars(child);
2354 pcicfgregs *cfg = &dinfo->cfg;
2356 int result, oldstate, highest, delay;
2358 if (cfg->pp.pp_cap == 0)
2359 return (EOPNOTSUPP);
2362 * Optimize a no state change request away. While it would be OK to
2363 * write to the hardware in theory, some devices have shown odd
2364 * behavior when going from D3 -> D3.
2366 oldstate = pci_get_powerstate(child);
2367 if (oldstate == state)
2371 * The PCI power management specification states that after a state
2372 * transition between PCI power states, system software must
2373 * guarantee a minimal delay before the function accesses the device.
2374 * Compute the worst case delay that we need to guarantee before we
2375 * access the device. Many devices will be responsive much more
2376 * quickly than this delay, but there are some that don't respond
2377 * instantly to state changes. Transitions to/from D3 state require
2378 * 10ms, while D2 requires 200us, and D0/1 require none. The delay
2379 * is done below with DELAY rather than a sleeper function because
2380 * this function can be called from contexts where we cannot sleep.
2382 highest = (oldstate > state) ? oldstate : state;
2383 if (highest == PCI_POWERSTATE_D3)
2385 else if (highest == PCI_POWERSTATE_D2)
2389 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2)
2390 & ~PCIM_PSTAT_DMASK;
2393 case PCI_POWERSTATE_D0:
2394 status |= PCIM_PSTAT_D0;
2396 case PCI_POWERSTATE_D1:
2397 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0)
2398 return (EOPNOTSUPP);
2399 status |= PCIM_PSTAT_D1;
2401 case PCI_POWERSTATE_D2:
2402 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0)
2403 return (EOPNOTSUPP);
2404 status |= PCIM_PSTAT_D2;
2406 case PCI_POWERSTATE_D3:
2407 status |= PCIM_PSTAT_D3;
2414 pci_printf(cfg, "Transition from D%d to D%d\n", oldstate,
2417 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2);
2424 pci_get_powerstate_method(device_t dev, device_t child)
2426 struct pci_devinfo *dinfo = device_get_ivars(child);
2427 pcicfgregs *cfg = &dinfo->cfg;
2431 if (cfg->pp.pp_cap != 0) {
2432 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2);
2433 switch (status & PCIM_PSTAT_DMASK) {
2435 result = PCI_POWERSTATE_D0;
2438 result = PCI_POWERSTATE_D1;
2441 result = PCI_POWERSTATE_D2;
2444 result = PCI_POWERSTATE_D3;
2447 result = PCI_POWERSTATE_UNKNOWN;
2451 /* No support, device is always at D0 */
2452 result = PCI_POWERSTATE_D0;
2458 * Some convenience functions for PCI device drivers.
2461 static __inline void
2462 pci_set_command_bit(device_t dev, device_t child, uint16_t bit)
2466 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2468 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2471 static __inline void
2472 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit)
2476 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2478 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2482 pci_enable_busmaster_method(device_t dev, device_t child)
2484 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2489 pci_disable_busmaster_method(device_t dev, device_t child)
2491 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2496 pci_enable_io_method(device_t dev, device_t child, int space)
2501 case SYS_RES_IOPORT:
2502 bit = PCIM_CMD_PORTEN;
2504 case SYS_RES_MEMORY:
2505 bit = PCIM_CMD_MEMEN;
2510 pci_set_command_bit(dev, child, bit);
2515 pci_disable_io_method(device_t dev, device_t child, int space)
2520 case SYS_RES_IOPORT:
2521 bit = PCIM_CMD_PORTEN;
2523 case SYS_RES_MEMORY:
2524 bit = PCIM_CMD_MEMEN;
2529 pci_clear_command_bit(dev, child, bit);
2534 * New style pci driver. Parent device is either a pci-host-bridge or a
2535 * pci-pci-bridge. Both kinds are represented by instances of pcib.
2539 pci_print_verbose(struct pci_devinfo *dinfo)
2543 pcicfgregs *cfg = &dinfo->cfg;
2545 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
2546 cfg->vendor, cfg->device, cfg->revid);
2547 printf("\tdomain=%d, bus=%d, slot=%d, func=%d\n",
2548 cfg->domain, cfg->bus, cfg->slot, cfg->func);
2549 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
2550 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype,
2552 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
2553 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
2554 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
2555 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt,
2556 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
2557 if (cfg->intpin > 0)
2558 printf("\tintpin=%c, irq=%d\n",
2559 cfg->intpin +'a' -1, cfg->intline);
2560 if (cfg->pp.pp_cap) {
2563 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2);
2564 printf("\tpowerspec %d supports D0%s%s D3 current D%d\n",
2565 cfg->pp.pp_cap & PCIM_PCAP_SPEC,
2566 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "",
2567 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "",
2568 status & PCIM_PSTAT_DMASK);
2570 if (cfg->msi.msi_location) {
2573 ctrl = cfg->msi.msi_ctrl;
2574 printf("\tMSI supports %d message%s%s%s\n",
2575 cfg->msi.msi_msgnum,
2576 (cfg->msi.msi_msgnum == 1) ? "" : "s",
2577 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
2578 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":"");
2580 if (cfg->msix.msix_location) {
2581 printf("\tMSI-X supports %d message%s ",
2582 cfg->msix.msix_msgnum,
2583 (cfg->msix.msix_msgnum == 1) ? "" : "s");
2584 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar)
2585 printf("in map 0x%x\n",
2586 cfg->msix.msix_table_bar);
2588 printf("in maps 0x%x and 0x%x\n",
2589 cfg->msix.msix_table_bar,
2590 cfg->msix.msix_pba_bar);
2596 pci_porten(device_t dev)
2598 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_PORTEN) != 0;
2602 pci_memen(device_t dev)
2604 return (pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_MEMEN) != 0;
2608 pci_read_bar(device_t dev, int reg, pci_addr_t *mapp, pci_addr_t *testvalp)
2610 struct pci_devinfo *dinfo;
2611 pci_addr_t map, testval;
2616 * The device ROM BAR is special. It is always a 32-bit
2617 * memory BAR. Bit 0 is special and should not be set when
2620 dinfo = device_get_ivars(dev);
2621 if (PCIR_IS_BIOS(&dinfo->cfg, reg)) {
2622 map = pci_read_config(dev, reg, 4);
2623 pci_write_config(dev, reg, 0xfffffffe, 4);
2624 testval = pci_read_config(dev, reg, 4);
2625 pci_write_config(dev, reg, map, 4);
2627 *testvalp = testval;
2631 map = pci_read_config(dev, reg, 4);
2632 ln2range = pci_maprange(map);
2634 map |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32;
2637 * Disable decoding via the command register before
2638 * determining the BAR's length since we will be placing it in
2641 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
2642 pci_write_config(dev, PCIR_COMMAND,
2643 cmd & ~(PCI_BAR_MEM(map) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN), 2);
2646 * Determine the BAR's length by writing all 1's. The bottom
2647 * log_2(size) bits of the BAR will stick as 0 when we read
2650 pci_write_config(dev, reg, 0xffffffff, 4);
2651 testval = pci_read_config(dev, reg, 4);
2652 if (ln2range == 64) {
2653 pci_write_config(dev, reg + 4, 0xffffffff, 4);
2654 testval |= (pci_addr_t)pci_read_config(dev, reg + 4, 4) << 32;
2658 * Restore the original value of the BAR. We may have reprogrammed
2659 * the BAR of the low-level console device and when booting verbose,
2660 * we need the console device addressable.
2662 pci_write_config(dev, reg, map, 4);
2664 pci_write_config(dev, reg + 4, map >> 32, 4);
2665 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
2668 *testvalp = testval;
2672 pci_write_bar(device_t dev, struct pci_map *pm, pci_addr_t base)
2674 struct pci_devinfo *dinfo;
2677 /* The device ROM BAR is always a 32-bit memory BAR. */
2678 dinfo = device_get_ivars(dev);
2679 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg))
2682 ln2range = pci_maprange(pm->pm_value);
2683 pci_write_config(dev, pm->pm_reg, base, 4);
2685 pci_write_config(dev, pm->pm_reg + 4, base >> 32, 4);
2686 pm->pm_value = pci_read_config(dev, pm->pm_reg, 4);
2688 pm->pm_value |= (pci_addr_t)pci_read_config(dev,
2689 pm->pm_reg + 4, 4) << 32;
2693 pci_find_bar(device_t dev, int reg)
2695 struct pci_devinfo *dinfo;
2698 dinfo = device_get_ivars(dev);
2699 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) {
2700 if (pm->pm_reg == reg)
2707 pci_bar_enabled(device_t dev, struct pci_map *pm)
2709 struct pci_devinfo *dinfo;
2712 dinfo = device_get_ivars(dev);
2713 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) &&
2714 !(pm->pm_value & PCIM_BIOS_ENABLE))
2716 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
2717 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg) || PCI_BAR_MEM(pm->pm_value))
2718 return ((cmd & PCIM_CMD_MEMEN) != 0);
2720 return ((cmd & PCIM_CMD_PORTEN) != 0);
2723 static struct pci_map *
2724 pci_add_bar(device_t dev, int reg, pci_addr_t value, pci_addr_t size)
2726 struct pci_devinfo *dinfo;
2727 struct pci_map *pm, *prev;
2729 dinfo = device_get_ivars(dev);
2730 pm = malloc(sizeof(*pm), M_DEVBUF, M_WAITOK | M_ZERO);
2732 pm->pm_value = value;
2734 STAILQ_FOREACH(prev, &dinfo->cfg.maps, pm_link) {
2735 KASSERT(prev->pm_reg != pm->pm_reg, ("duplicate map %02x",
2737 if (STAILQ_NEXT(prev, pm_link) == NULL ||
2738 STAILQ_NEXT(prev, pm_link)->pm_reg > pm->pm_reg)
2742 STAILQ_INSERT_AFTER(&dinfo->cfg.maps, prev, pm, pm_link);
2744 STAILQ_INSERT_TAIL(&dinfo->cfg.maps, pm, pm_link);
2749 pci_restore_bars(device_t dev)
2751 struct pci_devinfo *dinfo;
2755 dinfo = device_get_ivars(dev);
2756 STAILQ_FOREACH(pm, &dinfo->cfg.maps, pm_link) {
2757 if (PCIR_IS_BIOS(&dinfo->cfg, pm->pm_reg))
2760 ln2range = pci_maprange(pm->pm_value);
2761 pci_write_config(dev, pm->pm_reg, pm->pm_value, 4);
2763 pci_write_config(dev, pm->pm_reg + 4,
2764 pm->pm_value >> 32, 4);
2769 * Add a resource based on a pci map register. Return 1 if the map
2770 * register is a 32bit map register or 2 if it is a 64bit register.
2773 pci_add_map(device_t bus, device_t dev, int reg, struct resource_list *rl,
2774 int force, int prefetch)
2777 pci_addr_t base, map, testval;
2778 pci_addr_t start, end, count;
2779 int barlen, basezero, flags, maprange, mapsize, type;
2781 struct resource *res;
2784 * The BAR may already exist if the device is a CardBus card
2785 * whose CIS is stored in this BAR.
2787 pm = pci_find_bar(dev, reg);
2789 maprange = pci_maprange(pm->pm_value);
2790 barlen = maprange == 64 ? 2 : 1;
2794 pci_read_bar(dev, reg, &map, &testval);
2795 if (PCI_BAR_MEM(map)) {
2796 type = SYS_RES_MEMORY;
2797 if (map & PCIM_BAR_MEM_PREFETCH)
2800 type = SYS_RES_IOPORT;
2801 mapsize = pci_mapsize(testval);
2802 base = pci_mapbase(map);
2803 #ifdef __PCI_BAR_ZERO_VALID
2806 basezero = base == 0;
2808 maprange = pci_maprange(map);
2809 barlen = maprange == 64 ? 2 : 1;
2812 * For I/O registers, if bottom bit is set, and the next bit up
2813 * isn't clear, we know we have a BAR that doesn't conform to the
2814 * spec, so ignore it. Also, sanity check the size of the data
2815 * areas to the type of memory involved. Memory must be at least
2816 * 16 bytes in size, while I/O ranges must be at least 4.
2818 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0)
2820 if ((type == SYS_RES_MEMORY && mapsize < 4) ||
2821 (type == SYS_RES_IOPORT && mapsize < 2))
2824 /* Save a record of this BAR. */
2825 pm = pci_add_bar(dev, reg, map, mapsize);
2827 printf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d",
2828 reg, pci_maptype(map), maprange, (uintmax_t)base, mapsize);
2829 if (type == SYS_RES_IOPORT && !pci_porten(dev))
2830 printf(", port disabled\n");
2831 else if (type == SYS_RES_MEMORY && !pci_memen(dev))
2832 printf(", memory disabled\n");
2834 printf(", enabled\n");
2838 * If base is 0, then we have problems if this architecture does
2839 * not allow that. It is best to ignore such entries for the
2840 * moment. These will be allocated later if the driver specifically
2841 * requests them. However, some removable busses look better when
2842 * all resources are allocated, so allow '0' to be overriden.
2844 * Similarly treat maps whose values is the same as the test value
2845 * read back. These maps have had all f's written to them by the
2846 * BIOS in an attempt to disable the resources.
2848 if (!force && (basezero || map == testval))
2850 if ((u_long)base != base) {
2852 "pci%d:%d:%d:%d bar %#x too many address bits",
2853 pci_get_domain(dev), pci_get_bus(dev), pci_get_slot(dev),
2854 pci_get_function(dev), reg);
2859 * This code theoretically does the right thing, but has
2860 * undesirable side effects in some cases where peripherals
2861 * respond oddly to having these bits enabled. Let the user
2862 * be able to turn them off (since pci_enable_io_modes is 1 by
2865 if (pci_enable_io_modes) {
2866 /* Turn on resources that have been left off by a lazy BIOS */
2867 if (type == SYS_RES_IOPORT && !pci_porten(dev)) {
2868 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
2869 cmd |= PCIM_CMD_PORTEN;
2870 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
2872 if (type == SYS_RES_MEMORY && !pci_memen(dev)) {
2873 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
2874 cmd |= PCIM_CMD_MEMEN;
2875 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
2878 if (type == SYS_RES_IOPORT && !pci_porten(dev))
2880 if (type == SYS_RES_MEMORY && !pci_memen(dev))
2884 count = (pci_addr_t)1 << mapsize;
2885 flags = RF_ALIGNMENT_LOG2(mapsize);
2887 flags |= RF_PREFETCHABLE;
2888 if (basezero || base == pci_mapbase(testval) || pci_clear_bars) {
2889 start = 0; /* Let the parent decide. */
2893 end = base + count - 1;
2895 resource_list_add(rl, type, reg, start, end, count);
2898 * Try to allocate the resource for this BAR from our parent
2899 * so that this resource range is already reserved. The
2900 * driver for this device will later inherit this resource in
2901 * pci_alloc_resource().
2903 res = resource_list_reserve(rl, bus, dev, type, ®, start, end, count,
2905 if (pci_do_realloc_bars && res == NULL && (start != 0 || end != ~0ul)) {
2907 * If the allocation fails, try to allocate a resource for
2908 * this BAR using any available range. The firmware felt
2909 * it was important enough to assign a resource, so don't
2910 * disable decoding if we can help it.
2912 resource_list_delete(rl, type, reg);
2913 resource_list_add(rl, type, reg, 0, ~0ul, count);
2914 res = resource_list_reserve(rl, bus, dev, type, ®, 0, ~0ul,
2919 * If the allocation fails, delete the resource list entry
2920 * and disable decoding for this device.
2922 * If the driver requests this resource in the future,
2923 * pci_reserve_map() will try to allocate a fresh
2926 resource_list_delete(rl, type, reg);
2927 pci_disable_io(dev, type);
2930 "pci%d:%d:%d:%d bar %#x failed to allocate\n",
2931 pci_get_domain(dev), pci_get_bus(dev),
2932 pci_get_slot(dev), pci_get_function(dev), reg);
2934 start = rman_get_start(res);
2935 pci_write_bar(dev, pm, start);
2941 * For ATA devices we need to decide early what addressing mode to use.
2942 * Legacy demands that the primary and secondary ATA ports sits on the
2943 * same addresses that old ISA hardware did. This dictates that we use
2944 * those addresses and ignore the BAR's if we cannot set PCI native
2948 pci_ata_maps(device_t bus, device_t dev, struct resource_list *rl, int force,
2949 uint32_t prefetchmask)
2952 int rid, type, progif;
2954 /* if this device supports PCI native addressing use it */
2955 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2956 if ((progif & 0x8a) == 0x8a) {
2957 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
2958 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
2959 printf("Trying ATA native PCI addressing mode\n");
2960 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
2964 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2965 type = SYS_RES_IOPORT;
2966 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
2967 pci_add_map(bus, dev, PCIR_BAR(0), rl, force,
2968 prefetchmask & (1 << 0));
2969 pci_add_map(bus, dev, PCIR_BAR(1), rl, force,
2970 prefetchmask & (1 << 1));
2973 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8);
2974 r = resource_list_reserve(rl, bus, dev, type, &rid, 0x1f0,
2977 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1);
2978 r = resource_list_reserve(rl, bus, dev, type, &rid, 0x3f6,
2981 if (progif & PCIP_STORAGE_IDE_MODESEC) {
2982 pci_add_map(bus, dev, PCIR_BAR(2), rl, force,
2983 prefetchmask & (1 << 2));
2984 pci_add_map(bus, dev, PCIR_BAR(3), rl, force,
2985 prefetchmask & (1 << 3));
2988 resource_list_add(rl, type, rid, 0x170, 0x177, 8);
2989 r = resource_list_reserve(rl, bus, dev, type, &rid, 0x170,
2992 resource_list_add(rl, type, rid, 0x376, 0x376, 1);
2993 r = resource_list_reserve(rl, bus, dev, type, &rid, 0x376,
2996 pci_add_map(bus, dev, PCIR_BAR(4), rl, force,
2997 prefetchmask & (1 << 4));
2998 pci_add_map(bus, dev, PCIR_BAR(5), rl, force,
2999 prefetchmask & (1 << 5));
3003 pci_assign_interrupt(device_t bus, device_t dev, int force_route)
3005 struct pci_devinfo *dinfo = device_get_ivars(dev);
3006 pcicfgregs *cfg = &dinfo->cfg;
3007 char tunable_name[64];
3010 /* Has to have an intpin to have an interrupt. */
3011 if (cfg->intpin == 0)
3014 /* Let the user override the IRQ with a tunable. */
3015 irq = PCI_INVALID_IRQ;
3016 snprintf(tunable_name, sizeof(tunable_name),
3017 "hw.pci%d.%d.%d.INT%c.irq",
3018 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1);
3019 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0))
3020 irq = PCI_INVALID_IRQ;
3023 * If we didn't get an IRQ via the tunable, then we either use the
3024 * IRQ value in the intline register or we ask the bus to route an
3025 * interrupt for us. If force_route is true, then we only use the
3026 * value in the intline register if the bus was unable to assign an
3029 if (!PCI_INTERRUPT_VALID(irq)) {
3030 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route)
3031 irq = PCI_ASSIGN_INTERRUPT(bus, dev);
3032 if (!PCI_INTERRUPT_VALID(irq))
3036 /* If after all that we don't have an IRQ, just bail. */
3037 if (!PCI_INTERRUPT_VALID(irq))
3040 /* Update the config register if it changed. */
3041 if (irq != cfg->intline) {
3043 pci_write_config(dev, PCIR_INTLINE, irq, 1);
3046 /* Add this IRQ as rid 0 interrupt resource. */
3047 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1);
3050 /* Perform early OHCI takeover from SMM. */
3052 ohci_early_takeover(device_t self)
3054 struct resource *res;
3060 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
3064 ctl = bus_read_4(res, OHCI_CONTROL);
3065 if (ctl & OHCI_IR) {
3067 printf("ohci early: "
3068 "SMM active, request owner change\n");
3069 bus_write_4(res, OHCI_COMMAND_STATUS, OHCI_OCR);
3070 for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) {
3072 ctl = bus_read_4(res, OHCI_CONTROL);
3074 if (ctl & OHCI_IR) {
3076 printf("ohci early: "
3077 "SMM does not respond, resetting\n");
3078 bus_write_4(res, OHCI_CONTROL, OHCI_HCFS_RESET);
3080 /* Disable interrupts */
3081 bus_write_4(res, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS);
3084 bus_release_resource(self, SYS_RES_MEMORY, rid, res);
3087 /* Perform early UHCI takeover from SMM. */
3089 uhci_early_takeover(device_t self)
3091 struct resource *res;
3095 * Set the PIRQD enable bit and switch off all the others. We don't
3096 * want legacy support to interfere with us XXX Does this also mean
3097 * that the BIOS won't touch the keyboard anymore if it is connected
3098 * to the ports of the root hub?
3100 pci_write_config(self, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN, 2);
3102 /* Disable interrupts */
3103 rid = PCI_UHCI_BASE_REG;
3104 res = bus_alloc_resource_any(self, SYS_RES_IOPORT, &rid, RF_ACTIVE);
3106 bus_write_2(res, UHCI_INTR, 0);
3107 bus_release_resource(self, SYS_RES_IOPORT, rid, res);
3111 /* Perform early EHCI takeover from SMM. */
3113 ehci_early_takeover(device_t self)
3115 struct resource *res;
3125 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
3129 cparams = bus_read_4(res, EHCI_HCCPARAMS);
3131 /* Synchronise with the BIOS if it owns the controller. */
3132 for (eecp = EHCI_HCC_EECP(cparams); eecp != 0;
3133 eecp = EHCI_EECP_NEXT(eec)) {
3134 eec = pci_read_config(self, eecp, 4);
3135 if (EHCI_EECP_ID(eec) != EHCI_EC_LEGSUP) {
3138 bios_sem = pci_read_config(self, eecp +
3139 EHCI_LEGSUP_BIOS_SEM, 1);
3140 if (bios_sem == 0) {
3144 printf("ehci early: "
3145 "SMM active, request owner change\n");
3147 pci_write_config(self, eecp + EHCI_LEGSUP_OS_SEM, 1, 1);
3149 for (i = 0; (i < 100) && (bios_sem != 0); i++) {
3151 bios_sem = pci_read_config(self, eecp +
3152 EHCI_LEGSUP_BIOS_SEM, 1);
3155 if (bios_sem != 0) {
3157 printf("ehci early: "
3158 "SMM does not respond\n");
3160 /* Disable interrupts */
3161 offs = EHCI_CAPLENGTH(bus_read_4(res, EHCI_CAPLEN_HCIVERSION));
3162 bus_write_4(res, offs + EHCI_USBINTR, 0);
3164 bus_release_resource(self, SYS_RES_MEMORY, rid, res);
3167 /* Perform early XHCI takeover from SMM. */
3169 xhci_early_takeover(device_t self)
3171 struct resource *res;
3181 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
3185 cparams = bus_read_4(res, XHCI_HCSPARAMS0);
3189 /* Synchronise with the BIOS if it owns the controller. */
3190 for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec);
3191 eecp += XHCI_XECP_NEXT(eec) << 2) {
3192 eec = bus_read_4(res, eecp);
3194 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY)
3197 bios_sem = bus_read_1(res, eecp + XHCI_XECP_BIOS_SEM);
3202 printf("xhci early: "
3203 "SMM active, request owner change\n");
3205 bus_write_1(res, eecp + XHCI_XECP_OS_SEM, 1);
3207 /* wait a maximum of 5 second */
3209 for (i = 0; (i < 5000) && (bios_sem != 0); i++) {
3211 bios_sem = bus_read_1(res, eecp +
3212 XHCI_XECP_BIOS_SEM);
3215 if (bios_sem != 0) {
3217 printf("xhci early: "
3218 "SMM does not respond\n");
3221 /* Disable interrupts */
3222 offs = bus_read_1(res, XHCI_CAPLENGTH);
3223 bus_write_4(res, offs + XHCI_USBCMD, 0);
3224 bus_read_4(res, offs + XHCI_USBSTS);
3226 bus_release_resource(self, SYS_RES_MEMORY, rid, res);
3230 pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask)
3232 struct pci_devinfo *dinfo;
3234 struct resource_list *rl;
3235 const struct pci_quirk *q;
3239 dinfo = device_get_ivars(dev);
3241 rl = &dinfo->resources;
3242 devid = (cfg->device << 16) | cfg->vendor;
3244 /* ATA devices needs special map treatment */
3245 if ((pci_get_class(dev) == PCIC_STORAGE) &&
3246 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
3247 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
3248 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
3249 !pci_read_config(dev, PCIR_BAR(2), 4))) )
3250 pci_ata_maps(bus, dev, rl, force, prefetchmask);
3252 for (i = 0; i < cfg->nummaps;) {
3254 * Skip quirked resources.
3256 for (q = &pci_quirks[0]; q->devid != 0; q++)
3257 if (q->devid == devid &&
3258 q->type == PCI_QUIRK_UNMAP_REG &&
3259 q->arg1 == PCIR_BAR(i))
3261 if (q->devid != 0) {
3265 i += pci_add_map(bus, dev, PCIR_BAR(i), rl, force,
3266 prefetchmask & (1 << i));
3270 * Add additional, quirked resources.
3272 for (q = &pci_quirks[0]; q->devid != 0; q++)
3273 if (q->devid == devid && q->type == PCI_QUIRK_MAP_REG)
3274 pci_add_map(bus, dev, q->arg1, rl, force, 0);
3276 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
3277 #ifdef __PCI_REROUTE_INTERRUPT
3279 * Try to re-route interrupts. Sometimes the BIOS or
3280 * firmware may leave bogus values in these registers.
3281 * If the re-route fails, then just stick with what we
3284 pci_assign_interrupt(bus, dev, 1);
3286 pci_assign_interrupt(bus, dev, 0);
3290 if (pci_usb_takeover && pci_get_class(dev) == PCIC_SERIALBUS &&
3291 pci_get_subclass(dev) == PCIS_SERIALBUS_USB) {
3292 if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_XHCI)
3293 xhci_early_takeover(dev);
3294 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_EHCI)
3295 ehci_early_takeover(dev);
3296 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_OHCI)
3297 ohci_early_takeover(dev);
3298 else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_UHCI)
3299 uhci_early_takeover(dev);
3303 static struct pci_devinfo *
3304 pci_identify_function(device_t pcib, device_t dev, int domain, int busno,
3305 int slot, int func, size_t dinfo_size)
3307 struct pci_devinfo *dinfo;
3309 dinfo = pci_read_device(pcib, domain, busno, slot, func, dinfo_size);
3311 pci_add_child(dev, dinfo);
3317 pci_add_children(device_t dev, int domain, int busno, size_t dinfo_size)
3319 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
3320 device_t pcib = device_get_parent(dev);
3321 struct pci_devinfo *dinfo;
3323 int s, f, pcifunchigh;
3328 * Try to detect a device at slot 0, function 0. If it exists, try to
3329 * enable ARI. We must enable ARI before detecting the rest of the
3330 * functions on this bus as ARI changes the set of slots and functions
3331 * that are legal on this bus.
3333 dinfo = pci_identify_function(pcib, dev, domain, busno, 0, 0,
3335 if (dinfo != NULL && pci_enable_ari)
3336 PCIB_TRY_ENABLE_ARI(pcib, dinfo->cfg.dev);
3339 * Start looking for new devices on slot 0 at function 1 because we
3340 * just identified the device at slot 0, function 0.
3344 KASSERT(dinfo_size >= sizeof(struct pci_devinfo),
3345 ("dinfo_size too small"));
3346 maxslots = PCIB_MAXSLOTS(pcib);
3347 for (s = 0; s <= maxslots; s++, first_func = 0) {
3351 hdrtype = REG(PCIR_HDRTYPE, 1);
3352 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
3354 if (hdrtype & PCIM_MFDEV)
3355 pcifunchigh = PCIB_MAXFUNCS(pcib);
3356 for (f = first_func; f <= pcifunchigh; f++)
3357 pci_identify_function(pcib, dev, domain, busno, s, f,
3364 pci_add_child(device_t bus, struct pci_devinfo *dinfo)
3366 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
3367 device_set_ivars(dinfo->cfg.dev, dinfo);
3368 resource_list_init(&dinfo->resources);
3369 pci_cfg_save(dinfo->cfg.dev, dinfo, 0);
3370 pci_cfg_restore(dinfo->cfg.dev, dinfo);
3371 pci_print_verbose(dinfo);
3372 pci_add_resources(bus, dinfo->cfg.dev, 0, 0);
3376 pci_probe(device_t dev)
3379 device_set_desc(dev, "PCI bus");
3381 /* Allow other subclasses to override this driver. */
3382 return (BUS_PROBE_GENERIC);
3386 pci_attach_common(device_t dev)
3388 struct pci_softc *sc;
3390 #ifdef PCI_DMA_BOUNDARY
3391 int error, tag_valid;
3394 sc = device_get_softc(dev);
3395 domain = pcib_get_domain(dev);
3396 busno = pcib_get_bus(dev);
3398 device_printf(dev, "domain=%d, physical bus=%d\n",
3400 #ifdef PCI_DMA_BOUNDARY
3402 if (device_get_devclass(device_get_parent(device_get_parent(dev))) !=
3403 devclass_find("pci")) {
3404 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1,
3405 PCI_DMA_BOUNDARY, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3406 NULL, NULL, BUS_SPACE_MAXSIZE, BUS_SPACE_UNRESTRICTED,
3407 BUS_SPACE_MAXSIZE, 0, NULL, NULL, &sc->sc_dma_tag);
3409 device_printf(dev, "Failed to create DMA tag: %d\n",
3416 sc->sc_dma_tag = bus_get_dma_tag(dev);
3421 pci_attach(device_t dev)
3423 int busno, domain, error;
3425 error = pci_attach_common(dev);
3430 * Since there can be multiple independantly numbered PCI
3431 * busses on systems with multiple PCI domains, we can't use
3432 * the unit number to decide which bus we are probing. We ask
3433 * the parent pcib what our domain and bus numbers are.
3435 domain = pcib_get_domain(dev);
3436 busno = pcib_get_bus(dev);
3437 pci_add_children(dev, domain, busno, sizeof(struct pci_devinfo));
3438 return (bus_generic_attach(dev));
3442 pci_set_power_children(device_t dev, device_t *devlist, int numdevs,
3445 device_t child, pcib;
3446 struct pci_devinfo *dinfo;
3450 * Set the device to the given state. If the firmware suggests
3451 * a different power state, use it instead. If power management
3452 * is not present, the firmware is responsible for managing
3453 * device power. Skip children who aren't attached since they
3454 * are handled separately.
3456 pcib = device_get_parent(dev);
3457 for (i = 0; i < numdevs; i++) {
3459 dinfo = device_get_ivars(child);
3461 if (device_is_attached(child) &&
3462 PCIB_POWER_FOR_SLEEP(pcib, dev, &dstate) == 0)
3463 pci_set_powerstate(child, dstate);
3468 pci_suspend(device_t dev)
3470 device_t child, *devlist;
3471 struct pci_devinfo *dinfo;
3472 int error, i, numdevs;
3475 * Save the PCI configuration space for each child and set the
3476 * device in the appropriate power state for this sleep state.
3478 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0)
3480 for (i = 0; i < numdevs; i++) {
3482 dinfo = device_get_ivars(child);
3483 pci_cfg_save(child, dinfo, 0);
3486 /* Suspend devices before potentially powering them down. */
3487 error = bus_generic_suspend(dev);
3489 free(devlist, M_TEMP);
3492 if (pci_do_power_suspend)
3493 pci_set_power_children(dev, devlist, numdevs,
3495 free(devlist, M_TEMP);
3500 pci_resume(device_t dev)
3502 device_t child, *devlist;
3503 struct pci_devinfo *dinfo;
3504 int error, i, numdevs;
3507 * Set each child to D0 and restore its PCI configuration space.
3509 if ((error = device_get_children(dev, &devlist, &numdevs)) != 0)
3511 if (pci_do_power_resume)
3512 pci_set_power_children(dev, devlist, numdevs,
3515 /* Now the device is powered up, restore its config space. */
3516 for (i = 0; i < numdevs; i++) {
3518 dinfo = device_get_ivars(child);
3520 pci_cfg_restore(child, dinfo);
3521 if (!device_is_attached(child))
3522 pci_cfg_save(child, dinfo, 1);
3526 * Resume critical devices first, then everything else later.
3528 for (i = 0; i < numdevs; i++) {
3530 switch (pci_get_class(child)) {
3534 case PCIC_BASEPERIPH:
3535 DEVICE_RESUME(child);
3539 for (i = 0; i < numdevs; i++) {
3541 switch (pci_get_class(child)) {
3545 case PCIC_BASEPERIPH:
3548 DEVICE_RESUME(child);
3551 free(devlist, M_TEMP);
3556 pci_load_vendor_data(void)
3562 data = preload_search_by_type("pci_vendor_data");
3564 ptr = preload_fetch_addr(data);
3565 sz = preload_fetch_size(data);
3566 if (ptr != NULL && sz != 0) {
3567 pci_vendordata = ptr;
3568 pci_vendordata_size = sz;
3569 /* terminate the database */
3570 pci_vendordata[pci_vendordata_size] = '\n';
3576 pci_driver_added(device_t dev, driver_t *driver)
3581 struct pci_devinfo *dinfo;
3585 device_printf(dev, "driver added\n");
3586 DEVICE_IDENTIFY(driver, dev);
3587 if (device_get_children(dev, &devlist, &numdevs) != 0)
3589 for (i = 0; i < numdevs; i++) {
3591 if (device_get_state(child) != DS_NOTPRESENT)
3593 dinfo = device_get_ivars(child);
3594 pci_print_verbose(dinfo);
3596 pci_printf(&dinfo->cfg, "reprobing on driver added\n");
3597 pci_cfg_restore(child, dinfo);
3598 if (device_probe_and_attach(child) != 0)
3599 pci_child_detached(dev, child);
3601 free(devlist, M_TEMP);
3605 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags,
3606 driver_filter_t *filter, driver_intr_t *intr, void *arg, void **cookiep)
3608 struct pci_devinfo *dinfo;
3609 struct msix_table_entry *mte;
3610 struct msix_vector *mv;
3616 error = bus_generic_setup_intr(dev, child, irq, flags, filter, intr,
3621 /* If this is not a direct child, just bail out. */
3622 if (device_get_parent(child) != dev) {
3627 rid = rman_get_rid(irq);
3629 /* Make sure that INTx is enabled */
3630 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
3633 * Check to see if the interrupt is MSI or MSI-X.
3634 * Ask our parent to map the MSI and give
3635 * us the address and data register values.
3636 * If we fail for some reason, teardown the
3637 * interrupt handler.
3639 dinfo = device_get_ivars(child);
3640 if (dinfo->cfg.msi.msi_alloc > 0) {
3641 if (dinfo->cfg.msi.msi_addr == 0) {
3642 KASSERT(dinfo->cfg.msi.msi_handlers == 0,
3643 ("MSI has handlers, but vectors not mapped"));
3644 error = PCIB_MAP_MSI(device_get_parent(dev),
3645 child, rman_get_start(irq), &addr, &data);
3648 dinfo->cfg.msi.msi_addr = addr;
3649 dinfo->cfg.msi.msi_data = data;
3651 if (dinfo->cfg.msi.msi_handlers == 0)
3652 pci_enable_msi(child, dinfo->cfg.msi.msi_addr,
3653 dinfo->cfg.msi.msi_data);
3654 dinfo->cfg.msi.msi_handlers++;
3656 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3657 ("No MSI or MSI-X interrupts allocated"));
3658 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3659 ("MSI-X index too high"));
3660 mte = &dinfo->cfg.msix.msix_table[rid - 1];
3661 KASSERT(mte->mte_vector != 0, ("no message vector"));
3662 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1];
3663 KASSERT(mv->mv_irq == rman_get_start(irq),
3665 if (mv->mv_address == 0) {
3666 KASSERT(mte->mte_handlers == 0,
3667 ("MSI-X table entry has handlers, but vector not mapped"));
3668 error = PCIB_MAP_MSI(device_get_parent(dev),
3669 child, rman_get_start(irq), &addr, &data);
3672 mv->mv_address = addr;
3675 if (mte->mte_handlers == 0) {
3676 pci_enable_msix(child, rid - 1, mv->mv_address,
3678 pci_unmask_msix(child, rid - 1);
3680 mte->mte_handlers++;
3684 * Make sure that INTx is disabled if we are using MSI/MSI-X,
3685 * unless the device is affected by PCI_QUIRK_MSI_INTX_BUG,
3686 * in which case we "enable" INTx so MSI/MSI-X actually works.
3688 if (!pci_has_quirk(pci_get_devid(child),
3689 PCI_QUIRK_MSI_INTX_BUG))
3690 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3692 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
3695 (void)bus_generic_teardown_intr(dev, child, irq,
3705 pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
3708 struct msix_table_entry *mte;
3709 struct resource_list_entry *rle;
3710 struct pci_devinfo *dinfo;
3713 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE))
3716 /* If this isn't a direct child, just bail out */
3717 if (device_get_parent(child) != dev)
3718 return(bus_generic_teardown_intr(dev, child, irq, cookie));
3720 rid = rman_get_rid(irq);
3723 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3726 * Check to see if the interrupt is MSI or MSI-X. If so,
3727 * decrement the appropriate handlers count and mask the
3728 * MSI-X message, or disable MSI messages if the count
3731 dinfo = device_get_ivars(child);
3732 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid);
3733 if (rle->res != irq)
3735 if (dinfo->cfg.msi.msi_alloc > 0) {
3736 KASSERT(rid <= dinfo->cfg.msi.msi_alloc,
3737 ("MSI-X index too high"));
3738 if (dinfo->cfg.msi.msi_handlers == 0)
3740 dinfo->cfg.msi.msi_handlers--;
3741 if (dinfo->cfg.msi.msi_handlers == 0)
3742 pci_disable_msi(child);
3744 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3745 ("No MSI or MSI-X interrupts allocated"));
3746 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3747 ("MSI-X index too high"));
3748 mte = &dinfo->cfg.msix.msix_table[rid - 1];
3749 if (mte->mte_handlers == 0)
3751 mte->mte_handlers--;
3752 if (mte->mte_handlers == 0)
3753 pci_mask_msix(child, rid - 1);
3756 error = bus_generic_teardown_intr(dev, child, irq, cookie);
3759 ("%s: generic teardown failed for MSI/MSI-X", __func__));
3764 pci_print_child(device_t dev, device_t child)
3766 struct pci_devinfo *dinfo;
3767 struct resource_list *rl;
3770 dinfo = device_get_ivars(child);
3771 rl = &dinfo->resources;
3773 retval += bus_print_child_header(dev, child);
3775 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx");
3776 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx");
3777 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld");
3778 if (device_get_flags(dev))
3779 retval += printf(" flags %#x", device_get_flags(dev));
3781 retval += printf(" at device %d.%d", pci_get_slot(child),
3782 pci_get_function(child));
3784 retval += bus_print_child_domain(dev, child);
3785 retval += bus_print_child_footer(dev, child);
3794 int report; /* 0 = bootverbose, 1 = always */
3796 } pci_nomatch_tab[] = {
3797 {PCIC_OLD, -1, 1, "old"},
3798 {PCIC_OLD, PCIS_OLD_NONVGA, 1, "non-VGA display device"},
3799 {PCIC_OLD, PCIS_OLD_VGA, 1, "VGA-compatible display device"},
3800 {PCIC_STORAGE, -1, 1, "mass storage"},
3801 {PCIC_STORAGE, PCIS_STORAGE_SCSI, 1, "SCSI"},
3802 {PCIC_STORAGE, PCIS_STORAGE_IDE, 1, "ATA"},
3803 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, 1, "floppy disk"},
3804 {PCIC_STORAGE, PCIS_STORAGE_IPI, 1, "IPI"},
3805 {PCIC_STORAGE, PCIS_STORAGE_RAID, 1, "RAID"},
3806 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, 1, "ATA (ADMA)"},
3807 {PCIC_STORAGE, PCIS_STORAGE_SATA, 1, "SATA"},
3808 {PCIC_STORAGE, PCIS_STORAGE_SAS, 1, "SAS"},
3809 {PCIC_STORAGE, PCIS_STORAGE_NVM, 1, "NVM"},
3810 {PCIC_NETWORK, -1, 1, "network"},
3811 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, 1, "ethernet"},
3812 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, 1, "token ring"},
3813 {PCIC_NETWORK, PCIS_NETWORK_FDDI, 1, "fddi"},
3814 {PCIC_NETWORK, PCIS_NETWORK_ATM, 1, "ATM"},
3815 {PCIC_NETWORK, PCIS_NETWORK_ISDN, 1, "ISDN"},
3816 {PCIC_DISPLAY, -1, 1, "display"},
3817 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, 1, "VGA"},
3818 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, 1, "XGA"},
3819 {PCIC_DISPLAY, PCIS_DISPLAY_3D, 1, "3D"},
3820 {PCIC_MULTIMEDIA, -1, 1, "multimedia"},
3821 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, 1, "video"},
3822 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, 1, "audio"},
3823 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, 1, "telephony"},
3824 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, 1, "HDA"},
3825 {PCIC_MEMORY, -1, 1, "memory"},
3826 {PCIC_MEMORY, PCIS_MEMORY_RAM, 1, "RAM"},
3827 {PCIC_MEMORY, PCIS_MEMORY_FLASH, 1, "flash"},
3828 {PCIC_BRIDGE, -1, 1, "bridge"},
3829 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, 1, "HOST-PCI"},
3830 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, 1, "PCI-ISA"},
3831 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, 1, "PCI-EISA"},
3832 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, 1, "PCI-MCA"},
3833 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, 1, "PCI-PCI"},
3834 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, 1, "PCI-PCMCIA"},
3835 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, 1, "PCI-NuBus"},
3836 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, 1, "PCI-CardBus"},
3837 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, 1, "PCI-RACEway"},
3838 {PCIC_SIMPLECOMM, -1, 1, "simple comms"},
3839 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, 1, "UART"}, /* could detect 16550 */
3840 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, 1, "parallel port"},
3841 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, 1, "multiport serial"},
3842 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, 1, "generic modem"},
3843 {PCIC_BASEPERIPH, -1, 0, "base peripheral"},
3844 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, 1, "interrupt controller"},
3845 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, 1, "DMA controller"},
3846 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, 1, "timer"},
3847 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, 1, "realtime clock"},
3848 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, 1, "PCI hot-plug controller"},
3849 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, 1, "SD host controller"},
3850 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_IOMMU, 1, "IOMMU"},
3851 {PCIC_INPUTDEV, -1, 1, "input device"},
3852 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, 1, "keyboard"},
3853 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,1, "digitizer"},
3854 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, 1, "mouse"},
3855 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, 1, "scanner"},
3856 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, 1, "gameport"},
3857 {PCIC_DOCKING, -1, 1, "docking station"},
3858 {PCIC_PROCESSOR, -1, 1, "processor"},
3859 {PCIC_SERIALBUS, -1, 1, "serial bus"},
3860 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, 1, "FireWire"},
3861 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, 1, "AccessBus"},
3862 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, 1, "SSA"},
3863 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, 1, "USB"},
3864 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, 1, "Fibre Channel"},
3865 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, 0, "SMBus"},
3866 {PCIC_WIRELESS, -1, 1, "wireless controller"},
3867 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, 1, "iRDA"},
3868 {PCIC_WIRELESS, PCIS_WIRELESS_IR, 1, "IR"},
3869 {PCIC_WIRELESS, PCIS_WIRELESS_RF, 1, "RF"},
3870 {PCIC_INTELLIIO, -1, 1, "intelligent I/O controller"},
3871 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, 1, "I2O"},
3872 {PCIC_SATCOM, -1, 1, "satellite communication"},
3873 {PCIC_SATCOM, PCIS_SATCOM_TV, 1, "sat TV"},
3874 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, 1, "sat audio"},
3875 {PCIC_SATCOM, PCIS_SATCOM_VOICE, 1, "sat voice"},
3876 {PCIC_SATCOM, PCIS_SATCOM_DATA, 1, "sat data"},
3877 {PCIC_CRYPTO, -1, 1, "encrypt/decrypt"},
3878 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, 1, "network/computer crypto"},
3879 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, 1, "entertainment crypto"},
3880 {PCIC_DASP, -1, 0, "dasp"},
3881 {PCIC_DASP, PCIS_DASP_DPIO, 1, "DPIO module"},
3886 pci_probe_nomatch(device_t dev, device_t child)
3889 const char *cp, *scp;
3893 * Look for a listing for this device in a loaded device database.
3896 if ((device = pci_describe_device(child)) != NULL) {
3897 device_printf(dev, "<%s>", device);
3898 free(device, M_DEVBUF);
3901 * Scan the class/subclass descriptions for a general
3906 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) {
3907 if (pci_nomatch_tab[i].class == pci_get_class(child)) {
3908 if (pci_nomatch_tab[i].subclass == -1) {
3909 cp = pci_nomatch_tab[i].desc;
3910 report = pci_nomatch_tab[i].report;
3911 } else if (pci_nomatch_tab[i].subclass ==
3912 pci_get_subclass(child)) {
3913 scp = pci_nomatch_tab[i].desc;
3914 report = pci_nomatch_tab[i].report;
3918 if (report || bootverbose) {
3919 device_printf(dev, "<%s%s%s>",
3921 ((cp != NULL) && (scp != NULL)) ? ", " : "",
3925 if (report || bootverbose) {
3926 printf(" at device %d.%d (no driver attached)\n",
3927 pci_get_slot(child), pci_get_function(child));
3929 pci_cfg_save(child, device_get_ivars(child), 1);
3933 pci_child_detached(device_t dev, device_t child)
3935 struct pci_devinfo *dinfo;
3936 struct resource_list *rl;
3938 dinfo = device_get_ivars(child);
3939 rl = &dinfo->resources;
3942 * Have to deallocate IRQs before releasing any MSI messages and
3943 * have to release MSI messages before deallocating any memory
3946 if (resource_list_release_active(rl, dev, child, SYS_RES_IRQ) != 0)
3947 pci_printf(&dinfo->cfg, "Device leaked IRQ resources\n");
3948 if (dinfo->cfg.msi.msi_alloc != 0 || dinfo->cfg.msix.msix_alloc != 0) {
3949 pci_printf(&dinfo->cfg, "Device leaked MSI vectors\n");
3950 (void)pci_release_msi(child);
3952 if (resource_list_release_active(rl, dev, child, SYS_RES_MEMORY) != 0)
3953 pci_printf(&dinfo->cfg, "Device leaked memory resources\n");
3954 if (resource_list_release_active(rl, dev, child, SYS_RES_IOPORT) != 0)
3955 pci_printf(&dinfo->cfg, "Device leaked I/O resources\n");
3957 pci_cfg_save(child, dinfo, 1);
3961 * Parse the PCI device database, if loaded, and return a pointer to a
3962 * description of the device.
3964 * The database is flat text formatted as follows:
3966 * Any line not in a valid format is ignored.
3967 * Lines are terminated with newline '\n' characters.
3969 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then
3972 * A DEVICE line is entered immediately below the corresponding VENDOR ID.
3973 * - devices cannot be listed without a corresponding VENDOR line.
3974 * A DEVICE line consists of a TAB, the 4 digit (hex) device code,
3975 * another TAB, then the device name.
3979 * Assuming (ptr) points to the beginning of a line in the database,
3980 * return the vendor or device and description of the next entry.
3981 * The value of (vendor) or (device) inappropriate for the entry type
3982 * is set to -1. Returns nonzero at the end of the database.
3984 * Note that this is slightly unrobust in the face of corrupt data;
3985 * we attempt to safeguard against this by spamming the end of the
3986 * database with a newline when we initialise.
3989 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc)
3998 left = pci_vendordata_size - (cp - pci_vendordata);
4006 sscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2)
4010 sscanf(cp, "%x\t%80[^\n]", device, *desc) == 2)
4013 /* skip to next line */
4014 while (*cp != '\n' && left > 0) {
4023 /* skip to next line */
4024 while (*cp != '\n' && left > 0) {
4028 if (*cp == '\n' && left > 0)
4035 pci_describe_device(device_t dev)
4038 char *desc, *vp, *dp, *line;
4040 desc = vp = dp = NULL;
4043 * If we have no vendor data, we can't do anything.
4045 if (pci_vendordata == NULL)
4049 * Scan the vendor data looking for this device
4051 line = pci_vendordata;
4052 if ((vp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
4055 if (pci_describe_parse_line(&line, &vendor, &device, &vp))
4057 if (vendor == pci_get_vendor(dev))
4060 if ((dp = malloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
4063 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) {
4071 if (device == pci_get_device(dev))
4075 snprintf(dp, 80, "0x%x", pci_get_device(dev));
4076 if ((desc = malloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) !=
4078 sprintf(desc, "%s, %s", vp, dp);
4088 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
4090 struct pci_devinfo *dinfo;
4093 dinfo = device_get_ivars(child);
4097 case PCI_IVAR_ETHADDR:
4099 * The generic accessor doesn't deal with failure, so
4100 * we set the return value, then return an error.
4102 *((uint8_t **) result) = NULL;
4104 case PCI_IVAR_SUBVENDOR:
4105 *result = cfg->subvendor;
4107 case PCI_IVAR_SUBDEVICE:
4108 *result = cfg->subdevice;
4110 case PCI_IVAR_VENDOR:
4111 *result = cfg->vendor;
4113 case PCI_IVAR_DEVICE:
4114 *result = cfg->device;
4116 case PCI_IVAR_DEVID:
4117 *result = (cfg->device << 16) | cfg->vendor;
4119 case PCI_IVAR_CLASS:
4120 *result = cfg->baseclass;
4122 case PCI_IVAR_SUBCLASS:
4123 *result = cfg->subclass;
4125 case PCI_IVAR_PROGIF:
4126 *result = cfg->progif;
4128 case PCI_IVAR_REVID:
4129 *result = cfg->revid;
4131 case PCI_IVAR_INTPIN:
4132 *result = cfg->intpin;
4135 *result = cfg->intline;
4137 case PCI_IVAR_DOMAIN:
4138 *result = cfg->domain;
4144 *result = cfg->slot;
4146 case PCI_IVAR_FUNCTION:
4147 *result = cfg->func;
4149 case PCI_IVAR_CMDREG:
4150 *result = cfg->cmdreg;
4152 case PCI_IVAR_CACHELNSZ:
4153 *result = cfg->cachelnsz;
4155 case PCI_IVAR_MINGNT:
4156 *result = cfg->mingnt;
4158 case PCI_IVAR_MAXLAT:
4159 *result = cfg->maxlat;
4161 case PCI_IVAR_LATTIMER:
4162 *result = cfg->lattimer;
4171 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
4173 struct pci_devinfo *dinfo;
4175 dinfo = device_get_ivars(child);
4178 case PCI_IVAR_INTPIN:
4179 dinfo->cfg.intpin = value;
4181 case PCI_IVAR_ETHADDR:
4182 case PCI_IVAR_SUBVENDOR:
4183 case PCI_IVAR_SUBDEVICE:
4184 case PCI_IVAR_VENDOR:
4185 case PCI_IVAR_DEVICE:
4186 case PCI_IVAR_DEVID:
4187 case PCI_IVAR_CLASS:
4188 case PCI_IVAR_SUBCLASS:
4189 case PCI_IVAR_PROGIF:
4190 case PCI_IVAR_REVID:
4192 case PCI_IVAR_DOMAIN:
4195 case PCI_IVAR_FUNCTION:
4196 return (EINVAL); /* disallow for now */
4203 #include "opt_ddb.h"
4205 #include <ddb/ddb.h>
4206 #include <sys/cons.h>
4209 * List resources based on pci map registers, used for within ddb
4212 DB_SHOW_COMMAND(pciregs, db_pci_dump)
4214 struct pci_devinfo *dinfo;
4215 struct devlist *devlist_head;
4218 int i, error, none_count;
4221 /* get the head of the device queue */
4222 devlist_head = &pci_devq;
4225 * Go through the list of devices and print out devices
4227 for (error = 0, i = 0,
4228 dinfo = STAILQ_FIRST(devlist_head);
4229 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit;
4230 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
4232 /* Populate pd_name and pd_unit */
4235 name = device_get_name(dinfo->cfg.dev);
4238 db_printf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x "
4239 "chip=0x%08x rev=0x%02x hdr=0x%02x\n",
4240 (name && *name) ? name : "none",
4241 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) :
4243 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev,
4244 p->pc_sel.pc_func, (p->pc_class << 16) |
4245 (p->pc_subclass << 8) | p->pc_progif,
4246 (p->pc_subdevice << 16) | p->pc_subvendor,
4247 (p->pc_device << 16) | p->pc_vendor,
4248 p->pc_revid, p->pc_hdr);
4253 static struct resource *
4254 pci_reserve_map(device_t dev, device_t child, int type, int *rid,
4255 u_long start, u_long end, u_long count, u_int flags)
4257 struct pci_devinfo *dinfo = device_get_ivars(child);
4258 struct resource_list *rl = &dinfo->resources;
4259 struct resource *res;
4261 pci_addr_t map, testval;
4265 pm = pci_find_bar(child, *rid);
4267 /* This is a BAR that we failed to allocate earlier. */
4268 mapsize = pm->pm_size;
4272 * Weed out the bogons, and figure out how large the
4273 * BAR/map is. BARs that read back 0 here are bogus
4274 * and unimplemented. Note: atapci in legacy mode are
4275 * special and handled elsewhere in the code. If you
4276 * have a atapci device in legacy mode and it fails
4277 * here, that other code is broken.
4279 pci_read_bar(child, *rid, &map, &testval);
4282 * Determine the size of the BAR and ignore BARs with a size
4283 * of 0. Device ROM BARs use a different mask value.
4285 if (PCIR_IS_BIOS(&dinfo->cfg, *rid))
4286 mapsize = pci_romsize(testval);
4288 mapsize = pci_mapsize(testval);
4291 pm = pci_add_bar(child, *rid, map, mapsize);
4294 if (PCI_BAR_MEM(map) || PCIR_IS_BIOS(&dinfo->cfg, *rid)) {
4295 if (type != SYS_RES_MEMORY) {
4298 "child %s requested type %d for rid %#x,"
4299 " but the BAR says it is an memio\n",
4300 device_get_nameunit(child), type, *rid);
4304 if (type != SYS_RES_IOPORT) {
4307 "child %s requested type %d for rid %#x,"
4308 " but the BAR says it is an ioport\n",
4309 device_get_nameunit(child), type, *rid);
4315 * For real BARs, we need to override the size that
4316 * the driver requests, because that's what the BAR
4317 * actually uses and we would otherwise have a
4318 * situation where we might allocate the excess to
4319 * another driver, which won't work.
4321 count = (pci_addr_t)1 << mapsize;
4322 if (RF_ALIGNMENT(flags) < mapsize)
4323 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize);
4324 if (PCI_BAR_MEM(map) && (map & PCIM_BAR_MEM_PREFETCH))
4325 flags |= RF_PREFETCHABLE;
4328 * Allocate enough resource, and then write back the
4329 * appropriate BAR for that resource.
4331 resource_list_add(rl, type, *rid, start, end, count);
4332 res = resource_list_reserve(rl, dev, child, type, rid, start, end,
4333 count, flags & ~RF_ACTIVE);
4335 resource_list_delete(rl, type, *rid);
4336 device_printf(child,
4337 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n",
4338 count, *rid, type, start, end);
4342 device_printf(child,
4343 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n",
4344 count, *rid, type, rman_get_start(res));
4345 map = rman_get_start(res);
4346 pci_write_bar(child, pm, map);
4352 pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
4353 u_long start, u_long end, u_long count, u_int flags)
4355 struct pci_devinfo *dinfo;
4356 struct resource_list *rl;
4357 struct resource_list_entry *rle;
4358 struct resource *res;
4361 if (device_get_parent(child) != dev)
4362 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
4363 type, rid, start, end, count, flags));
4366 * Perform lazy resource allocation
4368 dinfo = device_get_ivars(child);
4369 rl = &dinfo->resources;
4374 * Can't alloc legacy interrupt once MSI messages have
4377 if (*rid == 0 && (cfg->msi.msi_alloc > 0 ||
4378 cfg->msix.msix_alloc > 0))
4382 * If the child device doesn't have an interrupt
4383 * routed and is deserving of an interrupt, try to
4386 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) &&
4388 pci_assign_interrupt(dev, child, 0);
4390 case SYS_RES_IOPORT:
4391 case SYS_RES_MEMORY:
4394 * PCI-PCI bridge I/O window resources are not BARs.
4395 * For those allocations just pass the request up the
4398 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE) {
4400 case PCIR_IOBASEL_1:
4401 case PCIR_MEMBASE_1:
4402 case PCIR_PMBASEL_1:
4404 * XXX: Should we bother creating a resource
4407 return (bus_generic_alloc_resource(dev, child,
4408 type, rid, start, end, count, flags));
4412 /* Reserve resources for this BAR if needed. */
4413 rle = resource_list_find(rl, type, *rid);
4415 res = pci_reserve_map(dev, child, type, rid, start, end,
4421 return (resource_list_alloc(rl, dev, child, type, rid,
4422 start, end, count, flags));
4426 pci_release_resource(device_t dev, device_t child, int type, int rid,
4429 struct pci_devinfo *dinfo;
4430 struct resource_list *rl;
4433 if (device_get_parent(child) != dev)
4434 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
4437 dinfo = device_get_ivars(child);
4441 * PCI-PCI bridge I/O window resources are not BARs. For
4442 * those allocations just pass the request up the tree.
4444 if (cfg->hdrtype == PCIM_HDRTYPE_BRIDGE &&
4445 (type == SYS_RES_IOPORT || type == SYS_RES_MEMORY)) {
4447 case PCIR_IOBASEL_1:
4448 case PCIR_MEMBASE_1:
4449 case PCIR_PMBASEL_1:
4450 return (bus_generic_release_resource(dev, child, type,
4456 rl = &dinfo->resources;
4457 return (resource_list_release(rl, dev, child, type, rid, r));
4461 pci_activate_resource(device_t dev, device_t child, int type, int rid,
4464 struct pci_devinfo *dinfo;
4467 error = bus_generic_activate_resource(dev, child, type, rid, r);
4471 /* Enable decoding in the command register when activating BARs. */
4472 if (device_get_parent(child) == dev) {
4473 /* Device ROMs need their decoding explicitly enabled. */
4474 dinfo = device_get_ivars(child);
4475 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid))
4476 pci_write_bar(child, pci_find_bar(child, rid),
4477 rman_get_start(r) | PCIM_BIOS_ENABLE);
4479 case SYS_RES_IOPORT:
4480 case SYS_RES_MEMORY:
4481 error = PCI_ENABLE_IO(dev, child, type);
4489 pci_deactivate_resource(device_t dev, device_t child, int type,
4490 int rid, struct resource *r)
4492 struct pci_devinfo *dinfo;
4495 error = bus_generic_deactivate_resource(dev, child, type, rid, r);
4499 /* Disable decoding for device ROMs. */
4500 if (device_get_parent(child) == dev) {
4501 dinfo = device_get_ivars(child);
4502 if (type == SYS_RES_MEMORY && PCIR_IS_BIOS(&dinfo->cfg, rid))
4503 pci_write_bar(child, pci_find_bar(child, rid),
4510 pci_delete_child(device_t dev, device_t child)
4512 struct resource_list_entry *rle;
4513 struct resource_list *rl;
4514 struct pci_devinfo *dinfo;
4516 dinfo = device_get_ivars(child);
4517 rl = &dinfo->resources;
4519 if (device_is_attached(child))
4520 device_detach(child);
4522 /* Turn off access to resources we're about to free */
4523 pci_write_config(child, PCIR_COMMAND, pci_read_config(child,
4524 PCIR_COMMAND, 2) & ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN), 2);
4526 /* Free all allocated resources */
4527 STAILQ_FOREACH(rle, rl, link) {
4529 if (rman_get_flags(rle->res) & RF_ACTIVE ||
4530 resource_list_busy(rl, rle->type, rle->rid)) {
4531 pci_printf(&dinfo->cfg,
4532 "Resource still owned, oops. "
4533 "(type=%d, rid=%d, addr=%lx)\n",
4534 rle->type, rle->rid,
4535 rman_get_start(rle->res));
4536 bus_release_resource(child, rle->type, rle->rid,
4539 resource_list_unreserve(rl, dev, child, rle->type,
4543 resource_list_free(rl);
4545 device_delete_child(dev, child);
4550 pci_delete_resource(device_t dev, device_t child, int type, int rid)
4552 struct pci_devinfo *dinfo;
4553 struct resource_list *rl;
4554 struct resource_list_entry *rle;
4556 if (device_get_parent(child) != dev)
4559 dinfo = device_get_ivars(child);
4560 rl = &dinfo->resources;
4561 rle = resource_list_find(rl, type, rid);
4566 if (rman_get_flags(rle->res) & RF_ACTIVE ||
4567 resource_list_busy(rl, type, rid)) {
4568 device_printf(dev, "delete_resource: "
4569 "Resource still owned by child, oops. "
4570 "(type=%d, rid=%d, addr=%lx)\n",
4571 type, rid, rman_get_start(rle->res));
4574 resource_list_unreserve(rl, dev, child, type, rid);
4576 resource_list_delete(rl, type, rid);
4579 struct resource_list *
4580 pci_get_resource_list (device_t dev, device_t child)
4582 struct pci_devinfo *dinfo = device_get_ivars(child);
4584 return (&dinfo->resources);
4588 pci_get_dma_tag(device_t bus, device_t dev)
4590 struct pci_softc *sc = device_get_softc(bus);
4592 return (sc->sc_dma_tag);
4596 pci_read_config_method(device_t dev, device_t child, int reg, int width)
4598 struct pci_devinfo *dinfo = device_get_ivars(child);
4599 pcicfgregs *cfg = &dinfo->cfg;
4601 return (PCIB_READ_CONFIG(device_get_parent(dev),
4602 cfg->bus, cfg->slot, cfg->func, reg, width));
4606 pci_write_config_method(device_t dev, device_t child, int reg,
4607 uint32_t val, int width)
4609 struct pci_devinfo *dinfo = device_get_ivars(child);
4610 pcicfgregs *cfg = &dinfo->cfg;
4612 PCIB_WRITE_CONFIG(device_get_parent(dev),
4613 cfg->bus, cfg->slot, cfg->func, reg, val, width);
4617 pci_child_location_str_method(device_t dev, device_t child, char *buf,
4621 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
4622 pci_get_function(child));
4627 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
4630 struct pci_devinfo *dinfo;
4633 dinfo = device_get_ivars(child);
4635 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
4636 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
4637 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
4643 pci_assign_interrupt_method(device_t dev, device_t child)
4645 struct pci_devinfo *dinfo = device_get_ivars(child);
4646 pcicfgregs *cfg = &dinfo->cfg;
4648 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
4653 pci_modevent(module_t mod, int what, void *arg)
4655 static struct cdev *pci_cdev;
4659 STAILQ_INIT(&pci_devq);
4661 pci_cdev = make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644,
4663 pci_load_vendor_data();
4667 destroy_dev(pci_cdev);
4675 pci_cfg_restore_pcie(device_t dev, struct pci_devinfo *dinfo)
4677 #define WREG(n, v) pci_write_config(dev, pos + (n), (v), 2)
4678 struct pcicfg_pcie *cfg;
4681 cfg = &dinfo->cfg.pcie;
4682 pos = cfg->pcie_location;
4684 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION;
4686 WREG(PCIER_DEVICE_CTL, cfg->pcie_device_ctl);
4688 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
4689 cfg->pcie_type == PCIEM_TYPE_ENDPOINT ||
4690 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT)
4691 WREG(PCIER_LINK_CTL, cfg->pcie_link_ctl);
4693 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
4694 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT &&
4695 (cfg->pcie_flags & PCIEM_FLAGS_SLOT))))
4696 WREG(PCIER_SLOT_CTL, cfg->pcie_slot_ctl);
4698 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
4699 cfg->pcie_type == PCIEM_TYPE_ROOT_EC)
4700 WREG(PCIER_ROOT_CTL, cfg->pcie_root_ctl);
4703 WREG(PCIER_DEVICE_CTL2, cfg->pcie_device_ctl2);
4704 WREG(PCIER_LINK_CTL2, cfg->pcie_link_ctl2);
4705 WREG(PCIER_SLOT_CTL2, cfg->pcie_slot_ctl2);
4711 pci_cfg_restore_pcix(device_t dev, struct pci_devinfo *dinfo)
4713 pci_write_config(dev, dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND,
4714 dinfo->cfg.pcix.pcix_command, 2);
4718 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
4722 * Only do header type 0 devices. Type 1 devices are bridges,
4723 * which we know need special treatment. Type 2 devices are
4724 * cardbus bridges which also require special treatment.
4725 * Other types are unknown, and we err on the side of safety
4728 if ((dinfo->cfg.hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL)
4732 * Restore the device to full power mode. We must do this
4733 * before we restore the registers because moving from D3 to
4734 * D0 will cause the chip's BARs and some other registers to
4735 * be reset to some unknown power on reset values. Cut down
4736 * the noise on boot by doing nothing if we are already in
4739 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0)
4740 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
4741 pci_restore_bars(dev);
4742 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
4743 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
4744 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
4745 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
4746 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
4747 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
4748 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
4749 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1);
4750 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1);
4753 * Restore extended capabilities for PCI-Express and PCI-X
4755 if (dinfo->cfg.pcie.pcie_location != 0)
4756 pci_cfg_restore_pcie(dev, dinfo);
4757 if (dinfo->cfg.pcix.pcix_location != 0)
4758 pci_cfg_restore_pcix(dev, dinfo);
4760 /* Restore MSI and MSI-X configurations if they are present. */
4761 if (dinfo->cfg.msi.msi_location != 0)
4762 pci_resume_msi(dev);
4763 if (dinfo->cfg.msix.msix_location != 0)
4764 pci_resume_msix(dev);
4768 pci_cfg_save_pcie(device_t dev, struct pci_devinfo *dinfo)
4770 #define RREG(n) pci_read_config(dev, pos + (n), 2)
4771 struct pcicfg_pcie *cfg;
4774 cfg = &dinfo->cfg.pcie;
4775 pos = cfg->pcie_location;
4777 cfg->pcie_flags = RREG(PCIER_FLAGS);
4779 version = cfg->pcie_flags & PCIEM_FLAGS_VERSION;
4781 cfg->pcie_device_ctl = RREG(PCIER_DEVICE_CTL);
4783 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
4784 cfg->pcie_type == PCIEM_TYPE_ENDPOINT ||
4785 cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT)
4786 cfg->pcie_link_ctl = RREG(PCIER_LINK_CTL);
4788 if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
4789 (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT &&
4790 (cfg->pcie_flags & PCIEM_FLAGS_SLOT))))
4791 cfg->pcie_slot_ctl = RREG(PCIER_SLOT_CTL);
4793 if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT ||
4794 cfg->pcie_type == PCIEM_TYPE_ROOT_EC)
4795 cfg->pcie_root_ctl = RREG(PCIER_ROOT_CTL);
4798 cfg->pcie_device_ctl2 = RREG(PCIER_DEVICE_CTL2);
4799 cfg->pcie_link_ctl2 = RREG(PCIER_LINK_CTL2);
4800 cfg->pcie_slot_ctl2 = RREG(PCIER_SLOT_CTL2);
4806 pci_cfg_save_pcix(device_t dev, struct pci_devinfo *dinfo)
4808 dinfo->cfg.pcix.pcix_command = pci_read_config(dev,
4809 dinfo->cfg.pcix.pcix_location + PCIXR_COMMAND, 2);
4813 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate)
4819 * Only do header type 0 devices. Type 1 devices are bridges, which
4820 * we know need special treatment. Type 2 devices are cardbus bridges
4821 * which also require special treatment. Other types are unknown, and
4822 * we err on the side of safety by ignoring them. Powering down
4823 * bridges should not be undertaken lightly.
4825 if ((dinfo->cfg.hdrtype & PCIM_HDRTYPE) != PCIM_HDRTYPE_NORMAL)
4829 * Some drivers apparently write to these registers w/o updating our
4830 * cached copy. No harm happens if we update the copy, so do so here
4831 * so we can restore them. The COMMAND register is modified by the
4832 * bus w/o updating the cache. This should represent the normally
4833 * writable portion of the 'defined' part of type 0 headers. In
4834 * theory we also need to save/restore the PCI capability structures
4835 * we know about, but apart from power we don't know any that are
4838 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2);
4839 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2);
4840 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2);
4841 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2);
4842 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
4843 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
4844 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
4845 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
4846 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
4847 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
4848 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
4849 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1);
4850 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1);
4851 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1);
4852 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1);
4854 if (dinfo->cfg.pcie.pcie_location != 0)
4855 pci_cfg_save_pcie(dev, dinfo);
4857 if (dinfo->cfg.pcix.pcix_location != 0)
4858 pci_cfg_save_pcix(dev, dinfo);
4861 * don't set the state for display devices, base peripherals and
4862 * memory devices since bad things happen when they are powered down.
4863 * We should (a) have drivers that can easily detach and (b) use
4864 * generic drivers for these devices so that some device actually
4865 * attaches. We need to make sure that when we implement (a) we don't
4866 * power the device down on a reattach.
4868 cls = pci_get_class(dev);
4871 switch (pci_do_power_nodriver)
4873 case 0: /* NO powerdown at all */
4875 case 1: /* Conservative about what to power down */
4876 if (cls == PCIC_STORAGE)
4879 case 2: /* Agressive about what to power down */
4880 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY ||
4881 cls == PCIC_BASEPERIPH)
4884 case 3: /* Power down everything */
4888 * PCI spec says we can only go into D3 state from D0 state.
4889 * Transition from D[12] into D0 before going to D3 state.
4891 ps = pci_get_powerstate(dev);
4892 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
4893 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
4894 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3)
4895 pci_set_powerstate(dev, PCI_POWERSTATE_D3);
4898 /* Wrapper APIs suitable for device driver use. */
4900 pci_save_state(device_t dev)
4902 struct pci_devinfo *dinfo;
4904 dinfo = device_get_ivars(dev);
4905 pci_cfg_save(dev, dinfo, 0);
4909 pci_restore_state(device_t dev)
4911 struct pci_devinfo *dinfo;
4913 dinfo = device_get_ivars(dev);
4914 pci_cfg_restore(dev, dinfo);
4918 pci_get_rid_method(device_t dev, device_t child)
4921 return (PCIB_GET_RID(device_get_parent(dev), child));