2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 * PCIM_xxx: mask to locate subfield in register
32 * PCIR_xxx: config register offset
33 * PCIC_xxx: device class
34 * PCIS_xxx: device subclass
35 * PCIP_xxx: device programming interface
36 * PCIV_xxx: PCI vendor ID (only required to fixup ancient devices)
38 * PCIY_xxx: capability identification number
39 * PCIZ_xxx: extended capability identification number
42 /* some PCI bus constants */
43 #define PCI_DOMAINMAX 65535 /* highest supported domain number */
44 #define PCI_BUSMAX 255 /* highest supported bus number */
45 #define PCI_SLOTMAX 31 /* highest supported slot number */
46 #define PCI_FUNCMAX 7 /* highest supported function number */
47 #define PCI_REGMAX 255 /* highest supported config register addr. */
48 #define PCIE_REGMAX 4095 /* highest supported config register addr. */
49 #define PCI_MAXHDRTYPE 2
51 /* PCI config header registers for all devices */
53 #define PCIR_DEVVENDOR 0x00
54 #define PCIR_VENDOR 0x00
55 #define PCIR_DEVICE 0x02
56 #define PCIR_COMMAND 0x04
57 #define PCIM_CMD_PORTEN 0x0001
58 #define PCIM_CMD_MEMEN 0x0002
59 #define PCIM_CMD_BUSMASTEREN 0x0004
60 #define PCIM_CMD_SPECIALEN 0x0008
61 #define PCIM_CMD_MWRICEN 0x0010
62 #define PCIM_CMD_PERRESPEN 0x0040
63 #define PCIM_CMD_SERRESPEN 0x0100
64 #define PCIM_CMD_BACKTOBACK 0x0200
65 #define PCIM_CMD_INTxDIS 0x0400
66 #define PCIR_STATUS 0x06
67 #define PCIM_STATUS_CAPPRESENT 0x0010
68 #define PCIM_STATUS_66CAPABLE 0x0020
69 #define PCIM_STATUS_BACKTOBACK 0x0080
70 #define PCIM_STATUS_MDPERR 0x0100
71 #define PCIM_STATUS_SEL_FAST 0x0000
72 #define PCIM_STATUS_SEL_MEDIMUM 0x0200
73 #define PCIM_STATUS_SEL_SLOW 0x0400
74 #define PCIM_STATUS_SEL_MASK 0x0600
75 #define PCIM_STATUS_STABORT 0x0800
76 #define PCIM_STATUS_RTABORT 0x1000
77 #define PCIM_STATUS_RMABORT 0x2000
78 #define PCIM_STATUS_SERR 0x4000
79 #define PCIM_STATUS_PERR 0x8000
80 #define PCIR_REVID 0x08
81 #define PCIR_PROGIF 0x09
82 #define PCIR_SUBCLASS 0x0a
83 #define PCIR_CLASS 0x0b
84 #define PCIR_CACHELNSZ 0x0c
85 #define PCIR_LATTIMER 0x0d
86 #define PCIR_HDRTYPE 0x0e
87 #define PCIM_HDRTYPE 0x7f
88 #define PCIM_HDRTYPE_NORMAL 0x00
89 #define PCIM_HDRTYPE_BRIDGE 0x01
90 #define PCIM_HDRTYPE_CARDBUS 0x02
91 #define PCIM_MFDEV 0x80
92 #define PCIR_BIST 0x0f
94 /* Capability Register Offsets */
97 #define PCICAP_NEXTPTR 0x1
99 /* Capability Identification Numbers */
101 #define PCIY_PMG 0x01 /* PCI Power Management */
102 #define PCIY_AGP 0x02 /* AGP */
103 #define PCIY_VPD 0x03 /* Vital Product Data */
104 #define PCIY_SLOTID 0x04 /* Slot Identification */
105 #define PCIY_MSI 0x05 /* Message Signaled Interrupts */
106 #define PCIY_CHSWP 0x06 /* CompactPCI Hot Swap */
107 #define PCIY_PCIX 0x07 /* PCI-X */
108 #define PCIY_HT 0x08 /* HyperTransport */
109 #define PCIY_VENDOR 0x09 /* Vendor Unique */
110 #define PCIY_DEBUG 0x0a /* Debug port */
111 #define PCIY_CRES 0x0b /* CompactPCI central resource control */
112 #define PCIY_HOTPLUG 0x0c /* PCI Hot-Plug */
113 #define PCIY_SUBVENDOR 0x0d /* PCI-PCI bridge subvendor ID */
114 #define PCIY_AGP8X 0x0e /* AGP 8x */
115 #define PCIY_SECDEV 0x0f /* Secure Device */
116 #define PCIY_EXPRESS 0x10 /* PCI Express */
117 #define PCIY_MSIX 0x11 /* MSI-X */
118 #define PCIY_SATA 0x12 /* SATA */
119 #define PCIY_PCIAF 0x13 /* PCI Advanced Features */
121 /* Extended Capability Register Fields */
123 #define PCIR_EXTCAP 0x100
124 #define PCIM_EXTCAP_ID 0x0000ffff
125 #define PCIM_EXTCAP_VER 0x000f0000
126 #define PCIM_EXTCAP_NEXTPTR 0xfff00000
127 #define PCI_EXTCAP_ID(ecap) ((ecap) & PCIM_EXTCAP_ID)
128 #define PCI_EXTCAP_VER(ecap) (((ecap) & PCIM_EXTCAP_VER) >> 16)
129 #define PCI_EXTCAP_NEXTPTR(ecap) (((ecap) & PCIM_EXTCAP_NEXTPTR) >> 20)
131 /* Extended Capability Identification Numbers */
133 #define PCIZ_AER 0x0001 /* Advanced Error Reporting */
134 #define PCIZ_VC 0x0002 /* Virtual Channel */
135 #define PCIZ_SERNUM 0x0003 /* Device Serial Number */
136 #define PCIZ_PWRBDGT 0x0004 /* Power Budgeting */
137 #define PCIZ_VENDOR 0x000b /* Vendor Unique */
138 #define PCIZ_ACS 0x000d /* Access Control Services */
139 #define PCIZ_ARI 0x000e /* Alternative Routing-ID Interpretation */
140 #define PCIZ_ATS 0x000f /* Address Translation Services */
141 #define PCIZ_SRIOV 0x0010 /* Single Root IO Virtualization */
143 /* config registers for header type 0 devices */
145 #define PCIR_BARS 0x10
146 #define PCIR_BAR(x) (PCIR_BARS + (x) * 4)
147 #define PCIR_MAX_BAR_0 5
148 #define PCI_RID2BAR(rid) (((rid) - PCIR_BARS) / 4)
149 #define PCI_BAR_IO(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_IO_SPACE)
150 #define PCI_BAR_MEM(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_MEM_SPACE)
151 #define PCIM_BAR_SPACE 0x00000001
152 #define PCIM_BAR_MEM_SPACE 0
153 #define PCIM_BAR_IO_SPACE 1
154 #define PCIM_BAR_MEM_TYPE 0x00000006
155 #define PCIM_BAR_MEM_32 0
156 #define PCIM_BAR_MEM_1MB 2 /* Locate below 1MB in PCI <= 2.1 */
157 #define PCIM_BAR_MEM_64 4
158 #define PCIM_BAR_MEM_PREFETCH 0x00000008
159 #define PCIM_BAR_MEM_BASE 0xfffffffffffffff0ULL
160 #define PCIM_BAR_IO_RESERVED 0x00000002
161 #define PCIM_BAR_IO_BASE 0xfffffffc
162 #define PCIR_CIS 0x28
163 #define PCIM_CIS_ASI_MASK 0x00000007
164 #define PCIM_CIS_ASI_CONFIG 0
165 #define PCIM_CIS_ASI_BAR0 1
166 #define PCIM_CIS_ASI_BAR1 2
167 #define PCIM_CIS_ASI_BAR2 3
168 #define PCIM_CIS_ASI_BAR3 4
169 #define PCIM_CIS_ASI_BAR4 5
170 #define PCIM_CIS_ASI_BAR5 6
171 #define PCIM_CIS_ASI_ROM 7
172 #define PCIM_CIS_ADDR_MASK 0x0ffffff8
173 #define PCIM_CIS_ROM_MASK 0xf0000000
174 #define PCIM_CIS_CONFIG_MASK 0xff
175 #define PCIR_SUBVEND_0 0x2c
176 #define PCIR_SUBDEV_0 0x2e
177 #define PCIR_BIOS 0x30
178 #define PCIM_BIOS_ENABLE 0x01
179 #define PCIM_BIOS_ADDR_MASK 0xfffff800
180 #define PCIR_CAP_PTR 0x34
181 #define PCIR_INTLINE 0x3c
182 #define PCIR_INTPIN 0x3d
183 #define PCIR_MINGNT 0x3e
184 #define PCIR_MAXLAT 0x3f
186 /* config registers for header type 1 (PCI-to-PCI bridge) devices */
188 #define PCIR_MAX_BAR_1 1
189 #define PCIR_SECSTAT_1 0x1e
191 #define PCIR_PRIBUS_1 0x18
192 #define PCIR_SECBUS_1 0x19
193 #define PCIR_SUBBUS_1 0x1a
194 #define PCIR_SECLAT_1 0x1b
196 #define PCIR_IOBASEL_1 0x1c
197 #define PCIR_IOLIMITL_1 0x1d
198 #define PCIR_IOBASEH_1 0x30
199 #define PCIR_IOLIMITH_1 0x32
200 #define PCIM_BRIO_16 0x0
201 #define PCIM_BRIO_32 0x1
202 #define PCIM_BRIO_MASK 0xf
204 #define PCIR_MEMBASE_1 0x20
205 #define PCIR_MEMLIMIT_1 0x22
207 #define PCIR_PMBASEL_1 0x24
208 #define PCIR_PMLIMITL_1 0x26
209 #define PCIR_PMBASEH_1 0x28
210 #define PCIR_PMLIMITH_1 0x2c
211 #define PCIM_BRPM_32 0x0
212 #define PCIM_BRPM_64 0x1
213 #define PCIM_BRPM_MASK 0xf
215 #define PCIR_BIOS_1 0x38
216 #define PCIR_BRIDGECTL_1 0x3e
218 /* config registers for header type 2 (CardBus) devices */
220 #define PCIR_MAX_BAR_2 0
221 #define PCIR_CAP_PTR_2 0x14
222 #define PCIR_SECSTAT_2 0x16
224 #define PCIR_PRIBUS_2 0x18
225 #define PCIR_SECBUS_2 0x19
226 #define PCIR_SUBBUS_2 0x1a
227 #define PCIR_SECLAT_2 0x1b
229 #define PCIR_MEMBASE0_2 0x1c
230 #define PCIR_MEMLIMIT0_2 0x20
231 #define PCIR_MEMBASE1_2 0x24
232 #define PCIR_MEMLIMIT1_2 0x28
233 #define PCIR_IOBASE0_2 0x2c
234 #define PCIR_IOLIMIT0_2 0x30
235 #define PCIR_IOBASE1_2 0x34
236 #define PCIR_IOLIMIT1_2 0x38
238 #define PCIR_BRIDGECTL_2 0x3e
240 #define PCIR_SUBVEND_2 0x40
241 #define PCIR_SUBDEV_2 0x42
243 #define PCIR_PCCARDIF_2 0x44
245 /* PCI device class, subclass and programming interface definitions */
247 #define PCIC_OLD 0x00
248 #define PCIS_OLD_NONVGA 0x00
249 #define PCIS_OLD_VGA 0x01
251 #define PCIC_STORAGE 0x01
252 #define PCIS_STORAGE_SCSI 0x00
253 #define PCIS_STORAGE_IDE 0x01
254 #define PCIP_STORAGE_IDE_MODEPRIM 0x01
255 #define PCIP_STORAGE_IDE_PROGINDPRIM 0x02
256 #define PCIP_STORAGE_IDE_MODESEC 0x04
257 #define PCIP_STORAGE_IDE_PROGINDSEC 0x08
258 #define PCIP_STORAGE_IDE_MASTERDEV 0x80
259 #define PCIS_STORAGE_FLOPPY 0x02
260 #define PCIS_STORAGE_IPI 0x03
261 #define PCIS_STORAGE_RAID 0x04
262 #define PCIS_STORAGE_ATA_ADMA 0x05
263 #define PCIS_STORAGE_SATA 0x06
264 #define PCIP_STORAGE_SATA_AHCI_1_0 0x01
265 #define PCIS_STORAGE_SAS 0x07
266 #define PCIS_STORAGE_OTHER 0x80
268 #define PCIC_NETWORK 0x02
269 #define PCIS_NETWORK_ETHERNET 0x00
270 #define PCIS_NETWORK_TOKENRING 0x01
271 #define PCIS_NETWORK_FDDI 0x02
272 #define PCIS_NETWORK_ATM 0x03
273 #define PCIS_NETWORK_ISDN 0x04
274 #define PCIS_NETWORK_WORLDFIP 0x05
275 #define PCIS_NETWORK_PICMG 0x06
276 #define PCIS_NETWORK_OTHER 0x80
278 #define PCIC_DISPLAY 0x03
279 #define PCIS_DISPLAY_VGA 0x00
280 #define PCIS_DISPLAY_XGA 0x01
281 #define PCIS_DISPLAY_3D 0x02
282 #define PCIS_DISPLAY_OTHER 0x80
284 #define PCIC_MULTIMEDIA 0x04
285 #define PCIS_MULTIMEDIA_VIDEO 0x00
286 #define PCIS_MULTIMEDIA_AUDIO 0x01
287 #define PCIS_MULTIMEDIA_TELE 0x02
288 #define PCIS_MULTIMEDIA_HDA 0x03
289 #define PCIS_MULTIMEDIA_OTHER 0x80
291 #define PCIC_MEMORY 0x05
292 #define PCIS_MEMORY_RAM 0x00
293 #define PCIS_MEMORY_FLASH 0x01
294 #define PCIS_MEMORY_OTHER 0x80
296 #define PCIC_BRIDGE 0x06
297 #define PCIS_BRIDGE_HOST 0x00
298 #define PCIS_BRIDGE_ISA 0x01
299 #define PCIS_BRIDGE_EISA 0x02
300 #define PCIS_BRIDGE_MCA 0x03
301 #define PCIS_BRIDGE_PCI 0x04
302 #define PCIP_BRIDGE_PCI_SUBTRACTIVE 0x01
303 #define PCIS_BRIDGE_PCMCIA 0x05
304 #define PCIS_BRIDGE_NUBUS 0x06
305 #define PCIS_BRIDGE_CARDBUS 0x07
306 #define PCIS_BRIDGE_RACEWAY 0x08
307 #define PCIS_BRIDGE_PCI_TRANSPARENT 0x09
308 #define PCIS_BRIDGE_INFINIBAND 0x0a
309 #define PCIS_BRIDGE_OTHER 0x80
311 #define PCIC_SIMPLECOMM 0x07
312 #define PCIS_SIMPLECOMM_UART 0x00
313 #define PCIP_SIMPLECOMM_UART_8250 0x00
314 #define PCIP_SIMPLECOMM_UART_16450A 0x01
315 #define PCIP_SIMPLECOMM_UART_16550A 0x02
316 #define PCIP_SIMPLECOMM_UART_16650A 0x03
317 #define PCIP_SIMPLECOMM_UART_16750A 0x04
318 #define PCIP_SIMPLECOMM_UART_16850A 0x05
319 #define PCIP_SIMPLECOMM_UART_16950A 0x06
320 #define PCIS_SIMPLECOMM_PAR 0x01
321 #define PCIS_SIMPLECOMM_MULSER 0x02
322 #define PCIS_SIMPLECOMM_MODEM 0x03
323 #define PCIS_SIMPLECOMM_GPIB 0x04
324 #define PCIS_SIMPLECOMM_SMART_CARD 0x05
325 #define PCIS_SIMPLECOMM_OTHER 0x80
327 #define PCIC_BASEPERIPH 0x08
328 #define PCIS_BASEPERIPH_PIC 0x00
329 #define PCIP_BASEPERIPH_PIC_8259A 0x00
330 #define PCIP_BASEPERIPH_PIC_ISA 0x01
331 #define PCIP_BASEPERIPH_PIC_EISA 0x02
332 #define PCIP_BASEPERIPH_PIC_IO_APIC 0x10
333 #define PCIP_BASEPERIPH_PIC_IOX_APIC 0x20
334 #define PCIS_BASEPERIPH_DMA 0x01
335 #define PCIS_BASEPERIPH_TIMER 0x02
336 #define PCIS_BASEPERIPH_RTC 0x03
337 #define PCIS_BASEPERIPH_PCIHOT 0x04
338 #define PCIS_BASEPERIPH_SDHC 0x05
339 #define PCIS_BASEPERIPH_OTHER 0x80
341 #define PCIC_INPUTDEV 0x09
342 #define PCIS_INPUTDEV_KEYBOARD 0x00
343 #define PCIS_INPUTDEV_DIGITIZER 0x01
344 #define PCIS_INPUTDEV_MOUSE 0x02
345 #define PCIS_INPUTDEV_SCANNER 0x03
346 #define PCIS_INPUTDEV_GAMEPORT 0x04
347 #define PCIS_INPUTDEV_OTHER 0x80
349 #define PCIC_DOCKING 0x0a
350 #define PCIS_DOCKING_GENERIC 0x00
351 #define PCIS_DOCKING_OTHER 0x80
353 #define PCIC_PROCESSOR 0x0b
354 #define PCIS_PROCESSOR_386 0x00
355 #define PCIS_PROCESSOR_486 0x01
356 #define PCIS_PROCESSOR_PENTIUM 0x02
357 #define PCIS_PROCESSOR_ALPHA 0x10
358 #define PCIS_PROCESSOR_POWERPC 0x20
359 #define PCIS_PROCESSOR_MIPS 0x30
360 #define PCIS_PROCESSOR_COPROC 0x40
362 #define PCIC_SERIALBUS 0x0c
363 #define PCIS_SERIALBUS_FW 0x00
364 #define PCIS_SERIALBUS_ACCESS 0x01
365 #define PCIS_SERIALBUS_SSA 0x02
366 #define PCIS_SERIALBUS_USB 0x03
367 #define PCIP_SERIALBUS_USB_UHCI 0x00
368 #define PCIP_SERIALBUS_USB_OHCI 0x10
369 #define PCIP_SERIALBUS_USB_EHCI 0x20
370 #define PCIP_SERIALBUS_USB_XHCI 0x30
371 #define PCIP_SERIALBUS_USB_DEVICE 0xfe
372 #define PCIS_SERIALBUS_FC 0x04
373 #define PCIS_SERIALBUS_SMBUS 0x05
374 #define PCIS_SERIALBUS_INFINIBAND 0x06
375 #define PCIS_SERIALBUS_IPMI 0x07
376 #define PCIP_SERIALBUS_IPMI_SMIC 0x00
377 #define PCIP_SERIALBUS_IPMI_KCS 0x01
378 #define PCIP_SERIALBUS_IPMI_BT 0x02
379 #define PCIS_SERIALBUS_SERCOS 0x08
380 #define PCIS_SERIALBUS_CANBUS 0x09
382 #define PCIC_WIRELESS 0x0d
383 #define PCIS_WIRELESS_IRDA 0x00
384 #define PCIS_WIRELESS_IR 0x01
385 #define PCIS_WIRELESS_RF 0x10
386 #define PCIS_WIRELESS_BLUETOOTH 0x11
387 #define PCIS_WIRELESS_BROADBAND 0x12
388 #define PCIS_WIRELESS_80211A 0x20
389 #define PCIS_WIRELESS_80211B 0x21
390 #define PCIS_WIRELESS_OTHER 0x80
392 #define PCIC_INTELLIIO 0x0e
393 #define PCIS_INTELLIIO_I2O 0x00
395 #define PCIC_SATCOM 0x0f
396 #define PCIS_SATCOM_TV 0x01
397 #define PCIS_SATCOM_AUDIO 0x02
398 #define PCIS_SATCOM_VOICE 0x03
399 #define PCIS_SATCOM_DATA 0x04
401 #define PCIC_CRYPTO 0x10
402 #define PCIS_CRYPTO_NETCOMP 0x00
403 #define PCIS_CRYPTO_ENTERTAIN 0x10
404 #define PCIS_CRYPTO_OTHER 0x80
406 #define PCIC_DASP 0x11
407 #define PCIS_DASP_DPIO 0x00
408 #define PCIS_DASP_PERFCNTRS 0x01
409 #define PCIS_DASP_COMM_SYNC 0x10
410 #define PCIS_DASP_MGMT_CARD 0x20
411 #define PCIS_DASP_OTHER 0x80
413 #define PCIC_OTHER 0xff
415 /* Bridge Control Values. */
416 #define PCIB_BCR_PERR_ENABLE 0x0001
417 #define PCIB_BCR_SERR_ENABLE 0x0002
418 #define PCIB_BCR_ISA_ENABLE 0x0004
419 #define PCIB_BCR_VGA_ENABLE 0x0008
420 #define PCIB_BCR_MASTER_ABORT_MODE 0x0020
421 #define PCIB_BCR_SECBUS_RESET 0x0040
422 #define PCIB_BCR_SECBUS_BACKTOBACK 0x0080
423 #define PCIB_BCR_PRI_DISCARD_TIMEOUT 0x0100
424 #define PCIB_BCR_SEC_DISCARD_TIMEOUT 0x0200
425 #define PCIB_BCR_DISCARD_TIMER_STATUS 0x0400
426 #define PCIB_BCR_DISCARD_TIMER_SERREN 0x0800
428 /* PCI power manangement */
429 #define PCIR_POWER_CAP 0x2
430 #define PCIM_PCAP_SPEC 0x0007
431 #define PCIM_PCAP_PMEREQCLK 0x0008
432 #define PCIM_PCAP_DEVSPECINIT 0x0020
433 #define PCIM_PCAP_AUXPWR_0 0x0000
434 #define PCIM_PCAP_AUXPWR_55 0x0040
435 #define PCIM_PCAP_AUXPWR_100 0x0080
436 #define PCIM_PCAP_AUXPWR_160 0x00c0
437 #define PCIM_PCAP_AUXPWR_220 0x0100
438 #define PCIM_PCAP_AUXPWR_270 0x0140
439 #define PCIM_PCAP_AUXPWR_320 0x0180
440 #define PCIM_PCAP_AUXPWR_375 0x01c0
441 #define PCIM_PCAP_AUXPWRMASK 0x01c0
442 #define PCIM_PCAP_D1SUPP 0x0200
443 #define PCIM_PCAP_D2SUPP 0x0400
444 #define PCIM_PCAP_D0PME 0x0800
445 #define PCIM_PCAP_D1PME 0x1000
446 #define PCIM_PCAP_D2PME 0x2000
447 #define PCIM_PCAP_D3PME_HOT 0x4000
448 #define PCIM_PCAP_D3PME_COLD 0x8000
450 #define PCIR_POWER_STATUS 0x4
451 #define PCIM_PSTAT_D0 0x0000
452 #define PCIM_PSTAT_D1 0x0001
453 #define PCIM_PSTAT_D2 0x0002
454 #define PCIM_PSTAT_D3 0x0003
455 #define PCIM_PSTAT_DMASK 0x0003
456 #define PCIM_PSTAT_NOSOFTRESET 0x0008
457 #define PCIM_PSTAT_PMEENABLE 0x0100
458 #define PCIM_PSTAT_D0POWER 0x0000
459 #define PCIM_PSTAT_D1POWER 0x0200
460 #define PCIM_PSTAT_D2POWER 0x0400
461 #define PCIM_PSTAT_D3POWER 0x0600
462 #define PCIM_PSTAT_D0HEAT 0x0800
463 #define PCIM_PSTAT_D1HEAT 0x0a00
464 #define PCIM_PSTAT_D2HEAT 0x0c00
465 #define PCIM_PSTAT_D3HEAT 0x0e00
466 #define PCIM_PSTAT_DATASELMASK 0x1e00
467 #define PCIM_PSTAT_DATAUNKN 0x0000
468 #define PCIM_PSTAT_DATADIV10 0x2000
469 #define PCIM_PSTAT_DATADIV100 0x4000
470 #define PCIM_PSTAT_DATADIV1000 0x6000
471 #define PCIM_PSTAT_DATADIVMASK 0x6000
472 #define PCIM_PSTAT_PME 0x8000
474 #define PCIR_POWER_BSE 0x6
475 #define PCIM_PMCSR_BSE_D3B3 0x00
476 #define PCIM_PMCSR_BSE_D3B2 0x40
477 #define PCIM_PMCSR_BSE_BPCCE 0x80
479 #define PCIR_POWER_DATA 0x7
481 /* VPD capability registers */
482 #define PCIR_VPD_ADDR 0x2
483 #define PCIR_VPD_DATA 0x4
485 /* PCI Message Signalled Interrupts (MSI) */
486 #define PCIR_MSI_CTRL 0x2
487 #define PCIM_MSICTRL_VECTOR 0x0100
488 #define PCIM_MSICTRL_64BIT 0x0080
489 #define PCIM_MSICTRL_MME_MASK 0x0070
490 #define PCIM_MSICTRL_MME_1 0x0000
491 #define PCIM_MSICTRL_MME_2 0x0010
492 #define PCIM_MSICTRL_MME_4 0x0020
493 #define PCIM_MSICTRL_MME_8 0x0030
494 #define PCIM_MSICTRL_MME_16 0x0040
495 #define PCIM_MSICTRL_MME_32 0x0050
496 #define PCIM_MSICTRL_MMC_MASK 0x000E
497 #define PCIM_MSICTRL_MMC_1 0x0000
498 #define PCIM_MSICTRL_MMC_2 0x0002
499 #define PCIM_MSICTRL_MMC_4 0x0004
500 #define PCIM_MSICTRL_MMC_8 0x0006
501 #define PCIM_MSICTRL_MMC_16 0x0008
502 #define PCIM_MSICTRL_MMC_32 0x000A
503 #define PCIM_MSICTRL_MSI_ENABLE 0x0001
504 #define PCIR_MSI_ADDR 0x4
505 #define PCIR_MSI_ADDR_HIGH 0x8
506 #define PCIR_MSI_DATA 0x8
507 #define PCIR_MSI_DATA_64BIT 0xc
508 #define PCIR_MSI_MASK 0x10
509 #define PCIR_MSI_PENDING 0x14
511 /* PCI-X definitions */
513 /* For header type 0 devices */
514 #define PCIXR_COMMAND 0x2
515 #define PCIXM_COMMAND_DPERR_E 0x0001 /* Data Parity Error Recovery */
516 #define PCIXM_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */
517 #define PCIXM_COMMAND_MAX_READ 0x000c /* Maximum Burst Read Count */
518 #define PCIXM_COMMAND_MAX_READ_512 0x0000
519 #define PCIXM_COMMAND_MAX_READ_1024 0x0004
520 #define PCIXM_COMMAND_MAX_READ_2048 0x0008
521 #define PCIXM_COMMAND_MAX_READ_4096 0x000c
522 #define PCIXM_COMMAND_MAX_SPLITS 0x0070 /* Maximum Split Transactions */
523 #define PCIXM_COMMAND_MAX_SPLITS_1 0x0000
524 #define PCIXM_COMMAND_MAX_SPLITS_2 0x0010
525 #define PCIXM_COMMAND_MAX_SPLITS_3 0x0020
526 #define PCIXM_COMMAND_MAX_SPLITS_4 0x0030
527 #define PCIXM_COMMAND_MAX_SPLITS_8 0x0040
528 #define PCIXM_COMMAND_MAX_SPLITS_12 0x0050
529 #define PCIXM_COMMAND_MAX_SPLITS_16 0x0060
530 #define PCIXM_COMMAND_MAX_SPLITS_32 0x0070
531 #define PCIXM_COMMAND_VERSION 0x3000
532 #define PCIXR_STATUS 0x4
533 #define PCIXM_STATUS_DEVFN 0x000000FF
534 #define PCIXM_STATUS_BUS 0x0000FF00
535 #define PCIXM_STATUS_64BIT 0x00010000
536 #define PCIXM_STATUS_133CAP 0x00020000
537 #define PCIXM_STATUS_SC_DISCARDED 0x00040000
538 #define PCIXM_STATUS_UNEXP_SC 0x00080000
539 #define PCIXM_STATUS_COMPLEX_DEV 0x00100000
540 #define PCIXM_STATUS_MAX_READ 0x00600000
541 #define PCIXM_STATUS_MAX_READ_512 0x00000000
542 #define PCIXM_STATUS_MAX_READ_1024 0x00200000
543 #define PCIXM_STATUS_MAX_READ_2048 0x00400000
544 #define PCIXM_STATUS_MAX_READ_4096 0x00600000
545 #define PCIXM_STATUS_MAX_SPLITS 0x03800000
546 #define PCIXM_STATUS_MAX_SPLITS_1 0x00000000
547 #define PCIXM_STATUS_MAX_SPLITS_2 0x00800000
548 #define PCIXM_STATUS_MAX_SPLITS_3 0x01000000
549 #define PCIXM_STATUS_MAX_SPLITS_4 0x01800000
550 #define PCIXM_STATUS_MAX_SPLITS_8 0x02000000
551 #define PCIXM_STATUS_MAX_SPLITS_12 0x02800000
552 #define PCIXM_STATUS_MAX_SPLITS_16 0x03000000
553 #define PCIXM_STATUS_MAX_SPLITS_32 0x03800000
554 #define PCIXM_STATUS_MAX_CUM_READ 0x1C000000
555 #define PCIXM_STATUS_RCVD_SC_ERR 0x20000000
556 #define PCIXM_STATUS_266CAP 0x40000000
557 #define PCIXM_STATUS_533CAP 0x80000000
559 /* For header type 1 devices (PCI-X bridges) */
560 #define PCIXR_SEC_STATUS 0x2
561 #define PCIXM_SEC_STATUS_64BIT 0x0001
562 #define PCIXM_SEC_STATUS_133CAP 0x0002
563 #define PCIXM_SEC_STATUS_SC_DISC 0x0004
564 #define PCIXM_SEC_STATUS_UNEXP_SC 0x0008
565 #define PCIXM_SEC_STATUS_SC_OVERRUN 0x0010
566 #define PCIXM_SEC_STATUS_SR_DELAYED 0x0020
567 #define PCIXM_SEC_STATUS_BUS_MODE 0x03c0
568 #define PCIXM_SEC_STATUS_VERSION 0x3000
569 #define PCIXM_SEC_STATUS_266CAP 0x4000
570 #define PCIXM_SEC_STATUS_533CAP 0x8000
571 #define PCIXR_BRIDGE_STATUS 0x4
572 #define PCIXM_BRIDGE_STATUS_DEVFN 0x000000FF
573 #define PCIXM_BRIDGE_STATUS_BUS 0x0000FF00
574 #define PCIXM_BRIDGE_STATUS_64BIT 0x00010000
575 #define PCIXM_BRIDGE_STATUS_133CAP 0x00020000
576 #define PCIXM_BRIDGE_STATUS_SC_DISCARDED 0x00040000
577 #define PCIXM_BRIDGE_STATUS_UNEXP_SC 0x00080000
578 #define PCIXM_BRIDGE_STATUS_SC_OVERRUN 0x00100000
579 #define PCIXM_BRIDGE_STATUS_SR_DELAYED 0x00200000
580 #define PCIXM_BRIDGE_STATUS_DEVID_MSGCAP 0x20000000
581 #define PCIXM_BRIDGE_STATUS_266CAP 0x40000000
582 #define PCIXM_BRIDGE_STATUS_533CAP 0x80000000
584 /* HT (HyperTransport) Capability definitions */
585 #define PCIR_HT_COMMAND 0x2
586 #define PCIM_HTCMD_CAP_MASK 0xf800 /* Capability type. */
587 #define PCIM_HTCAP_SLAVE 0x0000 /* 000xx */
588 #define PCIM_HTCAP_HOST 0x2000 /* 001xx */
589 #define PCIM_HTCAP_SWITCH 0x4000 /* 01000 */
590 #define PCIM_HTCAP_INTERRUPT 0x8000 /* 10000 */
591 #define PCIM_HTCAP_REVISION_ID 0x8800 /* 10001 */
592 #define PCIM_HTCAP_UNITID_CLUMPING 0x9000 /* 10010 */
593 #define PCIM_HTCAP_EXT_CONFIG_SPACE 0x9800 /* 10011 */
594 #define PCIM_HTCAP_ADDRESS_MAPPING 0xa000 /* 10100 */
595 #define PCIM_HTCAP_MSI_MAPPING 0xa800 /* 10101 */
596 #define PCIM_HTCAP_DIRECT_ROUTE 0xb000 /* 10110 */
597 #define PCIM_HTCAP_VCSET 0xb800 /* 10111 */
598 #define PCIM_HTCAP_RETRY_MODE 0xc000 /* 11000 */
599 #define PCIM_HTCAP_X86_ENCODING 0xc800 /* 11001 */
601 /* HT MSI Mapping Capability definitions. */
602 #define PCIM_HTCMD_MSI_ENABLE 0x0001
603 #define PCIM_HTCMD_MSI_FIXED 0x0002
604 #define PCIR_HTMSI_ADDRESS_LO 0x4
605 #define PCIR_HTMSI_ADDRESS_HI 0x8
607 /* PCI Vendor capability definitions */
608 #define PCIR_VENDOR_LENGTH 0x2
609 #define PCIR_VENDOR_DATA 0x3
611 /* PCI EHCI Debug Port definitions */
612 #define PCIR_DEBUG_PORT 0x2
613 #define PCIM_DEBUG_PORT_OFFSET 0x1FFF
614 #define PCIM_DEBUG_PORT_BAR 0xe000
616 /* PCI-PCI Bridge Subvendor definitions */
617 #define PCIR_SUBVENDCAP_ID 0x4
619 /* PCI Express definitions */
620 #define PCIR_EXPRESS_FLAGS 0x2
621 #define PCIM_EXP_FLAGS_VERSION 0x000F
622 #define PCIM_EXP_FLAGS_TYPE 0x00F0
623 #define PCIM_EXP_TYPE_ENDPOINT 0x0000
624 #define PCIM_EXP_TYPE_LEGACY_ENDPOINT 0x0010
625 #define PCIM_EXP_TYPE_ROOT_PORT 0x0040
626 #define PCIM_EXP_TYPE_UPSTREAM_PORT 0x0050
627 #define PCIM_EXP_TYPE_DOWNSTREAM_PORT 0x0060
628 #define PCIM_EXP_TYPE_PCI_BRIDGE 0x0070
629 #define PCIM_EXP_TYPE_PCIE_BRIDGE 0x0080
630 #define PCIM_EXP_TYPE_ROOT_INT_EP 0x0090
631 #define PCIM_EXP_TYPE_ROOT_EC 0x00a0
632 #define PCIM_EXP_FLAGS_SLOT 0x0100
633 #define PCIM_EXP_FLAGS_IRQ 0x3e00
634 #define PCIR_EXPRESS_DEVICE_CAP 0x4
635 #define PCIM_EXP_CAP_MAX_PAYLOAD 0x0007
636 #define PCIR_EXPRESS_DEVICE_CTL 0x8
637 #define PCIM_EXP_CTL_NFER_ENABLE 0x0002
638 #define PCIM_EXP_CTL_FER_ENABLE 0x0004
639 #define PCIM_EXP_CTL_URR_ENABLE 0x0008
640 #define PCIM_EXP_CTL_RELAXED_ORD_ENABLE 0x0010
641 #define PCIM_EXP_CTL_MAX_PAYLOAD 0x00e0
642 #define PCIM_EXP_CTL_NOSNOOP_ENABLE 0x0800
643 #define PCIM_EXP_CTL_MAX_READ_REQUEST 0x7000
644 #define PCIR_EXPRESS_DEVICE_STA 0xa
645 #define PCIM_EXP_STA_CORRECTABLE_ERROR 0x0001
646 #define PCIM_EXP_STA_NON_FATAL_ERROR 0x0002
647 #define PCIM_EXP_STA_FATAL_ERROR 0x0004
648 #define PCIM_EXP_STA_UNSUPPORTED_REQ 0x0008
649 #define PCIM_EXP_STA_AUX_POWER 0x0010
650 #define PCIM_EXP_STA_TRANSACTION_PND 0x0020
651 #define PCIR_EXPRESS_LINK_CAP 0xc
652 #define PCIM_LINK_CAP_MAX_SPEED 0x0000000f
653 #define PCIM_LINK_CAP_MAX_WIDTH 0x000003f0
654 #define PCIM_LINK_CAP_ASPM 0x00000c00
655 #define PCIM_LINK_CAP_L0S_EXIT 0x00007000
656 #define PCIM_LINK_CAP_L1_EXIT 0x00038000
657 #define PCIM_LINK_CAP_PORT 0xff000000
658 #define PCIR_EXPRESS_LINK_CTL 0x10
659 #define PCIR_EXPRESS_LINK_STA 0x12
660 #define PCIM_LINK_STA_SPEED 0x000f
661 #define PCIM_LINK_STA_WIDTH 0x03f0
662 #define PCIM_LINK_STA_TRAINING_ERROR 0x0400
663 #define PCIM_LINK_STA_TRAINING 0x0800
664 #define PCIM_LINK_STA_SLOT_CLOCK 0x1000
665 #define PCIR_EXPRESS_SLOT_CAP 0x14
666 #define PCIR_EXPRESS_SLOT_CTL 0x18
667 #define PCIR_EXPRESS_SLOT_STA 0x1a
668 #define PCIR_EXPRESS_ROOT_CTL 0x1c
669 #define PCIR_EXPRESS_ROOT_STA 0x20
671 /* MSI-X definitions */
672 #define PCIR_MSIX_CTRL 0x2
673 #define PCIM_MSIXCTRL_MSIX_ENABLE 0x8000
674 #define PCIM_MSIXCTRL_FUNCTION_MASK 0x4000
675 #define PCIM_MSIXCTRL_TABLE_SIZE 0x07FF
676 #define PCIR_MSIX_TABLE 0x4
677 #define PCIR_MSIX_PBA 0x8
678 #define PCIM_MSIX_BIR_MASK 0x7
679 #define PCIM_MSIX_BIR_BAR_10 0
680 #define PCIM_MSIX_BIR_BAR_14 1
681 #define PCIM_MSIX_BIR_BAR_18 2
682 #define PCIM_MSIX_BIR_BAR_1C 3
683 #define PCIM_MSIX_BIR_BAR_20 4
684 #define PCIM_MSIX_BIR_BAR_24 5
685 #define PCIM_MSIX_VCTRL_MASK 0x1
687 /* PCI Advanced Features definitions */
688 #define PCIR_PCIAF_CAP 0x3
689 #define PCIM_PCIAFCAP_TP 0x01
690 #define PCIM_PCIAFCAP_FLR 0x02
691 #define PCIR_PCIAF_CTRL 0x4
692 #define PCIR_PCIAFCTRL_FLR 0x01
693 #define PCIR_PCIAF_STATUS 0x5
694 #define PCIR_PCIAFSTATUS_TP 0x01
696 /* Advanced Error Reporting */
697 #define PCIR_AER_UC_STATUS 0x04
698 #define PCIM_AER_UC_TRAINING_ERROR 0x00000001
699 #define PCIM_AER_UC_DL_PROTOCOL_ERROR 0x00000010
700 #define PCIM_AER_UC_POISONED_TLP 0x00001000
701 #define PCIM_AER_UC_FC_PROTOCOL_ERROR 0x00002000
702 #define PCIM_AER_UC_COMPLETION_TIMEOUT 0x00004000
703 #define PCIM_AER_UC_COMPLETER_ABORT 0x00008000
704 #define PCIM_AER_UC_UNEXPECTED_COMPLETION 0x00010000
705 #define PCIM_AER_UC_RECEIVER_OVERFLOW 0x00020000
706 #define PCIM_AER_UC_MALFORMED_TLP 0x00040000
707 #define PCIM_AER_UC_ECRC_ERROR 0x00080000
708 #define PCIM_AER_UC_UNSUPPORTED_REQUEST 0x00100000
709 #define PCIM_AER_UC_ACS_VIOLATION 0x00200000
710 #define PCIR_AER_UC_MASK 0x08 /* Shares bits with UC_STATUS */
711 #define PCIR_AER_UC_SEVERITY 0x0c /* Shares bits with UC_STATUS */
712 #define PCIR_AER_COR_STATUS 0x10
713 #define PCIM_AER_COR_RECEIVER_ERROR 0x00000001
714 #define PCIM_AER_COR_BAD_TLP 0x00000040
715 #define PCIM_AER_COR_BAD_DLLP 0x00000080
716 #define PCIM_AER_COR_REPLAY_ROLLOVER 0x00000100
717 #define PCIM_AER_COR_REPLAY_TIMEOUT 0x00001000
718 #define PCIR_AER_COR_MASK 0x14 /* Shares bits with COR_STATUS */
719 #define PCIR_AER_CAP_CONTROL 0x18
720 #define PCIM_AER_FIRST_ERROR_PTR 0x0000001f
721 #define PCIM_AER_ECRC_GEN_CAPABLE 0x00000020
722 #define PCIM_AER_ECRC_GEN_ENABLE 0x00000040
723 #define PCIM_AER_ECRC_CHECK_CAPABLE 0x00000080
724 #define PCIM_AER_ECRC_CHECK_ENABLE 0x00000100
725 #define PCIR_AER_HEADER_LOG 0x1c
726 #define PCIR_AER_ROOTERR_CMD 0x2c /* Only for root complex ports */
727 #define PCIM_AER_ROOTERR_COR_ENABLE 0x00000001
728 #define PCIM_AER_ROOTERR_NF_ENABLE 0x00000002
729 #define PCIM_AER_ROOTERR_F_ENABLE 0x00000004
730 #define PCIR_AER_ROOTERR_STATUS 0x30 /* Only for root complex ports */
731 #define PCIM_AER_ROOTERR_COR_ERR 0x00000001
732 #define PCIM_AER_ROOTERR_MULTI_COR_ERR 0x00000002
733 #define PCIM_AER_ROOTERR_UC_ERR 0x00000004
734 #define PCIM_AER_ROOTERR_MULTI_UC_ERR 0x00000008
735 #define PCIM_AER_ROOTERR_FIRST_UC_FATAL 0x00000010
736 #define PCIM_AER_ROOTERR_NF_ERR 0x00000020
737 #define PCIM_AER_ROOTERR_F_ERR 0x00000040
738 #define PCIM_AER_ROOTERR_INT_MESSAGE 0xf8000000
739 #define PCIR_AER_COR_SOURCE_ID 0x34 /* Only for root complex ports */
740 #define PCIR_AER_ERR_SOURCE_ID 0x36 /* Only for root complex ports */
742 /* Virtual Channel definitions */
743 #define PCIR_VC_CAP1 0x04
744 #define PCIM_VC_CAP1_EXT_COUNT 0x00000007
745 #define PCIM_VC_CAP1_LOWPRI_EXT_COUNT 0x00000070
746 #define PCIR_VC_CAP2 0x08
747 #define PCIR_VC_CONTROL 0x0C
748 #define PCIR_VC_STATUS 0x0E
749 #define PCIR_VC_RESOURCE_CAP(n) (0x10 + (n) * 0x0C)
750 #define PCIR_VC_RESOURCE_CTL(n) (0x14 + (n) * 0x0C)
751 #define PCIR_VC_RESOURCE_STA(n) (0x18 + (n) * 0x0C)
753 /* Serial Number definitions */
754 #define PCIR_SERIAL_LOW 0x04
755 #define PCIR_SERIAL_HIGH 0x08