1 /* $NetBSD: pdqreg.h,v 1.14 2001/06/13 10:46:03 wiz Exp $ */
4 * Copyright (c) 1995, 1996 Matt Thomas <matt@3am-software.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * Id: pdqreg.h,v 1.11 1997/03/21 21:16:04 thomas Exp
32 * DEC PDQ FDDI Controller; PDQ port driver definitions
39 #if !defined(KERNEL) && !defined(_KERNEL)
41 #elif !defined(offsetof)
42 #define offsetof(t, m) ((char *) (&((t *)0L)->m) - (char *) 0L)
44 #if defined(PDQTEST) && !defined(PDQ_NDEBUG)
46 #define PDQ_ASSERT assert
48 #define PDQ_ASSERT(x) do { } while(0)
51 #define PDQ_RING_SIZE(array) ((sizeof(array) / sizeof(array[0])))
52 #define PDQ_ARRAY_SIZE(array) ((sizeof(array) / sizeof(array[0])))
53 #define PDQ_RING_MASK(array) (PDQ_RING_SIZE(array) - 1)
54 #define PDQ_BITMASK(n) (1L << (pdq_uint32_t) (n))
56 #define PDQ_FDDI_MAX 4495
57 #define PDQ_FDDI_LLC_MIN 20
58 #define PDQ_FDDI_SMT_MIN 37
60 #define PDQ_FDDI_SMT 0x40
61 #define PDQ_FDDI_LLC_ASYNC 0x50
62 #define PDQ_FDDI_LLC_SYNC 0xD0
63 #define PDQ_FDDI_IMP_ASYNC 0x60
64 #define PDQ_FDDI_IMP_SYNC 0xE0
66 #define PDQ_FDDIFC_C 0x80
67 #define PDQ_FDDIFC_L 0x40
68 #define PDQ_FDDIFC_F 0x30
69 #define PDQ_FDDIFC_Z 0x0F
71 #define PDQ_FDDI_PH0 0x20
72 #define PDQ_FDDI_PH1 0x38
73 #define PDQ_FDDI_PH2 0x00
75 typedef pdq_uint32_t pdq_physaddr_t;
77 struct _pdq_lanaddr_t {
78 pdq_uint8_t lanaddr_bytes[8];
82 pdq_uint8_t fwrev_bytes[4];
88 PDQS_DMA_UNAVAILABLE=2,
90 PDQS_LINK_AVAILABLE=4,
91 PDQS_LINK_UNAVAILABLE=5,
97 pdq_bus_memoffset_t csr_port_reset; /* 0x00 [RW] */
98 pdq_bus_memoffset_t csr_host_data; /* 0x04 [R] */
99 pdq_bus_memoffset_t csr_port_control; /* 0x08 [RW] */
100 pdq_bus_memoffset_t csr_port_data_a; /* 0x0C [RW] */
101 pdq_bus_memoffset_t csr_port_data_b; /* 0x10 [RW] */
102 pdq_bus_memoffset_t csr_port_status; /* 0x14 [R] */
103 pdq_bus_memoffset_t csr_host_int_type_0; /* 0x18 [RW] */
104 pdq_bus_memoffset_t csr_host_int_enable; /* 0x1C [RW] */
105 pdq_bus_memoffset_t csr_type_2_producer; /* 0x20 [RW] */
106 pdq_bus_memoffset_t csr_cmd_response_producer; /* 0x28 [RW] */
107 pdq_bus_memoffset_t csr_cmd_request_producer; /* 0x2C [RW] */
108 pdq_bus_memoffset_t csr_host_smt_producer; /* 0x30 [RW] */
109 pdq_bus_memoffset_t csr_unsolicited_producer; /* 0x34 [RW] */
111 pdq_bus_memaddr_t csr_base;
114 struct _pdq_pci_csrs_t {
115 pdq_bus_memoffset_t csr_pfi_mode_control; /* 0x40 [RW] */
116 pdq_bus_memoffset_t csr_pfi_status; /* 0x44 [RW] */
117 pdq_bus_memoffset_t csr_fifo_write; /* 0x48 [RW] */
118 pdq_bus_memoffset_t csr_fifo_read; /* 0x4C [RW] */
120 pdq_bus_memaddr_t csr_base;
123 #define PDQ_PFI_MODE_DMA_ENABLE 0x01 /* DMA Enable */
124 #define PDQ_PFI_MODE_PFI_PCI_INTR 0x02 /* PFI-to-PCI Int Enable */
125 #define PDQ_PFI_MODE_PDQ_PCI_INTR 0x04 /* PDQ-to-PCI Int Enable */
127 #define PDQ_PFI_STATUS_PDQ_INTR 0x10 /* PDQ Int received */
128 #define PDQ_PFI_STATUS_DMA_ABORT 0x08 /* PDQ DMA Abort asserted */
130 #define PDQ_EISA_BURST_HOLDOFF 0x0040
131 #define PDQ_EISA_SLOT_ID 0x0C80
132 #define PDQ_EISA_SLOT_CTRL 0x0C84
133 #define PDQ_EISA_MEM_ADD_CMP_0 0x0C85
134 #define PDQ_EISA_MEM_ADD_CMP_1 0x0C86
135 #define PDQ_EISA_MEM_ADD_CMP_2 0x0C87
136 #define PDQ_EISA_MEM_ADD_HI_CMP_0 0x0C88
137 #define PDQ_EISA_MEM_ADD_HI_CMP_1 0x0C89
138 #define PDQ_EISA_MEM_ADD_HI_CMP_2 0x0C8A
139 #define PDQ_EISA_MEM_ADD_MASK_0 0x0C8B
140 #define PDQ_EISA_MEM_ADD_MASK_1 0x0C8C
141 #define PDQ_EISA_MEM_ADD_MASK_2 0x0C8D
142 #define PDQ_EISA_MEM_ADD_LO_CMP_0 0x0C8E
143 #define PDQ_EISA_MEM_ADD_LO_CMP_1 0x0C8F
144 #define PDQ_EISA_MEM_ADD_LO_CMP_2 0x0C90
145 #define PDQ_EISA_IO_CMP_0_0 0x0C91
146 #define PDQ_EISA_IO_CMP_0_1 0x0C92
147 #define PDQ_EISA_IO_CMP_1_0 0x0C93
148 #define PDQ_EISA_IO_CMP_1_1 0x0C94
149 #define PDQ_EISA_IO_CMP_2_0 0x0C95
150 #define PDQ_EISA_IO_CMP_2_1 0x0C96
151 #define PDQ_EISA_IO_CMP_3_0 0x0C97
152 #define PDQ_EISA_IO_CMP_3_1 0x0C98
153 #define PDQ_EISA_IO_ADD_MASK_0_0 0x0C99
154 #define PDQ_EISA_IO_ADD_MASK_0_1 0x0C9A
155 #define PDQ_EISA_IO_ADD_MASK_1_0 0x0C9B
156 #define PDQ_EISA_IO_ADD_MASK_1_1 0x0C9C
157 #define PDQ_EISA_IO_ADD_MASK_2_0 0x0C9D
158 #define PDQ_EISA_IO_ADD_MASK_2_1 0x0C9E
159 #define PDQ_EISA_IO_ADD_MASK_3_0 0x0C9F
160 #define PDQ_EISA_IO_ADD_MASK_3_1 0x0CA0
161 #define PDQ_EISA_MOD_CONFIG_1 0x0CA1
162 #define PDQ_EISA_MOD_CONFIG_2 0x0CA2
163 #define PDQ_EISA_MOD_CONFIG_3 0x0CA3
164 #define PDQ_EISA_MOD_CONFIG_4 0x0CA4
165 #define PDQ_EISA_MOD_CONFIG_5 0x0CA5
166 #define PDQ_EISA_MOD_CONFIG_6 0x0CA6
167 #define PDQ_EISA_MOD_CONFIG_7 0x0CA7
168 #define PDQ_EISA_DIP_SWITCH 0x0CA8
169 #define PDQ_EISA_IO_CONFIG_STAT_0 0x0CA9
170 #define PDQ_EISA_IO_CONFIG_STAT_1 0x0CAA
171 #define PDQ_EISA_DMA_CONFIG 0x0CAB
172 #define PDQ_EISA_INPUT_PORT 0x0CAC
173 #define PDQ_EISA_OUTPUT_PORT 0x0CAD
174 #define PDQ_EISA_FUNCTION_CTRL 0x0CAE
176 #define PDQ_TC_CSR_OFFSET 0x00100000
177 #define PDQ_TC_CSR_SPACE 0x0040
178 #define PDQ_FBUS_CSR_OFFSET 0x00200000
179 #define PDQ_FBUS_CSR_SPACE 0x0080
182 * Port Reset Data A Definitions
184 #define PDQ_PRESET_SKIP_SELFTEST 0x0004
185 #define PDQ_PRESET_SOFT_RESET 0x0002
186 #define PDQ_PRESET_UPGRADE 0x0001
188 * Port Control Register Definitions
190 #define PDQ_PCTL_CMD_ERROR 0x8000
191 #define PDQ_PCTL_FLASH_BLAST 0x4000
192 #define PDQ_PCTL_HALT 0x2000
193 #define PDQ_PCTL_COPY_DATA 0x1000
194 #define PDQ_PCTL_ERROR_LOG_START 0x0800
195 #define PDQ_PCTL_ERROR_LOG_READ 0x0400
196 #define PDQ_PCTL_XMT_DATA_FLUSH_DONE 0x0200
197 #define PDQ_PCTL_DMA_INIT 0x0100
198 #define PDQ_DMA_INIT_LW_BSWAP_DATA 0x02
199 #define PDQ_DMA_INIT_LW_BSWAP_LITERAL 0x01
200 #define PDQ_PCTL_INIT_START 0x0080
201 #define PDQ_PCTL_CONSUMER_BLOCK 0x0040
202 #define PDQ_PCTL_DMA_UNINIT 0x0020
203 #define PDQ_PCTL_RING_MEMBER 0x0010
204 #define PDQ_PCTL_MLA_READ 0x0008
205 #define PDQ_PCTL_FW_REV_READ 0x0004
206 #define PDQ_PCTL_DEVICE_SPECIFIC 0x0002
207 #define PDQ_PCTL_SUB_CMD 0x0001
210 PDQ_SUB_CMD_LINK_UNINIT=1,
211 PDQ_SUB_CMD_DMA_BURST_SIZE_SET=2,
212 PDQ_SUB_CMD_PDQ_REV_GET=4
218 PDQ_DMA_BURST_16LW=2,
220 } pdq_dma_burst_size_t;
223 PDQ_CHIP_REV_A_B_OR_C=0,
228 * Port Status Register Definitions
230 #define PDQ_PSTS_RCV_DATA_PENDING 0x80000000ul
231 #define PDQ_PSTS_XMT_DATA_PENDING 0x40000000ul
232 #define PDQ_PSTS_HOST_SMT_PENDING 0x20000000ul
233 #define PDQ_PSTS_UNSOL_PENDING 0x10000000ul
234 #define PDQ_PSTS_CMD_RSP_PENDING 0x08000000ul
235 #define PDQ_PSTS_CMD_REQ_PENDING 0x04000000ul
236 #define PDQ_PSTS_TYPE_0_PENDING 0x02000000ul
237 #define PDQ_PSTS_INTR_PENDING 0xFE000000ul
238 #define PDQ_PSTS_ADAPTER_STATE(sts) ((pdq_state_t) (((sts) >> 8) & 0x07))
239 #define PDQ_PSTS_HALT_ID(sts) ((pdq_halt_code_t) ((sts) & 0xFF))
241 * Host Interrupt Register Definitions
243 #define PDQ_HOST_INT_TX_ENABLE 0x80000000ul
244 #define PDQ_HOST_INT_RX_ENABLE 0x40000000ul
245 #define PDQ_HOST_INT_UNSOL_ENABLE 0x20000000ul
246 #define PDQ_HOST_INT_HOST_SMT_ENABLE 0x10000000ul
247 #define PDQ_HOST_INT_CMD_RSP_ENABLE 0x08000000ul
248 #define PDQ_HOST_INT_CMD_RQST_ENABLE 0x04000000ul
250 #define PDQ_HOST_INT_1MS 0x80
251 #define PDQ_HOST_INT_20MS 0x40
252 #define PDQ_HOST_INT_CSR_CMD_DONE 0x20
253 #define PDQ_HOST_INT_STATE_CHANGE 0x10
254 #define PDQ_HOST_INT_XMT_DATA_FLUSH 0x08
255 #define PDQ_HOST_INT_NXM 0x04
256 #define PDQ_HOST_INT_PM_PARITY_ERROR 0x02
257 #define PDQ_HOST_INT_HOST_BUS_PARITY_ERROR 0x01
258 #define PDQ_HOST_INT_FATAL_ERROR 0x07
261 PDQH_SELFTEST_TIMEOUT=0,
262 PDQH_HOST_BUS_PARITY_ERROR=1,
263 PDQH_HOST_DIRECTED_HALT=2,
264 PDQH_SOFTWARE_FAULT=3,
265 PDQH_HARDWARE_FAULT=4,
266 PDQH_PC_TRACE_PATH_TEST=5,
268 PDQH_IMAGE_CRC_ERROR=7,
269 PDQH_ADAPTER_PROCESSOR_ERROR=8,
274 pdq_uint16_t pdqcb_receives;
275 pdq_uint16_t pdqcb_transmits;
276 pdq_uint32_t pdqcb__filler1;
277 pdq_uint32_t pdqcb_host_smt;
278 pdq_uint32_t pdqcb__filler2;
279 pdq_uint32_t pdqcb_unsolicited_event;
280 pdq_uint32_t pdqcb__filler3;
281 pdq_uint32_t pdqcb_command_response;
282 pdq_uint32_t pdqcb__filler4;
283 pdq_uint32_t pdqcb_command_request;
284 pdq_uint32_t pdqcb__filler5[7];
285 } pdq_consumer_block_t;
287 #if defined(BYTE_ORDER) && BYTE_ORDER == BIG_ENDIAN
288 #define PDQ_BITFIELD2(a, b) b, a
289 #define PDQ_BITFIELD3(a, b, c) c, b, a
290 #define PDQ_BITFIELD4(a, b, c, d) d, c, b, a
291 #define PDQ_BITFIELD5(a, b, c, d, e) e, d, c, b, a
292 #define PDQ_BITFIELD12(a, b, c, d, e, f, g, h, i, j, k, l) \
293 l, k, j, i, h, g, f, e, d, c, b, a
295 #define PDQ_BITFIELD2(a, b) a, b
296 #define PDQ_BITFIELD3(a, b, c) a, b, c
297 #define PDQ_BITFIELD4(a, b, c, d) a, b, c, d
298 #define PDQ_BITFIELD5(a, b, c, d, e) a, b, c, d, e
299 #define PDQ_BITFIELD12(a, b, c, d, e, f, g, h, i, j, k, l) \
300 a, b, c, d, e, f, g, h, i, j, k, l
304 pdq_uint32_t PDQ_BITFIELD5(rxd_pa_hi : 16,
309 pdq_uint32_t rxd_pa_lo;
313 pdq_uint32_t rxs_status;
315 pdq_uint32_t PDQ_BITFIELD12(st_len : 13,
321 st_fsb__reserved : 2,
329 #define rxs_len rxs_st.st_len
330 #define rxs_rcc_ss rxs_st.st_rcc_ss
331 #define rxs_rcc_dd rxs_st.st_rcc_dd
332 #define rxs_rcc_reason rxs_st.st_rcc_reason
333 #define rxs_rcc_badcrc rxs_st.st_rcc_badcrc
334 #define rxs_rcc_badpdu rxs_st.st_rcc_badpdu
335 #define rxs_fsb_c rxs_st.st_fsb_c
336 #define rxs_fsb_a rxs_st.st_fsb_a
337 #define rxs_fsb_e rxs_st.st_fsb_e
338 #define rxs_fsc rxs_st.st_fsc
340 #define PDQ_RXS_RCC_DD_NO_MATCH 0x00
341 #define PDQ_RXS_RCC_DD_PROMISC_MATCH 0x01
342 #define PDQ_RXS_RCC_DD_CAM_MATCH 0x02
343 #define PDQ_RXS_RCC_DD_MLA_MATCH 0x03
346 pdq_uint32_t PDQ_BITFIELD5(txd_pa_hi : 16,
351 pdq_uint32_t txd_pa_lo;
355 pdq_rxdesc_t pdqdb_receives[256]; /* 2048; 0x0000..0x07FF */
356 pdq_txdesc_t pdqdb_transmits[256]; /* 2048; 0x0800..0x0FFF */
357 pdq_rxdesc_t pdqdb_host_smt[64]; /* 512; 0x1000..0x11FF */
358 pdq_rxdesc_t pdqdb_unsolicited_events[16]; /* 128; 0x1200..0x127F */
359 pdq_rxdesc_t pdqdb_command_responses[16]; /* 128; 0x1280..0x12FF */
360 pdq_txdesc_t pdqdb_command_requests[16]; /* 128; 0x1300..0x137F */
362 * The rest of the descriptor block is unused.
363 * As such we could use it for other things.
365 pdq_uint32_t pdqdb__filler1[16]; /* 64; 0x1380..0x13BF */
366 pdq_consumer_block_t pdqdb_consumer; /* 64; 0x13C0..0x13FF */
368 * The maximum command size is 512 so as long as thes
369 * command is at least that long all will be fine.
371 pdq_uint32_t pdqdb__filler2[64]; /* 256; 0x1400..0x14FF */
372 pdq_uint8_t pdqdb_cmd_request_buf[1024]; /* 1024; 0x1500..0x18FF */
373 pdq_uint8_t pdqdb_cmd_response_buf[1024]; /* 1024; 0x1900..0x1CFF */
374 pdq_uint32_t pdqdb__filler3[128]; /* 512; 0x1D00..0x1EFF */
375 pdq_uint8_t pdqdb_tx_hdr[4]; /* 4; 0x1F00..0x1F03 */
376 pdq_uint32_t pdqdb__filler4[63]; /* 252; 0x1F04..0x1FFF */
377 } pdq_descriptor_block_t;
379 #define PDQ_SIZE_COMMAND_RESPONSE 512
386 PDQC_STATUS_CHARS_GET=4,
389 PDQC_ADDR_FILTER_SET=7,
390 PDQC_ADDR_FILTER_GET=8,
391 PDQC_ERROR_LOG_CLEAR=9,
392 PDQC_ERROR_LOG_GET=10,
393 PDQC_FDDI_MIB_GET=11,
394 PDQC_DEC_EXT_MIB_GET=12,
395 PDQC_DEV_SPECIFIC_GET=13,
404 * These value manage the available space in command/response
407 pdq_physaddr_t ci_pa_request_bufstart;
408 pdq_uint8_t *ci_request_bufstart;
409 pdq_physaddr_t ci_pa_response_bufstart;
410 pdq_uint8_t *ci_response_bufstart;
412 * Bitmask of commands to sent to the PDQ
414 pdq_uint32_t ci_pending_commands;
416 * Variables to maintain the PDQ queues.
418 pdq_uint32_t ci_command_active;
419 pdq_uint32_t ci_request_producer;
420 pdq_uint32_t ci_response_producer;
421 pdq_uint32_t ci_request_completion;
422 pdq_uint32_t ci_response_completion;
426 pdq_physaddr_t ci_pa_request_descriptors;
427 pdq_physaddr_t ci_pa_response_descriptors;
429 pdq_cmd_code_t ci_queued_commands[16];
430 } pdq_command_info_t;
432 #define PDQ_SIZE_UNSOLICITED_EVENT 512
433 #define PDQ_NUM_UNSOLICITED_EVENTS (PDQ_OS_PAGESIZE / PDQ_SIZE_UNSOLICITED_EVENT)
435 typedef struct _pdq_unsolicited_event_t pdq_unsolicited_event_t;
438 pdq_physaddr_t ui_pa_bufstart;
439 pdq_physaddr_t ui_pa_descriptors;
440 pdq_unsolicited_event_t *ui_events;
442 pdq_uint32_t ui_free;
443 pdq_uint32_t ui_producer;
444 pdq_uint32_t ui_completion;
445 } pdq_unsolicited_info_t;
447 #define PDQ_RX_FC_OFFSET (sizeof(pdq_rxstatus_t) + 3)
448 #define PDQ_RX_SEGCNT ((PDQ_FDDI_MAX + PDQ_OS_DATABUF_SIZE - 1) / PDQ_OS_DATABUF_SIZE)
449 #define PDQ_DO_TYPE2_PRODUCER(pdq) \
450 PDQ_CSR_WRITE(&(pdq)->pdq_csrs, csr_type_2_producer, \
451 ((pdq)->pdq_rx_info.rx_producer << 0) \
452 | ((pdq)->pdq_tx_info.tx_producer << 8) \
453 | ((pdq)->pdq_rx_info.rx_completion << 16) \
454 | ((pdq)->pdq_tx_info.tx_completion << 24))
456 #define PDQ_DO_HOST_SMT_PRODUCER(pdq) \
457 PDQ_CSR_WRITE(&(pdq)->pdq_csrs, csr_host_smt_producer, \
458 ((pdq)->pdq_host_smt_info.rx_producer << 0) \
459 | ((pdq)->pdq_host_smt_info.rx_completion << 8))\
461 #define PDQ_ADVANCE(n, a, m) ((n) = ((n) + (a)) & (m))
466 } pdq_databuf_queue_t;
470 pdq_physaddr_t rx_pa_descriptors;
472 pdq_uint32_t rx_target;
473 pdq_uint32_t rx_free;
474 pdq_uint32_t rx_producer;
475 pdq_uint32_t rx_completion;
479 pdq_databuf_queue_t tx_txq;
480 pdq_txdesc_t tx_hdrdesc;
481 pdq_uint8_t tx_descriptor_count[256];
482 pdq_physaddr_t tx_pa_descriptors;
484 pdq_uint32_t tx_free;
485 pdq_uint32_t tx_producer;
486 pdq_uint32_t tx_completion;
489 typedef struct _pdq_os_ctx_t pdq_os_ctx_t;
492 pdq_pci_csrs_t pdq_pci_csrs;
494 pdq_chip_rev_t pdq_chip_rev;
495 pdq_lanaddr_t pdq_hwaddr;
496 pdq_fwrev_t pdq_fwrev;
497 pdq_descriptor_block_t *pdq_dbp;
498 volatile pdq_consumer_block_t *pdq_cbp;
499 pdq_uint32_t pdq_intrmask;
500 pdq_uint32_t pdq_flags;
501 #define PDQ_PROMISC 0x0001
502 #define PDQ_ALLMULTI 0x0002
503 #define PDQ_PASS_SMT 0x0004
504 #define PDQ_RUNNING 0x0008
505 #define PDQ_PRINTCHARS 0x0010
506 #define PDQ_TXOK 0x0020
507 #define PDQ_WANT_FDX 0x0040
508 #define PDQ_IS_FDX 0x0080
509 #define PDQ_IS_ONRING 0x0100
510 const char *pdq_os_name;
511 pdq_os_ctx_t *pdq_os_ctx;
512 pdq_uint32_t pdq_unit;
513 pdq_command_info_t pdq_command_info;
514 pdq_unsolicited_info_t pdq_unsolicited_info;
515 pdq_tx_info_t pdq_tx_info;
516 pdq_rx_info_t pdq_rx_info;
517 pdq_rx_info_t pdq_host_smt_info;
518 void *pdq_receive_buffers[256];
519 void *pdq_host_smt_buffers[64];
520 pdq_physaddr_t pdq_pa_consumer_block;
521 pdq_physaddr_t pdq_pa_descriptor_block;
524 #define PDQ_DB_BUSPA(pdq, m) \
525 ((pdq)->pdq_pa_descriptor_block + \
526 ((volatile u_int8_t *) (m) - (u_int8_t *) (pdq)->pdq_dbp))
533 PDQR_LOOP_MODE_BAD=3,
534 PDQR_ITEM_CODE_BAD=4,
537 PDQR_RESTRICTED_TOKEN_BAD=7,
539 PDQR_FILTER_STATE_BAD=13,
540 PDQR_CMD_TYPE_BAD=14,
541 PDQR_ADAPTER_STATE_BAD=15,
542 PDQR_RING_PURGER_BAD=16,
543 PDQR_LEM_THRESHOLD_BAD=17,
544 PDQR_LOOP_NOT_SUPPORTED=18,
545 PDQR_FLUSH_TIME_BAD=19,
546 PDQR_NOT_YET_IMPLEMENTED=20,
547 PDQR_CONFIG_POLICY_BAD=21,
548 PDQR_STATION_ACTION_BAD=22,
549 PDQR_MAC_ACTION_BAD=23,
550 PDQR_CON_POLICIES_BAD=24,
551 PDQR_MAC_LOOP_TIME_BAD=25,
553 PDQR_LER_CUTOFF_BAD=27,
554 PDQR_LER_ALARM_BAD=28,
555 PDQR_MAC_PATHS_REQ_BAD=29,
556 PDQR_MAC_T_REQ_BAD=30,
557 PDQR_EMAC_RING_PURGER_BAD=31,
558 PDQR_EMAC_RTOKEN_TIMOUT_AD=32,
559 PDQR_NO_SUCH_ENTRY=33,
560 PDQR_T_NOTIFY_BAD=34,
561 PDQR_TR_MAX_EXP_BAD=35,
562 PDQR_FRAME_ERR_THRESHOLD_BAD=36,
563 PDQR_MAX_TREQ_BAD=37,
564 PDQR_FULL_DUPLEX_ENABLE_BAD=38,
565 PDQR_ITEM_INDEX_BAD=39
566 } pdq_response_code_t;
572 PDQI_RESTRICTED_TOKEN=3,
573 PDQI_LEM_THRESHOLD=4,
575 PDQI_COUNTER_INTERVAL=6,
576 PDQI_IND_GROUP_PROM=7,
583 PDQI_LOOPBACK_MODE=14,
584 PDQI_SMT_CONFIG_POLICY=16,
585 PDQI_SMT_CONNECTION_POLICY=17,
586 PDQI_SMT_T_NOTIFY=18,
587 PDQI_SMT_STATION_ACTION=19,
588 PDQI_MAC_PATHS_REQUESTED=21,
590 PDQI_PORT_CONNECTION_POLICIES=24,
591 PDQI_PORT_PATHS_REQUESTED=25,
592 PDQI_PORT_MAC_LOOP_TIME=26,
594 PDQI_PORT_LER_CUTOFF=28,
595 PDQI_PORT_LER_ALARM=29,
598 PDQI_SMT_USER_DATA=33,
599 PDQI_SMT_STATUS_REPORT_POLICY=34,
600 PDQI_SMT_TRACE_MAX_EXPIRATION=35,
601 PDQI_MAC_FRAME_ERR_THRESHOLD=36,
602 PDQI_MAC_UNIT_DATA_ENABLE=37,
603 PDQI_PATH_TVX_LOWER_BOUND=38,
604 PDQI_PATH_TMAX_LOWER_BOUND=39,
605 PDQI_PATH_MAX_TREQ=40,
607 PDQI_EMAC_RING_PURGER=42,
608 PDQI_EMAC_RTOKEN_TIMEOUT=43,
609 PDQI_FULL_DUPLEX_ENABLE=44
614 PDQSNMP_FULL_DUPLEX_ENABLE=0x2F11
615 } pdq_snmp_item_code_t;
617 enum _pdq_boolean_t {
625 } pdq_filter_state_t;
628 PDQ_STATION_TYPE_SAS=0,
629 PDQ_STATION_TYPE_DAC=1,
630 PDQ_STATION_TYPE_SAC=2,
631 PDQ_STATION_TYPE_NAC=3,
632 PDQ_STATION_TYPE_DAS=4
633 } pdq_station_type_t;
636 PDQ_STATION_STATE_OFF=0,
637 PDQ_STATION_STATE_ON=1,
638 PDQ_STATION_STATE_LOOPBACK=2
639 } pdq_station_state_t;
642 PDQ_LINK_STATE_OFF_READY=1,
643 PDQ_LINK_STATE_OFF_FAULT_RECOVERY=2,
644 PDQ_LINK_STATE_ON_RING_INIT=3,
645 PDQ_LINK_STATE_ON_RING_RUN=4,
646 PDQ_LINK_STATE_BROKEN=5
650 PDQ_DA_TEST_STATE_UNKNOWN=0,
651 PDQ_DA_TEST_STATE_SUCCESS=1,
652 PDQ_DA_TEST_STATE_DUPLICATE=2
653 } pdq_da_test_state_t;
656 PDQ_RING_PURGER_STATE_OFF=0,
657 PDQ_RING_PURGER_STATE_CANDIDATE=1,
658 PDQ_RING_PURGER_STATE_NON_PURGER=2,
659 PDQ_RING_PURGER_STATE_PURGER=3
660 } pdq_ring_purger_state_t;
663 PDQ_FRAME_STRING_MODE_SA_MATCH=0,
664 PDQ_FRAME_STRING_MODE_FCI_STRIP=1
665 } pdq_frame_strip_mode_t;
668 PDQ_RING_ERROR_REASON_NO_ERROR=0,
669 PDQ_RING_ERROR_REASON_RING_INIT_INITIATED=5,
670 PDQ_RING_ERROR_REASON_RING_INIT_RECEIVED=6,
671 PDQ_RING_ERROR_REASON_RING_BEACONING_INITIATED=7,
672 PDQ_RING_ERROR_REASON_DUPLICATE_ADDRESS_DETECTED=8,
673 PDQ_RING_ERROR_REASON_DUPLICATE_TOKEN_DETECTED=9,
674 PDQ_RING_ERROR_REASON_RING_PURGER_ERROR=10,
675 PDQ_RING_ERROR_REASON_FCI_STRIP_ERROR=11,
676 PDQ_RING_ERROR_REASON_RING_OP_OSCILLATION=12,
677 PDQ_RING_ERROR_REASON_DIRECTED_BEACON_RECEVIED=13,
678 PDQ_RING_ERROR_REASON_PC_TRACE_INITIATED=14,
679 PDQ_RING_ERROR_REASON_PC_TRACE_RECEVIED=15
680 } pdq_ring_error_reason_t;
683 PDQ_STATION_MODE_NORMAL=0,
684 PDQ_STATION_MODE_INTERNAL_LOOPBACK=1
685 } pdq_station_mode_t;
692 PDQ_PHY_TYPE_UNKNOWN=4
696 PDQ_PMD_TYPE_ANSI_MUTLI_MODE=0,
697 PDQ_PMD_TYPE_ANSI_SINGLE_MODE_TYPE_1=1,
698 PDQ_PMD_TYPE_ANSI_SIGNLE_MODE_TYPE_2=2,
699 PDQ_PMD_TYPE_ANSI_SONET=3,
700 PDQ_PMD_TYPE_LOW_POWER=100,
701 PDQ_PMD_TYPE_THINWIRE=101,
702 PDQ_PMD_TYPE_SHIELDED_TWISTED_PAIR=102,
703 PDQ_PMD_TYPE_UNSHIELDED_TWISTED_PAIR=103
707 PDQ_PMD_CLASS_ANSI_MULTI_MODE=0,
708 PDQ_PMD_CLASS_SINGLE_MODE_TYPE_1=1,
709 PDQ_PMD_CLASS_SINGLE_MODE_TYPE_2=2,
710 PDQ_PMD_CLASS_SONET=3,
711 PDQ_PMD_CLASS_LOW_COST_POWER_FIBER=4,
712 PDQ_PMD_CLASS_TWISTED_PAIR=5,
713 PDQ_PMD_CLASS_UNKNOWN=6,
714 PDQ_PMD_CLASS_UNSPECIFIED=7
718 PDQ_PHY_STATE_INTERNAL_LOOPBACK=0,
719 PDQ_PHY_STATE_BROKEN=1,
720 PDQ_PHY_STATE_OFF_READY=2,
721 PDQ_PHY_STATE_WAITING=3,
722 PDQ_PHY_STATE_STARTING=4,
723 PDQ_PHY_STATE_FAILED=5,
724 PDQ_PHY_STATE_WATCH=6,
725 PDQ_PHY_STATE_INUSE=7
729 PDQ_REJECT_REASON_NONE=0,
730 PDQ_REJECT_REASON_LOCAL_LCT=1,
731 PDQ_REJECT_REASON_REMOTE_LCT=2,
732 PDQ_REJECT_REASON_LCT_BOTH_SIDES=3,
733 PDQ_REJECT_REASON_LEM_REJECT=4,
734 PDQ_REJECT_REASON_TOPOLOGY_ERROR=5,
735 PDQ_REJECT_REASON_NOISE_REJECT=6,
736 PDQ_REJECT_REASON_REMOTE_REJECT=7,
737 PDQ_REJECT_REASON_TRACE_IN_PROGRESS=8,
738 PDQ_REJECT_REASON_TRACE_RECEIVED_DISABLED=9,
739 PDQ_REJECT_REASON_STANDBY=10,
740 PDQ_REJECT_REASON_LCT_PROTOCOL_ERROR=11
741 } pdq_reject_reason_t;
744 PDQ_BROKEN_REASON_NONE=0
745 } pdq_broken_reason_t;
748 PDQ_RI_REASON_TVX_EXPIRED=0,
749 PDQ_RI_REASON_TRT_EXPIRED=1,
750 PDQ_RI_REASON_RING_PURGER_ELECTION_ATTEMPT_LIMIT_EXCEEDED=2,
751 PDQ_RI_REASON_PURGE_ERROR_LIMIT_EXCEEDED=3,
752 PDQ_RI_REASON_RESTRICTED_TOKEN_TIMEOUT=4
756 PDQ_LCT_DIRECTION_LOCAL_LCT=0,
757 PDQ_LCT_DIRECTION_REMOTE_LCT=1,
758 PDQ_LCT_DIRECTION_LCT_BOTH_SIDES=2
759 } pdq_lct_direction_t;
767 pdq_uint8_t station_id_bytes[8];
770 typedef pdq_uint32_t pdq_fdditimer_t;
772 * Command format for Start, Filter_Get, ... commands
775 pdq_cmd_code_t generic_op;
779 * Response format for Start, Filter_Set, ... commands
782 pdq_uint32_t generic_reserved;
783 pdq_cmd_code_t generic_op;
784 pdq_response_code_t generic_status;
785 } pdq_response_generic_t;
788 * Command format for Filter_Set command
791 pdq_cmd_code_t filter_set_op;
793 pdq_item_code_t item_code;
794 pdq_filter_state_t filter_state;
795 } filter_set_items[7];
796 pdq_item_code_t filter_set_eol_item_code;
797 } pdq_cmd_filter_set_t;
800 * Response format for Filter_Get command.
803 pdq_uint32_t filter_get_reserved;
804 pdq_cmd_code_t filter_get_op;
805 pdq_response_code_t filter_get_status;
806 pdq_filter_state_t filter_get_ind_group_prom;
807 pdq_filter_state_t filter_get_group_prom;
808 pdq_filter_state_t filter_get_broadcast_all;
809 pdq_filter_state_t filter_get_smt_prom;
810 pdq_filter_state_t filter_get_smt_user;
811 pdq_filter_state_t filter_get_reserved_all;
812 pdq_filter_state_t filter_get_implementor_all;
813 } pdq_response_filter_get_t;
815 #define PDQ_SIZE_RESPONSE_FILTER_GET 0x28
818 pdq_cmd_code_t chars_set_op;
820 pdq_item_code_t item_code;
821 pdq_uint32_t item_value;
822 pdq_port_type_t item_port;
823 } chars_set_items[1];
824 pdq_item_code_t chars_set_eol_item_code;
825 } pdq_cmd_chars_set_t;
828 pdq_cmd_code_t addr_filter_set_op;
829 pdq_lanaddr_t addr_filter_set_addresses[62];
830 } pdq_cmd_addr_filter_set_t;
832 #define PDQ_SIZE_CMD_ADDR_FILTER_SET 0x1F4
835 pdq_uint32_t addr_filter_get_reserved;
836 pdq_cmd_code_t addr_filter_get_op;
837 pdq_response_code_t addr_filter_get_status;
838 pdq_lanaddr_t addr_filter_get_addresses[62];
839 } pdq_response_addr_filter_get_t;
841 #define PDQ_SIZE_RESPONSE_ADDR_FILTER_GET 0x1FC
844 pdq_uint32_t status_chars_get_reserved;
845 pdq_cmd_code_t status_chars_get_op;
846 pdq_response_code_t status_chars_get_status;
848 /* Station Characteristic Attributes */
849 pdq_station_id_t station_id;
850 pdq_station_type_t station_type;
851 pdq_uint32_t smt_version_id;
852 pdq_uint32_t smt_max_version_id;
853 pdq_uint32_t smt_min_version_id;
854 /* Station Status Attributes */
855 pdq_station_state_t station_state;
856 /* Link Characteristic Attributes */
857 pdq_lanaddr_t link_address;
858 pdq_fdditimer_t t_req;
860 pdq_fdditimer_t restricted_token_timeout;
861 pdq_boolean_t ring_purger_enable;
862 pdq_link_state_t link_state;
863 pdq_fdditimer_t negotiated_trt;
864 pdq_da_test_state_t dup_addr_flag;
865 /* Link Status Attributes */
866 pdq_lanaddr_t upstream_neighbor;
867 pdq_lanaddr_t old_upstream_neighbor;
868 pdq_boolean_t upstream_neighbor_dup_addr_flag;
869 pdq_lanaddr_t downstream_neighbor;
870 pdq_lanaddr_t old_downstream_neighbor;
871 pdq_ring_purger_state_t ring_purger_state;
872 pdq_frame_strip_mode_t frame_strip_mode;
873 pdq_ring_error_reason_t ring_error_reason;
874 pdq_boolean_t loopback;
875 pdq_fdditimer_t ring_latency;
876 pdq_lanaddr_t last_dir_beacon_sa;
877 pdq_lanaddr_t last_dir_beacon_una;
878 /* Phy Characteristic Attributes */
879 pdq_phy_type_t phy_type[2];
880 pdq_pmd_type_t pmd_type[2];
881 pdq_uint32_t lem_threshold[2];
882 /* Phy Status Attributes */
883 pdq_phy_state_t phy_state[2];
884 pdq_phy_type_t neighbor_phy_type[2];
885 pdq_uint32_t link_error_estimate[2];
886 pdq_broken_reason_t broken_reason[2];
887 pdq_reject_reason_t reject_reason[2];
889 pdq_uint32_t counter_interval;
890 pdq_fwrev_t module_rev;
891 pdq_fwrev_t firmware_rev;
892 pdq_uint32_t mop_device_type;
893 pdq_uint32_t fddi_led[2];
896 } pdq_response_status_chars_get_t;
898 #define PDQ_SIZE_RESPONSE_STATUS_CHARS_GET 0xF0
901 pdq_uint32_t fddi_mib_get_reserved;
902 pdq_cmd_code_t fddi_mib_get_op;
903 pdq_response_code_t fddi_mib_get_status;
906 pdq_station_id_t smt_station_id;
907 pdq_uint32_t smt_op_version_id;
908 pdq_uint32_t smt_hi_version_id;
909 pdq_uint32_t smt_lo_version_id;
910 pdq_uint32_t smt_mac_ct;
911 pdq_uint32_t smt_non_master_ct;
912 pdq_uint32_t smt_master_ct;
913 pdq_uint32_t smt_paths_available;
914 pdq_uint32_t smt_config_capabilities;
915 pdq_uint32_t smt_config_policy;
916 pdq_uint32_t smt_connection_policy;
917 pdq_uint32_t smt_t_notify;
918 pdq_uint32_t smt_status_reporting;
919 pdq_uint32_t smt_ecm_state;
920 pdq_uint32_t smt_cf_state;
921 pdq_uint32_t smt_hold_state;
922 pdq_uint32_t smt_remote_disconnect_flag;
923 pdq_uint32_t smt_station_action;
925 pdq_uint32_t mac_frame_status_capabilities;
926 pdq_uint32_t mac_t_max_greatest_lower_bound;
927 pdq_uint32_t mac_tvx_greatest_lower_bound;
928 pdq_uint32_t mac_paths_available;
929 pdq_uint32_t mac_current_path;
930 pdq_lanaddr_t mac_upstream_neighbor;
931 pdq_lanaddr_t mac_old_upstream_neighbor;
932 pdq_uint32_t mac_dup_addr_test;
933 pdq_uint32_t mac_paths_requested;
934 pdq_uint32_t mac_downstream_port_type;
935 pdq_lanaddr_t mac_smt_address;
936 pdq_uint32_t mac_t_req;
937 pdq_uint32_t mac_t_neg;
938 pdq_uint32_t mac_t_max;
939 pdq_uint32_t mac_tvx_value;
940 pdq_uint32_t mac_t_min;
941 pdq_uint32_t mac_current_frame_status;
942 pdq_uint32_t mac_frame_error_threshold;
943 pdq_uint32_t mac_frame_error_ratio;
944 pdq_uint32_t mac_rmt_state;
945 pdq_uint32_t mac_da_flag;
946 pdq_uint32_t mac_una_da_flag;
947 pdq_uint32_t mac_frame_condition;
948 pdq_uint32_t mac_chip_set;
949 pdq_uint32_t mac_action;
951 pdq_uint32_t port_pc_type[2];
952 pdq_uint32_t port_pc_neighbor[2];
953 pdq_uint32_t port_connection_policies[2];
954 pdq_uint32_t port_remote_mac_indicated[2];
955 pdq_uint32_t port_ce_state[2];
956 pdq_uint32_t port_paths_requested[2];
957 pdq_uint32_t port_mac_placement[2];
958 pdq_uint32_t port_available_paths[2];
959 pdq_uint32_t port_mac_loop_time[2];
960 pdq_uint32_t port_tb_max[2];
961 pdq_uint32_t port_bs_flag[2];
962 pdq_uint32_t port_ler_estimate[2];
963 pdq_uint32_t port_ler_cutoff[2];
964 pdq_uint32_t port_ler_alarm[2];
965 pdq_uint32_t port_connect_state[2];
966 pdq_uint32_t port_pcm_state[2];
967 pdq_uint32_t port_pc_withhold[2];
968 pdq_uint32_t port_ler_condition[2];
969 pdq_uint32_t port_chip_set[2];
970 pdq_uint32_t port_action[2];
971 /* Attachment Objects */
972 pdq_uint32_t attachment_class;
973 pdq_uint32_t attachment_optical_bypass_present;
974 pdq_uint32_t attachment_imax_expiration;
975 pdq_uint32_t attachment_inserted_status;
976 pdq_uint32_t attachment_insert_policy;
978 } pdq_response_fddi_mib_get_t;
980 #define PDQ_SIZE_RESPONSE_FDDI_MIB_GET 0x17C
983 PDQ_FDX_STATE_IDLE=0,
984 PDQ_FDX_STATE_REQUEST=1,
985 PDQ_FDX_STATE_CONFIRM=2,
986 PDQ_FDX_STATE_OPERATION=3
990 pdq_uint32_t dec_ext_mib_get_reserved;
991 pdq_cmd_code_t dec_ext_mib_get_op;
992 pdq_response_code_t dec_ext_mib_get_response;
995 pdq_uint32_t esmt_station_type;
997 pdq_uint32_t emac_link_state;
998 pdq_uint32_t emac_ring_purger_state;
999 pdq_uint32_t emac_ring_purger_enable;
1000 pdq_uint32_t emac_frame_strip_mode;
1001 pdq_uint32_t emac_ring_error_reason;
1002 pdq_uint32_t emac_upstream_nbr_dupl_address_flag;
1003 pdq_uint32_t emac_restricted_token_timeout;
1005 pdq_uint32_t eport_pmd_type[2];
1006 pdq_uint32_t eport_phy_state[2];
1007 pdq_uint32_t eport_reject_reason[2];
1008 /* Full Duplex Objects */
1009 pdq_boolean_t fdx_enable;
1010 pdq_boolean_t fdx_operational;
1011 pdq_fdx_state_t fdx_state;
1013 } pdq_response_dec_ext_mib_get_t;
1015 #define PDQ_SIZE_RESPONSE_DEC_EXT_MIB_GET 0x50
1018 pdq_cmd_code_t snmp_set_op;
1020 pdq_item_code_t item_code;
1021 pdq_uint32_t item_value;
1022 pdq_port_type_t item_port;
1023 } snmp_set_items[7];
1024 pdq_item_code_t snmp_set_eol_item_code;
1025 } pdq_cmd_snmp_set_t;
1028 PDQ_CALLER_ID_NONE=0,
1029 PDQ_CALLER_ID_SELFTEST=1,
1030 PDQ_CALLER_ID_MFG=2,
1031 PDQ_CALLER_ID_FIRMWARE=5,
1032 PDQ_CALLER_ID_CONSOLE=8
1036 pdq_uint32_t error_log_get__reserved;
1037 pdq_cmd_code_t error_log_get_op;
1038 pdq_response_code_t error_log_get_status;
1040 pdq_uint32_t error_log_get_event_status;
1041 /* Event Information Block */
1042 pdq_caller_id_t error_log_get_caller_id;
1043 pdq_uint32_t error_log_get_timestamp[2];
1044 pdq_uint32_t error_log_get_write_count;
1045 /* Diagnostic Information */
1046 pdq_uint32_t error_log_get_fru_implication_mask;
1047 pdq_uint32_t error_log_get_test_id;
1048 pdq_uint32_t error_log_get_diag_reserved[6];
1049 /* Firmware Information */
1050 pdq_uint32_t error_log_get_fw_reserved[112];
1051 } pdq_response_error_log_get_t;
1055 * Definitions for the Unsolicited Event Queue.
1058 PDQ_UNSOLICITED_EVENT=0,
1059 PDQ_UNSOLICITED_COUNTERS=1
1063 PDQ_ENTITY_STATION=0,
1065 PDQ_ENTITY_PHY_PORT=2,
1070 PDQ_STATION_EVENT_TRACE_RECEIVED=1,
1071 PDQ_STATION_EVENT_MAX=2
1072 } pdq_station_event_t;
1075 PDQ_STATION_EVENT_ARGUMENT_REASON=0, /* pdq_uint32_t */
1076 PDQ_STATION_EVENT_ARGUMENT_EOL=0xFF
1077 } pdq_station_event_argument_t;
1080 PDQ_LINK_EVENT_TRANSMIT_UNDERRUN=0,
1081 PDQ_LINK_EVENT_TRANSMIT_FAILED=1,
1082 PDQ_LINK_EVENT_BLOCK_CHECK_ERROR=2,
1083 PDQ_LINK_EVENT_FRAME_STATUS_ERROR=3,
1084 PDQ_LINK_EVENT_PDU_LENGTH_ERROR=4,
1085 PDQ_LINK_EVENT_RECEIVE_DATA_OVERRUN=7,
1086 PDQ_LINK_EVENT_NO_USER_BUFFER=9,
1087 PDQ_LINK_EVENT_RING_INITIALIZATION_INITIATED=10,
1088 PDQ_LINK_EVENT_RING_INITIALIZATION_RECEIVED=11,
1089 PDQ_LINK_EVENT_RING_BEACON_INITIATED=12,
1090 PDQ_LINK_EVENT_DUPLICATE_ADDRESS_FAILURE=13,
1091 PDQ_LINK_EVENT_DUPLICATE_TOKEN_DETECTED=14,
1092 PDQ_LINK_EVENT_RING_PURGE_ERROR=15,
1093 PDQ_LINK_EVENT_FCI_STRIP_ERROR=16,
1094 PDQ_LINK_EVENT_TRACE_INITIATED=17,
1095 PDQ_LINK_EVENT_DIRECTED_BEACON_RECEIVED=18,
1096 PDQ_LINK_EVENT_MAX=19
1100 PDQ_LINK_EVENT_ARGUMENT_REASON=0, /* pdq_rireason_t */
1101 PDQ_LINK_EVENT_ARGUMENT_DATA_LINK_HEADER=1, /* pdq_dlhdr_t */
1102 PDQ_LINK_EVENT_ARGUMENT_SOURCE=2, /* pdq_lanaddr_t */
1103 PDQ_LINK_EVENT_ARGUMENT_UPSTREAM_NEIGHBOR=3,/* pdq_lanaddr_t */
1104 PDQ_LINK_EVENT_ARGUMENT_EOL=0xFF
1105 } pdq_link_event_argument_t;
1108 PDQ_PHY_EVENT_LEM_ERROR_MONITOR_REJECT=0,
1109 PDQ_PHY_EVENT_ELASTICITY_BUFFER_ERROR=1,
1110 PDQ_PHY_EVENT_LINK_CONFIDENCE_TEST_REJECT=2,
1115 PDQ_PHY_EVENT_ARGUMENT_DIRECTION=0, /* pdq_lct_direction_t */
1116 PDQ_PHY_EVENT_ARGUMENT_EOL=0xFF
1117 } pdq_phy_event_arguments;
1119 struct _pdq_unsolicited_event_t {
1120 pdq_uint32_t rvent_reserved;
1121 pdq_event_t event_type;
1122 pdq_entity_t event_entity;
1123 pdq_uint32_t event_index;
1125 pdq_station_event_t station_event;
1126 pdq_link_event_t link_event;
1127 pdq_phy_event_t phy_event;
1131 * The remainder of this event is an argument list.
1133 pdq_uint32_t event__filler[123];
1136 #endif /* _PDQREG_H */