1 /*******************************************************************************
2 *Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved.
4 *Redistribution and use in source and binary forms, with or without modification, are permitted provided
5 *that the following conditions are met:
6 *1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
8 *2. Redistributions in binary form must reproduce the above copyright notice,
9 *this list of conditions and the following disclaimer in the documentation and/or other materials provided
10 *with the distribution.
12 *THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 *WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
14 *FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
15 *FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 *NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
17 *BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
18 *LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
19 *SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
23 ********************************************************************************/
24 /*******************************************************************************/
27 * The file contains defines and data structures for SAS/SATA TD layer
45 #define agNULL ((void *)0)
65 #define os_bit16 bit16
69 #define os_bit32 bit32
81 #define MIN(a,b) ((a) < (b) ? (a) : (b))
85 #define MAX(a,b) ((a) < (b) ? (b) : (a))
88 #define TD_OPERATION_INITIATOR 0x1
89 #define TD_OPERATION_TARGET 0x2
91 /* indices for mem_t structures */
92 #define DEK_MEM_INDEX_1 15
93 #define DEK_MEM_INDEX_2 16
95 /* some useful macros */
97 #define AG_ALIGNSIZE(count, alignment) (bit32) ( (bitptr)(count)+(bitptr)(alignment) )
100 #define DEFAULT_KEY_BUFFER_SIZE 64
102 /**< the default maximum number of phys */
105 #define TD_MAX_NUM_PHYS 2
108 #define TD_MAX_NUM_PHYS 16
109 #define TD_MAX_CARD_NUM 20
112 #define TD_CARD_ID_FREE 0
113 #define TD_CARD_ID_ALLOC 1
114 #define TD_CARD_ID_LEN 128
116 /**< the maximum number of port context */
117 /* should be the number of phyical phys in chip + 1 */
118 #define TD_MAX_PORT_CONTEXT 16
119 /**< the maximum number of target device */
120 /* For Initiator and Target
121 this is initial value for MaxTargets in the configuration(adj) file */
122 #define DEFAULT_MAX_DEV 256
123 /* the maximum number of interrupt coalesce context */
124 #define TD_MAX_INT_COALESCE 512
126 #if (defined(__FreeBSD__))
127 #define MAX_OUTSTANDING_IO_PER_LUN 64
129 #define MAX_OUTSTANDING_IO_PER_LUN 254 //64
133 #define DEFAULT_MAX_ACTIVE_IOS 128
134 #define DEFAULT_NUM_REG_CLIENTS 256
135 #define DEFAULT_NUM_INBOUND_QUEUE 1
136 #define DEFAULT_NUM_OUTBOUND_QUEUE 1
137 #define DEFAULT_INBOUND_QUEUE_SIZE 512
138 #define DEFAULT_INBOUND_QUEUE_ELE_SIZE 128
139 #define DEFAULT_OUTBOUND_QUEUE_SIZE 512
140 #define DEFAULT_OUTBOUND_QUEUE_ELE_SIZE 128
141 #define DEFAULT_OUTBOUND_QUEUE_INTERRUPT_DELAY 0
142 #define DEFAULT_OUTBOUND_QUEUE_INTERRUPT_COUNT 1
143 #define DEFAULT_OUTBOUND_INTERRUPT_ENABLE 1
144 #define DEFAULT_INBOUND_QUEUE_PRIORITY 0
145 #define DEFAULT_QUEUE_OPTION 0
146 #define DEFAULT_FW_MAX_PORTS 8
150 /* SAS device type definition. SAS spec(r.7) p206 */
151 #define SAS_NO_DEVICE 0
152 #define SAS_END_DEVICE 1
153 #define SAS_EDGE_EXPANDER_DEVICE 2
154 #define SAS_FANOUT_EXPANDER_DEVICE 3
156 /* routing attributes */
157 #define SAS_ROUTING_DIRECT 0x00
158 #define SAS_ROUTING_SUBTRACTIVE 0x01
159 #define SAS_ROUTING_TABLE 0x02
161 #define SAS_CONNECTION_RATE_1_5G 0x08
162 #define SAS_CONNECTION_RATE_3_0G 0x09
163 #define SAS_CONNECTION_RATE_6_0G 0x0A
164 #define SAS_CONNECTION_RATE_12_0G 0x0B
166 /**< defines the maximum number of expanders */
167 #define TD_MAX_EXPANDER_PHYS 256
168 /**< the maximum number of expanders at TD */
169 #define TD_MAX_EXPANDER 128
171 /*****************************************************************************
172 ** SCSI Operation Codes (first byte in CDB)
173 *****************************************************************************/
176 #define SCSIOPC_TEST_UNIT_READY 0x00
177 #define SCSIOPC_INQUIRY 0x12
178 #define SCSIOPC_MODE_SENSE_6 0x1A
179 #define SCSIOPC_MODE_SENSE_10 0x5A
180 #define SCSIOPC_MODE_SELECT_6 0x15
181 #define SCSIOPC_START_STOP_UNIT 0x1B
182 #define SCSIOPC_READ_CAPACITY_10 0x25
183 #define SCSIOPC_READ_CAPACITY_16 0x9E
184 #define SCSIOPC_READ_6 0x08
185 #define SCSIOPC_READ_10 0x28
186 #define SCSIOPC_READ_12 0xA8
187 #define SCSIOPC_READ_16 0x88
188 #define SCSIOPC_WRITE_6 0x0A
189 #define SCSIOPC_WRITE_10 0x2A
190 #define SCSIOPC_WRITE_12 0xAA
191 #define SCSIOPC_WRITE_16 0x8A
192 #define SCSIOPC_WRITE_VERIFY 0x2E
193 #define SCSIOPC_VERIFY_10 0x2F
194 #define SCSIOPC_VERIFY_12 0xAF
195 #define SCSIOPC_VERIFY_16 0x8F
196 #define SCSIOPC_REQUEST_SENSE 0x03
197 #define SCSIOPC_REPORT_LUN 0xA0
198 #define SCSIOPC_FORMAT_UNIT 0x04
199 #define SCSIOPC_SEND_DIAGNOSTIC 0x1D
200 #define SCSIOPC_WRITE_SAME_10 0x41
201 #define SCSIOPC_WRITE_SAME_16 0x93
202 #define SCSIOPC_READ_BUFFER 0x3C
203 #define SCSIOPC_WRITE_BUFFER 0x3B
205 #define SCSIOPC_GET_CONFIG 0x46
206 #define SCSIOPC_GET_EVENT_STATUS_NOTIFICATION 0x4a
207 #define SCSIOPC_REPORT_KEY 0xA4
208 #define SCSIOPC_SEND_KEY 0xA3
209 #define SCSIOPC_READ_DVD_STRUCTURE 0xAD
210 #define SCSIOPC_TOC 0x43
211 #define SCSIOPC_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1E
212 #define SCSIOPC_READ_VERIFY 0x42
214 #define SCSIOPC_LOG_SENSE 0x4D
215 #define SCSIOPC_LOG_SELECT 0x4C
216 #define SCSIOPC_MODE_SELECT_6 0x15
217 #define SCSIOPC_MODE_SELECT_10 0x55
218 #define SCSIOPC_SYNCHRONIZE_CACHE_10 0x35
219 #define SCSIOPC_SYNCHRONIZE_CACHE_16 0x91
220 #define SCSIOPC_WRITE_AND_VERIFY_10 0x2E
221 #define SCSIOPC_WRITE_AND_VERIFY_12 0xAE
222 #define SCSIOPC_WRITE_AND_VERIFY_16 0x8E
223 #define SCSIOPC_READ_MEDIA_SERIAL_NUMBER 0xAB
224 #define SCSIOPC_REASSIGN_BLOCKS 0x07
230 /*****************************************************************************
231 ** SCSI GENERIC 6 BYTE CDB
232 *****************************************************************************/
233 typedef struct CBD6_s {
235 bit8 rsv; /* not 100% correct */
236 bit8 lba[2]; /* not 100% correct */
243 /*****************************************************************************
244 ** SCSI GENERIC 10 BYTE CDB
245 *****************************************************************************/
246 typedef struct CBD10_s {
255 /*****************************************************************************
256 ** SCSI GENERIC 12 BYTE CDB
257 *****************************************************************************/
258 typedef struct CBD12_s {
268 /*****************************************************************************
269 ** SCSI GENERIC 16 BYTE CDB
270 *****************************************************************************/
271 typedef struct CBD16_s {
281 #define BLOCK_BYTE_LENGTH 512
283 /*****************************************************************************
285 *****************************************************************************/
287 #define SCSI_STATUS_GOOD 0x00
288 #define SCSI_STATUS_CHECK_CONDITION 0x02
289 #define SCSI_STATUS_BUSY 0x08
290 #define SCSI_STATUS_COMMAND_TERMINATED 0x22
291 #define SCSI_STATUS_TASK_SET_FULL 0x28
293 /*****************************************************************************
294 ** SAS TM Function data present see SAS spec p311 Table 109 (Revision 7)
295 *****************************************************************************/
297 #define RESPONSE_DATA 1
300 /* 4 bytes, SAS spec p312 Table 110 (Revision 7) */
301 #define RESPONSE_DATA_LEN 4
307 #define SMP_REQUEST 0x40
308 #define SMP_RESPONSE 0x41
310 #define SMP_INITIATOR 0x01
311 #define SMP_TARGET 0x02
313 /* default SMP timeout: 0xFFFF is the Maximum Allowed */
314 #define DEFAULT_SMP_TIMEOUT 0xFFFF
316 /* SMP direct payload size limit: IOMB direct payload size = 48 */
317 #define SMP_DIRECT_PAYLOAD_LIMIT 44
320 #define SMP_REPORT_GENERAL 0x00
321 #define SMP_REPORT_MANUFACTURE_INFORMATION 0x01
322 #define SMP_READ_GPIO_REGISTER 0x02
323 #define SMP_DISCOVER 0x10
324 #define SMP_REPORT_PHY_ERROR_LOG 0x11
325 #define SMP_REPORT_PHY_SATA 0x12
326 #define SMP_REPORT_ROUTING_INFORMATION 0x13
327 #define SMP_WRITE_GPIO_REGISTER 0x82
328 #define SMP_CONFIGURE_ROUTING_INFORMATION 0x90
329 #define SMP_PHY_CONTROL 0x91
330 #define SMP_PHY_TEST_FUNCTION 0x92
331 #define SMP_PMC_SPECIFIC 0xC0
334 /* SMP function results */
335 #define SMP_FUNCTION_ACCEPTED 0x00
336 #define UNKNOWN_SMP_FUNCTION 0x01
337 #define SMP_FUNCTION_FAILED 0x02
338 #define INVALID_REQUEST_FRAME_LENGTH 0x03
339 #define INVALID_EXPANDER_CHANGE_COUNT 0x04
340 #define SMP_FN_BUSY 0x05
341 #define INCOMPLETE_DESCRIPTOR_LIST 0x06
342 #define PHY_DOES_NOT_EXIST 0x10
343 #define INDEX_DOES_NOT_EXIST 0x11
344 #define PHY_DOES_NOT_SUPPORT_SATA 0x12
345 #define UNKNOWN_PHY_OPERATION 0x13
346 #define UNKNOWN_PHY_TEST_FUNCTION 0x14
347 #define PHY_TEST_FUNCTION_IN_PROGRESS 0x15
348 #define PHY_VACANT 0x16
349 #define UNKNOWN_PHY_EVENT_SOURCE 0x17
350 #define UNKNOWN_DESCRIPTOT_TYPE 0x18
351 #define UNKNOWN_PHY_FILETER 0x19
352 #define AFFILIATION_VIOLATION 0x1A
353 #define SMP_ZONE_VIOLATION 0x20
354 #define NO_MANAGEMENT_ACCESS_RIGHTS 0x21
355 #define UNKNOWN_ENABLE_DISABLE_ZONING_VALUE 0x22
356 #define ZONE_LOCK_VIOLATION 0x23
357 #define NOT_ACTIVATED 0x24
358 #define ZONE_GROUP_OUT_OF_RANGE 0x25
359 #define NO_PHYSICAL_PRESENCE 0x26
360 #define SAVING_NOT_SUPPORTED 0x27
361 #define SOURCE_ZONE_GROUP_DOES_NOT_EXIST 0x28
362 #define DISABLED_PASSWORD_NOT_SUPPORTED 0x29
364 /* SMP PHY CONTROL OPERATION */
365 #define SMP_PHY_CONTROL_NOP 0x00
366 #define SMP_PHY_CONTROL_LINK_RESET 0x01
367 #define SMP_PHY_CONTROL_HARD_RESET 0x02
368 #define SMP_PHY_CONTROL_DISABLE 0x03
369 #define SMP_PHY_CONTROL_CLEAR_ERROR_LOG 0x05
370 #define SMP_PHY_CONTROL_CLEAR_AFFILIATION 0x06
371 #define SMP_PHY_CONTROL_XMIT_SATA_PS_SIGNAL 0x07
374 #define IT_NEXUS_TIMEOUT 0x7D0 /* 2000 ms; old value was 0xFFFF */
376 #define PORT_RECOVERY_TIMEOUT ((IT_NEXUS_TIMEOUT/100) + 30) /* 5000 ms; in 100ms; should be large than IT_NEXUS_TIMEOUT */
378 #define STP_IDLE_TIME 5 /* 5 us; the defaulf of the controller */
380 #define SET_ESGL_EXTEND(val) \
381 ((val) = (val) | 0x80000000)
383 #define CLEAR_ESGL_EXTEND(val) \
384 ((val) = (val) & 0x7FFFFFFF)
386 #define DEVINFO_GET_SAS_ADDRESSLO(devInfo) \
387 DMA_BEBIT32_TO_BIT32(*(bit32 *)(devInfo)->sasAddressLo)
389 #define DEVINFO_GET_SAS_ADDRESSHI(devInfo) \
390 DMA_BEBIT32_TO_BIT32(*(bit32 *)(devInfo)->sasAddressHi)
392 /* this macro is based on SAS spec, not sTSDK 0xC0 */
393 #define DEVINFO_GET_DEVICETTYPE(devInfo) \
394 (((devInfo)->devType_S_Rate & 0xC0) >> 6)
396 #define DEVINFO_GET_LINKRATE(devInfo) \
397 ((devInfo)->devType_S_Rate & 0x0F)
399 #define DEVINFO_GET_EXT_MCN(devInfo) \
400 (((devInfo)->ext & 0x7800) >> 11)
403 #define DEVINFO_PUT_SMPTO(devInfo, smpto) \
404 ((devInfo)->smpTimeout) = smpto
406 #define DEVINFO_PUT_ITNEXUSTO(devInfo, itnexusto) \
407 ((devInfo)->it_NexusTimeout) = itnexusto
409 #define DEVINFO_PUT_FBS(devInfo, fbs) \
410 ((devInfo)->firstBurstSize) = fbs
412 #define DEVINFO_PUT_FLAG(devInfo, tlr) \
413 ((devInfo)->flag) = tlr
415 #define DEVINFO_PUT_DEV_S_RATE(devInfo, dev_s_rate) \
416 ((devInfo)->devType_S_Rate) = dev_s_rate
418 #define DEVINFO_PUT_SAS_ADDRESSLO(devInfo, src32) \
419 *(bit32 *)((devInfo)->sasAddressLo) = BIT32_TO_DMA_BEBIT32(src32)
421 #define DEVINFO_PUT_SAS_ADDRESSHI(devInfo, src32) \
422 *(bit32 *)((devInfo)->sasAddressHi) = BIT32_TO_DMA_BEBIT32(src32)
424 #define DEVICE_SSP_BIT 0x8 /* SSP Initiator port */
425 #define DEVICE_STP_BIT 0x4 /* STP Initiator port */
426 #define DEVICE_SMP_BIT 0x2 /* SMP Initiator port */
427 #define DEVICE_SATA_BIT 0x1 /* SATA device, valid in the discovery response only */
429 #define DEVICE_IS_SSP_INITIATOR(DeviceData) \
430 (((DeviceData)->initiator_ssp_stp_smp & DEVICE_SSP_BIT) == DEVICE_SSP_BIT)
432 #define DEVICE_IS_STP_INITIATOR(DeviceData) \
433 (((DeviceData)->initiator_ssp_stp_smp & DEVICE_STP_BIT) == DEVICE_STP_BIT)
435 #define DEVICE_IS_SMP_INITIATOR(DeviceData) \
436 (((DeviceData)->initiator_ssp_stp_smp & DEVICE_SMP_BIT) == DEVICE_SMP_BIT)
438 #define DEVICE_IS_SSP_TARGET(DeviceData) \
439 (((DeviceData)->target_ssp_stp_smp & DEVICE_SSP_BIT) == DEVICE_SSP_BIT)
441 #define DEVICE_IS_STP_TARGET(DeviceData) \
442 (((DeviceData)->target_ssp_stp_smp & DEVICE_STP_BIT) == DEVICE_STP_BIT)
444 #define DEVICE_IS_SMP_TARGET(DeviceData) \
445 (((DeviceData)->target_ssp_stp_smp & DEVICE_SMP_BIT) == DEVICE_SMP_BIT)
447 #define DEVICE_IS_SATA_DEVICE(DeviceData) \
448 (((DeviceData)->target_ssp_stp_smp & DEVICE_SATA_BIT) == DEVICE_SATA_BIT)
453 /* Negotiated Phyical Link Rate
454 #define Phy_ENABLED_UNKNOWN
456 /* old SMP header definition */
457 typedef struct tdssSMPFrameHeader_s
459 bit8 smpFrameType; /* The first byte of SMP frame represents the SMP FRAME TYPE */
460 bit8 smpFunction; /* The second byte of the SMP frame represents the SMP FUNCTION */
461 bit8 smpFunctionResult; /* The third byte of SMP frame represents FUNCTION RESULT of the SMP response. */
462 bit8 smpReserved; /* reserved */
463 } tdssSMPFrameHeader_t;
465 /****************************************************************
466 * report general request
467 ****************************************************************/
468 #ifdef FOR_COMPLETENESS
469 typedef struct smpReqReportGeneral_s
471 /* nothing. some compiler disallowed structure with no member */
472 } smpReqReportGeneral_t;
475 /****************************************************************
476 * report general response
477 ****************************************************************/
478 #define REPORT_GENERAL_CONFIGURING_BIT 0x2
479 #define REPORT_GENERAL_CONFIGURABLE_BIT 0x1
481 typedef struct smpRespReportGeneral_s
483 bit8 expanderChangeCount16[2];
484 bit8 expanderRouteIndexes16[2];
487 bit8 configuring_configurable;
488 /* B7-2 : reserved */
489 /* B1 : configuring */
490 /* B0 : configurable */
492 } smpRespReportGeneral_t;
494 #define REPORT_GENERAL_IS_CONFIGURING(pResp) \
495 (((pResp)->configuring_configurable & REPORT_GENERAL_CONFIGURING_BIT) == \
496 REPORT_GENERAL_CONFIGURING_BIT)
498 #define REPORT_GENERAL_IS_CONFIGURABLE(pResp) \
499 (((pResp)->configuring_configurable & REPORT_GENERAL_CONFIGURABLE_BIT) == \
500 REPORT_GENERAL_CONFIGURABLE_BIT)
502 #define REPORT_GENERAL_GET_ROUTEINDEXES(pResp) \
503 DMA_BEBIT16_TO_BIT16(*(bit16 *)((pResp)->expanderRouteIndexes16))
506 /****************************************************************
507 * report manufacturer info response
508 ****************************************************************/
509 typedef struct smpRespReportManufactureInfo_s
512 bit8 vendorIdentification[8];
513 bit8 productIdentification[16];
514 bit8 productRevisionLevel[4];
515 bit8 vendorSpecific[20];
516 } smpRespReportManufactureInfo_t;
518 /****************************************************************
520 ****************************************************************/
521 typedef struct smpReqDiscover_s
530 /****************************************************************
532 ****************************************************************/
533 typedef struct smpRespDiscover_s
539 bit8 attachedDeviceType;
541 /* B6-4 : attachedDeviceType */
542 /* B3-0 : reserved */
543 bit8 negotiatedPhyLinkRate;
544 /* B7-4 : reserved */
545 /* B3-0 : negotiatedPhyLinkRate */
546 bit8 attached_Ssp_Stp_Smp_Sata_Initiator;
547 /* B7-4 : reserved */
548 /* B3 : attachedSspInitiator */
549 /* B2 : attachedStpInitiator */
550 /* B1 : attachedSmpInitiator */
551 /* B0 : attachedSataHost */
552 bit8 attached_SataPS_Ssp_Stp_Smp_Sata_Target;
553 /* B7 : attachedSataPortSelector */
554 /* B6-4 : reserved */
555 /* B3 : attachedSspTarget */
556 /* B2 : attachedStpTarget */
557 /* B1 : attachedSmpTarget */
558 /* B0 : attachedSatadevice */
559 bit8 sasAddressHi[4];
560 bit8 sasAddressLo[4];
561 bit8 attachedSasAddressHi[4];
562 bit8 attachedSasAddressLo[4];
563 bit8 attachedPhyIdentifier;
565 bit8 programmedAndHardware_MinPhyLinkRate;
566 /* B7-4 : programmedMinPhyLinkRate */
567 /* B3-0 : hardwareMinPhyLinkRate */
568 bit8 programmedAndHardware_MaxPhyLinkRate;
569 /* B7-4 : programmedMaxPhyLinkRate */
570 /* B3-0 : hardwareMaxPhyLinkRate */
572 bit8 virtualPhy_partialPathwayTimeout;
574 /* B6-4 : reserved */
575 /* B3-0 : partialPathwayTimeout */
576 bit8 routingAttribute;
577 /* B7-4 : reserved */
578 /* B3-0 : routingAttribute */
580 bit8 vendorSpecific[2];
583 #define DISCRSP_SSP_BIT 0x08
584 #define DISCRSP_STP_BIT 0x04
585 #define DISCRSP_SMP_BIT 0x02
586 #define DISCRSP_SATA_BIT 0x01
588 #define DISCRSP_SATA_PS_BIT 0x80
590 #define DISCRSP_GET_ATTACHED_DEVTYPE(pResp) \
591 (((pResp)->attachedDeviceType & 0x70) >> 4)
592 #define DISCRSP_GET_LINKRATE(pResp) \
593 ((bit8)((pResp)->negotiatedPhyLinkRate & 0x0F))
595 #define DISCRSP_IS_SSP_INITIATOR(pResp) \
596 (((pResp)->attached_Ssp_Stp_Smp_Sata_Initiator & DISCRSP_SSP_BIT) == DISCRSP_SSP_BIT)
597 #define DISCRSP_IS_STP_INITIATOR(pResp) \
598 (((pResp)->attached_Ssp_Stp_Smp_Sata_Initiator & DISCRSP_STP_BIT) == DISCRSP_STP_BIT)
599 #define DISCRSP_IS_SMP_INITIATOR(pResp) \
600 (((pResp)->attached_Ssp_Stp_Smp_Sata_Initiator & DISCRSP_SMP_BIT) == DISCRSP_SMP_BIT)
601 #define DISCRSP_IS_SATA_HOST(pResp) \
602 (((pResp)->attached_Ssp_Stp_Smp_Sata_Initiator & DISCRSP_SATA_BIT) == DISCRSP_SATA_BIT)
604 #define DISCRSP_IS_SSP_TARGET(pResp) \
605 (((pResp)->attached_SataPS_Ssp_Stp_Smp_Sata_Target & DISCRSP_SSP_BIT) == DISCRSP_SSP_BIT)
606 #define DISCRSP_IS_STP_TARGET(pResp) \
607 (((pResp)->attached_SataPS_Ssp_Stp_Smp_Sata_Target & DISCRSP_STP_BIT) == DISCRSP_STP_BIT)
608 #define DISCRSP_IS_SMP_TARGET(pResp) \
609 (((pResp)->attached_SataPS_Ssp_Stp_Smp_Sata_Target & DISCRSP_SMP_BIT) == DISCRSP_SMP_BIT)
610 #define DISCRSP_IS_SATA_DEVICE(pResp) \
611 (((pResp)->attached_SataPS_Ssp_Stp_Smp_Sata_Target & DISCRSP_SATA_BIT) == DISCRSP_SATA_BIT)
612 #define DISCRSP_IS_SATA_PORTSELECTOR(pResp) \
613 (((pResp)->attached_SataPS_Ssp_Stp_Smp_Sata_Target & DISCRSP_SATA_PS_BIT) == DISCRSP_SATA_PS_BIT)
615 #define DISCRSP_GET_SAS_ADDRESSHI(pResp) \
616 DMA_BEBIT32_TO_BIT32(*(bit32 *)(pResp)->sasAddressHi)
617 #define DISCRSP_GET_SAS_ADDRESSLO(pResp) \
618 DMA_BEBIT32_TO_BIT32(*(bit32 *)(pResp)->sasAddressLo)
620 #define DISCRSP_GET_ATTACHED_SAS_ADDRESSHI(pResp) \
621 DMA_BEBIT32_TO_BIT32(*(bit32 *)(pResp)->attachedSasAddressHi)
622 #define DISCRSP_GET_ATTACHED_SAS_ADDRESSLO(pResp) \
623 DMA_BEBIT32_TO_BIT32(*(bit32 *)(pResp)->attachedSasAddressLo)
625 #define DISCRSP_VIRTUALPHY_BIT 0x80
626 #define DISCRSP_IS_VIRTUALPHY(pResp) \
627 (((pResp)->virtualPhy_partialPathwayTimeout & DISCRSP_VIRTUALPHY_BIT) == DISCRSP_VIRTUALPHY_BIT)
629 #define DISCRSP_GET_ROUTINGATTRIB(pResp) \
630 ((bit8)((pResp)->routingAttribute & 0x0F))
632 /****************************************************************
633 * report route table request
634 ****************************************************************/
635 typedef struct smpReqReportRouteTable_s
638 bit8 expanderRouteIndex16[20];
642 } smpReqReportRouteTable_t;
644 /****************************************************************
645 * report route response
646 ****************************************************************/
647 typedef struct smpRespReportRouteTable_s
650 bit8 expanderRouteIndex16[2];
655 /* B7 : expander route entry disabled */
656 /* B6-0 : reserved */
658 bit8 routedSasAddressHi32[4];
659 bit8 routedSasAddressLo32[4];
661 } smpRespReportRouteTable_t;
663 /****************************************************************
664 * configure route information request
665 ****************************************************************/
666 typedef struct smpReqConfigureRouteInformation_s
669 bit8 expanderRouteIndex[2];
673 bit8 disabledBit_reserved4;
675 bit8 routedSasAddressHi[4];
676 bit8 routedSasAddressLo[4];
678 } smpReqConfigureRouteInformation_t;
680 /****************************************************************
681 * configure route response
682 ****************************************************************/
683 #ifdef FOR_COMPLETENESS
684 typedef struct smpRespConfigureRouteInformation_s
686 /* nothing. some compiler disallowed structure with no member */
687 } smpRespConfigureRouteInformation_t;
690 /****************************************************************
691 * report Phy Sata request
692 ****************************************************************/
693 typedef struct smpReqReportPhySata_s
699 } smpReqReportPhySata_t;
701 /****************************************************************
702 * report Phy Sata response
703 ****************************************************************/
704 typedef struct smpRespReportPhySata_s
710 bit8 affiliations_sup_valid;
711 /* b7-2 : reserved */
712 /* b1 : Affiliations supported */
713 /* b0 : Affiliation valid */
715 bit8 stpSasAddressHi[4];
716 bit8 stpSasAddressLo[4];
717 bit8 regDevToHostFis[20];
719 bit8 affiliatedStpInitiatorSasAddressHi[4];
720 bit8 affiliatedStpInitiatorSasAddressLo[4];
721 } smpRespReportPhySata_t;
724 /****************************************************************
725 * Phy Control request
726 ****************************************************************/
727 typedef struct smpReqPhyControl_s
733 bit8 updatePartialPathwayTOValue;
734 /* b7-1 : reserved */
735 /* b0 : update partial pathway timeout value */
737 bit8 programmedMinPhysicalLinkRate;
738 /* b7-4 : programmed Minimum Physical Link Rate*/
739 /* b3-0 : reserved */
740 bit8 programmedMaxPhysicalLinkRate;
741 /* b7-4 : programmed Maximum Physical Link Rate*/
742 /* b3-0 : reserved */
744 bit8 partialPathwayTOValue;
745 /* b7-4 : reserved */
746 /* b3-0 : partial Pathway TO Value */
748 } smpReqPhyControl_t;
750 /****************************************************************
751 * Phy Control response
752 ****************************************************************/
753 #ifdef FOR_COMPLETENESS
754 typedef struct smpRespPhyControl_s
756 /* nothing. some compiler disallowed structure with no member */
757 } smpRespPhyControl_t;
761 /*****************************************************************************
762 ** SCSI SENSE KEY VALUES
763 *****************************************************************************/
765 #define SCSI_SNSKEY_NO_SENSE 0x00
766 #define SCSI_SNSKEY_RECOVERED_ERROR 0x01
767 #define SCSI_SNSKEY_NOT_READY 0x02
768 #define SCSI_SNSKEY_MEDIUM_ERROR 0x03
769 #define SCSI_SNSKEY_HARDWARE_ERROR 0x04
770 #define SCSI_SNSKEY_ILLEGAL_REQUEST 0x05
771 #define SCSI_SNSKEY_UNIT_ATTENTION 0x06
772 #define SCSI_SNSKEY_DATA_PROTECT 0x07
773 #define SCSI_SNSKEY_ABORTED_COMMAND 0x0B
774 #define SCSI_SNSKEY_MISCOMPARE 0x0E
776 /*****************************************************************************
777 ** SCSI Additional Sense Codes and Qualifiers combo two-bytes
778 *****************************************************************************/
780 #define SCSI_SNSCODE_NO_ADDITIONAL_INFO 0x0000
781 #define SCSI_SNSCODE_LUN_CRC_ERROR_DETECTED 0x0803
782 #define SCSI_SNSCODE_INVALID_COMMAND 0x2000
783 #define SCSI_SNSCODE_LOGICAL_BLOCK_OUT 0x2100
784 #define SCSI_SNSCODE_INVALID_FIELD_IN_CDB 0x2400
785 #define SCSI_SNSCODE_LOGICAL_NOT_SUPPORTED 0x2500
786 #define SCSI_SNSCODE_POWERON_RESET 0x2900
787 #define SCSI_SNSCODE_EVERLAPPED_CMDS 0x4e00
788 #define SCSI_SNSCODE_INTERNAL_TARGET_FAILURE 0x4400
789 #define SCSI_SNSCODE_MEDIUM_NOT_PRESENT 0x3a00
790 #define SCSI_SNSCODE_UNRECOVERED_READ_ERROR 0x1100
791 #define SCSI_SNSCODE_RECORD_NOT_FOUND 0x1401
792 #define SCSI_SNSCODE_NOT_READY_TO_READY_CHANGE 0x2800
793 #define SCSI_SNSCODE_OPERATOR_MEDIUM_REMOVAL_REQUEST 0x5a01
794 #define SCSI_SNSCODE_INFORMATION_UNIT_CRC_ERROR 0x4703
795 #define SCSI_SNSCODE_LOGICAL_UNIT_NOT_READY_FORMAT_IN_PROGRESS 0x0404
796 #define SCSI_SNSCODE_HARDWARE_IMPENDING_FAILURE 0x5d10
797 #define SCSI_SNSCODE_LOW_POWER_CONDITION_ON 0x5e00
798 #define SCSI_SNSCODE_LOGICAL_UNIT_NOT_READY_INIT_REQUIRED 0x0402
799 #define SCSI_SNSCODE_INVALID_FIELD_PARAMETER_LIST 0x2600
800 #define SCSI_SNSCODE_ATA_DEVICE_FAILED_SET_FEATURES 0x4471
801 #define SCSI_SNSCODE_ATA_DEVICE_FEATURE_NOT_ENABLED 0x670B
802 #define SCSI_SNSCODE_LOGICAL_UNIT_FAILED_SELF_TEST 0x3E03
803 #define SCSI_SNSCODE_COMMAND_SEQUENCE_ERROR 0x2C00
804 #define SCSI_SNSCODE_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE 0x2100
805 #define SCSI_SNSCODE_LOGICAL_UNIT_FAILURE 0x3E01
806 #define SCSI_SNSCODE_MEDIA_LOAD_OR_EJECT_FAILED 0x5300
807 #define SCSI_SNSCODE_LOGICAL_UNIT_NOT_READY_INITIALIZING_COMMAND_REQUIRED 0x0402
808 #define SCSI_SNSCODE_LOGICAL_UNIT_NOT_READY_CAUSE_NOT_REPORTABLE 0x0400
809 #define SCSI_SNSCODE_LOGICAL_UNIT_DOES_NOT_RESPOND_TO_SELECTION 0x0500
810 #define SCSI_SNSCODE_DIAGNOSTIC_FAILURE_ON_COMPONENT_NN 0x4000
811 #define SCSI_SNSCODE_COMMANDS_CLEARED_BY_ANOTHER_INITIATOR 0x2F00
812 #define SCSI_SNSCODE_WRITE_ERROR_AUTO_REALLOCATION_FAILED 0x0C02
813 /*****************************************************************************
814 ** SCSI Additional Sense Codes and Qualifiers saparate bytes
815 *****************************************************************************/
817 #define SCSI_ASC_NOTREADY_INIT_CMD_REQ 0x04
818 #define SCSI_ASCQ_NOTREADY_INIT_CMD_REQ 0x02
821 /*****************************************************************************
822 ** Inquiry command fields and response sizes
823 *****************************************************************************/
824 #define SCSIOP_INQUIRY_CMDDT 0x02
825 #define SCSIOP_INQUIRY_EVPD 0x01
826 #define STANDARD_INQUIRY_SIZE 36
827 #define SATA_PAGE83_INQUIRY_WWN_SIZE 16 /* SAT, revision8, Table81, p78, 12 + 4 */
828 #define SATA_PAGE83_INQUIRY_NO_WWN_SIZE 76 /* SAT, revision8, Table81, p78, 72 + 4 */
829 #define SATA_PAGE89_INQUIRY_SIZE 572 /* SAT, revision8, Table87, p84 */
830 #define SATA_PAGE0_INQUIRY_SIZE 8 /* SPC-4, 7.6.9 Table331, p345 */
831 #define SATA_PAGE80_INQUIRY_SIZE 24 /* SAT, revision8, Table79, p77 */
835 /* define byte swap macro */
836 #define AGSA_FLIP_2_BYTES(_x) ((bit16)(((((bit16)(_x))&0x00FF)<<8)| \
837 ((((bit16)(_x))&0xFF00)>>8)))
839 #define AGSA_FLIP_4_BYTES(_x) ((bit32)(((((bit32)(_x))&0x000000FF)<<24)| \
840 ((((bit32)(_x))&0x0000FF00)<<8)| \
841 ((((bit32)(_x))&0x00FF0000)>>8)| \
842 ((((bit32)(_x))&0xFF000000)>>24)))
845 /*********************************************************************
846 ** BUFFER CONVERTION MACROS
847 *********************************************************************/
849 /*********************************************************************
850 * CPU buffer access macro *
854 #define OSSA_OFFSET_OF(STRUCT_TYPE, FEILD) \
855 (bitptr)&(((STRUCT_TYPE *)0)->FEILD)
858 #if defined(SA_CPU_LITTLE_ENDIAN)
860 #define OSSA_WRITE_LE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \
861 (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit16)(VALUE16);
863 #define OSSA_WRITE_LE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \
864 (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit32)(VALUE32);
866 #define OSSA_READ_LE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \
867 (*((bit16 *)ADDR16)) = (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET))))
869 #define OSSA_READ_LE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \
870 (*((bit32 *)ADDR32)) = (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET))))
872 #define OSSA_WRITE_BE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \
873 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)((((bit16)VALUE16)>>8)&0xFF); \
874 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)(((bit16)VALUE16)&0xFF);
876 #define OSSA_WRITE_BE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \
877 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)((((bit32)VALUE32)>>24)&0xFF); \
878 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit32)VALUE32)>>16)&0xFF); \
879 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))) = (bit8)((((bit32)VALUE32)>>8)&0xFF); \
880 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))) = (bit8)(((bit32)VALUE32)&0xFF);
882 #define OSSA_READ_BE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \
883 (*(bit8 *)(((bit8 *)ADDR16)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \
884 (*(bit8 *)(((bit8 *)ADDR16))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1)));
886 #define OSSA_READ_BE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \
887 (*(bit8 *)(((bit8 *)ADDR32)+3)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \
888 (*(bit8 *)(((bit8 *)ADDR32)+2)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); \
889 (*(bit8 *)(((bit8 *)ADDR32)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))); \
890 (*(bit8 *)(((bit8 *)ADDR32))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3)));
892 #define OSSA_WRITE_BYTE_STRING(AGROOT, DEST_ADDR, SRC_ADDR, LEN) \
893 si_memcpy(DEST_ADDR, SRC_ADDR, LEN);
896 #elif defined(SA_CPU_BIG_ENDIAN)
898 #define OSSA_WRITE_LE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \
899 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit16)VALUE16)>>8)&0xFF); \
900 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)(((bit16)VALUE16)&0xFF);
902 #define OSSA_WRITE_LE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \
903 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))) = (bit8)((((bit32)VALUE32)>>24)&0xFF); \
904 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))) = (bit8)((((bit32)VALUE32)>>16)&0xFF); \
905 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit32)VALUE32)>>8)&0xFF); \
906 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)(((bit32)VALUE32)&0xFF);
908 #define OSSA_READ_LE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \
909 (*(bit8 *)(((bit8 *)ADDR16)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \
910 (*(bit8 *)(((bit8 *)ADDR16))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1)));
912 #define OSSA_READ_LE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \
913 (*((bit8 *)(((bit8 *)ADDR32)+3))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \
914 (*((bit8 *)(((bit8 *)ADDR32)+2))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); \
915 (*((bit8 *)(((bit8 *)ADDR32)+1))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))); \
916 (*((bit8 *)(((bit8 *)ADDR32)))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3)));
918 #define OSSA_WRITE_BE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \
919 (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit16)(VALUE16);
921 #define OSSA_WRITE_BE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \
922 (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit32)(VALUE32);
924 #define OSSA_READ_BE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \
925 (*((bit16 *)ADDR16)) = (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET))));
927 #define OSSA_READ_BE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \
928 (*((bit32 *)ADDR32)) = (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET))));
930 #define OSSA_WRITE_BYTE_STRING(AGROOT, DEST_ADDR, SRC_ADDR, LEN) \
931 si_memcpy(DEST_ADDR, SRC_ADDR, LEN);
935 #error (Host CPU endianess undefined!!)
940 #if defined(SA_CPU_LITTLE_ENDIAN)
942 #ifndef LEBIT16_TO_BIT16
943 #define LEBIT16_TO_BIT16(_x) (_x)
946 #ifndef BIT16_TO_LEBIT16
947 #define BIT16_TO_LEBIT16(_x) (_x)
950 #ifndef BIT16_TO_BEBIT16
951 #define BIT16_TO_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
954 #ifndef BEBIT16_TO_BIT16
955 #define BEBIT16_TO_BIT16(_x) AGSA_FLIP_2_BYTES(_x)
958 #ifndef LEBIT32_TO_BIT32
959 #define LEBIT32_TO_BIT32(_x) (_x)
962 #ifndef BIT32_TO_LEBIT32
963 #define BIT32_TO_LEBIT32(_x) (_x)
967 #ifndef BEBIT32_TO_BIT32
968 #define BEBIT32_TO_BIT32(_x) AGSA_FLIP_4_BYTES(_x)
971 #ifndef BIT32_TO_BEBIT32
972 #define BIT32_TO_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
975 #elif defined(SA_CPU_BIG_ENDIAN)
977 #ifndef LEBIT16_TO_BIT16
978 #define LEBIT16_TO_BIT16(_x) AGSA_FLIP_2_BYTES(_x)
981 #ifndef BIT16_TO_LEBIT16
982 #define BIT16_TO_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
985 #ifndef BIT16_TO_BEBIT16
986 #define BIT16_TO_BEBIT16(_x) (_x)
989 #ifndef BEBIT16_TO_BIT16
990 #define BEBIT16_TO_BIT16(_x) (_x)
993 #ifndef LEBIT32_TO_BIT32
994 #define LEBIT32_TO_BIT32(_x) AGSA_FLIP_4_BYTES(_x)
997 #ifndef BIT32_TO_LEBIT32
998 #define BIT32_TO_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
1001 #ifndef BEBIT32_TO_BIT32
1002 #define BEBIT32_TO_BIT32(_x) (_x)
1005 #ifndef BIT32_TO_BEBIT32
1006 #define BIT32_TO_BEBIT32(_x) (_x)
1011 #error No definition of SA_CPU_BIG_ENDIAN or SA_CPU_LITTLE_ENDIAN
1016 #define TargetUnknown 0
1017 #define TargetRead 1
1018 #define TargetWrite 2
1021 #define CDB_GRP_MASK 0xE0 /* 1110 0000 */
1022 #define CDB_6BYTE 0x00
1023 #define CDB_10BYTE1 0x20
1024 #define CDB_10BYTE2 0x40
1025 #define CDB_12BYTE 0xA0
1026 #define CDB_16BYTE 0x80
1028 /* ATA device type */
1029 #define SATA_ATA_DEVICE 0x01 /**< ATA ATA device type */
1030 #define SATA_ATAPI_DEVICE 0x02 /**< ATA ATAPI device type */
1031 #define SATA_PM_DEVICE 0x03 /**< ATA PM device type */
1032 #define SATA_SEMB_DEVICE 0x04 /**< ATA SEMB device type */
1033 #define SATA_SEMB_WO_SEP_DEVICE 0x05 /**< ATA SEMB without SEP device type */
1034 #define UNKNOWN_DEVICE 0xFF
1036 /****************************************************************
1037 * SATA Specification related defines *
1038 ****************************************************************/
1039 #define SATA_MAX_QUEUED_COMMANDS 32
1040 #define SATA_MAX_PM_PORTS 15
1043 /* PMC IOCTL signature */
1044 #define PMC_IOCTL_SIGNATURE 0x1234
1051 #define PIO_SETUP_DEV_TO_HOST_FIS 0x5F
1052 #define REG_DEV_TO_HOST_FIS 0x34
1053 #define SET_DEV_BITS_FIS 0xA1
1055 #define TD_ASSERT OS_ASSERT
1058 #define TDSA_DISCOVERY_OPTION_FULL_START 0
1059 #define TDSA_DISCOVERY_OPTION_INCREMENTAL_START 1
1060 #define TDSA_DISCOVERY_OPTION_ABORT 2
1062 #define TDSA_DISCOVERY_TYPE_SAS 0
1063 #define TDSA_DISCOVERY_TYPE_SATA 1
1066 #define DISCOVERY_TIMER_VALUE (2 * 1000 * 1000) /* 2 seconds */
1067 #define DISCOVERY_RETRIES 3
1068 #define CONFIGURE_ROUTE_TIMER_VALUE (1 * 1000 * 1000) /* 1 seconds */
1069 #define DEVICE_REGISTRATION_TIMER_VALUE (2 * 1000 * 1000) /* 2 seconds */
1070 #define SMP_RETRIES 5
1071 #define SMP_BUSY_TIMER_VALUE (1 * 1000 * 1000) /* 1 second */
1072 #define SMP_BUSY_RETRIES 5
1073 #define SATA_ID_DEVICE_DATA_TIMER_VALUE (3 * 1000 * 1000) /* 3 second */
1074 #define SATA_ID_DEVICE_DATA_RETRIES 3
1075 #define BC_TIMER_VALUE (5 * 1000 * 1000 ) /* 5 second */
1076 #define SMP_TIMER_VALUE (10 * 1000 * 1000) /* 10 second */
1079 #define STP_DEVICE_TYPE 0 /* SATA behind expander 00*/
1080 #define SAS_DEVICE_TYPE 1 /* SSP or SMP 01 */
1081 #define SATA_DEVICE_TYPE 2 /* direct SATA 10 */
1083 #define ATAPI_DEVICE_FLAG 0x200000 /* ATAPI device flag*/
1085 #define TD_INTERNAL_TM_RESET 0xFF
1087 /* in terms of Kbytes*/
1088 #define HOST_EVENT_LOG_SIZE 128
1089 #define DEFAULT_EVENT_LOG_OPTION 3
1092 #define SAT_DEV_STATE_NORMAL 0 /* Normal */
1093 #define SAT_DEV_STATE_IN_RECOVERY 1 /* SAT in recovery mode */
1094 #define SAT_DEV_STATE_FORMAT_IN_PROGRESS 2 /* Format unit in progress */
1095 #define SAT_DEV_STATE_SMART_THRESHOLD 3 /* SMART Threshold Exceeded Condition*/
1096 #define SAT_DEV_STATE_LOW_POWER 4 /* Low Power State*/
1098 #define TD_GET_PHY_ID(input) (input & 0x0F)
1099 #define TD_GET_PHY_NUMS(input) ((input & 0xF0) >> 4)
1100 #define TD_GET_LINK_RATE(input) ((input & 0xFF00) >> 8)
1101 #define TD_GET_PORT_STATE(input) ((input & 0xF0000) >> 16)
1102 #define TD_GET_PHY_STATUS(input) ((input & 0xFF00) >> 8)
1103 #define TD_GET_RESET_STATUS(input) ((input & 0xFF00) >> 8)
1105 #define TD_MAX_NUM_NOTIFY_SPINUP 20
1107 #define SPC_VPD_SIGNATURE 0xFEDCBA98
1109 #define TD_GET_FRAME_TYPE(input) (input & 0xFF)
1110 #define TD_GET_TLR(input) ((input & 0x300) >> 8)
1112 /* PORT RESET TMO is in 100ms */
1113 #define SAS_PORT_RESET_TMO 3 /* 300 ms */
1114 #define SATA_PORT_RESET_TMO 80 /* 8000 ms = 8 sec */
1115 #define SAS_12G_PORT_RESET_TMO 8 /* 800 ms */
1117 /* task attribute based on sTSDK API */
1118 #define TD_TASK_SIMPLE 0x0 /* Simple */
1119 #define TD_TASK_ORDERED 0x2 /* Ordered */
1120 #define TD_TASK_HEAD_OF_QUEUE 0x1 /* Head of Queue */
1121 #define TD_TASK_ACA 0x4 /* ACA */
1123 /* compiler flag for direct smp */
1127 #define CONFIGURE_FW_MAX_PORTS 0x20000000
1129 #define NO_ACK 0xFFFF
1131 #define OPEN_RETRY_RETRIES 10
1134 /* scsi command/page */
1135 #define MODE_SELECT 0x15
1136 #define PAGE_FORMAT 0x10
1137 #define DR_MODE_PG_SZ 16
1138 #define DR_MODE_PG_CODE 0x02
1139 #define DR_MODE_PG_LENGTH 0x0e
1140 #endif /* AGTIAPI_CTL */
1144 /* for tdsaAllShared->FreeDeviceList, tdsaAllShared->MainDeviceList,
1145 oneDeviceData->MainLink, oneDeviceData->FreeLink */
1147 /* for tdsaAllShared->FreePortContextList, tdsaAllShared->MainPortContextList,
1148 onePortContext->MainLink, onePortContext->FreeLink */
1150 /* for onePortContext->discovery.discoveringExpanderList,
1151 onePortContext->discovery.UpdiscoveringExpanderList,
1152 tdsaAllShared->freeExpanderList */
1154 /* for onePortContext->discovery.DiscoverySMPTimer,
1155 oneDeviceData->SATAIDDeviceTimer, discovery->discoveryTimer,
1156 discovery->SMPBusyTimer, discovery->BCTimer,
1157 discovery->deviceRegistrationTimer, discovery->configureRouteTimer,
1158 tdsaAllShared->itdsaIni->timerlist, tdsaAllShared->timerlist */
1160 #ifdef INITIATOR_DRIVER
1161 /* for tdsaAllShared->pEsglAllInfo->freelist
1162 tdsaAllShared->pEsglAllInfo->NumFreeEsglPages
1163 tdsaAllShared->pEsglPageInfo->tdlist */
1165 /* for satIOContext->pSatDevData->satVerifyState,
1166 satIOContext->pSatDevData->satSectorDone,
1167 satIOContext->pSatDevData->satPendingNCQIO,
1168 satIOContext->pSatDevData->satPendingIO,
1169 satIOContext->pSatDevData->satPendingNONNCQIO,
1170 satIOContext->pSatDevData->satFreeIntIoLinkList,
1171 satIOContext->pSatDevData->satActiveIntIoLinkList,
1172 satIOContext->pSatDevData->freeSATAFDMATagBitmap,
1173 satIOContext->satIoContextLink,
1174 oneDeviceData->satDevData.satIoLinkList */
1176 #ifdef TD_INT_COALESCE
1177 /* for tdsaIntCoalCxt->FreeLink, tdsaIntCoalCxt->MainLink,
1178 tdsaIntCoalCxtHead->FreeLink, tdsaIntCoalCxtHead->MainLink */
1182 #ifdef TARGET_DRIVER
1183 /* for tdsaAllShared->ttdsaTgt->ttdsaXchgData.xchgFreeList,
1184 tdsaAllShared->ttdsaTgt->ttdsaXchgData.xchgBusyList */
1190 #define TD_GET_SAS_ADDRESSLO(sasAddressLo) \
1191 DMA_BEBIT32_TO_BIT32(*(bit32 *)sasAddressLo)
1193 #define TD_GET_SAS_ADDRESSHI(sasAddressHi) \
1194 DMA_BEBIT32_TO_BIT32(*(bit32 *)sasAddressHi)
1196 #define TD_XFER_RDY_PRIORTY_DEVICE_FLAG (1 << 22)
1200 /* bit32 -> bit8 array[4] */
1201 #define PORTINFO_PUT_SAS_LOCAL_ADDRESSLO(portInfo, src32) \
1202 *(bit32 *)((portInfo)->sasLocalAddressLo) = BIT32_TO_DMA_BEBIT32(src32)
1204 #define PORTINFO_PUT_SAS_LOCAL_ADDRESSHI(portInfo, src32) \
1205 *(bit32 *)((portInfo)->sasLocalAddressHi) = BIT32_TO_DMA_BEBIT32(src32)
1206 /* bit32 -> bit8 array[4] */
1207 #define PORTINFO_PUT_SAS_REMOTE_ADDRESSLO(portInfo, src32) \
1208 *(bit32 *)((portInfo)->sasRemoteAddressLo) = BIT32_TO_DMA_BEBIT32(src32)
1209 #define PORTINFO_PUT_SAS_REMOTE_ADDRESSHI(portInfo, src32) \
1210 *(bit32 *)((portInfo)->sasRemoteAddressHi) = BIT32_TO_DMA_BEBIT32(src32)
1214 /* this applies to ID data and all other SATA IOs */
1215 #define SM_RETRIES 10
1218 #define TI_TIROOT_TO_tdsaRoot(t_r) (((tdsaRoot_t *)((tiRoot_t *)t_r)->tdData) )
1220 #define TI_TIROOT_TO_tdsaAllShared(t_r1) (tdsaContext_t *)&(t_r1->tdsaAllShared)
1222 #define TI_TIROOT_TO_agroot(t_r2) (agsaRoot_t *)&((t_r2)->agRootNonInt)
1225 #define TI_TIROOT_TO_AGROOT(t_root) (TI_TIROOT_TO_agroot(TI_TIROOT_TO_tdsaAllShared(TI_TIROOT_TO_tdsaRoot(t_root)) ))
1227 #define TI_VEN_DEV_SPC 0x80010000
1228 #define TI_VEN_DEV_SPCADAP 0x80810000
1229 #define TI_VEN_DEV_SPCv 0x80080000
1230 #define TI_VEN_DEV_SPCve 0x80090000
1231 #define TI_VEN_DEV_SPCvplus 0x80180000
1232 #define TI_VEN_DEV_SPCveplus 0x80190000
1233 #define TI_VEN_DEV_SPCADAPvplus 0x80880000
1234 #define TI_VEN_DEV_SPCADAPveplus 0x80890000
1236 #define TI_VEN_DEV_SPC12Gv 0x80700000
1237 #define TI_VEN_DEV_SPC12Gve 0x80710000
1238 #define TI_VEN_DEV_SPC12Gvplus 0x80720000
1239 #define TI_VEN_DEV_SPC12Gveplus 0x80730000
1240 #define TI_VEN_DEV_9015 0x90150000
1241 #define TI_VEN_DEV_SPC12ADP 0x80740000 /* 8 ports KBP added*/
1242 #define TI_VEN_DEV_SPC12ADPP 0x80760000 /* 16 ports */
1243 #define TI_VEN_DEV_SPC12SATA 0x80060000 /* SATA HBA */
1244 #define TI_VEN_DEV_9060 0x90600000
1246 #define tIsSPC(agr) (TI_VEN_DEV_SPC == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC */
1247 #define tIsSPCHIL(agr) (TI_VEN_DEV_SPCADAP == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC */
1248 #define tIsSPCv(agr) (TI_VEN_DEV_SPCv == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPCv */
1249 #define tIsSPCve(agr) (TI_VEN_DEV_SPCve == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPCve */
1250 #define tIsSPCvplus(agr) (TI_VEN_DEV_SPCvplus == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPCv+ */
1251 #define tIsSPCveplus(agr) (TI_VEN_DEV_SPCveplus == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPCve+ */
1252 #define tIsSPCADAPvplus(agr) (TI_VEN_DEV_SPCADAPvplus == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPCv+ */
1253 #define tIsSPCADAPveplus(agr) (TI_VEN_DEV_SPCADAPveplus == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPCve+ */
1255 #define tIsSPC12Gv(agr) (TI_VEN_DEV_SPC12Gv == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC12Gv */
1256 #define tIsSPC12Gve(agr) (TI_VEN_DEV_SPC12Gve == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC12Gve */
1257 #define tIsSPC12Gvplus(agr) (TI_VEN_DEV_SPC12Gvplus == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC12Gv+ */
1258 #define tIsSPC12Gveplus(agr) (TI_VEN_DEV_SPC12Gveplus == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC12Gve+ */
1259 #define tIsSPC9015(agr) (TI_VEN_DEV_9015 == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC12Gve+ */
1260 #define tIsSPC9060(agr) (TI_VEN_DEV_9060 == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0) /* returns true config space read is SPC12Gve+ */
1261 #define tIsSPC12ADP(agr) (TI_VEN_DEV_SPC12ADP == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0)
1262 #define tIsSPC12ADPP(agr) (TI_VEN_DEV_SPC12ADPP == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0)
1263 #define tIsSPC12SATA(agr) (TI_VEN_DEV_SPC12SATA == (ossaHwRegReadConfig32(agr,0 ) & 0xFFFF0000) ? 1 : 0)
1265 #define tiIS_SPC(agr) (( tIsSPC((agr)) == 1) ? 1 : \
1266 ( tIsSPCHIL((agr)) == 1) ? 1 : 0 )
1268 #define tiIS_HIL(agr) ((tIsSPCHIL ((agr)) == 1) ? 1 : \
1269 (tIsSPCADAPvplus((agr)) == 1) ? 1 : \
1270 (tIsSPCADAPveplus((agr)) == 1) ? 1 : 0 )
1272 #define tiIS_SPC6V(agr) ((tIsSPCv((agr)) == 1) ? 1 : \
1273 (tIsSPCve((agr)) == 1) ? 1 : \
1274 (tIsSPCvplus((agr)) == 1) ? 1 : \
1275 (tIsSPCveplus((agr)) == 1) ? 1 : \
1276 (tIsSPCADAPvplus((agr)) == 1) ? 1 : \
1277 (tIsSPCADAPveplus((agr)) == 1) ? 1 : 0 )
1279 #define tIsSPCV12G(agr) ((tIsSPC12Gv(agr) == 1) ? 1 : \
1280 (tIsSPC12Gve(agr) == 1) ? 1 : \
1281 (tIsSPC12Gvplus(agr)== 1) ? 1 : \
1282 (tIsSPC12Gveplus(agr)== 1) ? 1 : \
1283 (tIsSPC9015(agr)== 1) ? 1 : \
1284 (tIsSPC12ADP(agr)== 1) ? 1 : \
1285 (tIsSPC12ADPP(agr)== 1) ? 1 : \
1286 (tIsSPC12SATA(agr) == 1) ? 1 : \
1287 (tIsSPC9060(agr) == 1) ? 1 : 0)
1289 #define tiIS_8PHY(agr) ((tIsSPCv((agr)) == 1) ? 1 : \
1290 (tIsSPCve((agr)) == 1) ? 1 : \
1291 (tIsSPC12Gv((agr)) == 1) ? 1 : \
1292 (tIsSPC12Gve((agr)) == 1) ? 1 : \
1293 (tIsSPC12ADP(agr) == 1) ? 1 : 0 )
1295 #define tiIS_16PHY(agr) ((tIsSPCvplus((agr)) == 1) ? 1 : \
1296 (tIsSPCveplus((agr)) == 1) ? 1 : \
1297 (tIsSPCADAPvplus((agr)) == 1) ? 1 : \
1298 (tIsSPCADAPveplus((agr)) == 1) ? 1 : \
1299 (tIsSPC12ADPP(agr) == 1) ? 1 : \
1300 (tIsSPC12SATA(agr) == 1) ? 1 : 0 )
1302 #define tiIS_SPC_ENC(agr)((tIsSPCve((agr)) == 1) ? 1 : \
1303 (tIsSPCveplus((agr)) == 1) ? 1 : \
1304 (tIsSPCADAPveplus((agr)) == 1) ? 1 : 0 )
1306 #define tIsSPCV12or6G(agr) ((tiIS_SPC6V(agr) == 1) ? 1 : \
1307 (tIsSPCV12G(agr) == 1) ? 1 : 0)
1309 #endif /* __TDDEFS_H__ */