2 * Copyright (c) 2006 Marcel Moolenaar
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
31 * PCI "universal" communications card driver configuration data (used to
32 * match/attach the cards).
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/kernel.h>
40 #include <machine/resource.h>
41 #include <machine/bus.h>
44 #include <dev/pci/pcivar.h>
46 #include <dev/puc/puc_bus.h>
47 #include <dev/puc/puc_cfg.h>
48 #include <dev/puc/puc_bfe.h>
50 static puc_config_f puc_config_amc;
51 static puc_config_f puc_config_cronyx;
52 static puc_config_f puc_config_diva;
53 static puc_config_f puc_config_icbook;
54 static puc_config_f puc_config_quatech;
55 static puc_config_f puc_config_syba;
56 static puc_config_f puc_config_siig;
57 static puc_config_f puc_config_timedia;
58 static puc_config_f puc_config_titan;
60 const struct puc_cfg puc_pci_devices[] = {
62 { 0x0009, 0x7168, 0xffff, 0,
65 PUC_PORT_2S, 0x10, 0, 8,
68 { 0x103c, 0x1048, 0x103c, 0x1049,
69 "HP Diva Serial [GSP] Multiport UART - Tosca Console",
71 PUC_PORT_3S, 0x10, 0, -1,
72 .config_function = puc_config_diva
75 { 0x103c, 0x1048, 0x103c, 0x104a,
76 "HP Diva Serial [GSP] Multiport UART - Tosca Secondary",
78 PUC_PORT_2S, 0x10, 0, -1,
79 .config_function = puc_config_diva
82 { 0x103c, 0x1048, 0x103c, 0x104b,
83 "HP Diva Serial [GSP] Multiport UART - Maestro SP2",
85 PUC_PORT_4S, 0x10, 0, -1,
86 .config_function = puc_config_diva
89 { 0x103c, 0x1048, 0x103c, 0x1223,
90 "HP Diva Serial [GSP] Multiport UART - Superdome Console",
92 PUC_PORT_3S, 0x10, 0, -1,
93 .config_function = puc_config_diva
96 { 0x103c, 0x1048, 0x103c, 0x1226,
97 "HP Diva Serial [GSP] Multiport UART - Keystone SP2",
99 PUC_PORT_3S, 0x10, 0, -1,
100 .config_function = puc_config_diva
103 { 0x103c, 0x1048, 0x103c, 0x1282,
104 "HP Diva Serial [GSP] Multiport UART - Everest SP2",
106 PUC_PORT_3S, 0x10, 0, -1,
107 .config_function = puc_config_diva
110 { 0x10b5, 0x1076, 0x10b5, 0x1076,
113 PUC_PORT_8S, 0x18, 0, 8,
116 { 0x10b5, 0x1077, 0x10b5, 0x1077,
119 PUC_PORT_4S, 0x18, 0, 8,
122 { 0x10b5, 0x1103, 0x10b5, 0x1103,
125 PUC_PORT_2S, 0x18, 4, 0,
129 * Boca Research Turbo Serial 658 (8 serial port) card.
130 * Appears to be the same as Chase Research PLC PCI-FAST8
131 * and Perle PCI-FAST8 Multi-Port serial cards.
133 { 0x10b5, 0x9050, 0x12e0, 0x0021,
134 "Boca Research Turbo Serial 658",
136 PUC_PORT_8S, 0x18, 0, 8,
139 { 0x10b5, 0x9050, 0x12e0, 0x0031,
140 "Boca Research Turbo Serial 654",
142 PUC_PORT_4S, 0x18, 0, 8,
146 * Dolphin Peripherals 4035 (dual serial port) card. PLX 9050, with
147 * a seemingly-lame EEPROM setup that puts the Dolphin IDs
148 * into the subsystem fields, and claims that it's a
149 * network/misc (0x02/0x80) device.
151 { 0x10b5, 0x9050, 0xd84d, 0x6808,
152 "Dolphin Peripherals 4035",
154 PUC_PORT_2S, 0x18, 4, 0,
158 * Dolphin Peripherals 4014 (dual parallel port) card. PLX 9050, with
159 * a seemingly-lame EEPROM setup that puts the Dolphin IDs
160 * into the subsystem fields, and claims that it's a
161 * network/misc (0x02/0x80) device.
163 { 0x10b5, 0x9050, 0xd84d, 0x6810,
164 "Dolphin Peripherals 4014",
166 PUC_PORT_2P, 0x20, 4, 0,
169 { 0x10e8, 0x818e, 0xffff, 0,
170 "Applied Micro Circuits 8 Port UART",
172 PUC_PORT_8S, 0x14, -1, -1,
173 .config_function = puc_config_amc
176 { 0x11fe, 0x8010, 0xffff, 0,
177 "Comtrol RocketPort 550/8 RJ11 part A",
179 PUC_PORT_4S, 0x10, 0, 8,
182 { 0x11fe, 0x8011, 0xffff, 0,
183 "Comtrol RocketPort 550/8 RJ11 part B",
185 PUC_PORT_4S, 0x10, 0, 8,
188 { 0x11fe, 0x8012, 0xffff, 0,
189 "Comtrol RocketPort 550/8 Octa part A",
191 PUC_PORT_4S, 0x10, 0, 8,
194 { 0x11fe, 0x8013, 0xffff, 0,
195 "Comtrol RocketPort 550/8 Octa part B",
197 PUC_PORT_4S, 0x10, 0, 8,
200 { 0x11fe, 0x8014, 0xffff, 0,
201 "Comtrol RocketPort 550/4 RJ45",
203 PUC_PORT_4S, 0x10, 0, 8,
206 { 0x11fe, 0x8015, 0xffff, 0,
207 "Comtrol RocketPort 550/Quad",
209 PUC_PORT_4S, 0x10, 0, 8,
212 { 0x11fe, 0x8016, 0xffff, 0,
213 "Comtrol RocketPort 550/16 part A",
215 PUC_PORT_4S, 0x10, 0, 8,
218 { 0x11fe, 0x8017, 0xffff, 0,
219 "Comtrol RocketPort 550/16 part B",
221 PUC_PORT_12S, 0x10, 0, 8,
224 { 0x11fe, 0x8018, 0xffff, 0,
225 "Comtrol RocketPort 550/8 part A",
227 PUC_PORT_4S, 0x10, 0, 8,
230 { 0x11fe, 0x8019, 0xffff, 0,
231 "Comtrol RocketPort 550/8 part B",
233 PUC_PORT_4S, 0x10, 0, 8,
237 * IBM SurePOS 300 Series (481033H) serial ports
238 * Details can be found on the IBM RSS websites
241 { 0x1014, 0x0297, 0xffff, 0,
242 "IBM SurePOS 300 Series (481033H) serial ports",
244 PUC_PORT_4S, 0x10, 4, 0
250 * SIIG provides documentation for their boards at:
251 * <URL:http://www.siig.com/downloads.asp>
254 { 0x131f, 0x1010, 0xffff, 0,
255 "SIIG Cyber I/O PCI 16C550 (10x family)",
257 PUC_PORT_1S1P, 0x18, 4, 0,
260 { 0x131f, 0x1011, 0xffff, 0,
261 "SIIG Cyber I/O PCI 16C650 (10x family)",
263 PUC_PORT_1S1P, 0x18, 4, 0,
266 { 0x131f, 0x1012, 0xffff, 0,
267 "SIIG Cyber I/O PCI 16C850 (10x family)",
269 PUC_PORT_1S1P, 0x18, 4, 0,
272 { 0x131f, 0x1021, 0xffff, 0,
273 "SIIG Cyber Parallel Dual PCI (10x family)",
275 PUC_PORT_2P, 0x18, 8, 0,
278 { 0x131f, 0x1030, 0xffff, 0,
279 "SIIG Cyber Serial Dual PCI 16C550 (10x family)",
281 PUC_PORT_2S, 0x18, 4, 0,
284 { 0x131f, 0x1031, 0xffff, 0,
285 "SIIG Cyber Serial Dual PCI 16C650 (10x family)",
287 PUC_PORT_2S, 0x18, 4, 0,
290 { 0x131f, 0x1032, 0xffff, 0,
291 "SIIG Cyber Serial Dual PCI 16C850 (10x family)",
293 PUC_PORT_2S, 0x18, 4, 0,
296 { 0x131f, 0x1034, 0xffff, 0, /* XXX really? */
297 "SIIG Cyber 2S1P PCI 16C550 (10x family)",
299 PUC_PORT_2S1P, 0x18, 4, 0,
302 { 0x131f, 0x1035, 0xffff, 0, /* XXX really? */
303 "SIIG Cyber 2S1P PCI 16C650 (10x family)",
305 PUC_PORT_2S1P, 0x18, 4, 0,
308 { 0x131f, 0x1036, 0xffff, 0, /* XXX really? */
309 "SIIG Cyber 2S1P PCI 16C850 (10x family)",
311 PUC_PORT_2S1P, 0x18, 4, 0,
314 { 0x131f, 0x1050, 0xffff, 0,
315 "SIIG Cyber 4S PCI 16C550 (10x family)",
317 PUC_PORT_4S, 0x18, 4, 0,
320 { 0x131f, 0x1051, 0xffff, 0,
321 "SIIG Cyber 4S PCI 16C650 (10x family)",
323 PUC_PORT_4S, 0x18, 4, 0,
326 { 0x131f, 0x1052, 0xffff, 0,
327 "SIIG Cyber 4S PCI 16C850 (10x family)",
329 PUC_PORT_4S, 0x18, 4, 0,
332 { 0x131f, 0x2010, 0xffff, 0,
333 "SIIG Cyber I/O PCI 16C550 (20x family)",
335 PUC_PORT_1S1P, 0x10, 4, 0,
338 { 0x131f, 0x2011, 0xffff, 0,
339 "SIIG Cyber I/O PCI 16C650 (20x family)",
341 PUC_PORT_1S1P, 0x10, 4, 0,
344 { 0x131f, 0x2012, 0xffff, 0,
345 "SIIG Cyber I/O PCI 16C850 (20x family)",
347 PUC_PORT_1S1P, 0x10, 4, 0,
350 { 0x131f, 0x2021, 0xffff, 0,
351 "SIIG Cyber Parallel Dual PCI (20x family)",
353 PUC_PORT_2P, 0x10, 8, 0,
356 { 0x131f, 0x2030, 0xffff, 0,
357 "SIIG Cyber Serial Dual PCI 16C550 (20x family)",
359 PUC_PORT_2S, 0x10, 4, 0,
362 { 0x131f, 0x2031, 0xffff, 0,
363 "SIIG Cyber Serial Dual PCI 16C650 (20x family)",
365 PUC_PORT_2S, 0x10, 4, 0,
368 { 0x131f, 0x2032, 0xffff, 0,
369 "SIIG Cyber Serial Dual PCI 16C850 (20x family)",
371 PUC_PORT_2S, 0x10, 4, 0,
374 { 0x131f, 0x2040, 0xffff, 0,
375 "SIIG Cyber 2P1S PCI 16C550 (20x family)",
377 PUC_PORT_1S2P, 0x10, -1, 0,
378 .config_function = puc_config_siig
381 { 0x131f, 0x2041, 0xffff, 0,
382 "SIIG Cyber 2P1S PCI 16C650 (20x family)",
384 PUC_PORT_1S2P, 0x10, -1, 0,
385 .config_function = puc_config_siig
388 { 0x131f, 0x2042, 0xffff, 0,
389 "SIIG Cyber 2P1S PCI 16C850 (20x family)",
391 PUC_PORT_1S2P, 0x10, -1, 0,
392 .config_function = puc_config_siig
395 { 0x131f, 0x2050, 0xffff, 0,
396 "SIIG Cyber 4S PCI 16C550 (20x family)",
398 PUC_PORT_4S, 0x10, 4, 0,
401 { 0x131f, 0x2051, 0xffff, 0,
402 "SIIG Cyber 4S PCI 16C650 (20x family)",
404 PUC_PORT_4S, 0x10, 4, 0,
407 { 0x131f, 0x2052, 0xffff, 0,
408 "SIIG Cyber 4S PCI 16C850 (20x family)",
410 PUC_PORT_4S, 0x10, 4, 0,
413 { 0x131f, 0x2060, 0xffff, 0,
414 "SIIG Cyber 2S1P PCI 16C550 (20x family)",
416 PUC_PORT_2S1P, 0x10, 4, 0,
419 { 0x131f, 0x2061, 0xffff, 0,
420 "SIIG Cyber 2S1P PCI 16C650 (20x family)",
422 PUC_PORT_2S1P, 0x10, 4, 0,
425 { 0x131f, 0x2062, 0xffff, 0,
426 "SIIG Cyber 2S1P PCI 16C850 (20x family)",
428 PUC_PORT_2S1P, 0x10, 4, 0,
431 { 0x131f, 0x2081, 0xffff, 0,
432 "SIIG PS8000 8S PCI 16C650 (20x family)",
434 PUC_PORT_8S, 0x10, -1, -1,
435 .config_function = puc_config_siig
438 { 0x135c, 0x0010, 0xffff, 0,
440 -3, /* max 8x clock rate */
441 PUC_PORT_4S, 0x14, 0, 8,
442 .config_function = puc_config_quatech
445 { 0x135c, 0x0020, 0xffff, 0,
447 -1, /* max 2x clock rate */
448 PUC_PORT_2S, 0x14, 0, 8,
449 .config_function = puc_config_quatech
452 { 0x135c, 0x0030, 0xffff, 0,
453 "Quatech DSC-200/300",
454 -1, /* max 2x clock rate */
455 PUC_PORT_2S, 0x14, 0, 8,
456 .config_function = puc_config_quatech
459 { 0x135c, 0x0040, 0xffff, 0,
460 "Quatech QSC-200/300",
461 -3, /* max 8x clock rate */
462 PUC_PORT_4S, 0x14, 0, 8,
463 .config_function = puc_config_quatech
466 { 0x135c, 0x0050, 0xffff, 0,
468 -3, /* max 8x clock rate */
469 PUC_PORT_8S, 0x14, 0, 8,
470 .config_function = puc_config_quatech
473 { 0x135c, 0x0060, 0xffff, 0,
475 -3, /* max 8x clock rate */
476 PUC_PORT_8S, 0x14, 0, 8,
477 .config_function = puc_config_quatech
480 { 0x135c, 0x0170, 0xffff, 0,
482 -1, /* max 2x clock rate */
483 PUC_PORT_4S, 0x18, 0, 8,
484 .config_function = puc_config_quatech
487 { 0x135c, 0x0180, 0xffff, 0,
489 -1, /* max 3x clock rate */
490 PUC_PORT_2S, 0x18, 0, 8,
491 .config_function = puc_config_quatech
494 { 0x135c, 0x01b0, 0xffff, 0,
495 "Quatech DSCLP-200/300",
496 -1, /* max 2x clock rate */
497 PUC_PORT_2S, 0x18, 0, 8,
498 .config_function = puc_config_quatech
501 { 0x135c, 0x01e0, 0xffff, 0,
503 -3, /* max 8x clock rate */
504 PUC_PORT_8S, 0x10, 0, 8,
505 .config_function = puc_config_quatech
508 { 0x1393, 0x1040, 0xffff, 0,
509 "Moxa Technologies, Smartio C104H/PCI",
511 PUC_PORT_4S, 0x18, 0, 8,
514 { 0x1393, 0x1041, 0xffff, 0,
515 "Moxa Technologies, Smartio CP-104UL/PCI",
517 PUC_PORT_4S, 0x18, 0, 8,
520 { 0x1393, 0x1043, 0xffff, 0,
521 "Moxa Technologies, Smartio CP-104EL/PCIe",
523 PUC_PORT_4S, 0x18, 0, 8,
526 { 0x1393, 0x1141, 0xffff, 0,
527 "Moxa Technologies, Industio CP-114",
529 PUC_PORT_4S, 0x18, 0, 8,
532 { 0x1393, 0x1680, 0xffff, 0,
533 "Moxa Technologies, C168H/PCI",
535 PUC_PORT_8S, 0x18, 0, 8,
538 { 0x1393, 0x1681, 0xffff, 0,
539 "Moxa Technologies, C168U/PCI",
541 PUC_PORT_8S, 0x18, 0, 8,
544 { 0x1393, 0x1682, 0xffff, 0,
545 "Moxa Technologies, CP-168EL/PCIe",
547 PUC_PORT_8S, 0x18, 0, 8,
550 { 0x13a8, 0x0158, 0xffff, 0,
553 PUC_PORT_8S, 0x10, 0, -1,
554 .config_function = puc_config_cronyx
557 { 0x1407, 0x0100, 0xffff, 0,
558 "Lava Computers Dual Serial",
560 PUC_PORT_2S, 0x10, 4, 0,
563 { 0x1407, 0x0101, 0xffff, 0,
564 "Lava Computers Quatro A",
566 PUC_PORT_2S, 0x10, 4, 0,
569 { 0x1407, 0x0102, 0xffff, 0,
570 "Lava Computers Quatro B",
572 PUC_PORT_2S, 0x10, 4, 0,
575 { 0x1407, 0x0120, 0xffff, 0,
576 "Lava Computers Quattro-PCI A",
578 PUC_PORT_2S, 0x10, 4, 0,
581 { 0x1407, 0x0121, 0xffff, 0,
582 "Lava Computers Quattro-PCI B",
584 PUC_PORT_2S, 0x10, 4, 0,
587 { 0x1407, 0x0180, 0xffff, 0,
588 "Lava Computers Octo A",
590 PUC_PORT_4S, 0x10, 4, 0,
593 { 0x1407, 0x0181, 0xffff, 0,
594 "Lava Computers Octo B",
596 PUC_PORT_4S, 0x10, 4, 0,
599 { 0x1409, 0x7268, 0xffff, 0,
602 PUC_PORT_2P, 0x10, 0, 8,
605 { 0x1409, 0x7168, 0xffff, 0,
608 PUC_PORT_NONSTANDARD, 0x10, -1, -1,
609 .config_function = puc_config_timedia
613 * Boards with an Oxford Semiconductor chip.
615 * Oxford Semiconductor provides documentation for their chip at:
616 * <URL:http://www.oxsemi.com/products/uarts/index.html>
618 * As sold by Kouwell <URL:http://www.kouwell.com/>.
619 * I/O Flex PCI I/O Card Model-223 with 4 serial and 1 parallel ports.
622 { 0x1415, 0x9501, 0x131f, 0x2050,
623 "SIIG Cyber 4 PCI 16550",
625 PUC_PORT_4S, 0x10, 0, 8,
628 { 0x1415, 0x9501, 0x131f, 0x2051,
629 "SIIG Cyber 4S PCI 16C650 (20x family)",
631 PUC_PORT_4S, 0x10, 0, 8,
634 { 0x1415, 0x9501, 0xffff, 0,
635 "Oxford Semiconductor OX16PCI954 UARTs",
637 PUC_PORT_4S, 0x10, 0, 8,
640 { 0x1415, 0x950a, 0xffff, 0,
641 "Oxford Semiconductor OX16PCI954 UARTs",
643 PUC_PORT_4S, 0x10, 0, 8,
646 { 0x1415, 0x9511, 0xffff, 0,
647 "Oxford Semiconductor OX9160/OX16PCI954 UARTs (function 1)",
649 PUC_PORT_4S, 0x10, 0, 8,
652 { 0x1415, 0x9521, 0xffff, 0,
653 "Oxford Semiconductor OX16PCI952 UARTs",
655 PUC_PORT_2S, 0x10, 4, 0,
658 { 0x1415, 0x9538, 0xffff, 0,
659 "Oxford Semiconductor OX16PCI958 UARTs",
661 PUC_PORT_8S, 0x18, 0, 8,
665 * Perle boards use Oxford Semiconductor chips, but they store the
666 * Oxford Semiconductor device ID as a subvendor device ID and use
667 * their own device IDs.
670 { 0x155f, 0x0331, 0xffff, 0,
673 PUC_PORT_4S, 0x10, 0, 8,
676 { 0x14d2, 0x8010, 0xffff, 0,
679 PUC_PORT_1S, 0x14, 0, 0,
682 { 0x14d2, 0x8020, 0xffff, 0,
685 PUC_PORT_2S, 0x14, 4, 0,
688 { 0x14d2, 0x8028, 0xffff, 0,
691 PUC_PORT_2S, 0x20, 0, 8,
695 * VScom (Titan?) PCI-800L. More modern variant of the
696 * PCI-800. Uses 6 discrete 16550 UARTs, plus another
697 * two of them obviously implemented as macro cells in
698 * the ASIC. This causes the weird port access pattern
699 * below, where two of the IO port ranges each access
700 * one of the ASIC UARTs, and a block of IO addresses
701 * access the external UARTs.
703 { 0x14d2, 0x8080, 0xffff, 0,
704 "Titan VScom PCI-800L",
706 PUC_PORT_8S, 0x14, -1, -1,
707 .config_function = puc_config_titan
711 * VScom PCI-800H. Uses 8 16950 UART, behind a PCI chips that offers
712 * 4 com port on PCI device 0 and 4 on PCI device 1. PCI device 0 has
713 * device ID 3 and PCI device 1 device ID 4.
715 { 0x14d2, 0xa003, 0xffff, 0,
718 PUC_PORT_4S, 0x10, 0, 8,
720 { 0x14d2, 0xa004, 0xffff, 0,
723 PUC_PORT_4S, 0x10, 0, 8,
726 { 0x14d2, 0xa005, 0xffff, 0,
729 PUC_PORT_2S, 0x10, 0, 8,
732 { 0x14d2, 0xe020, 0xffff, 0,
733 "Titan VScom PCI-200HV2",
735 PUC_PORT_2S, 0x10, 4, 0,
738 { 0x14db, 0x2130, 0xffff, 0,
739 "Avlab Technology, PCI IO 2S",
741 PUC_PORT_2S, 0x10, 4, 0,
744 { 0x14db, 0x2150, 0xffff, 0,
745 "Avlab Low Profile PCI 4 Serial",
747 PUC_PORT_4S, 0x10, 4, 0,
750 { 0x14db, 0x2152, 0xffff, 0,
751 "Avlab Low Profile PCI 4 Serial",
753 PUC_PORT_4S, 0x10, 4, 0,
756 { 0x1592, 0x0781, 0xffff, 0,
757 "Syba Tech Ltd. PCI-4S2P-550-ECP",
759 PUC_PORT_4S1P, 0x10, 0, -1,
760 .config_function = puc_config_syba
763 { 0x6666, 0x0001, 0xffff, 0,
764 "Decision Computer Inc, PCCOM 4-port serial",
766 PUC_PORT_4S, 0x1c, 0, 8,
769 { 0x6666, 0x0002, 0xffff, 0,
770 "Decision Computer Inc, PCCOM 8-port serial",
772 PUC_PORT_8S, 0x1c, 0, 8,
775 { 0x6666, 0x0004, 0xffff, 0,
776 "PCCOM dual port RS232/422/485",
778 PUC_PORT_2S, 0x1c, 0, 8,
781 { 0x9710, 0x9815, 0xffff, 0,
782 "NetMos NM9815 Dual 1284 Printer port",
784 PUC_PORT_2P, 0x10, 8, 0,
788 * This is more specific than the generic NM9835 entry that follows, and
789 * is placed here to _prevent_ puc from claiming this single port card.
791 * uart(4) will claim this device.
793 { 0x9710, 0x9835, 0x1000, 1,
794 "NetMos NM9835 based 1-port serial",
796 PUC_PORT_1S, 0x10, 4, 0,
799 { 0x9710, 0x9835, 0x1000, 2,
800 "NetMos NM9835 based 2-port serial",
802 PUC_PORT_2S, 0x10, 4, 0,
805 { 0x9710, 0x9835, 0xffff, 0,
806 "NetMos NM9835 Dual UART and 1284 Printer port",
808 PUC_PORT_2S1P, 0x10, 4, 0,
811 { 0x9710, 0x9845, 0x1000, 0x0006,
812 "NetMos NM9845 6 Port UART",
814 PUC_PORT_6S, 0x10, 4, 0,
817 { 0x9710, 0x9845, 0xffff, 0,
818 "NetMos NM9845 Quad UART and 1284 Printer port",
820 PUC_PORT_4S1P, 0x10, 4, 0,
823 { 0x9710, 0x9865, 0xa000, 0x3002,
824 "NetMos NM9865 Dual UART",
826 PUC_PORT_2S, 0x10, 4, 0,
829 { 0x9710, 0x9865, 0xa000, 0x3003,
830 "NetMos NM9865 Triple UART",
832 PUC_PORT_3S, 0x10, 4, 0,
835 { 0x9710, 0x9865, 0xa000, 0x3004,
836 "NetMos NM9865 Quad UART",
838 PUC_PORT_4S, 0x10, 4, 0,0
841 { 0x9710, 0x9865, 0xa000, 0x3011,
842 "NetMos NM9865 Single UART and 1284 Printer port",
844 PUC_PORT_1S1P, 0x10, 4, 0,
847 { 0x9710, 0x9865, 0xa000, 0x3012,
848 "NetMos NM9865 Dual UART and 1284 Printer port",
850 PUC_PORT_2S1P, 0x10, 4, 0,
853 { 0x9710, 0x9865, 0xa000, 0x3020,
854 "NetMos NM9865 Dual 1284 Printer port",
856 PUC_PORT_2P, 0x10, 4, 0,
859 { 0xb00c, 0x021c, 0xffff, 0,
860 "IC Book Labs Gunboat x4 Lite",
862 PUC_PORT_4S, 0x10, 0, 8,
863 .config_function = puc_config_icbook
866 { 0xb00c, 0x031c, 0xffff, 0,
867 "IC Book Labs Gunboat x4 Pro",
869 PUC_PORT_4S, 0x10, 0, 8,
870 .config_function = puc_config_icbook
873 { 0xb00c, 0x041c, 0xffff, 0,
874 "IC Book Labs Ironclad x8 Lite",
876 PUC_PORT_8S, 0x10, 0, 8,
877 .config_function = puc_config_icbook
880 { 0xb00c, 0x051c, 0xffff, 0,
881 "IC Book Labs Ironclad x8 Pro",
883 PUC_PORT_8S, 0x10, 0, 8,
884 .config_function = puc_config_icbook
887 { 0xb00c, 0x081c, 0xffff, 0,
888 "IC Book Labs Dreadnought x16 Pro",
890 PUC_PORT_16S, 0x10, 0, 8,
891 .config_function = puc_config_icbook
894 { 0xb00c, 0x091c, 0xffff, 0,
895 "IC Book Labs Dreadnought x16 Lite",
897 PUC_PORT_16S, 0x10, 0, 8,
898 .config_function = puc_config_icbook
901 { 0xb00c, 0x0a1c, 0xffff, 0,
902 "IC Book Labs Gunboat x2 Low Profile",
904 PUC_PORT_2S, 0x10, 0, 8,
907 { 0xb00c, 0x0b1c, 0xffff, 0,
908 "IC Book Labs Gunboat x4 Low Profile",
910 PUC_PORT_4S, 0x10, 0, 8,
911 .config_function = puc_config_icbook
914 { 0xffff, 0, 0xffff, 0, NULL, 0 }
918 puc_config_amc(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
922 case PUC_CFG_GET_OFS:
923 *res = 8 * (port & 1);
925 case PUC_CFG_GET_RID:
926 *res = 0x14 + (port >> 1) * 4;
935 puc_config_cronyx(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
938 if (cmd == PUC_CFG_GET_OFS) {
946 puc_config_diva(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
949 const struct puc_cfg *cfg = sc->sc_cfg;
951 if (cmd == PUC_CFG_GET_OFS) {
952 if (cfg->subdevice == 0x1282) /* Everest SP */
954 else if (cfg->subdevice == 0x104b) /* Maestro SP2 */
955 port = (port == 3) ? 4 : port;
956 *res = port * 8 + ((port > 2) ? 0x18 : 0);
963 puc_config_icbook(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
966 if (cmd == PUC_CFG_GET_ILR) {
974 puc_config_quatech(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
977 const struct puc_cfg *cfg = sc->sc_cfg;
984 * Check if the scratchpad register is enabled or if the
985 * interrupt status and options registers are active.
987 bar = puc_get_bar(sc, cfg->rid);
990 /* Set DLAB in the LCR register of UART 0. */
991 bus_write_1(bar->b_res, 3, 0x80);
992 /* Write 0 to the SPR register of UART 0. */
993 bus_write_1(bar->b_res, 7, 0);
994 /* Read back the contents of the SPR register of UART 0. */
995 v0 = bus_read_1(bar->b_res, 7);
996 /* Write a specific value to the SPR register of UART 0. */
997 bus_write_1(bar->b_res, 7, 0x80 + -cfg->clock);
998 /* Read back the contents of the SPR register of UART 0. */
999 v1 = bus_read_1(bar->b_res, 7);
1000 /* Clear DLAB in the LCR register of UART 0. */
1001 bus_write_1(bar->b_res, 3, 0);
1002 /* Save the two values read-back from the SPR register. */
1003 sc->sc_cfg_data = (v0 << 8) | v1;
1004 if (v0 == 0 && v1 == 0x80 + -cfg->clock) {
1006 * The SPR register echoed the two values written
1007 * by us. This means that the SPAD jumper is set.
1009 device_printf(sc->sc_dev, "warning: extra features "
1010 "not usable -- SPAD compatibility enabled\n");
1015 * The first value doesn't match. This can only mean
1016 * that the SPAD jumper is not set and that a non-
1017 * standard fixed clock multiplier jumper is set.
1020 device_printf(sc->sc_dev, "fixed clock rate "
1021 "multiplier of %d\n", 1 << v0);
1022 if (v0 < -cfg->clock)
1023 device_printf(sc->sc_dev, "warning: "
1024 "suboptimal fixed clock rate multiplier "
1029 * The first value matched, but the second didn't. We know
1030 * that the SPAD jumper is not set. We also know that the
1031 * clock rate multiplier is software controlled *and* that
1032 * we just programmed it to the maximum allowed.
1035 device_printf(sc->sc_dev, "clock rate multiplier of "
1036 "%d selected\n", 1 << -cfg->clock);
1038 case PUC_CFG_GET_CLOCK:
1039 v0 = (sc->sc_cfg_data >> 8) & 0xff;
1040 v1 = sc->sc_cfg_data & 0xff;
1041 if (v0 == 0 && v1 == 0x80 + -cfg->clock) {
1043 * XXX With the SPAD jumper applied, there's no
1044 * easy way of knowing if there's also a clock
1045 * rate multiplier jumper installed. Let's hope
1048 *res = DEFAULT_RCLK;
1049 } else if (v0 == 0) {
1051 * No clock rate multiplier jumper installed,
1052 * so we programmed the board with the maximum
1053 * multiplier allowed as given to us in the
1054 * clock field of the config record (negated).
1056 *res = DEFAULT_RCLK << -cfg->clock;
1058 *res = DEFAULT_RCLK << v0;
1060 case PUC_CFG_GET_ILR:
1061 v0 = (sc->sc_cfg_data >> 8) & 0xff;
1062 v1 = sc->sc_cfg_data & 0xff;
1063 *res = (v0 == 0 && v1 == 0x80 + -cfg->clock)
1064 ? PUC_ILR_NONE : PUC_ILR_QUATECH;
1073 puc_config_syba(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1076 static int base[] = { 0x251, 0x3f0, 0 };
1077 const struct puc_cfg *cfg = sc->sc_cfg;
1078 struct puc_bar *bar;
1084 bar = puc_get_bar(sc, cfg->rid);
1088 /* configure both W83877TFs */
1089 bus_write_1(bar->b_res, 0x250, 0x89);
1090 bus_write_1(bar->b_res, 0x3f0, 0x87);
1091 bus_write_1(bar->b_res, 0x3f0, 0x87);
1093 while (base[idx] != 0) {
1095 bus_write_1(bar->b_res, efir, 0x09);
1096 v = bus_read_1(bar->b_res, efir + 1);
1097 if ((v & 0x0f) != 0x0c)
1099 bus_write_1(bar->b_res, efir, 0x16);
1100 v = bus_read_1(bar->b_res, efir + 1);
1101 bus_write_1(bar->b_res, efir, 0x16);
1102 bus_write_1(bar->b_res, efir + 1, v | 0x04);
1103 bus_write_1(bar->b_res, efir, 0x16);
1104 bus_write_1(bar->b_res, efir + 1, v & ~0x04);
1105 ofs = base[idx] & 0x300;
1106 bus_write_1(bar->b_res, efir, 0x23);
1107 bus_write_1(bar->b_res, efir + 1, (ofs + 0x78) >> 2);
1108 bus_write_1(bar->b_res, efir, 0x24);
1109 bus_write_1(bar->b_res, efir + 1, (ofs + 0xf8) >> 2);
1110 bus_write_1(bar->b_res, efir, 0x25);
1111 bus_write_1(bar->b_res, efir + 1, (ofs + 0xe8) >> 2);
1112 bus_write_1(bar->b_res, efir, 0x17);
1113 bus_write_1(bar->b_res, efir + 1, 0x03);
1114 bus_write_1(bar->b_res, efir, 0x28);
1115 bus_write_1(bar->b_res, efir + 1, 0x43);
1118 bus_write_1(bar->b_res, 0x250, 0xaa);
1119 bus_write_1(bar->b_res, 0x3f0, 0xaa);
1121 case PUC_CFG_GET_OFS:
1147 puc_config_siig(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1150 const struct puc_cfg *cfg = sc->sc_cfg;
1153 case PUC_CFG_GET_OFS:
1154 if (cfg->ports == PUC_PORT_8S) {
1155 *res = (port > 4) ? 8 * (port - 4) : 0;
1159 case PUC_CFG_GET_RID:
1160 if (cfg->ports == PUC_PORT_8S) {
1161 *res = 0x10 + ((port > 4) ? 0x10 : 4 * port);
1164 if (cfg->ports == PUC_PORT_2S1P) {
1166 case 0: *res = 0x10; return (0);
1167 case 1: *res = 0x14; return (0);
1168 case 2: *res = 0x1c; return (0);
1179 puc_config_timedia(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1182 static uint16_t dual[] = {
1183 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
1184 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
1185 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
1186 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
1189 static uint16_t quad[] = {
1190 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
1191 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
1192 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
1195 static uint16_t octa[] = {
1196 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
1197 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
1208 static char desc[64];
1213 case PUC_CFG_GET_DESC:
1214 snprintf(desc, sizeof(desc),
1215 "Timedia technology %d Port Serial", (int)sc->sc_cfg_data);
1216 *res = (intptr_t)desc;
1218 case PUC_CFG_GET_NPORTS:
1219 subdev = pci_get_subdevice(sc->sc_dev);
1221 while (subdevs[dev].ports != 0) {
1223 while (subdevs[dev].ids[id] != 0) {
1224 if (subdev == subdevs[dev].ids[id]) {
1225 sc->sc_cfg_data = subdevs[dev].ports;
1226 *res = sc->sc_cfg_data;
1234 case PUC_CFG_GET_OFS:
1235 *res = (port == 1 || port == 3) ? 8 : 0;
1237 case PUC_CFG_GET_RID:
1238 *res = 0x10 + ((port > 3) ? port - 2 : port >> 1) * 4;
1240 case PUC_CFG_GET_TYPE:
1241 *res = PUC_TYPE_SERIAL;
1250 puc_config_titan(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1254 case PUC_CFG_GET_OFS:
1255 *res = (port < 3) ? 0 : (port - 2) << 3;
1257 case PUC_CFG_GET_RID:
1258 *res = 0x14 + ((port >= 2) ? 0x0c : port << 2);