2 * Copyright (c) 2006 Marcel Moolenaar
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
31 * PCI "universal" communications card driver configuration data (used to
32 * match/attach the cards).
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/kernel.h>
40 #include <machine/resource.h>
41 #include <machine/bus.h>
44 #include <dev/pci/pcivar.h>
46 #include <dev/puc/puc_bus.h>
47 #include <dev/puc/puc_cfg.h>
48 #include <dev/puc/puc_bfe.h>
50 static puc_config_f puc_config_amc;
51 static puc_config_f puc_config_diva;
52 static puc_config_f puc_config_exar;
53 static puc_config_f puc_config_exar_pcie;
54 static puc_config_f puc_config_icbook;
55 static puc_config_f puc_config_moxa;
56 static puc_config_f puc_config_oxford_pci954;
57 static puc_config_f puc_config_oxford_pcie;
58 static puc_config_f puc_config_quatech;
59 static puc_config_f puc_config_syba;
60 static puc_config_f puc_config_siig;
61 static puc_config_f puc_config_sunix;
62 static puc_config_f puc_config_timedia;
63 static puc_config_f puc_config_titan;
65 const struct puc_cfg puc_pci_devices[] = {
67 { 0x0009, 0x7168, 0xffff, 0,
70 PUC_PORT_2S, 0x10, 0, 8,
73 { 0x103c, 0x1048, 0x103c, 0x1049,
74 "HP Diva Serial [GSP] Multiport UART - Tosca Console",
76 PUC_PORT_3S, 0x10, 0, -1,
77 .config_function = puc_config_diva
80 { 0x103c, 0x1048, 0x103c, 0x104a,
81 "HP Diva Serial [GSP] Multiport UART - Tosca Secondary",
83 PUC_PORT_2S, 0x10, 0, -1,
84 .config_function = puc_config_diva
87 { 0x103c, 0x1048, 0x103c, 0x104b,
88 "HP Diva Serial [GSP] Multiport UART - Maestro SP2",
90 PUC_PORT_4S, 0x10, 0, -1,
91 .config_function = puc_config_diva
94 { 0x103c, 0x1048, 0x103c, 0x1223,
95 "HP Diva Serial [GSP] Multiport UART - Superdome Console",
97 PUC_PORT_3S, 0x10, 0, -1,
98 .config_function = puc_config_diva
101 { 0x103c, 0x1048, 0x103c, 0x1226,
102 "HP Diva Serial [GSP] Multiport UART - Keystone SP2",
104 PUC_PORT_3S, 0x10, 0, -1,
105 .config_function = puc_config_diva
108 { 0x103c, 0x1048, 0x103c, 0x1282,
109 "HP Diva Serial [GSP] Multiport UART - Everest SP2",
111 PUC_PORT_3S, 0x10, 0, -1,
112 .config_function = puc_config_diva
115 { 0x10b5, 0x1076, 0x10b5, 0x1076,
118 PUC_PORT_8S, 0x18, 0, 8,
121 { 0x10b5, 0x1077, 0x10b5, 0x1077,
124 PUC_PORT_4S, 0x18, 0, 8,
127 { 0x10b5, 0x1103, 0x10b5, 0x1103,
130 PUC_PORT_2S, 0x18, 4, 0,
134 * Boca Research Turbo Serial 658 (8 serial port) card.
135 * Appears to be the same as Chase Research PLC PCI-FAST8
136 * and Perle PCI-FAST8 Multi-Port serial cards.
138 { 0x10b5, 0x9050, 0x12e0, 0x0021,
139 "Boca Research Turbo Serial 658",
141 PUC_PORT_8S, 0x18, 0, 8,
144 { 0x10b5, 0x9050, 0x12e0, 0x0031,
145 "Boca Research Turbo Serial 654",
147 PUC_PORT_4S, 0x18, 0, 8,
151 * Dolphin Peripherals 4035 (dual serial port) card. PLX 9050, with
152 * a seemingly-lame EEPROM setup that puts the Dolphin IDs
153 * into the subsystem fields, and claims that it's a
154 * network/misc (0x02/0x80) device.
156 { 0x10b5, 0x9050, 0xd84d, 0x6808,
157 "Dolphin Peripherals 4035",
159 PUC_PORT_2S, 0x18, 4, 0,
163 * Dolphin Peripherals 4014 (dual parallel port) card. PLX 9050, with
164 * a seemingly-lame EEPROM setup that puts the Dolphin IDs
165 * into the subsystem fields, and claims that it's a
166 * network/misc (0x02/0x80) device.
168 { 0x10b5, 0x9050, 0xd84d, 0x6810,
169 "Dolphin Peripherals 4014",
171 PUC_PORT_2P, 0x20, 4, 0,
174 { 0x10e8, 0x818e, 0xffff, 0,
175 "Applied Micro Circuits 8 Port UART",
177 PUC_PORT_8S, 0x14, -1, -1,
178 .config_function = puc_config_amc
181 { 0x11fe, 0x8010, 0xffff, 0,
182 "Comtrol RocketPort 550/8 RJ11 part A",
184 PUC_PORT_4S, 0x10, 0, 8,
187 { 0x11fe, 0x8011, 0xffff, 0,
188 "Comtrol RocketPort 550/8 RJ11 part B",
190 PUC_PORT_4S, 0x10, 0, 8,
193 { 0x11fe, 0x8012, 0xffff, 0,
194 "Comtrol RocketPort 550/8 Octa part A",
196 PUC_PORT_4S, 0x10, 0, 8,
199 { 0x11fe, 0x8013, 0xffff, 0,
200 "Comtrol RocketPort 550/8 Octa part B",
202 PUC_PORT_4S, 0x10, 0, 8,
205 { 0x11fe, 0x8014, 0xffff, 0,
206 "Comtrol RocketPort 550/4 RJ45",
208 PUC_PORT_4S, 0x10, 0, 8,
211 { 0x11fe, 0x8015, 0xffff, 0,
212 "Comtrol RocketPort 550/Quad",
214 PUC_PORT_4S, 0x10, 0, 8,
217 { 0x11fe, 0x8016, 0xffff, 0,
218 "Comtrol RocketPort 550/16 part A",
220 PUC_PORT_4S, 0x10, 0, 8,
223 { 0x11fe, 0x8017, 0xffff, 0,
224 "Comtrol RocketPort 550/16 part B",
226 PUC_PORT_12S, 0x10, 0, 8,
229 { 0x11fe, 0x8018, 0xffff, 0,
230 "Comtrol RocketPort 550/8 part A",
232 PUC_PORT_4S, 0x10, 0, 8,
235 { 0x11fe, 0x8019, 0xffff, 0,
236 "Comtrol RocketPort 550/8 part B",
238 PUC_PORT_4S, 0x10, 0, 8,
242 * IBM SurePOS 300 Series (481033H) serial ports
243 * Details can be found on the IBM RSS websites
246 { 0x1014, 0x0297, 0xffff, 0,
247 "IBM SurePOS 300 Series (481033H) serial ports",
249 PUC_PORT_4S, 0x10, 4, 0
255 * SIIG provides documentation for their boards at:
256 * <URL:http://www.siig.com/downloads.asp>
259 { 0x131f, 0x1010, 0xffff, 0,
260 "SIIG Cyber I/O PCI 16C550 (10x family)",
262 PUC_PORT_1S1P, 0x18, 4, 0,
265 { 0x131f, 0x1011, 0xffff, 0,
266 "SIIG Cyber I/O PCI 16C650 (10x family)",
268 PUC_PORT_1S1P, 0x18, 4, 0,
271 { 0x131f, 0x1012, 0xffff, 0,
272 "SIIG Cyber I/O PCI 16C850 (10x family)",
274 PUC_PORT_1S1P, 0x18, 4, 0,
277 { 0x131f, 0x1021, 0xffff, 0,
278 "SIIG Cyber Parallel Dual PCI (10x family)",
280 PUC_PORT_2P, 0x18, 8, 0,
283 { 0x131f, 0x1030, 0xffff, 0,
284 "SIIG Cyber Serial Dual PCI 16C550 (10x family)",
286 PUC_PORT_2S, 0x18, 4, 0,
289 { 0x131f, 0x1031, 0xffff, 0,
290 "SIIG Cyber Serial Dual PCI 16C650 (10x family)",
292 PUC_PORT_2S, 0x18, 4, 0,
295 { 0x131f, 0x1032, 0xffff, 0,
296 "SIIG Cyber Serial Dual PCI 16C850 (10x family)",
298 PUC_PORT_2S, 0x18, 4, 0,
301 { 0x131f, 0x1034, 0xffff, 0, /* XXX really? */
302 "SIIG Cyber 2S1P PCI 16C550 (10x family)",
304 PUC_PORT_2S1P, 0x18, 4, 0,
307 { 0x131f, 0x1035, 0xffff, 0, /* XXX really? */
308 "SIIG Cyber 2S1P PCI 16C650 (10x family)",
310 PUC_PORT_2S1P, 0x18, 4, 0,
313 { 0x131f, 0x1036, 0xffff, 0, /* XXX really? */
314 "SIIG Cyber 2S1P PCI 16C850 (10x family)",
316 PUC_PORT_2S1P, 0x18, 4, 0,
319 { 0x131f, 0x1050, 0xffff, 0,
320 "SIIG Cyber 4S PCI 16C550 (10x family)",
322 PUC_PORT_4S, 0x18, 4, 0,
325 { 0x131f, 0x1051, 0xffff, 0,
326 "SIIG Cyber 4S PCI 16C650 (10x family)",
328 PUC_PORT_4S, 0x18, 4, 0,
331 { 0x131f, 0x1052, 0xffff, 0,
332 "SIIG Cyber 4S PCI 16C850 (10x family)",
334 PUC_PORT_4S, 0x18, 4, 0,
337 { 0x131f, 0x2010, 0xffff, 0,
338 "SIIG Cyber I/O PCI 16C550 (20x family)",
340 PUC_PORT_1S1P, 0x10, 4, 0,
343 { 0x131f, 0x2011, 0xffff, 0,
344 "SIIG Cyber I/O PCI 16C650 (20x family)",
346 PUC_PORT_1S1P, 0x10, 4, 0,
349 { 0x131f, 0x2012, 0xffff, 0,
350 "SIIG Cyber I/O PCI 16C850 (20x family)",
352 PUC_PORT_1S1P, 0x10, 4, 0,
355 { 0x131f, 0x2021, 0xffff, 0,
356 "SIIG Cyber Parallel Dual PCI (20x family)",
358 PUC_PORT_2P, 0x10, 8, 0,
361 { 0x131f, 0x2030, 0xffff, 0,
362 "SIIG Cyber Serial Dual PCI 16C550 (20x family)",
364 PUC_PORT_2S, 0x10, 4, 0,
367 { 0x131f, 0x2031, 0xffff, 0,
368 "SIIG Cyber Serial Dual PCI 16C650 (20x family)",
370 PUC_PORT_2S, 0x10, 4, 0,
373 { 0x131f, 0x2032, 0xffff, 0,
374 "SIIG Cyber Serial Dual PCI 16C850 (20x family)",
376 PUC_PORT_2S, 0x10, 4, 0,
379 { 0x131f, 0x2040, 0xffff, 0,
380 "SIIG Cyber 2P1S PCI 16C550 (20x family)",
382 PUC_PORT_1S2P, 0x10, -1, 0,
383 .config_function = puc_config_siig
386 { 0x131f, 0x2041, 0xffff, 0,
387 "SIIG Cyber 2P1S PCI 16C650 (20x family)",
389 PUC_PORT_1S2P, 0x10, -1, 0,
390 .config_function = puc_config_siig
393 { 0x131f, 0x2042, 0xffff, 0,
394 "SIIG Cyber 2P1S PCI 16C850 (20x family)",
396 PUC_PORT_1S2P, 0x10, -1, 0,
397 .config_function = puc_config_siig
400 { 0x131f, 0x2050, 0xffff, 0,
401 "SIIG Cyber 4S PCI 16C550 (20x family)",
403 PUC_PORT_4S, 0x10, 4, 0,
406 { 0x131f, 0x2051, 0xffff, 0,
407 "SIIG Cyber 4S PCI 16C650 (20x family)",
409 PUC_PORT_4S, 0x10, 4, 0,
412 { 0x131f, 0x2052, 0xffff, 0,
413 "SIIG Cyber 4S PCI 16C850 (20x family)",
415 PUC_PORT_4S, 0x10, 4, 0,
418 { 0x131f, 0x2060, 0xffff, 0,
419 "SIIG Cyber 2S1P PCI 16C550 (20x family)",
421 PUC_PORT_2S1P, 0x10, 4, 0,
424 { 0x131f, 0x2061, 0xffff, 0,
425 "SIIG Cyber 2S1P PCI 16C650 (20x family)",
427 PUC_PORT_2S1P, 0x10, 4, 0,
430 { 0x131f, 0x2062, 0xffff, 0,
431 "SIIG Cyber 2S1P PCI 16C850 (20x family)",
433 PUC_PORT_2S1P, 0x10, 4, 0,
436 { 0x131f, 0x2081, 0xffff, 0,
437 "SIIG PS8000 8S PCI 16C650 (20x family)",
439 PUC_PORT_8S, 0x10, -1, -1,
440 .config_function = puc_config_siig
443 { 0x135c, 0x0010, 0xffff, 0,
445 -3, /* max 8x clock rate */
446 PUC_PORT_4S, 0x14, 0, 8,
447 .config_function = puc_config_quatech
450 { 0x135c, 0x0020, 0xffff, 0,
452 -1, /* max 2x clock rate */
453 PUC_PORT_2S, 0x14, 0, 8,
454 .config_function = puc_config_quatech
457 { 0x135c, 0x0030, 0xffff, 0,
458 "Quatech DSC-200/300",
459 -1, /* max 2x clock rate */
460 PUC_PORT_2S, 0x14, 0, 8,
461 .config_function = puc_config_quatech
464 { 0x135c, 0x0040, 0xffff, 0,
465 "Quatech QSC-200/300",
466 -3, /* max 8x clock rate */
467 PUC_PORT_4S, 0x14, 0, 8,
468 .config_function = puc_config_quatech
471 { 0x135c, 0x0050, 0xffff, 0,
473 -3, /* max 8x clock rate */
474 PUC_PORT_8S, 0x14, 0, 8,
475 .config_function = puc_config_quatech
478 { 0x135c, 0x0060, 0xffff, 0,
480 -3, /* max 8x clock rate */
481 PUC_PORT_8S, 0x14, 0, 8,
482 .config_function = puc_config_quatech
485 { 0x135c, 0x0170, 0xffff, 0,
487 -1, /* max 2x clock rate */
488 PUC_PORT_4S, 0x18, 0, 8,
489 .config_function = puc_config_quatech
492 { 0x135c, 0x0180, 0xffff, 0,
494 -1, /* max 3x clock rate */
495 PUC_PORT_2S, 0x18, 0, 8,
496 .config_function = puc_config_quatech
499 { 0x135c, 0x01b0, 0xffff, 0,
500 "Quatech DSCLP-200/300",
501 -1, /* max 2x clock rate */
502 PUC_PORT_2S, 0x18, 0, 8,
503 .config_function = puc_config_quatech
506 { 0x135c, 0x01e0, 0xffff, 0,
508 -3, /* max 8x clock rate */
509 PUC_PORT_8S, 0x10, 0, 8,
510 .config_function = puc_config_quatech
513 { 0x1393, 0x1024, 0xffff, 0,
514 "Moxa Technologies, Smartio CP-102E/PCIe",
516 PUC_PORT_2S, 0x14, 0, -1,
517 .config_function = puc_config_moxa
520 { 0x1393, 0x1025, 0xffff, 0,
521 "Moxa Technologies, Smartio CP-102EL/PCIe",
523 PUC_PORT_2S, 0x14, 0, -1,
524 .config_function = puc_config_moxa
527 { 0x1393, 0x1040, 0xffff, 0,
528 "Moxa Technologies, Smartio C104H/PCI",
530 PUC_PORT_4S, 0x18, 0, 8,
533 { 0x1393, 0x1041, 0xffff, 0,
534 "Moxa Technologies, Smartio CP-104UL/PCI",
536 PUC_PORT_4S, 0x18, 0, 8,
539 { 0x1393, 0x1042, 0xffff, 0,
540 "Moxa Technologies, Smartio CP-104JU/PCI",
542 PUC_PORT_4S, 0x18, 0, 8,
545 { 0x1393, 0x1043, 0xffff, 0,
546 "Moxa Technologies, Smartio CP-104EL/PCIe",
548 PUC_PORT_4S, 0x18, 0, 8,
551 { 0x1393, 0x1045, 0xffff, 0,
552 "Moxa Technologies, Smartio CP-104EL-A/PCIe",
554 PUC_PORT_4S, 0x14, 0, -1,
555 .config_function = puc_config_moxa
558 { 0x1393, 0x1120, 0xffff, 0,
559 "Moxa Technologies, CP-112UL",
561 PUC_PORT_2S, 0x18, 0, 8,
564 { 0x1393, 0x1141, 0xffff, 0,
565 "Moxa Technologies, Industio CP-114",
567 PUC_PORT_4S, 0x18, 0, 8,
570 { 0x1393, 0x1144, 0xffff, 0,
571 "Moxa Technologies, Smartio CP-114EL/PCIe",
573 PUC_PORT_4S, 0x14, 0, -1,
574 .config_function = puc_config_moxa
577 { 0x1393, 0x1182, 0xffff, 0,
578 "Moxa Technologies, Smartio CP-118EL-A/PCIe",
580 PUC_PORT_8S, 0x14, 0, -1,
581 .config_function = puc_config_moxa
584 { 0x1393, 0x1680, 0xffff, 0,
585 "Moxa Technologies, C168H/PCI",
587 PUC_PORT_8S, 0x18, 0, 8,
590 { 0x1393, 0x1681, 0xffff, 0,
591 "Moxa Technologies, C168U/PCI",
593 PUC_PORT_8S, 0x18, 0, 8,
596 { 0x1393, 0x1682, 0xffff, 0,
597 "Moxa Technologies, CP-168EL/PCIe",
599 PUC_PORT_8S, 0x18, 0, 8,
602 { 0x1393, 0x1683, 0xffff, 0,
603 "Moxa Technologies, Smartio CP-168EL-A/PCIe",
605 PUC_PORT_8S, 0x14, 0, -1,
606 .config_function = puc_config_moxa
609 { 0x13a8, 0x0152, 0xffff, 0,
612 PUC_PORT_2S, 0x10, 0, -1,
613 .config_function = puc_config_exar
616 { 0x13a8, 0x0154, 0xffff, 0,
619 PUC_PORT_4S, 0x10, 0, -1,
620 .config_function = puc_config_exar
623 { 0x13a8, 0x0158, 0xffff, 0,
626 PUC_PORT_8S, 0x10, 0, -1,
627 .config_function = puc_config_exar
630 { 0x13a8, 0x0258, 0xffff, 0,
633 PUC_PORT_8S, 0x10, 0, -1,
634 .config_function = puc_config_exar
637 /* The XR17V358 uses the 125MHz PCIe clock as its reference clock. */
638 { 0x13a8, 0x0358, 0xffff, 0,
641 PUC_PORT_8S, 0x10, 0, -1,
642 .config_function = puc_config_exar_pcie
645 { 0x13fe, 0x1600, 0x1602, 0x0002,
646 "Advantech PCI-1602",
648 PUC_PORT_2S, 0x10, 0, 8,
651 { 0x1407, 0x0100, 0xffff, 0,
652 "Lava Computers Dual Serial",
654 PUC_PORT_2S, 0x10, 4, 0,
657 { 0x1407, 0x0101, 0xffff, 0,
658 "Lava Computers Quatro A",
660 PUC_PORT_2S, 0x10, 4, 0,
663 { 0x1407, 0x0102, 0xffff, 0,
664 "Lava Computers Quatro B",
666 PUC_PORT_2S, 0x10, 4, 0,
669 { 0x1407, 0x0120, 0xffff, 0,
670 "Lava Computers Quattro-PCI A",
672 PUC_PORT_2S, 0x10, 4, 0,
675 { 0x1407, 0x0121, 0xffff, 0,
676 "Lava Computers Quattro-PCI B",
678 PUC_PORT_2S, 0x10, 4, 0,
681 { 0x1407, 0x0180, 0xffff, 0,
682 "Lava Computers Octo A",
684 PUC_PORT_4S, 0x10, 4, 0,
687 { 0x1407, 0x0181, 0xffff, 0,
688 "Lava Computers Octo B",
690 PUC_PORT_4S, 0x10, 4, 0,
693 { 0x1409, 0x7268, 0xffff, 0,
696 PUC_PORT_2P, 0x10, 0, 8,
699 { 0x1409, 0x7168, 0xffff, 0,
702 PUC_PORT_NONSTANDARD, 0x10, -1, -1,
703 .config_function = puc_config_timedia
707 * Boards with an Oxford Semiconductor chip.
709 * Oxford Semiconductor provides documentation for their chip at:
710 * <URL:http://www.plxtech.com/products/uart/>
712 * As sold by Kouwell <URL:http://www.kouwell.com/>.
713 * I/O Flex PCI I/O Card Model-223 with 4 serial and 1 parallel ports.
716 0x1415, 0x9501, 0x10fc, 0xc070,
717 "I-O DATA RSA-PCI2/R",
719 PUC_PORT_2S, 0x10, 0, 8,
722 { 0x1415, 0x9501, 0x131f, 0x2050,
723 "SIIG Cyber 4 PCI 16550",
725 PUC_PORT_4S, 0x10, 0, 8,
728 { 0x1415, 0x9501, 0x131f, 0x2051,
729 "SIIG Cyber 4S PCI 16C650 (20x family)",
731 PUC_PORT_4S, 0x10, 0, 8,
734 { 0x1415, 0x9501, 0x131f, 0x2052,
735 "SIIG Quartet Serial 850",
737 PUC_PORT_4S, 0x10, 0, 8,
740 { 0x1415, 0x9501, 0x14db, 0x2150,
741 "Kuroutoshikou SERIAL4P-LPPCI2",
743 PUC_PORT_4S, 0x10, 0, 8,
746 { 0x1415, 0x9501, 0xffff, 0,
747 "Oxford Semiconductor OX16PCI954 UARTs",
749 PUC_PORT_4S, 0x10, 0, 8,
750 .config_function = puc_config_oxford_pci954
753 { 0x1415, 0x950a, 0x131f, 0x2030,
754 "SIIG Cyber 2S PCIe",
756 PUC_PORT_2S, 0x10, 0, 8,
759 { 0x1415, 0x950a, 0x131f, 0x2032,
760 "SIIG Cyber Serial Dual PCI 16C850",
762 PUC_PORT_4S, 0x10, 0, 8,
765 { 0x1415, 0x950a, 0xffff, 0,
766 "Oxford Semiconductor OX16PCI954 UARTs",
768 PUC_PORT_4S, 0x10, 0, 8,
771 { 0x1415, 0x9511, 0xffff, 0,
772 "Oxford Semiconductor OX9160/OX16PCI954 UARTs (function 1)",
774 PUC_PORT_4S, 0x10, 0, 8,
777 { 0x1415, 0x9521, 0xffff, 0,
778 "Oxford Semiconductor OX16PCI952 UARTs",
780 PUC_PORT_2S, 0x10, 4, 0,
783 { 0x1415, 0x9538, 0xffff, 0,
784 "Oxford Semiconductor OX16PCI958 UARTs",
786 PUC_PORT_8S, 0x18, 0, 8,
790 * Perle boards use Oxford Semiconductor chips, but they store the
791 * Oxford Semiconductor device ID as a subvendor device ID and use
792 * their own device IDs.
795 { 0x155f, 0x0331, 0xffff, 0,
796 "Perle Ultraport4 Express",
798 PUC_PORT_4S, 0x10, 0, 8,
801 { 0x155f, 0xB012, 0xffff, 0,
804 PUC_PORT_2S, 0x10, 0, 8,
807 { 0x155f, 0xB022, 0xffff, 0,
810 PUC_PORT_2S, 0x10, 0, 8,
813 { 0x155f, 0xB004, 0xffff, 0,
816 PUC_PORT_4S, 0x10, 0, 8,
819 { 0x155f, 0xB008, 0xffff, 0,
822 PUC_PORT_8S, 0x10, 0, 8,
827 * Oxford Semiconductor PCI Express Expresso family
829 * Found in many 'native' PCI Express serial boards such as:
831 * eMegatech MP954ER4 (4 port) and MP958ER8 (8 port)
832 * <URL:http://www.emegatech.com.tw/pdrs232pcie.html>
834 * Lindy 51189 (4 port)
835 * <URL:http://www.lindy.com> <URL:http://tinyurl.com/lindy-51189>
837 * StarTech.com PEX4S952 (4 port) and PEX8S952 (8 port)
838 * <URL:http://www.startech.com>
841 { 0x1415, 0xc138, 0xffff, 0,
842 "Oxford Semiconductor OXPCIe952 UARTs",
844 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
845 .config_function = puc_config_oxford_pcie
848 { 0x1415, 0xc158, 0xffff, 0,
849 "Oxford Semiconductor OXPCIe952 UARTs",
851 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
852 .config_function = puc_config_oxford_pcie
855 { 0x1415, 0xc15d, 0xffff, 0,
856 "Oxford Semiconductor OXPCIe952 UARTs (function 1)",
858 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
859 .config_function = puc_config_oxford_pcie
862 { 0x1415, 0xc208, 0xffff, 0,
863 "Oxford Semiconductor OXPCIe954 UARTs",
865 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
866 .config_function = puc_config_oxford_pcie
869 { 0x1415, 0xc20d, 0xffff, 0,
870 "Oxford Semiconductor OXPCIe954 UARTs (function 1)",
872 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
873 .config_function = puc_config_oxford_pcie
876 { 0x1415, 0xc308, 0xffff, 0,
877 "Oxford Semiconductor OXPCIe958 UARTs",
879 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
880 .config_function = puc_config_oxford_pcie
883 { 0x1415, 0xc30d, 0xffff, 0,
884 "Oxford Semiconductor OXPCIe958 UARTs (function 1)",
886 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
887 .config_function = puc_config_oxford_pcie
890 { 0x14d2, 0x8010, 0xffff, 0,
893 PUC_PORT_1S, 0x14, 0, 0,
896 { 0x14d2, 0x8020, 0xffff, 0,
899 PUC_PORT_2S, 0x14, 4, 0,
902 { 0x14d2, 0x8028, 0xffff, 0,
905 PUC_PORT_2S, 0x20, 0, 8,
909 * VScom (Titan?) PCI-800L. More modern variant of the
910 * PCI-800. Uses 6 discrete 16550 UARTs, plus another
911 * two of them obviously implemented as macro cells in
912 * the ASIC. This causes the weird port access pattern
913 * below, where two of the IO port ranges each access
914 * one of the ASIC UARTs, and a block of IO addresses
915 * access the external UARTs.
917 { 0x14d2, 0x8080, 0xffff, 0,
918 "Titan VScom PCI-800L",
920 PUC_PORT_8S, 0x14, -1, -1,
921 .config_function = puc_config_titan
925 * VScom PCI-800H. Uses 8 16950 UART, behind a PCI chips that offers
926 * 4 com port on PCI device 0 and 4 on PCI device 1. PCI device 0 has
927 * device ID 3 and PCI device 1 device ID 4.
929 { 0x14d2, 0xa003, 0xffff, 0,
932 PUC_PORT_4S, 0x10, 0, 8,
935 { 0x14d2, 0xa004, 0xffff, 0,
938 PUC_PORT_4S, 0x10, 0, 8,
941 { 0x14d2, 0xa005, 0xffff, 0,
944 PUC_PORT_2S, 0x10, 0, 8,
947 { 0x14d2, 0xe020, 0xffff, 0,
948 "Titan VScom PCI-200HV2",
950 PUC_PORT_2S, 0x10, 4, 0,
953 { 0x14d2, 0xa007, 0xffff, 0,
954 "Titan VScom PCIex-800H",
956 PUC_PORT_4S, 0x10, 0, 8,
959 { 0x14d2, 0xa008, 0xffff, 0,
960 "Titan VScom PCIex-800H",
962 PUC_PORT_4S, 0x10, 0, 8,
965 { 0x14db, 0x2130, 0xffff, 0,
966 "Avlab Technology, PCI IO 2S",
968 PUC_PORT_2S, 0x10, 4, 0,
971 { 0x14db, 0x2150, 0xffff, 0,
972 "Avlab Low Profile PCI 4 Serial",
974 PUC_PORT_4S, 0x10, 4, 0,
977 { 0x14db, 0x2152, 0xffff, 0,
978 "Avlab Low Profile PCI 4 Serial",
980 PUC_PORT_4S, 0x10, 4, 0,
983 { 0x1592, 0x0781, 0xffff, 0,
984 "Syba Tech Ltd. PCI-4S2P-550-ECP",
986 PUC_PORT_4S1P, 0x10, 0, -1,
987 .config_function = puc_config_syba
990 { 0x1fd4, 0x1999, 0x1fd4, 0x0002,
991 "Sunix SER5xxxx 2-port serial",
993 PUC_PORT_2S, 0x10, 0, 8,
996 { 0x1fd4, 0x1999, 0x1fd4, 0x0004,
997 "Sunix SER5xxxx 4-port serial",
999 PUC_PORT_4S, 0x10, 0, 8,
1002 { 0x1fd4, 0x1999, 0x1fd4, 0x0008,
1003 "Sunix SER5xxxx 8-port serial",
1005 PUC_PORT_8S, -1, -1, -1,
1006 .config_function = puc_config_sunix
1009 { 0x1fd4, 0x1999, 0x1fd4, 0x0101,
1010 "Sunix MIO5xxxx 1-port serial and 1284 Printer port",
1012 PUC_PORT_1S1P, -1, -1, -1,
1013 .config_function = puc_config_sunix
1016 { 0x1fd4, 0x1999, 0x1fd4, 0x0102,
1017 "Sunix MIO5xxxx 2-port serial and 1284 Printer port",
1019 PUC_PORT_2S1P, -1, -1, -1,
1020 .config_function = puc_config_sunix
1023 { 0x1fd4, 0x1999, 0x1fd4, 0x0104,
1024 "Sunix MIO5xxxx 4-port serial and 1284 Printer port",
1026 PUC_PORT_4S1P, -1, -1, -1,
1027 .config_function = puc_config_sunix
1030 { 0x5372, 0x6873, 0xffff, 0,
1031 "Sun 1040 PCI Quad Serial",
1033 PUC_PORT_4S, 0x10, 4, 0,
1036 { 0x6666, 0x0001, 0xffff, 0,
1037 "Decision Computer Inc, PCCOM 4-port serial",
1039 PUC_PORT_4S, 0x1c, 0, 8,
1042 { 0x6666, 0x0002, 0xffff, 0,
1043 "Decision Computer Inc, PCCOM 8-port serial",
1045 PUC_PORT_8S, 0x1c, 0, 8,
1048 { 0x6666, 0x0004, 0xffff, 0,
1049 "PCCOM dual port RS232/422/485",
1051 PUC_PORT_2S, 0x1c, 0, 8,
1054 { 0x9710, 0x9815, 0xffff, 0,
1055 "NetMos NM9815 Dual 1284 Printer port",
1057 PUC_PORT_2P, 0x10, 8, 0,
1061 * This is more specific than the generic NM9835 entry, and is placed
1062 * here to _prevent_ puc(4) from claiming this single port card.
1064 * uart(4) will claim this device.
1066 { 0x9710, 0x9835, 0x1000, 1,
1067 "NetMos NM9835 based 1-port serial",
1069 PUC_PORT_1S, 0x10, 4, 0,
1072 { 0x9710, 0x9835, 0x1000, 2,
1073 "NetMos NM9835 based 2-port serial",
1075 PUC_PORT_2S, 0x10, 4, 0,
1078 { 0x9710, 0x9835, 0xffff, 0,
1079 "NetMos NM9835 Dual UART and 1284 Printer port",
1081 PUC_PORT_2S1P, 0x10, 4, 0,
1084 { 0x9710, 0x9845, 0x1000, 0x0006,
1085 "NetMos NM9845 6 Port UART",
1087 PUC_PORT_6S, 0x10, 4, 0,
1090 { 0x9710, 0x9845, 0xffff, 0,
1091 "NetMos NM9845 Quad UART and 1284 Printer port",
1093 PUC_PORT_4S1P, 0x10, 4, 0,
1096 { 0x9710, 0x9865, 0xa000, 0x3002,
1097 "NetMos NM9865 Dual UART",
1099 PUC_PORT_2S, 0x10, 4, 0,
1102 { 0x9710, 0x9865, 0xa000, 0x3003,
1103 "NetMos NM9865 Triple UART",
1105 PUC_PORT_3S, 0x10, 4, 0,
1108 { 0x9710, 0x9865, 0xa000, 0x3004,
1109 "NetMos NM9865 Quad UART",
1111 PUC_PORT_4S, 0x10, 4, 0,
1114 { 0x9710, 0x9865, 0xa000, 0x3011,
1115 "NetMos NM9865 Single UART and 1284 Printer port",
1117 PUC_PORT_1S1P, 0x10, 4, 0,
1120 { 0x9710, 0x9865, 0xa000, 0x3012,
1121 "NetMos NM9865 Dual UART and 1284 Printer port",
1123 PUC_PORT_2S1P, 0x10, 4, 0,
1126 { 0x9710, 0x9865, 0xa000, 0x3020,
1127 "NetMos NM9865 Dual 1284 Printer port",
1129 PUC_PORT_2P, 0x10, 4, 0,
1132 { 0xb00c, 0x021c, 0xffff, 0,
1133 "IC Book Labs Gunboat x4 Lite",
1135 PUC_PORT_4S, 0x10, 0, 8,
1136 .config_function = puc_config_icbook
1139 { 0xb00c, 0x031c, 0xffff, 0,
1140 "IC Book Labs Gunboat x4 Pro",
1142 PUC_PORT_4S, 0x10, 0, 8,
1143 .config_function = puc_config_icbook
1146 { 0xb00c, 0x041c, 0xffff, 0,
1147 "IC Book Labs Ironclad x8 Lite",
1149 PUC_PORT_8S, 0x10, 0, 8,
1150 .config_function = puc_config_icbook
1153 { 0xb00c, 0x051c, 0xffff, 0,
1154 "IC Book Labs Ironclad x8 Pro",
1156 PUC_PORT_8S, 0x10, 0, 8,
1157 .config_function = puc_config_icbook
1160 { 0xb00c, 0x081c, 0xffff, 0,
1161 "IC Book Labs Dreadnought x16 Pro",
1163 PUC_PORT_16S, 0x10, 0, 8,
1164 .config_function = puc_config_icbook
1167 { 0xb00c, 0x091c, 0xffff, 0,
1168 "IC Book Labs Dreadnought x16 Lite",
1170 PUC_PORT_16S, 0x10, 0, 8,
1171 .config_function = puc_config_icbook
1174 { 0xb00c, 0x0a1c, 0xffff, 0,
1175 "IC Book Labs Gunboat x2 Low Profile",
1177 PUC_PORT_2S, 0x10, 0, 8,
1180 { 0xb00c, 0x0b1c, 0xffff, 0,
1181 "IC Book Labs Gunboat x4 Low Profile",
1183 PUC_PORT_4S, 0x10, 0, 8,
1184 .config_function = puc_config_icbook
1187 { 0xffff, 0, 0xffff, 0, NULL, 0 }
1191 puc_config_amc(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1195 case PUC_CFG_GET_OFS:
1196 *res = 8 * (port & 1);
1198 case PUC_CFG_GET_RID:
1199 *res = 0x14 + (port >> 1) * 4;
1208 puc_config_diva(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1211 const struct puc_cfg *cfg = sc->sc_cfg;
1213 if (cmd == PUC_CFG_GET_OFS) {
1214 if (cfg->subdevice == 0x1282) /* Everest SP */
1216 else if (cfg->subdevice == 0x104b) /* Maestro SP2 */
1217 port = (port == 3) ? 4 : port;
1218 *res = port * 8 + ((port > 2) ? 0x18 : 0);
1225 puc_config_exar(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1228 if (cmd == PUC_CFG_GET_OFS) {
1229 *res = port * 0x200;
1236 puc_config_exar_pcie(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1239 if (cmd == PUC_CFG_GET_OFS) {
1240 *res = port * 0x400;
1247 puc_config_icbook(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1250 if (cmd == PUC_CFG_GET_ILR) {
1251 *res = PUC_ILR_DIGI;
1258 puc_config_moxa(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1261 if (cmd == PUC_CFG_GET_OFS) {
1262 const struct puc_cfg *cfg = sc->sc_cfg;
1264 if (port == 3 && (cfg->device == 0x1045 || cfg->device == 0x1144))
1266 *res = port * 0x200;
1274 puc_config_quatech(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1277 const struct puc_cfg *cfg = sc->sc_cfg;
1278 struct puc_bar *bar;
1284 * Check if the scratchpad register is enabled or if the
1285 * interrupt status and options registers are active.
1287 bar = puc_get_bar(sc, cfg->rid);
1290 /* Set DLAB in the LCR register of UART 0. */
1291 bus_write_1(bar->b_res, 3, 0x80);
1292 /* Write 0 to the SPR register of UART 0. */
1293 bus_write_1(bar->b_res, 7, 0);
1294 /* Read back the contents of the SPR register of UART 0. */
1295 v0 = bus_read_1(bar->b_res, 7);
1296 /* Write a specific value to the SPR register of UART 0. */
1297 bus_write_1(bar->b_res, 7, 0x80 + -cfg->clock);
1298 /* Read back the contents of the SPR register of UART 0. */
1299 v1 = bus_read_1(bar->b_res, 7);
1300 /* Clear DLAB in the LCR register of UART 0. */
1301 bus_write_1(bar->b_res, 3, 0);
1302 /* Save the two values read-back from the SPR register. */
1303 sc->sc_cfg_data = (v0 << 8) | v1;
1304 if (v0 == 0 && v1 == 0x80 + -cfg->clock) {
1306 * The SPR register echoed the two values written
1307 * by us. This means that the SPAD jumper is set.
1309 device_printf(sc->sc_dev, "warning: extra features "
1310 "not usable -- SPAD compatibility enabled\n");
1315 * The first value doesn't match. This can only mean
1316 * that the SPAD jumper is not set and that a non-
1317 * standard fixed clock multiplier jumper is set.
1320 device_printf(sc->sc_dev, "fixed clock rate "
1321 "multiplier of %d\n", 1 << v0);
1322 if (v0 < -cfg->clock)
1323 device_printf(sc->sc_dev, "warning: "
1324 "suboptimal fixed clock rate multiplier "
1329 * The first value matched, but the second didn't. We know
1330 * that the SPAD jumper is not set. We also know that the
1331 * clock rate multiplier is software controlled *and* that
1332 * we just programmed it to the maximum allowed.
1335 device_printf(sc->sc_dev, "clock rate multiplier of "
1336 "%d selected\n", 1 << -cfg->clock);
1338 case PUC_CFG_GET_CLOCK:
1339 v0 = (sc->sc_cfg_data >> 8) & 0xff;
1340 v1 = sc->sc_cfg_data & 0xff;
1341 if (v0 == 0 && v1 == 0x80 + -cfg->clock) {
1343 * XXX With the SPAD jumper applied, there's no
1344 * easy way of knowing if there's also a clock
1345 * rate multiplier jumper installed. Let's hope
1348 *res = DEFAULT_RCLK;
1349 } else if (v0 == 0) {
1351 * No clock rate multiplier jumper installed,
1352 * so we programmed the board with the maximum
1353 * multiplier allowed as given to us in the
1354 * clock field of the config record (negated).
1356 *res = DEFAULT_RCLK << -cfg->clock;
1358 *res = DEFAULT_RCLK << v0;
1360 case PUC_CFG_GET_ILR:
1361 v0 = (sc->sc_cfg_data >> 8) & 0xff;
1362 v1 = sc->sc_cfg_data & 0xff;
1363 *res = (v0 == 0 && v1 == 0x80 + -cfg->clock)
1364 ? PUC_ILR_NONE : PUC_ILR_QUATECH;
1373 puc_config_syba(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1376 static int base[] = { 0x251, 0x3f0, 0 };
1377 const struct puc_cfg *cfg = sc->sc_cfg;
1378 struct puc_bar *bar;
1384 bar = puc_get_bar(sc, cfg->rid);
1388 /* configure both W83877TFs */
1389 bus_write_1(bar->b_res, 0x250, 0x89);
1390 bus_write_1(bar->b_res, 0x3f0, 0x87);
1391 bus_write_1(bar->b_res, 0x3f0, 0x87);
1393 while (base[idx] != 0) {
1395 bus_write_1(bar->b_res, efir, 0x09);
1396 v = bus_read_1(bar->b_res, efir + 1);
1397 if ((v & 0x0f) != 0x0c)
1399 bus_write_1(bar->b_res, efir, 0x16);
1400 v = bus_read_1(bar->b_res, efir + 1);
1401 bus_write_1(bar->b_res, efir, 0x16);
1402 bus_write_1(bar->b_res, efir + 1, v | 0x04);
1403 bus_write_1(bar->b_res, efir, 0x16);
1404 bus_write_1(bar->b_res, efir + 1, v & ~0x04);
1405 ofs = base[idx] & 0x300;
1406 bus_write_1(bar->b_res, efir, 0x23);
1407 bus_write_1(bar->b_res, efir + 1, (ofs + 0x78) >> 2);
1408 bus_write_1(bar->b_res, efir, 0x24);
1409 bus_write_1(bar->b_res, efir + 1, (ofs + 0xf8) >> 2);
1410 bus_write_1(bar->b_res, efir, 0x25);
1411 bus_write_1(bar->b_res, efir + 1, (ofs + 0xe8) >> 2);
1412 bus_write_1(bar->b_res, efir, 0x17);
1413 bus_write_1(bar->b_res, efir + 1, 0x03);
1414 bus_write_1(bar->b_res, efir, 0x28);
1415 bus_write_1(bar->b_res, efir + 1, 0x43);
1418 bus_write_1(bar->b_res, 0x250, 0xaa);
1419 bus_write_1(bar->b_res, 0x3f0, 0xaa);
1421 case PUC_CFG_GET_OFS:
1447 puc_config_siig(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1450 const struct puc_cfg *cfg = sc->sc_cfg;
1453 case PUC_CFG_GET_OFS:
1454 if (cfg->ports == PUC_PORT_8S) {
1455 *res = (port > 4) ? 8 * (port - 4) : 0;
1459 case PUC_CFG_GET_RID:
1460 if (cfg->ports == PUC_PORT_8S) {
1461 *res = 0x10 + ((port > 4) ? 0x10 : 4 * port);
1464 if (cfg->ports == PUC_PORT_2S1P) {
1466 case 0: *res = 0x10; return (0);
1467 case 1: *res = 0x14; return (0);
1468 case 2: *res = 0x1c; return (0);
1479 puc_config_timedia(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1482 static const uint16_t dual[] = {
1483 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
1484 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
1485 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
1486 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
1489 static const uint16_t quad[] = {
1490 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
1491 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
1492 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
1495 static const uint16_t octa[] = {
1496 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
1497 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
1499 static const struct {
1501 const uint16_t *ids;
1508 static char desc[64];
1513 case PUC_CFG_GET_CLOCK:
1515 *res = DEFAULT_RCLK * 8;
1517 *res = DEFAULT_RCLK;
1519 case PUC_CFG_GET_DESC:
1520 snprintf(desc, sizeof(desc),
1521 "Timedia technology %d Port Serial", (int)sc->sc_cfg_data);
1522 *res = (intptr_t)desc;
1524 case PUC_CFG_GET_NPORTS:
1525 subdev = pci_get_subdevice(sc->sc_dev);
1527 while (subdevs[dev].ports != 0) {
1529 while (subdevs[dev].ids[id] != 0) {
1530 if (subdev == subdevs[dev].ids[id]) {
1531 sc->sc_cfg_data = subdevs[dev].ports;
1532 *res = sc->sc_cfg_data;
1540 case PUC_CFG_GET_OFS:
1541 *res = (port == 1 || port == 3) ? 8 : 0;
1543 case PUC_CFG_GET_RID:
1544 *res = 0x10 + ((port > 3) ? port - 2 : port >> 1) * 4;
1546 case PUC_CFG_GET_TYPE:
1547 *res = PUC_TYPE_SERIAL;
1556 puc_config_oxford_pci954(struct puc_softc *sc, enum puc_cfg_cmd cmd,
1557 int port __unused, intptr_t *res)
1561 case PUC_CFG_GET_CLOCK:
1563 * OXu16PCI954 use a 14.7456 MHz clock by default while
1564 * OX16PCI954 and OXm16PCI954 employ a 1.8432 MHz one.
1566 if (pci_get_revid(sc->sc_dev) == 1)
1567 *res = DEFAULT_RCLK * 8;
1569 *res = DEFAULT_RCLK;
1578 puc_config_oxford_pcie(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1581 const struct puc_cfg *cfg = sc->sc_cfg;
1583 struct puc_bar *bar;
1588 device_printf(sc->sc_dev, "%d UARTs detected\n",
1591 /* Set UARTs to enhanced mode */
1592 bar = puc_get_bar(sc, cfg->rid);
1595 for (idx = 0; idx < sc->sc_nports; idx++) {
1596 value = bus_read_1(bar->b_res, 0x1000 + (idx << 9) +
1598 bus_write_1(bar->b_res, 0x1000 + (idx << 9) + 0x92,
1602 case PUC_CFG_GET_LEN:
1605 case PUC_CFG_GET_NPORTS:
1607 * Check if we are being called from puc_bfe_attach()
1608 * or puc_bfe_probe(). If puc_bfe_probe(), we cannot
1609 * puc_get_bar(), so we return a value of 16. This has cosmetic
1610 * side-effects at worst; in PUC_CFG_GET_DESC,
1611 * (int)sc->sc_cfg_data will not contain the true number of
1612 * ports in PUC_CFG_GET_DESC, but we are not implementing that
1613 * call for this device family anyway.
1615 * The check is for initialisation of sc->sc_bar[idx], which is
1616 * only done in puc_bfe_attach().
1620 if (sc->sc_bar[idx++].b_rid != -1) {
1621 sc->sc_cfg_data = 16;
1622 *res = sc->sc_cfg_data;
1625 } while (idx < PUC_PCI_BARS);
1627 bar = puc_get_bar(sc, cfg->rid);
1631 value = bus_read_1(bar->b_res, 0x04);
1635 sc->sc_cfg_data = value;
1636 *res = sc->sc_cfg_data;
1638 case PUC_CFG_GET_OFS:
1639 *res = 0x1000 + (port << 9);
1641 case PUC_CFG_GET_TYPE:
1642 *res = PUC_TYPE_SERIAL;
1651 puc_config_sunix(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1657 case PUC_CFG_GET_OFS:
1658 error = puc_config(sc, PUC_CFG_GET_TYPE, port, res);
1661 *res = (*res == PUC_TYPE_SERIAL) ? (port & 3) * 8 : 0;
1663 case PUC_CFG_GET_RID:
1664 error = puc_config(sc, PUC_CFG_GET_TYPE, port, res);
1667 *res = (*res == PUC_TYPE_SERIAL && port <= 3) ? 0x10 : 0x14;
1676 puc_config_titan(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1680 case PUC_CFG_GET_OFS:
1681 *res = (port < 3) ? 0 : (port - 2) << 3;
1683 case PUC_CFG_GET_RID:
1684 *res = 0x14 + ((port >= 2) ? 0x0c : port << 2);