sys/dev/qlnx/qlnxe/ecore_cxt.c

   1 /*
   2  * Copyright (c) 2017-2018 Cavium, Inc.
   3  * All rights reserved.
   4  *
   5  *  Redistribution and use in source and binary forms, with or without
   6  *  modification, are permitted provided that the following conditions
   7  *  are met:
   8  *
   9  *  1. Redistributions of source code must retain the above copyright
  10  *     notice, this list of conditions and the following disclaimer.
  11  *  2. Redistributions in binary form must reproduce the above copyright
  12  *     notice, this list of conditions and the following disclaimer in the
  13  *     documentation and/or other materials provided with the distribution.
  14  *
  15  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  16  *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  19  *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  20  *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  21  *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  22  *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  23  *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  24  *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  25  *  POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 /*
  29  * File : ecore_cxt.c
  30  */
  31 #include <sys/cdefs.h>
  32 __FBSDID("$FreeBSD$");
  33
  34 #include "bcm_osal.h"
  35 #include "reg_addr.h"
  36 #include "common_hsi.h"
  37 #include "ecore_hsi_common.h"
  38 #include "ecore_hsi_eth.h"
  39 #include "tcp_common.h"
  40 #include "ecore_hsi_iscsi.h"
  41 #include "ecore_hsi_fcoe.h"
  42 #include "ecore_hsi_roce.h"
  43 #include "ecore_hsi_iwarp.h"
  44 #include "ecore_rt_defs.h"
  45 #include "ecore_status.h"
  46 #include "ecore.h"
  47 #include "ecore_init_ops.h"
  48 #include "ecore_init_fw_funcs.h"
  49 #include "ecore_cxt.h"
  50 #include "ecore_hw.h"
  51 #include "ecore_dev_api.h"
  52 #include "ecore_sriov.h"
  53 #include "ecore_roce.h"
  54 #include "ecore_mcp.h"
  55
  56 /* Max number of connection types in HW (DQ/CDU etc.) */
  57 #define MAX_CONN_TYPES          PROTOCOLID_COMMON
  58 #define NUM_TASK_TYPES          2
  59 #define NUM_TASK_PF_SEGMENTS    4
  60 #define NUM_TASK_VF_SEGMENTS    1
  61
  62 /* Doorbell-Queue constants */
  63 #define DQ_RANGE_SHIFT  4
  64 #define DQ_RANGE_ALIGN  (1 << DQ_RANGE_SHIFT)
  65
  66 /* Searcher constants */
  67 #define SRC_MIN_NUM_ELEMS 256
  68
  69 /* Timers constants */
  70 #define TM_SHIFT        7
  71 #define TM_ALIGN        (1 << TM_SHIFT)
  72 #define TM_ELEM_SIZE    4
  73
  74 /* ILT constants */
  75 #define ILT_DEFAULT_HW_P_SIZE   4
  76
  77 #define ILT_PAGE_IN_BYTES(hw_p_size)    (1U << ((hw_p_size) + 12))
  78 #define ILT_CFG_REG(cli, reg)           PSWRQ2_REG_##cli##_##reg##_RT_OFFSET
  79
  80 /* ILT entry structure */
  81 #define ILT_ENTRY_PHY_ADDR_MASK         0x000FFFFFFFFFFFULL
  82 #define ILT_ENTRY_PHY_ADDR_SHIFT        0
  83 #define ILT_ENTRY_VALID_MASK            0x1ULL
  84 #define ILT_ENTRY_VALID_SHIFT           52
  85 #define ILT_ENTRY_IN_REGS               2
  86 #define ILT_REG_SIZE_IN_BYTES           4
  87
  88 /* connection context union */
  89 union conn_context {
  90         struct e4_core_conn_context  core_ctx;
  91         struct e4_eth_conn_context        eth_ctx;
  92         struct e4_iscsi_conn_context iscsi_ctx;
  93         struct e4_fcoe_conn_context  fcoe_ctx;
  94         struct e4_roce_conn_context  roce_ctx;
  95 };
  96
  97 /* TYPE-0 task context - iSCSI, FCOE */
  98 union type0_task_context {
  99         struct e4_iscsi_task_context iscsi_ctx;
 100         struct e4_fcoe_task_context  fcoe_ctx;
 101 };
 102
 103 /* TYPE-1 task context - ROCE */
 104 union type1_task_context {
 105         struct e4_rdma_task_context roce_ctx;
 106 };
 107
 108 struct src_ent {
 109         u8  opaque[56];
 110         u64 next;
 111 };
 112
 113 #define CDUT_SEG_ALIGNMET 3 /* in 4k chunks */
 114 #define CDUT_SEG_ALIGNMET_IN_BYTES (1 << (CDUT_SEG_ALIGNMET + 12))
 115
 116 #define CONN_CXT_SIZE(p_hwfn) \
 117         ALIGNED_TYPE_SIZE(union conn_context, p_hwfn)
 118
 119 #define SRQ_CXT_SIZE (sizeof(struct rdma_srq_context))
 120
 121 #define TYPE0_TASK_CXT_SIZE(p_hwfn) \
 122         ALIGNED_TYPE_SIZE(union type0_task_context, p_hwfn)
 123
 124 /* Alignment is inherent to the type1_task_context structure */
 125 #define TYPE1_TASK_CXT_SIZE(p_hwfn) sizeof(union type1_task_context)
 126
 127 /* PF per protocl configuration object */
 128 #define TASK_SEGMENTS   (NUM_TASK_PF_SEGMENTS + NUM_TASK_VF_SEGMENTS)
 129 #define TASK_SEGMENT_VF (NUM_TASK_PF_SEGMENTS)
 130
 131 struct ecore_tid_seg {
 132         u32     count;
 133         u8      type;
 134         bool    has_fl_mem;
 135 };
 136
 137 struct ecore_conn_type_cfg {
 138         u32                     cid_count;
 139         u32                     cids_per_vf;
 140         struct ecore_tid_seg    tid_seg[TASK_SEGMENTS];
 141 };
 142
 143 /* ILT Client configuration,
 144  * Per connection type (protocol) resources (cids, tis, vf cids etc.)
 145  * 1 - for connection context (CDUC) and for each task context we need two
 146  * values, for regular task context and for force load memory
 147  */
 148 #define ILT_CLI_PF_BLOCKS       (1 + NUM_TASK_PF_SEGMENTS * 2)
 149 #define ILT_CLI_VF_BLOCKS       (1 + NUM_TASK_VF_SEGMENTS * 2)
 150 #define CDUC_BLK                (0)
 151 #define SRQ_BLK                 (0)
 152 #define CDUT_SEG_BLK(n)         (1 + (u8)(n))
 153 #define CDUT_FL_SEG_BLK(n, X)   (1 + (n) + NUM_TASK_##X##_SEGMENTS)
 154
 155 enum ilt_clients {
 156         ILT_CLI_CDUC,
 157         ILT_CLI_CDUT,
 158         ILT_CLI_QM,
 159         ILT_CLI_TM,
 160         ILT_CLI_SRC,
 161         ILT_CLI_TSDM,
 162         ILT_CLI_MAX
 163 };
 164
 165 struct ilt_cfg_pair {
 166         u32 reg;
 167         u32 val;
 168 };
 169
 170 struct ecore_ilt_cli_blk {
 171         u32 total_size; /* 0 means not active */
 172         u32 real_size_in_page;
 173         u32 start_line;
 174         u32 dynamic_line_cnt;
 175 };
 176
 177 struct ecore_ilt_client_cfg {
 178         bool                            active;
 179
 180         /* ILT boundaries */
 181         struct ilt_cfg_pair             first;
 182         struct ilt_cfg_pair             last;
 183         struct ilt_cfg_pair             p_size;
 184
 185         /* ILT client blocks for PF */
 186         struct ecore_ilt_cli_blk        pf_blks[ILT_CLI_PF_BLOCKS];
 187         u32                             pf_total_lines;
 188
 189         /* ILT client blocks for VFs */
 190         struct ecore_ilt_cli_blk        vf_blks[ILT_CLI_VF_BLOCKS];
 191         u32                             vf_total_lines;
 192 };
 193
 194 /* Per Path -
 195  *      ILT shadow table
 196  *      Protocol acquired CID lists
 197  *      PF start line in ILT
 198  */
 199 struct ecore_dma_mem {
 200         dma_addr_t      p_phys;
 201         void            *p_virt;
 202         osal_size_t     size;
 203 };
 204
 205 #define MAP_WORD_SIZE           sizeof(unsigned long)
 206 #define BITS_PER_MAP_WORD       (MAP_WORD_SIZE * 8)
 207
 208 struct ecore_cid_acquired_map {
 209         u32             start_cid;
 210         u32             max_count;
 211         unsigned long   *cid_map;
 212 };
 213
 214 struct ecore_cxt_mngr {
 215         /* Per protocl configuration */
 216         struct ecore_conn_type_cfg      conn_cfg[MAX_CONN_TYPES];
 217
 218         /* computed ILT structure */
 219         struct ecore_ilt_client_cfg     clients[ILT_CLI_MAX];
 220
 221         /* Task type sizes */
 222         u32                             task_type_size[NUM_TASK_TYPES];
 223
 224         /* total number of VFs for this hwfn -
 225          * ALL VFs are symmetric in terms of HW resources
 226          */
 227         u32                             vf_count;
 228
 229         /* Acquired CIDs */
 230         struct ecore_cid_acquired_map acquired[MAX_CONN_TYPES];
 231         /* TBD - do we want this allocated to reserve space? */
 232         struct ecore_cid_acquired_map acquired_vf[MAX_CONN_TYPES][COMMON_MAX_NUM_VFS];
 233
 234         /* ILT shadow table */
 235         struct ecore_dma_mem            *ilt_shadow;
 236         u32                             pf_start_line;
 237
 238         /* Mutex for a dynamic ILT allocation */
 239         osal_mutex_t                    mutex;
 240
 241         /* SRC T2 */
 242         struct ecore_dma_mem            *t2;
 243         u32                             t2_num_pages;
 244         u64                             first_free;
 245         u64                             last_free;
 246
 247         /* The infrastructure originally was very generic and context/task
 248          * oriented - per connection-type we would set how many of those
 249          * are needed, and later when determining how much memory we're
 250          * needing for a given block we'd iterate over all the relevant
 251          * connection-types.
 252          * But since then we've had some additional resources, some of which
 253          * require memory which is indepent of the general context/task
 254          * scheme. We add those here explicitly per-feature.
 255          */
 256
 257         /* total number of SRQ's for this hwfn */
 258         u32                             srq_count;
 259
 260         /* Maximal number of L2 steering filters */
 261         u32                             arfs_count;
 262
 263         /* TODO - VF arfs filters ? */
 264 };
 265
 266 /* check if resources/configuration is required according to protocol type */
 267 static bool src_proto(enum protocol_type type)
 268 {
 269         return  type == PROTOCOLID_ISCSI        ||
 270                 type == PROTOCOLID_FCOE         ||
 271                 type == PROTOCOLID_IWARP;
 272 }
 273
 274 static bool tm_cid_proto(enum protocol_type type)
 275 {
 276         return type == PROTOCOLID_ISCSI ||
 277                type == PROTOCOLID_FCOE  ||
 278                type == PROTOCOLID_ROCE  ||
 279                type == PROTOCOLID_IWARP;
 280 }
 281
 282 static bool tm_tid_proto(enum protocol_type type)
 283 {
 284         return type == PROTOCOLID_FCOE;
 285 }
 286
 287 /* counts the iids for the CDU/CDUC ILT client configuration */
 288 struct ecore_cdu_iids {
 289         u32 pf_cids;
 290         u32 per_vf_cids;
 291 };
 292
 293 static void ecore_cxt_cdu_iids(struct ecore_cxt_mngr   *p_mngr,
 294                                struct ecore_cdu_iids    *iids)
 295 {
 296         u32 type;
 297
 298         for (type = 0; type < MAX_CONN_TYPES; type++) {
 299                 iids->pf_cids += p_mngr->conn_cfg[type].cid_count;
 300                 iids->per_vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
 301         }
 302 }
 303
 304 /* counts the iids for the Searcher block configuration */
 305 struct ecore_src_iids {
 306         u32                     pf_cids;
 307         u32                     per_vf_cids;
 308 };
 309
 310 static void ecore_cxt_src_iids(struct ecore_cxt_mngr *p_mngr,
 311                                struct ecore_src_iids *iids)
 312 {
 313         u32 i;
 314
 315         for (i = 0; i < MAX_CONN_TYPES; i++) {
 316                 if (!src_proto(i))
 317                         continue;
 318
 319                 iids->pf_cids += p_mngr->conn_cfg[i].cid_count;
 320                 iids->per_vf_cids += p_mngr->conn_cfg[i].cids_per_vf;
 321         }
 322
 323         /* Add L2 filtering filters in addition */
 324         iids->pf_cids += p_mngr->arfs_count;
 325 }
 326
 327 /* counts the iids for the Timers block configuration */
 328 struct ecore_tm_iids {
 329         u32 pf_cids;
 330         u32 pf_tids[NUM_TASK_PF_SEGMENTS]; /* per segment */
 331         u32 pf_tids_total;
 332         u32 per_vf_cids;
 333         u32 per_vf_tids;
 334 };
 335
 336 static void ecore_cxt_tm_iids(struct ecore_cxt_mngr *p_mngr,
 337                               struct ecore_tm_iids *iids)
 338 {
 339         bool tm_vf_required = false;
 340         bool tm_required = false;
 341         int i, j;
 342
 343         /* Timers is a special case -> we don't count how many cids require
 344          * timers but what's the max cid that will be used by the timer block.
 345          * therefore we traverse in reverse order, and once we hit a protocol
 346          * that requires the timers memory, we'll sum all the protocols up
 347          * to that one.
 348          */
 349         for (i = MAX_CONN_TYPES - 1; i >= 0; i--) {
 350                 struct ecore_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[i];
 351
 352                 if (tm_cid_proto(i) || tm_required) {
 353                         if (p_cfg->cid_count)
 354                                 tm_required = true;
 355
 356                         iids->pf_cids += p_cfg->cid_count;
 357                 }
 358
 359                 if (tm_cid_proto(i) || tm_vf_required) {
 360                         if (p_cfg->cids_per_vf)
 361                                 tm_vf_required = true;
 362
 363                         iids->per_vf_cids += p_cfg->cids_per_vf;
 364                 }
 365
 366                 if (tm_tid_proto(i)) {
 367                         struct ecore_tid_seg *segs = p_cfg->tid_seg;
 368
 369                         /* for each segment there is at most one
 370                          * protocol for which count is not 0.
 371                          */
 372                         for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
 373                                 iids->pf_tids[j] += segs[j].count;
 374
 375                         /* The last array elelment is for the VFs. As for PF
 376                          * segments there can be only one protocol for
 377                          * which this value is not 0.
 378                          */
 379                         iids->per_vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
 380                 }
 381         }
 382
 383         iids->pf_cids = ROUNDUP(iids->pf_cids, TM_ALIGN);
 384         iids->per_vf_cids = ROUNDUP(iids->per_vf_cids, TM_ALIGN);
 385         iids->per_vf_tids = ROUNDUP(iids->per_vf_tids, TM_ALIGN);
 386
 387         for (iids->pf_tids_total = 0, j = 0; j < NUM_TASK_PF_SEGMENTS; j++) {
 388                 iids->pf_tids[j] = ROUNDUP(iids->pf_tids[j], TM_ALIGN);
 389                 iids->pf_tids_total += iids->pf_tids[j];
 390         }
 391 }
 392
 393 static void ecore_cxt_qm_iids(struct ecore_hwfn *p_hwfn,
 394                               struct ecore_qm_iids *iids)
 395 {
 396         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 397         struct ecore_tid_seg *segs;
 398         u32 vf_cids = 0, type, j;
 399         u32 vf_tids = 0;
 400
 401         for (type = 0; type < MAX_CONN_TYPES; type++) {
 402                 iids->cids += p_mngr->conn_cfg[type].cid_count;
 403                 vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
 404
 405                 segs = p_mngr->conn_cfg[type].tid_seg;
 406                 /* for each segment there is at most one
 407                  * protocol for which count is not 0.
 408                  */
 409                 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
 410                         iids->tids += segs[j].count;
 411
 412                 /* The last array elelment is for the VFs. As for PF
 413                  * segments there can be only one protocol for
 414                  * which this value is not 0.
 415                  */
 416                 vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
 417         }
 418
 419         iids->vf_cids += vf_cids * p_mngr->vf_count;
 420         iids->tids += vf_tids * p_mngr->vf_count;
 421
 422         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 423                    "iids: CIDS %08x vf_cids %08x tids %08x vf_tids %08x\n",
 424                    iids->cids, iids->vf_cids, iids->tids, vf_tids);
 425 }
 426
 427 static struct ecore_tid_seg *ecore_cxt_tid_seg_info(struct ecore_hwfn   *p_hwfn,
 428                                                     u32                 seg)
 429 {
 430         struct ecore_cxt_mngr *p_cfg = p_hwfn->p_cxt_mngr;
 431         u32 i;
 432
 433         /* Find the protocol with tid count > 0 for this segment.
 434            Note: there can only be one and this is already validated.
 435          */
 436         for (i = 0; i < MAX_CONN_TYPES; i++) {
 437                 if (p_cfg->conn_cfg[i].tid_seg[seg].count)
 438                         return &p_cfg->conn_cfg[i].tid_seg[seg];
 439         }
 440         return OSAL_NULL;
 441 }
 442
 443 static void ecore_cxt_set_srq_count(struct ecore_hwfn *p_hwfn, u32 num_srqs)
 444 {
 445         struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
 446
 447         p_mgr->srq_count = num_srqs;
 448 }
 449
 450 u32 ecore_cxt_get_srq_count(struct ecore_hwfn *p_hwfn)
 451 {
 452         struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
 453
 454         return p_mgr->srq_count;
 455 }
 456
 457 /* set the iids (cid/tid) count per protocol */
 458 static void ecore_cxt_set_proto_cid_count(struct ecore_hwfn *p_hwfn,
 459                                           enum protocol_type type,
 460                                           u32 cid_count, u32 vf_cid_cnt)
 461 {
 462         struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
 463         struct ecore_conn_type_cfg *p_conn = &p_mgr->conn_cfg[type];
 464
 465         p_conn->cid_count = ROUNDUP(cid_count, DQ_RANGE_ALIGN);
 466         p_conn->cids_per_vf = ROUNDUP(vf_cid_cnt, DQ_RANGE_ALIGN);
 467
 468         if (type == PROTOCOLID_ROCE) {
 469                 u32 page_sz = p_mgr->clients[ILT_CLI_CDUC].p_size.val;
 470                 u32 cxt_size = CONN_CXT_SIZE(p_hwfn);
 471                 u32 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
 472                 u32 align = elems_per_page * DQ_RANGE_ALIGN;
 473
 474                 p_conn->cid_count = ROUNDUP(p_conn->cid_count, align);
 475         }
 476 }
 477
 478 u32 ecore_cxt_get_proto_cid_count(struct ecore_hwfn     *p_hwfn,
 479                                   enum protocol_type    type,
 480                                   u32                   *vf_cid)
 481 {
 482         if (vf_cid)
 483                 *vf_cid = p_hwfn->p_cxt_mngr->conn_cfg[type].cids_per_vf;
 484
 485         return p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
 486 }
 487
 488 u32 ecore_cxt_get_proto_cid_start(struct ecore_hwfn     *p_hwfn,
 489                                   enum protocol_type    type)
 490 {
 491         return p_hwfn->p_cxt_mngr->acquired[type].start_cid;
 492 }
 493
 494 u32 ecore_cxt_get_proto_tid_count(struct ecore_hwfn *p_hwfn,
 495                                   enum protocol_type type)
 496 {
 497         u32 cnt = 0;
 498         int i;
 499
 500         for (i = 0; i < TASK_SEGMENTS; i++)
 501                 cnt += p_hwfn->p_cxt_mngr->conn_cfg[type].tid_seg[i].count;
 502
 503         return cnt;
 504 }
 505
 506 static void ecore_cxt_set_proto_tid_count(struct ecore_hwfn *p_hwfn,
 507                                           enum protocol_type proto,
 508                                           u8 seg,
 509                                           u8 seg_type,
 510                                           u32 count,
 511                                           bool has_fl)
 512 {
 513         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 514         struct ecore_tid_seg *p_seg = &p_mngr->conn_cfg[proto].tid_seg[seg];
 515
 516         p_seg->count = count;
 517         p_seg->has_fl_mem = has_fl;
 518         p_seg->type = seg_type;
 519 }
 520
 521 /* the *p_line parameter must be either 0 for the first invocation or the
 522    value returned in the previous invocation.
 523  */
 524 static void ecore_ilt_cli_blk_fill(struct ecore_ilt_client_cfg  *p_cli,
 525                                    struct ecore_ilt_cli_blk     *p_blk,
 526                                    u32                          start_line,
 527                                    u32                          total_size,
 528                                    u32                          elem_size)
 529 {
 530         u32 ilt_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val);
 531
 532         /* verify that it's called once for each block */
 533         if (p_blk->total_size)
 534                 return;
 535
 536         p_blk->total_size = total_size;
 537         p_blk->real_size_in_page = 0;
 538         if (elem_size)
 539                 p_blk->real_size_in_page = (ilt_size / elem_size) * elem_size;
 540         p_blk->start_line = start_line;
 541 }
 542
 543 static void ecore_ilt_cli_adv_line(struct ecore_hwfn            *p_hwfn,
 544                                     struct ecore_ilt_client_cfg *p_cli,
 545                                     struct ecore_ilt_cli_blk    *p_blk,
 546                                     u32                         *p_line,
 547                                     enum ilt_clients            client_id)
 548 {
 549         if (!p_blk->total_size)
 550                 return;
 551
 552         if (!p_cli->active)
 553                 p_cli->first.val = *p_line;
 554
 555         p_cli->active = true;
 556         *p_line += DIV_ROUND_UP(p_blk->total_size, p_blk->real_size_in_page);
 557         p_cli->last.val = *p_line-1;
 558
 559         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 560                    "ILT[Client %d] - Lines: [%08x - %08x]. Block - Size %08x [Real %08x] Start line %d\n",
 561                    client_id, p_cli->first.val, p_cli->last.val,
 562                    p_blk->total_size, p_blk->real_size_in_page,
 563                    p_blk->start_line);
 564 }
 565
 566 static u32 ecore_ilt_get_dynamic_line_cnt(struct ecore_hwfn *p_hwfn,
 567                                           enum ilt_clients ilt_client)
 568 {
 569         u32 cid_count = p_hwfn->p_cxt_mngr->conn_cfg[PROTOCOLID_ROCE].cid_count;
 570         struct ecore_ilt_client_cfg *p_cli;
 571         u32 lines_to_skip = 0;
 572         u32 cxts_per_p;
 573
 574         /* TBD MK: ILT code should be simplified once PROTO enum is changed */
 575
 576         if (ilt_client == ILT_CLI_CDUC) {
 577                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
 578
 579                 cxts_per_p = ILT_PAGE_IN_BYTES(p_cli->p_size.val) /
 580                              (u32)CONN_CXT_SIZE(p_hwfn);
 581
 582                 lines_to_skip = cid_count / cxts_per_p;
 583         }
 584
 585         return lines_to_skip;
 586 }
 587
 588 static struct ecore_ilt_client_cfg *
 589 ecore_cxt_set_cli(struct ecore_ilt_client_cfg *p_cli)
 590 {
 591         p_cli->active = false;
 592         p_cli->first.val = 0;
 593         p_cli->last.val = 0;
 594         return p_cli;
 595 }
 596
 597 static struct ecore_ilt_cli_blk *
 598 ecore_cxt_set_blk(struct ecore_ilt_cli_blk *p_blk)
 599 {
 600         p_blk->total_size = 0;
 601         return p_blk;
 602 }
 603
 604 enum _ecore_status_t ecore_cxt_cfg_ilt_compute(struct ecore_hwfn *p_hwfn,
 605                                                u32 *line_count)
 606 {
 607         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 608         u32 curr_line, total, i, task_size, line;
 609         struct ecore_ilt_client_cfg *p_cli;
 610         struct ecore_ilt_cli_blk *p_blk;
 611         struct ecore_cdu_iids cdu_iids;
 612         struct ecore_src_iids src_iids;
 613         struct ecore_qm_iids qm_iids;
 614         struct ecore_tm_iids tm_iids;
 615         struct ecore_tid_seg *p_seg;
 616
 617         OSAL_MEM_ZERO(&qm_iids, sizeof(qm_iids));
 618         OSAL_MEM_ZERO(&cdu_iids, sizeof(cdu_iids));
 619         OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
 620         OSAL_MEM_ZERO(&tm_iids, sizeof(tm_iids));
 621
 622         p_mngr->pf_start_line = RESC_START(p_hwfn, ECORE_ILT);
 623
 624         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 625                    "hwfn [%d] - Set context manager starting line to be 0x%08x\n",
 626                    p_hwfn->my_id, p_hwfn->p_cxt_mngr->pf_start_line);
 627
 628         /* CDUC */
 629         p_cli = ecore_cxt_set_cli(&p_mngr->clients[ILT_CLI_CDUC]);
 630
 631         curr_line = p_mngr->pf_start_line;
 632
 633         /* CDUC PF */
 634         p_cli->pf_total_lines = 0;
 635
 636         /* get the counters for the CDUC,CDUC and QM clients  */
 637         ecore_cxt_cdu_iids(p_mngr, &cdu_iids);
 638
 639         p_blk = ecore_cxt_set_blk(&p_cli->pf_blks[CDUC_BLK]);
 640
 641         total = cdu_iids.pf_cids * CONN_CXT_SIZE(p_hwfn);
 642
 643         ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 644                                total, CONN_CXT_SIZE(p_hwfn));
 645
 646         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
 647         p_cli->pf_total_lines = curr_line - p_blk->start_line;
 648
 649         p_blk->dynamic_line_cnt = ecore_ilt_get_dynamic_line_cnt(p_hwfn,
 650                                                                  ILT_CLI_CDUC);
 651
 652         /* CDUC VF */
 653         p_blk = ecore_cxt_set_blk(&p_cli->vf_blks[CDUC_BLK]);
 654         total = cdu_iids.per_vf_cids * CONN_CXT_SIZE(p_hwfn);
 655
 656         ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 657                                total, CONN_CXT_SIZE(p_hwfn));
 658
 659         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
 660         p_cli->vf_total_lines = curr_line - p_blk->start_line;
 661
 662         for (i = 1; i < p_mngr->vf_count; i++)
 663                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 664                                        ILT_CLI_CDUC);
 665
 666         /* CDUT PF */
 667         p_cli = ecore_cxt_set_cli(&p_mngr->clients[ILT_CLI_CDUT]);
 668         p_cli->first.val = curr_line;
 669
 670         /* first the 'working' task memory */
 671         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
 672                 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
 673                 if (!p_seg || p_seg->count == 0)
 674                         continue;
 675
 676                 p_blk = ecore_cxt_set_blk(&p_cli->pf_blks[CDUT_SEG_BLK(i)]);
 677                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 678                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total,
 679                                        p_mngr->task_type_size[p_seg->type]);
 680
 681                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 682                                        ILT_CLI_CDUT);
 683         }
 684
 685         /* next the 'init' task memory (forced load memory) */
 686         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
 687                 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
 688                 if (!p_seg || p_seg->count == 0)
 689                         continue;
 690
 691                 p_blk = ecore_cxt_set_blk(
 692                                 &p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)]);
 693
 694                 if (!p_seg->has_fl_mem) {
 695                         /* The segment is active (total size pf 'working'
 696                          * memory is > 0) but has no FL (forced-load, Init)
 697                          * memory. Thus:
 698                          *
 699                          * 1.   The total-size in the corrsponding FL block of
 700                          *      the ILT client is set to 0 - No ILT line are
 701                          *      provisioned and no ILT memory allocated.
 702                          *
 703                          * 2.   The start-line of said block is set to the
 704                          *      start line of the matching working memory
 705                          *      block in the ILT client. This is later used to
 706                          *      configure the CDU segment offset registers and
 707                          *      results in an FL command for TIDs of this
 708                          *      segement behaves as regular load commands
 709                          *      (loading TIDs from the working memory).
 710                          */
 711                         line = p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line;
 712
 713                         ecore_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
 714                         continue;
 715                 }
 716                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 717
 718                 ecore_ilt_cli_blk_fill(p_cli, p_blk,
 719                                        curr_line, total,
 720                                        p_mngr->task_type_size[p_seg->type]);
 721
 722                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 723                                        ILT_CLI_CDUT);
 724         }
 725         p_cli->pf_total_lines = curr_line - p_cli->pf_blks[0].start_line;
 726
 727         /* CDUT VF */
 728         p_seg = ecore_cxt_tid_seg_info(p_hwfn, TASK_SEGMENT_VF);
 729         if (p_seg && p_seg->count) {
 730                 /* Stricly speaking we need to iterate over all VF
 731                  * task segment types, but a VF has only 1 segment
 732                  */
 733
 734                 /* 'working' memory */
 735                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 736
 737                 p_blk = ecore_cxt_set_blk(&p_cli->vf_blks[CDUT_SEG_BLK(0)]);
 738                 ecore_ilt_cli_blk_fill(p_cli, p_blk,
 739                                        curr_line, total,
 740                                        p_mngr->task_type_size[p_seg->type]);
 741
 742                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 743                                        ILT_CLI_CDUT);
 744
 745                 /* 'init' memory */
 746                 p_blk = ecore_cxt_set_blk(
 747                                 &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)]);
 748                 if (!p_seg->has_fl_mem) {
 749                         /* see comment above */
 750                         line = p_cli->vf_blks[CDUT_SEG_BLK(0)].start_line;
 751                         ecore_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
 752                 } else {
 753                         task_size = p_mngr->task_type_size[p_seg->type];
 754                         ecore_ilt_cli_blk_fill(p_cli, p_blk,
 755                                                curr_line, total,
 756                                                task_size);
 757                         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 758                                                ILT_CLI_CDUT);
 759                 }
 760                 p_cli->vf_total_lines = curr_line -
 761                                         p_cli->vf_blks[0].start_line;
 762
 763                 /* Now for the rest of the VFs */
 764                 for (i = 1; i < p_mngr->vf_count; i++) {
 765                         /* don't set p_blk i.e. don't clear total_size */
 766                         p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
 767                         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 768                                                ILT_CLI_CDUT);
 769
 770                         /* don't set p_blk i.e. don't clear total_size */
 771                         p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
 772                         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 773                                                ILT_CLI_CDUT);
 774                 }
 775         }
 776
 777         /* QM */
 778         p_cli = ecore_cxt_set_cli(&p_mngr->clients[ILT_CLI_QM]);
 779         p_blk = ecore_cxt_set_blk(&p_cli->pf_blks[0]);
 780
 781         ecore_cxt_qm_iids(p_hwfn, &qm_iids);
 782         total = ecore_qm_pf_mem_size(qm_iids.cids,
 783                                      qm_iids.vf_cids, qm_iids.tids,
 784                                      p_hwfn->qm_info.num_pqs,
 785                                      p_hwfn->qm_info.num_vf_pqs);
 786
 787         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 788                    "QM ILT Info, (cids=%d, vf_cids=%d, tids=%d, num_pqs=%d, num_vf_pqs=%d, memory_size=%d)\n",
 789                    qm_iids.cids, qm_iids.vf_cids, qm_iids.tids,
 790                    p_hwfn->qm_info.num_pqs, p_hwfn->qm_info.num_vf_pqs, total);
 791
 792         ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total * 0x1000,
 793                                QM_PQ_ELEMENT_SIZE);
 794
 795         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_QM);
 796         p_cli->pf_total_lines = curr_line - p_blk->start_line;
 797
 798         /* SRC */
 799         p_cli = ecore_cxt_set_cli(&p_mngr->clients[ILT_CLI_SRC]);
 800         ecore_cxt_src_iids(p_mngr, &src_iids);
 801
 802         /* Both the PF and VFs searcher connections are stored in the per PF
 803          * database. Thus sum the PF searcher cids and all the VFs searcher
 804          * cids.
 805          */
 806         total = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
 807         if (total) {
 808                 u32 local_max = OSAL_MAX_T(u32, total,
 809                                            SRC_MIN_NUM_ELEMS);
 810
 811                 total = OSAL_ROUNDUP_POW_OF_TWO(local_max);
 812
 813                 p_blk = ecore_cxt_set_blk(&p_cli->pf_blks[0]);
 814                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 815                                        total * sizeof(struct src_ent),
 816                                        sizeof(struct src_ent));
 817
 818                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 819                                        ILT_CLI_SRC);
 820                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 821         }
 822
 823         /* TM PF */
 824         p_cli = ecore_cxt_set_cli(&p_mngr->clients[ILT_CLI_TM]);
 825         ecore_cxt_tm_iids(p_mngr, &tm_iids);
 826         total = tm_iids.pf_cids + tm_iids.pf_tids_total;
 827         if (total) {
 828                 p_blk = ecore_cxt_set_blk(&p_cli->pf_blks[0]);
 829                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 830                                        total * TM_ELEM_SIZE,
 831                                        TM_ELEM_SIZE);
 832
 833                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 834                                        ILT_CLI_TM);
 835                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 836         }
 837
 838         /* TM VF */
 839         total = tm_iids.per_vf_cids + tm_iids.per_vf_tids;
 840         if (total) {
 841                 p_blk = ecore_cxt_set_blk(&p_cli->vf_blks[0]);
 842                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 843                                        total * TM_ELEM_SIZE,
 844                                        TM_ELEM_SIZE);
 845
 846                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 847                                        ILT_CLI_TM);
 848
 849                 p_cli->vf_total_lines = curr_line - p_blk->start_line;
 850                 for (i = 1; i < p_mngr->vf_count; i++) {
 851                         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 852                                                ILT_CLI_TM);
 853                 }
 854         }
 855
 856         /* TSDM (SRQ CONTEXT) */
 857         total = ecore_cxt_get_srq_count(p_hwfn);
 858
 859         if (total) {
 860                 p_cli = ecore_cxt_set_cli(&p_mngr->clients[ILT_CLI_TSDM]);
 861                 p_blk = ecore_cxt_set_blk(&p_cli->pf_blks[SRQ_BLK]);
 862                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 863                                        total * SRQ_CXT_SIZE, SRQ_CXT_SIZE);
 864
 865                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 866                                        ILT_CLI_TSDM);
 867                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 868         }
 869
 870         *line_count = curr_line - p_hwfn->p_cxt_mngr->pf_start_line;
 871
 872         if (curr_line - p_hwfn->p_cxt_mngr->pf_start_line >
 873             RESC_NUM(p_hwfn, ECORE_ILT)) {
 874                 return ECORE_INVAL;
 875         }
 876
 877         return ECORE_SUCCESS;
 878 }
 879
 880 u32 ecore_cxt_cfg_ilt_compute_excess(struct ecore_hwfn *p_hwfn, u32 used_lines)
 881 {
 882         struct ecore_ilt_client_cfg *p_cli;
 883         u32 excess_lines, available_lines;
 884         struct ecore_cxt_mngr *p_mngr;
 885         u32 ilt_page_size, elem_size;
 886         struct ecore_tid_seg *p_seg;
 887         int i;
 888
 889         available_lines = RESC_NUM(p_hwfn, ECORE_ILT);
 890         excess_lines = used_lines - available_lines;
 891
 892         if (!excess_lines)
 893                 return 0;
 894
 895         if (!ECORE_IS_RDMA_PERSONALITY(p_hwfn))
 896                 return 0;
 897
 898         p_mngr = p_hwfn->p_cxt_mngr;
 899         p_cli = &p_mngr->clients[ILT_CLI_CDUT];
 900         ilt_page_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val);
 901
 902         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
 903                 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
 904                 if (!p_seg || p_seg->count == 0)
 905                         continue;
 906
 907                 elem_size = p_mngr->task_type_size[p_seg->type];
 908                 if (!elem_size)
 909                         continue;
 910
 911                 return (ilt_page_size / elem_size) * excess_lines;
 912         }
 913
 914         DP_ERR(p_hwfn, "failed computing excess ILT lines\n");
 915         return 0;
 916 }
 917
 918 static void ecore_cxt_src_t2_free(struct ecore_hwfn *p_hwfn)
 919 {
 920         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 921         u32 i;
 922
 923         if (!p_mngr->t2)
 924                 return;
 925
 926         for (i = 0; i < p_mngr->t2_num_pages; i++)
 927                 if (p_mngr->t2[i].p_virt)
 928                         OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
 929                                                p_mngr->t2[i].p_virt,
 930                                                p_mngr->t2[i].p_phys,
 931                                                p_mngr->t2[i].size);
 932
 933         OSAL_FREE(p_hwfn->p_dev, p_mngr->t2);
 934         p_mngr->t2 = OSAL_NULL;
 935 }
 936
 937 static enum _ecore_status_t ecore_cxt_src_t2_alloc(struct ecore_hwfn *p_hwfn)
 938 {
 939         struct ecore_cxt_mngr *p_mngr  = p_hwfn->p_cxt_mngr;
 940         u32 conn_num, total_size, ent_per_page, psz, i;
 941         struct ecore_ilt_client_cfg *p_src;
 942         struct ecore_src_iids src_iids;
 943         struct ecore_dma_mem *p_t2;
 944         enum _ecore_status_t rc;
 945
 946         OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
 947
 948         /* if the SRC ILT client is inactive - there are no connection
 949          * requiring the searcer, leave.
 950          */
 951         p_src = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_SRC];
 952         if (!p_src->active)
 953                 return ECORE_SUCCESS;
 954
 955         ecore_cxt_src_iids(p_mngr, &src_iids);
 956         conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
 957         total_size = conn_num * sizeof(struct src_ent);
 958
 959         /* use the same page size as the SRC ILT client */
 960         psz = ILT_PAGE_IN_BYTES(p_src->p_size.val);
 961         p_mngr->t2_num_pages = DIV_ROUND_UP(total_size, psz);
 962
 963         /* allocate t2 */
 964         p_mngr->t2 = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 965                                  p_mngr->t2_num_pages *
 966                                  sizeof(struct ecore_dma_mem));
 967         if (!p_mngr->t2) {
 968                 DP_NOTICE(p_hwfn, true, "Failed to allocate t2 table\n");
 969                 rc = ECORE_NOMEM;
 970                 goto t2_fail;
 971         }
 972
 973         /* allocate t2 pages */
 974         for (i = 0; i < p_mngr->t2_num_pages; i++) {
 975                 u32 size = OSAL_MIN_T(u32, total_size, psz);
 976                 void **p_virt = &p_mngr->t2[i].p_virt;
 977
 978                 *p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
 979                                                   &p_mngr->t2[i].p_phys,
 980                                                   size);
 981                 if (!p_mngr->t2[i].p_virt) {
 982                         rc = ECORE_NOMEM;
 983                         goto t2_fail;
 984                 }
 985                 OSAL_MEM_ZERO(*p_virt, size);
 986                 p_mngr->t2[i].size = size;
 987                 total_size -= size;
 988         }
 989
 990         /* Set the t2 pointers */
 991
 992         /* entries per page - must be a power of two */
 993         ent_per_page = psz / sizeof(struct src_ent);
 994
 995         p_mngr->first_free = (u64)p_mngr->t2[0].p_phys;
 996
 997         p_t2 = &p_mngr->t2[(conn_num - 1) / ent_per_page];
 998         p_mngr->last_free = (u64)p_t2->p_phys +
 999                                  ((conn_num - 1) & (ent_per_page - 1)) *
1000                                  sizeof(struct src_ent);
1001
1002         for (i = 0; i < p_mngr->t2_num_pages; i++) {
1003                 u32 ent_num = OSAL_MIN_T(u32, ent_per_page, conn_num);
1004                 struct src_ent *entries = p_mngr->t2[i].p_virt;
1005                 u64 p_ent_phys = (u64)p_mngr->t2[i].p_phys, val;
1006                 u32 j;
1007
1008                 for (j = 0; j < ent_num - 1; j++) {
1009                         val = p_ent_phys +
1010                               (j + 1) * sizeof(struct src_ent);
1011                         entries[j].next = OSAL_CPU_TO_BE64(val);
1012                 }
1013
1014                 if (i < p_mngr->t2_num_pages - 1)
1015                         val = (u64)p_mngr->t2[i + 1].p_phys;
1016                 else
1017                         val = 0;
1018                 entries[j].next = OSAL_CPU_TO_BE64(val);
1019
1020                 conn_num -= ent_num;
1021         }
1022
1023         return ECORE_SUCCESS;
1024
1025 t2_fail:
1026         ecore_cxt_src_t2_free(p_hwfn);
1027         return rc;
1028 }
1029
1030 #define for_each_ilt_valid_client(pos, clients) \
1031         for (pos = 0; pos < ILT_CLI_MAX; pos++) \
1032                 if (!clients[pos].active) {     \
1033                         continue;               \
1034                 } else                          \
1035
1036
1037 /* Total number of ILT lines used by this PF */
1038 static u32 ecore_cxt_ilt_shadow_size(struct ecore_ilt_client_cfg *ilt_clients)
1039 {
1040         u32 size = 0;
1041         u32 i;
1042
1043         for_each_ilt_valid_client(i, ilt_clients)
1044                 size += (ilt_clients[i].last.val -
1045                          ilt_clients[i].first.val + 1);
1046
1047         return size;
1048 }
1049
1050 static void ecore_ilt_shadow_free(struct ecore_hwfn *p_hwfn)
1051 {
1052         struct ecore_ilt_client_cfg *p_cli = p_hwfn->p_cxt_mngr->clients;
1053         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1054         u32 ilt_size, i;
1055
1056         ilt_size = ecore_cxt_ilt_shadow_size(p_cli);
1057
1058         for (i = 0; p_mngr->ilt_shadow && i < ilt_size; i++) {
1059                 struct ecore_dma_mem *p_dma = &p_mngr->ilt_shadow[i];
1060
1061                 if (p_dma->p_virt)
1062                         OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
1063                                                p_dma->p_virt,
1064                                                p_dma->p_phys,
1065                                                p_dma->size);
1066                 p_dma->p_virt = OSAL_NULL;
1067         }
1068         OSAL_FREE(p_hwfn->p_dev, p_mngr->ilt_shadow);
1069 }
1070
1071 static enum _ecore_status_t ecore_ilt_blk_alloc(struct ecore_hwfn *p_hwfn,
1072                                                 struct ecore_ilt_cli_blk *p_blk,
1073                                                 enum ilt_clients ilt_client,
1074                                                 u32 start_line_offset)
1075 {
1076         struct ecore_dma_mem *ilt_shadow = p_hwfn->p_cxt_mngr->ilt_shadow;
1077         u32 lines, line, sz_left, lines_to_skip = 0;
1078
1079         /* Special handling for RoCE that supports dynamic allocation */
1080         if (ECORE_IS_RDMA_PERSONALITY(p_hwfn) &&
1081             ((ilt_client == ILT_CLI_CDUT) || ilt_client == ILT_CLI_TSDM))
1082                 return ECORE_SUCCESS;
1083
1084         lines_to_skip = p_blk->dynamic_line_cnt;
1085
1086         if (!p_blk->total_size)
1087                 return ECORE_SUCCESS;
1088
1089         sz_left = p_blk->total_size;
1090         lines = DIV_ROUND_UP(sz_left, p_blk->real_size_in_page) -
1091                 lines_to_skip;
1092         line = p_blk->start_line + start_line_offset -
1093                p_hwfn->p_cxt_mngr->pf_start_line + lines_to_skip;
1094
1095         for (; lines; lines--) {
1096                 dma_addr_t p_phys;
1097                 void *p_virt;
1098                 u32 size;
1099
1100                 size = OSAL_MIN_T(u32, sz_left, p_blk->real_size_in_page);
1101                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
1102                                                  &p_phys, size);
1103                 if (!p_virt)
1104                         return ECORE_NOMEM;
1105                 OSAL_MEM_ZERO(p_virt, size);
1106
1107                 ilt_shadow[line].p_phys = p_phys;
1108                 ilt_shadow[line].p_virt = p_virt;
1109                 ilt_shadow[line].size = size;
1110
1111                 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
1112                            "ILT shadow: Line [%d] Physical 0x%llx Virtual %p Size %d\n",
1113                            line, (unsigned long long)p_phys, p_virt, size);
1114
1115                 sz_left -= size;
1116                 line++;
1117         }
1118
1119         return ECORE_SUCCESS;
1120 }
1121
1122 static enum _ecore_status_t ecore_ilt_shadow_alloc(struct ecore_hwfn *p_hwfn)
1123 {
1124         struct ecore_cxt_mngr *p_mngr  = p_hwfn->p_cxt_mngr;
1125         struct ecore_ilt_client_cfg *clients = p_mngr->clients;
1126         struct ecore_ilt_cli_blk *p_blk;
1127         u32 size, i, j, k;
1128         enum _ecore_status_t rc;
1129
1130         size = ecore_cxt_ilt_shadow_size(clients);
1131         p_mngr->ilt_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1132                                          size * sizeof(struct ecore_dma_mem));
1133
1134         if (!p_mngr->ilt_shadow) {
1135                 DP_NOTICE(p_hwfn, true, "Failed to allocate ilt shadow table\n");
1136                 rc = ECORE_NOMEM;
1137                 goto ilt_shadow_fail;
1138         }
1139
1140         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
1141                    "Allocated 0x%x bytes for ilt shadow\n",
1142                    (u32)(size * sizeof(struct ecore_dma_mem)));
1143
1144         for_each_ilt_valid_client(i, clients) {
1145                 for (j = 0; j < ILT_CLI_PF_BLOCKS; j++) {
1146                         p_blk = &clients[i].pf_blks[j];
1147                         rc = ecore_ilt_blk_alloc(p_hwfn, p_blk, i, 0);
1148                         if (rc != ECORE_SUCCESS)
1149                                 goto ilt_shadow_fail;
1150                 }
1151                 for (k = 0; k < p_mngr->vf_count; k++) {
1152                         for (j = 0; j < ILT_CLI_VF_BLOCKS; j++) {
1153                                 u32 lines = clients[i].vf_total_lines * k;
1154
1155                                 p_blk = &clients[i].vf_blks[j];
1156                                 rc = ecore_ilt_blk_alloc(p_hwfn, p_blk,
1157                                                          i, lines);
1158                                 if (rc != ECORE_SUCCESS)
1159                                         goto ilt_shadow_fail;
1160                         }
1161                 }
1162         }
1163
1164         return ECORE_SUCCESS;
1165
1166 ilt_shadow_fail:
1167         ecore_ilt_shadow_free(p_hwfn);
1168         return rc;
1169 }
1170
1171 static void ecore_cid_map_free(struct ecore_hwfn *p_hwfn)
1172 {
1173         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1174         u32 type, vf;
1175
1176         for (type = 0; type < MAX_CONN_TYPES; type++) {
1177                 OSAL_FREE(p_hwfn->p_dev, p_mngr->acquired[type].cid_map);
1178                 p_mngr->acquired[type].max_count = 0;
1179                 p_mngr->acquired[type].start_cid = 0;
1180
1181                 for (vf = 0; vf < COMMON_MAX_NUM_VFS; vf++) {
1182                         OSAL_FREE(p_hwfn->p_dev,
1183                                   p_mngr->acquired_vf[type][vf].cid_map);
1184                         p_mngr->acquired_vf[type][vf].max_count = 0;
1185                         p_mngr->acquired_vf[type][vf].start_cid = 0;
1186                 }
1187         }
1188 }
1189
1190 static enum _ecore_status_t
1191 ecore_cid_map_alloc_single(struct ecore_hwfn *p_hwfn, u32 type,
1192                            u32 cid_start, u32 cid_count,
1193                            struct ecore_cid_acquired_map *p_map)
1194 {
1195         u32 size;
1196
1197         if (!cid_count)
1198                 return ECORE_SUCCESS;
1199
1200         size = MAP_WORD_SIZE * DIV_ROUND_UP(cid_count, BITS_PER_MAP_WORD);
1201         p_map->cid_map = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
1202         if (p_map->cid_map == OSAL_NULL)
1203                 return ECORE_NOMEM;
1204
1205         p_map->max_count = cid_count;
1206         p_map->start_cid = cid_start;
1207
1208         DP_VERBOSE(p_hwfn, ECORE_MSG_CXT,
1209                    "Type %08x start: %08x count %08x\n",
1210                    type, p_map->start_cid, p_map->max_count);
1211
1212         return ECORE_SUCCESS;
1213 }
1214
1215 static enum _ecore_status_t ecore_cid_map_alloc(struct ecore_hwfn *p_hwfn)
1216 {
1217         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1218         u32 start_cid = 0, vf_start_cid = 0;
1219         u32 type, vf;
1220
1221         for (type = 0; type < MAX_CONN_TYPES; type++) {
1222                 struct ecore_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[type];
1223                 struct ecore_cid_acquired_map *p_map;
1224
1225                 /* Handle PF maps */
1226                 p_map = &p_mngr->acquired[type];
1227                 if (ecore_cid_map_alloc_single(p_hwfn, type, start_cid,
1228                                                p_cfg->cid_count, p_map))
1229                         goto cid_map_fail;
1230
1231                 /* Handle VF maps */
1232                 for (vf = 0; vf < COMMON_MAX_NUM_VFS; vf++) {
1233                         p_map = &p_mngr->acquired_vf[type][vf];
1234                         if (ecore_cid_map_alloc_single(p_hwfn, type,
1235                                                        vf_start_cid,
1236                                                        p_cfg->cids_per_vf,
1237                                                        p_map))
1238                                 goto cid_map_fail;
1239                 }
1240
1241                 start_cid += p_cfg->cid_count;
1242                 vf_start_cid += p_cfg->cids_per_vf;
1243         }
1244
1245         return ECORE_SUCCESS;
1246
1247 cid_map_fail:
1248         ecore_cid_map_free(p_hwfn);
1249         return ECORE_NOMEM;
1250 }
1251
1252 enum _ecore_status_t ecore_cxt_mngr_alloc(struct ecore_hwfn *p_hwfn)
1253 {
1254         struct ecore_ilt_client_cfg *clients;
1255         struct ecore_cxt_mngr *p_mngr;
1256         u32 i;
1257
1258         p_mngr = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*p_mngr));
1259         if (!p_mngr) {
1260                 DP_NOTICE(p_hwfn, true, "Failed to allocate `struct ecore_cxt_mngr'\n");
1261                 return ECORE_NOMEM;
1262         }
1263
1264         /* Initialize ILT client registers */
1265         clients = p_mngr->clients;
1266         clients[ILT_CLI_CDUC].first.reg = ILT_CFG_REG(CDUC, FIRST_ILT);
1267         clients[ILT_CLI_CDUC].last.reg  = ILT_CFG_REG(CDUC, LAST_ILT);
1268         clients[ILT_CLI_CDUC].p_size.reg = ILT_CFG_REG(CDUC, P_SIZE);
1269
1270         clients[ILT_CLI_QM].first.reg   = ILT_CFG_REG(QM, FIRST_ILT);
1271         clients[ILT_CLI_QM].last.reg    = ILT_CFG_REG(QM, LAST_ILT);
1272         clients[ILT_CLI_QM].p_size.reg  = ILT_CFG_REG(QM, P_SIZE);
1273
1274         clients[ILT_CLI_TM].first.reg   = ILT_CFG_REG(TM, FIRST_ILT);
1275         clients[ILT_CLI_TM].last.reg    = ILT_CFG_REG(TM, LAST_ILT);
1276         clients[ILT_CLI_TM].p_size.reg  = ILT_CFG_REG(TM, P_SIZE);
1277
1278         clients[ILT_CLI_SRC].first.reg  = ILT_CFG_REG(SRC, FIRST_ILT);
1279         clients[ILT_CLI_SRC].last.reg   = ILT_CFG_REG(SRC, LAST_ILT);
1280         clients[ILT_CLI_SRC].p_size.reg = ILT_CFG_REG(SRC, P_SIZE);
1281
1282         clients[ILT_CLI_CDUT].first.reg = ILT_CFG_REG(CDUT, FIRST_ILT);
1283         clients[ILT_CLI_CDUT].last.reg  = ILT_CFG_REG(CDUT, LAST_ILT);
1284         clients[ILT_CLI_CDUT].p_size.reg = ILT_CFG_REG(CDUT, P_SIZE);
1285
1286         clients[ILT_CLI_TSDM].first.reg = ILT_CFG_REG(TSDM, FIRST_ILT);
1287         clients[ILT_CLI_TSDM].last.reg  = ILT_CFG_REG(TSDM, LAST_ILT);
1288         clients[ILT_CLI_TSDM].p_size.reg = ILT_CFG_REG(TSDM, P_SIZE);
1289
1290         /* default ILT page size for all clients is 64K */
1291         for (i = 0; i < ILT_CLI_MAX; i++)
1292                 p_mngr->clients[i].p_size.val = ILT_DEFAULT_HW_P_SIZE;
1293
1294         /* Initialize task sizes */
1295         p_mngr->task_type_size[0] = TYPE0_TASK_CXT_SIZE(p_hwfn);
1296         p_mngr->task_type_size[1] = TYPE1_TASK_CXT_SIZE(p_hwfn);
1297
1298         if (p_hwfn->p_dev->p_iov_info)
1299                 p_mngr->vf_count = p_hwfn->p_dev->p_iov_info->total_vfs;
1300
1301         /* Initialize the dynamic ILT allocation mutex */
1302 #ifdef CONFIG_ECORE_LOCK_ALLOC
1303         OSAL_MUTEX_ALLOC(p_hwfn, &p_mngr->mutex);
1304 #endif
1305         OSAL_MUTEX_INIT(&p_mngr->mutex);
1306
1307         /* Set the cxt mangr pointer priori to further allocations */
1308         p_hwfn->p_cxt_mngr = p_mngr;
1309
1310         return ECORE_SUCCESS;
1311 }
1312
1313 enum _ecore_status_t ecore_cxt_tables_alloc(struct ecore_hwfn *p_hwfn)
1314 {
1315         enum _ecore_status_t    rc;
1316
1317         /* Allocate the ILT shadow table */
1318         rc = ecore_ilt_shadow_alloc(p_hwfn);
1319         if (rc) {
1320                 DP_NOTICE(p_hwfn, true, "Failed to allocate ilt memory\n");
1321                 goto tables_alloc_fail;
1322         }
1323
1324         /* Allocate the T2  table */
1325         rc = ecore_cxt_src_t2_alloc(p_hwfn);
1326         if (rc) {
1327                 DP_NOTICE(p_hwfn, true, "Failed to allocate T2 memory\n");
1328                 goto tables_alloc_fail;
1329         }
1330
1331         /* Allocate and initialize the acquired cids bitmaps */
1332         rc = ecore_cid_map_alloc(p_hwfn);
1333         if (rc) {
1334                 DP_NOTICE(p_hwfn, true, "Failed to allocate cid maps\n");
1335                 goto tables_alloc_fail;
1336         }
1337
1338         return ECORE_SUCCESS;
1339
1340 tables_alloc_fail:
1341         ecore_cxt_mngr_free(p_hwfn);
1342         return rc;
1343 }
1344 void ecore_cxt_mngr_free(struct ecore_hwfn *p_hwfn)
1345 {
1346         if (!p_hwfn->p_cxt_mngr)
1347                 return;
1348
1349         ecore_cid_map_free(p_hwfn);
1350         ecore_cxt_src_t2_free(p_hwfn);
1351         ecore_ilt_shadow_free(p_hwfn);
1352 #ifdef CONFIG_ECORE_LOCK_ALLOC
1353         OSAL_MUTEX_DEALLOC(&p_hwfn->p_cxt_mngr->mutex);
1354 #endif
1355         OSAL_FREE(p_hwfn->p_dev, p_hwfn->p_cxt_mngr);
1356
1357         p_hwfn->p_cxt_mngr = OSAL_NULL;
1358 }
1359
1360 void ecore_cxt_mngr_setup(struct ecore_hwfn *p_hwfn)
1361 {
1362         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1363         struct ecore_cid_acquired_map *p_map;
1364         struct ecore_conn_type_cfg *p_cfg;
1365         int type;
1366         u32 len;
1367
1368         /* Reset acquired cids */
1369         for (type = 0; type < MAX_CONN_TYPES; type++) {
1370                 u32 vf;
1371
1372                 p_cfg = &p_mngr->conn_cfg[type];
1373                 if (p_cfg->cid_count) {
1374                         p_map = &p_mngr->acquired[type];
1375                         len = DIV_ROUND_UP(p_map->max_count,
1376                                            BITS_PER_MAP_WORD) *
1377                               MAP_WORD_SIZE;
1378                         OSAL_MEM_ZERO(p_map->cid_map, len);
1379                 }
1380
1381                 if (!p_cfg->cids_per_vf)
1382                         continue;
1383
1384                 for (vf = 0; vf < COMMON_MAX_NUM_VFS; vf++) {
1385                         p_map = &p_mngr->acquired_vf[type][vf];
1386                         len = DIV_ROUND_UP(p_map->max_count,
1387                                            BITS_PER_MAP_WORD) *
1388                               MAP_WORD_SIZE;
1389                         OSAL_MEM_ZERO(p_map->cid_map, len);
1390                 }
1391         }
1392 }
1393
1394 /* HW initialization helper (per Block, per phase) */
1395
1396 /* CDU Common */
1397 #define CDUC_CXT_SIZE_SHIFT                                             \
1398         CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT
1399
1400 #define CDUC_CXT_SIZE_MASK                                              \
1401         (CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE >> CDUC_CXT_SIZE_SHIFT)
1402
1403 #define CDUC_BLOCK_WASTE_SHIFT                                          \
1404         CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT
1405
1406 #define CDUC_BLOCK_WASTE_MASK                                           \
1407         (CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE >> CDUC_BLOCK_WASTE_SHIFT)
1408
1409 #define CDUC_NCIB_SHIFT                                                 \
1410         CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT
1411
1412 #define CDUC_NCIB_MASK                                                  \
1413         (CDU_REG_CID_ADDR_PARAMS_NCIB >> CDUC_NCIB_SHIFT)
1414
1415 #define CDUT_TYPE0_CXT_SIZE_SHIFT                                       \
1416         CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT
1417
1418 #define CDUT_TYPE0_CXT_SIZE_MASK                                        \
1419         (CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE >>                         \
1420         CDUT_TYPE0_CXT_SIZE_SHIFT)
1421
1422 #define CDUT_TYPE0_BLOCK_WASTE_SHIFT                                    \
1423         CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT
1424
1425 #define CDUT_TYPE0_BLOCK_WASTE_MASK                                     \
1426         (CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE >>                  \
1427         CDUT_TYPE0_BLOCK_WASTE_SHIFT)
1428
1429 #define CDUT_TYPE0_NCIB_SHIFT                                           \
1430         CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT
1431
1432 #define CDUT_TYPE0_NCIB_MASK                                            \
1433         (CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK >>                \
1434         CDUT_TYPE0_NCIB_SHIFT)
1435
1436 #define CDUT_TYPE1_CXT_SIZE_SHIFT                                       \
1437         CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT
1438
1439 #define CDUT_TYPE1_CXT_SIZE_MASK                                        \
1440         (CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE >>                         \
1441         CDUT_TYPE1_CXT_SIZE_SHIFT)
1442
1443 #define CDUT_TYPE1_BLOCK_WASTE_SHIFT                                    \
1444         CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT
1445
1446 #define CDUT_TYPE1_BLOCK_WASTE_MASK                                     \
1447         (CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE >>                  \
1448         CDUT_TYPE1_BLOCK_WASTE_SHIFT)
1449
1450 #define CDUT_TYPE1_NCIB_SHIFT                                           \
1451         CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT
1452
1453 #define CDUT_TYPE1_NCIB_MASK                                            \
1454         (CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK >>                \
1455         CDUT_TYPE1_NCIB_SHIFT)
1456
1457 static void ecore_cdu_init_common(struct ecore_hwfn *p_hwfn)
1458 {
1459         u32 page_sz, elems_per_page, block_waste,  cxt_size, cdu_params = 0;
1460
1461         /* CDUC - connection configuration */
1462         page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1463         cxt_size = CONN_CXT_SIZE(p_hwfn);
1464         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1465         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1466
1467         SET_FIELD(cdu_params, CDUC_CXT_SIZE, cxt_size);
1468         SET_FIELD(cdu_params, CDUC_BLOCK_WASTE, block_waste);
1469         SET_FIELD(cdu_params, (u32)CDUC_NCIB, elems_per_page);
1470         STORE_RT_REG(p_hwfn, CDU_REG_CID_ADDR_PARAMS_RT_OFFSET, cdu_params);
1471
1472         /* CDUT - type-0 tasks configuration */
1473         page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT].p_size.val;
1474         cxt_size = p_hwfn->p_cxt_mngr->task_type_size[0];
1475         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1476         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1477
1478         /* cxt size and block-waste are multipes of 8 */
1479         cdu_params = 0;
1480         SET_FIELD(cdu_params, (u32)CDUT_TYPE0_CXT_SIZE, (cxt_size >> 3));
1481         SET_FIELD(cdu_params, CDUT_TYPE0_BLOCK_WASTE, (block_waste >> 3));
1482         SET_FIELD(cdu_params, CDUT_TYPE0_NCIB, elems_per_page);
1483         STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT0_PARAMS_RT_OFFSET, cdu_params);
1484
1485         /* CDUT - type-1 tasks configuration */
1486         cxt_size = p_hwfn->p_cxt_mngr->task_type_size[1];
1487         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1488         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1489
1490         /* cxt size and block-waste are multipes of 8 */
1491         cdu_params = 0;
1492         SET_FIELD(cdu_params, (u32)CDUT_TYPE1_CXT_SIZE, (cxt_size >> 3));
1493         SET_FIELD(cdu_params, CDUT_TYPE1_BLOCK_WASTE, (block_waste >> 3));
1494         SET_FIELD(cdu_params, CDUT_TYPE1_NCIB, elems_per_page);
1495         STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT1_PARAMS_RT_OFFSET, cdu_params);
1496 }
1497
1498 /* CDU PF */
1499 #define CDU_SEG_REG_TYPE_SHIFT          CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT
1500 #define CDU_SEG_REG_TYPE_MASK           0x1
1501 #define CDU_SEG_REG_OFFSET_SHIFT        0
1502 #define CDU_SEG_REG_OFFSET_MASK         CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK
1503
1504 static void ecore_cdu_init_pf(struct ecore_hwfn *p_hwfn)
1505 {
1506         struct ecore_ilt_client_cfg *p_cli;
1507         struct ecore_tid_seg *p_seg;
1508         u32 cdu_seg_params, offset;
1509         int i;
1510
1511         static const u32 rt_type_offset_arr[] = {
1512                 CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET,
1513                 CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET,
1514                 CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET,
1515                 CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET
1516         };
1517
1518         static const u32 rt_type_offset_fl_arr[] = {
1519                 CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET,
1520                 CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET,
1521                 CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET,
1522                 CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET
1523         };
1524
1525         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1526
1527         /* There are initializations only for CDUT during pf Phase */
1528         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1529                 /* Segment 0*/
1530                 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
1531                 if (!p_seg)
1532                         continue;
1533
1534                 /* Note: start_line is already adjusted for the CDU
1535                  * segment register granularity, so we just need to
1536                  * divide. Adjustment is implicit as we assume ILT
1537                  * Page size is larger than 32K!
1538                  */
1539                 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1540                          (p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line -
1541                           p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1542
1543                 cdu_seg_params = 0;
1544                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1545                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1546                 STORE_RT_REG(p_hwfn, rt_type_offset_arr[i],
1547                              cdu_seg_params);
1548
1549                 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1550                          (p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)].start_line -
1551                           p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1552
1553                 cdu_seg_params = 0;
1554                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1555                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1556                 STORE_RT_REG(p_hwfn, rt_type_offset_fl_arr[i],
1557                              cdu_seg_params);
1558
1559         }
1560 }
1561
1562 void ecore_qm_init_pf(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1563 {
1564         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1565         struct ecore_qm_iids iids;
1566
1567         OSAL_MEM_ZERO(&iids, sizeof(iids));
1568         ecore_cxt_qm_iids(p_hwfn, &iids);
1569
1570         ecore_qm_pf_rt_init(p_hwfn, p_ptt, p_hwfn->port_id,
1571                             p_hwfn->rel_pf_id, qm_info->max_phys_tcs_per_port,
1572                             iids.cids, iids.vf_cids, iids.tids,
1573                             qm_info->start_pq,
1574                             qm_info->num_pqs - qm_info->num_vf_pqs,
1575                             qm_info->num_vf_pqs,
1576                             qm_info->start_vport,
1577                             qm_info->num_vports, qm_info->pf_wfq, qm_info->pf_rl,
1578                             p_hwfn->qm_info.qm_pq_params,
1579                             p_hwfn->qm_info.qm_vport_params);
1580 }
1581
1582 /* CM PF */
1583 static void ecore_cm_init_pf(struct ecore_hwfn *p_hwfn)
1584 {
1585         STORE_RT_REG(p_hwfn, XCM_REG_CON_PHY_Q3_RT_OFFSET, ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LB));
1586 }
1587
1588 /* DQ PF */
1589 static void ecore_dq_init_pf(struct ecore_hwfn *p_hwfn)
1590 {
1591         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1592         u32 dq_pf_max_cid = 0, dq_vf_max_cid = 0;
1593
1594         dq_pf_max_cid += (p_mngr->conn_cfg[0].cid_count >> DQ_RANGE_SHIFT);
1595         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_0_RT_OFFSET, dq_pf_max_cid);
1596
1597         dq_vf_max_cid += (p_mngr->conn_cfg[0].cids_per_vf >> DQ_RANGE_SHIFT);
1598         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_0_RT_OFFSET, dq_vf_max_cid);
1599
1600         dq_pf_max_cid += (p_mngr->conn_cfg[1].cid_count >> DQ_RANGE_SHIFT);
1601         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_1_RT_OFFSET, dq_pf_max_cid);
1602
1603         dq_vf_max_cid += (p_mngr->conn_cfg[1].cids_per_vf >> DQ_RANGE_SHIFT);
1604         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_1_RT_OFFSET, dq_vf_max_cid);
1605
1606         dq_pf_max_cid += (p_mngr->conn_cfg[2].cid_count >> DQ_RANGE_SHIFT);
1607         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_2_RT_OFFSET, dq_pf_max_cid);
1608
1609         dq_vf_max_cid += (p_mngr->conn_cfg[2].cids_per_vf >> DQ_RANGE_SHIFT);
1610         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_2_RT_OFFSET, dq_vf_max_cid);
1611
1612         dq_pf_max_cid += (p_mngr->conn_cfg[3].cid_count >> DQ_RANGE_SHIFT);
1613         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_3_RT_OFFSET, dq_pf_max_cid);
1614
1615         dq_vf_max_cid += (p_mngr->conn_cfg[3].cids_per_vf >> DQ_RANGE_SHIFT);
1616         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_3_RT_OFFSET, dq_vf_max_cid);
1617
1618         dq_pf_max_cid += (p_mngr->conn_cfg[4].cid_count >> DQ_RANGE_SHIFT);
1619         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_4_RT_OFFSET, dq_pf_max_cid);
1620
1621         dq_vf_max_cid += (p_mngr->conn_cfg[4].cids_per_vf >> DQ_RANGE_SHIFT);
1622         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_4_RT_OFFSET, dq_vf_max_cid);
1623
1624         dq_pf_max_cid += (p_mngr->conn_cfg[5].cid_count >> DQ_RANGE_SHIFT);
1625         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_5_RT_OFFSET, dq_pf_max_cid);
1626
1627         dq_vf_max_cid += (p_mngr->conn_cfg[5].cids_per_vf >> DQ_RANGE_SHIFT);
1628         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_5_RT_OFFSET, dq_vf_max_cid);
1629
1630         /* Connection types 6 & 7 are not in use, yet they must be configured
1631          * as the highest possible connection. Not configuring them means the
1632          * defaults will be  used, and with a large number of cids a bug may
1633          * occur, if the defaults will be smaller than dq_pf_max_cid /
1634          * dq_vf_max_cid.
1635          */
1636         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_6_RT_OFFSET, dq_pf_max_cid);
1637         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_6_RT_OFFSET, dq_vf_max_cid);
1638
1639         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_7_RT_OFFSET, dq_pf_max_cid);
1640         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_7_RT_OFFSET, dq_vf_max_cid);
1641 }
1642
1643 static void ecore_ilt_bounds_init(struct ecore_hwfn *p_hwfn)
1644 {
1645         struct ecore_ilt_client_cfg *ilt_clients;
1646         int i;
1647
1648         ilt_clients = p_hwfn->p_cxt_mngr->clients;
1649         for_each_ilt_valid_client(i, ilt_clients) {
1650                 STORE_RT_REG(p_hwfn,
1651                              ilt_clients[i].first.reg,
1652                              ilt_clients[i].first.val);
1653                 STORE_RT_REG(p_hwfn,
1654                              ilt_clients[i].last.reg,
1655                              ilt_clients[i].last.val);
1656                 STORE_RT_REG(p_hwfn,
1657                              ilt_clients[i].p_size.reg,
1658                              ilt_clients[i].p_size.val);
1659         }
1660 }
1661
1662 static void ecore_ilt_vf_bounds_init(struct ecore_hwfn *p_hwfn)
1663 {
1664         struct ecore_ilt_client_cfg *p_cli;
1665         u32 blk_factor;
1666
1667         /* For simplicty  we set the 'block' to be an ILT page */
1668         if (p_hwfn->p_dev->p_iov_info) {
1669                 struct ecore_hw_sriov_info *p_iov = p_hwfn->p_dev->p_iov_info;
1670
1671                 STORE_RT_REG(p_hwfn,
1672                              PSWRQ2_REG_VF_BASE_RT_OFFSET,
1673                              p_iov->first_vf_in_pf);
1674                 STORE_RT_REG(p_hwfn,
1675                              PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET,
1676                              p_iov->first_vf_in_pf + p_iov->total_vfs);
1677         }
1678
1679         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
1680         blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1681         if (p_cli->active) {
1682                 STORE_RT_REG(p_hwfn,
1683                              PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET,
1684                              blk_factor);
1685                 STORE_RT_REG(p_hwfn,
1686                              PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1687                              p_cli->pf_total_lines);
1688                 STORE_RT_REG(p_hwfn,
1689                              PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET,
1690                              p_cli->vf_total_lines);
1691         }
1692
1693         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1694         blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1695         if (p_cli->active) {
1696                 STORE_RT_REG(p_hwfn,
1697                              PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET,
1698                              blk_factor);
1699                 STORE_RT_REG(p_hwfn,
1700                              PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1701                              p_cli->pf_total_lines);
1702                 STORE_RT_REG(p_hwfn,
1703                              PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET,
1704                              p_cli->vf_total_lines);
1705         }
1706
1707         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TM];
1708         blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1709         if (p_cli->active) {
1710                 STORE_RT_REG(p_hwfn,
1711                              PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET,
1712                              blk_factor);
1713                 STORE_RT_REG(p_hwfn,
1714                              PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1715                              p_cli->pf_total_lines);
1716                 STORE_RT_REG(p_hwfn,
1717                              PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET,
1718                              p_cli->vf_total_lines);
1719         }
1720 }
1721
1722 /* ILT (PSWRQ2) PF */
1723 static void ecore_ilt_init_pf(struct ecore_hwfn *p_hwfn)
1724 {
1725         struct ecore_ilt_client_cfg *clients;
1726         struct ecore_cxt_mngr *p_mngr;
1727         struct ecore_dma_mem *p_shdw;
1728         u32 line, rt_offst, i;
1729
1730         ecore_ilt_bounds_init(p_hwfn);
1731         ecore_ilt_vf_bounds_init(p_hwfn);
1732
1733         p_mngr  = p_hwfn->p_cxt_mngr;
1734         p_shdw  = p_mngr->ilt_shadow;
1735         clients = p_hwfn->p_cxt_mngr->clients;
1736
1737         for_each_ilt_valid_client(i, clients) {
1738                 /* Client's 1st val and RT array are absolute, ILT shadows'
1739                  * lines are relative.
1740                  */
1741                 line = clients[i].first.val - p_mngr->pf_start_line;
1742                 rt_offst = PSWRQ2_REG_ILT_MEMORY_RT_OFFSET +
1743                            clients[i].first.val * ILT_ENTRY_IN_REGS;
1744
1745                 for (; line <= clients[i].last.val - p_mngr->pf_start_line;
1746                      line++, rt_offst += ILT_ENTRY_IN_REGS) {
1747                         u64 ilt_hw_entry = 0;
1748
1749                         /** p_virt could be OSAL_NULL incase of dynamic
1750                          *  allocation
1751                          */
1752                         if (p_shdw[line].p_virt != OSAL_NULL) {
1753                                 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
1754                                 SET_FIELD(ilt_hw_entry, ILT_ENTRY_PHY_ADDR,
1755                                          (unsigned long long)(p_shdw[line].p_phys >> 12));
1756
1757                                 DP_VERBOSE(
1758                                         p_hwfn, ECORE_MSG_ILT,
1759                                         "Setting RT[0x%08x] from ILT[0x%08x] [Client is %d] to Physical addr: 0x%llx\n",
1760                                         rt_offst, line, i,
1761                                         (unsigned long long)(p_shdw[line].p_phys >> 12));
1762                         }
1763
1764                         STORE_RT_REG_AGG(p_hwfn, rt_offst, ilt_hw_entry);
1765                 }
1766         }
1767 }
1768
1769 /* SRC (Searcher) PF */
1770 static void ecore_src_init_pf(struct ecore_hwfn *p_hwfn)
1771 {
1772         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1773         u32 rounded_conn_num, conn_num, conn_max;
1774         struct ecore_src_iids src_iids;
1775
1776         OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
1777         ecore_cxt_src_iids(p_mngr, &src_iids);
1778         conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
1779         if (!conn_num)
1780                 return;
1781
1782         conn_max = OSAL_MAX_T(u32, conn_num, SRC_MIN_NUM_ELEMS);
1783         rounded_conn_num = OSAL_ROUNDUP_POW_OF_TWO(conn_max);
1784
1785         STORE_RT_REG(p_hwfn, SRC_REG_COUNTFREE_RT_OFFSET, conn_num);
1786         STORE_RT_REG(p_hwfn, SRC_REG_NUMBER_HASH_BITS_RT_OFFSET,
1787                      OSAL_LOG2(rounded_conn_num));
1788
1789         STORE_RT_REG_AGG(p_hwfn, SRC_REG_FIRSTFREE_RT_OFFSET,
1790                          p_hwfn->p_cxt_mngr->first_free);
1791         STORE_RT_REG_AGG(p_hwfn, SRC_REG_LASTFREE_RT_OFFSET,
1792                          p_hwfn->p_cxt_mngr->last_free);
1793         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
1794                    "Configured SEARCHER for 0x%08x connections\n",
1795                    conn_num);
1796 }
1797
1798 /* Timers PF */
1799 #define TM_CFG_NUM_IDS_SHIFT            0
1800 #define TM_CFG_NUM_IDS_MASK             0xFFFFULL
1801 #define TM_CFG_PRE_SCAN_OFFSET_SHIFT    16
1802 #define TM_CFG_PRE_SCAN_OFFSET_MASK     0x1FFULL
1803 #define TM_CFG_PARENT_PF_SHIFT          25
1804 #define TM_CFG_PARENT_PF_MASK           0x7ULL
1805
1806 #define TM_CFG_CID_PRE_SCAN_ROWS_SHIFT  30
1807 #define TM_CFG_CID_PRE_SCAN_ROWS_MASK   0x1FFULL
1808
1809 #define TM_CFG_TID_OFFSET_SHIFT         30
1810 #define TM_CFG_TID_OFFSET_MASK          0x7FFFFULL
1811 #define TM_CFG_TID_PRE_SCAN_ROWS_SHIFT  49
1812 #define TM_CFG_TID_PRE_SCAN_ROWS_MASK   0x1FFULL
1813
1814 static void ecore_tm_init_pf(struct ecore_hwfn *p_hwfn)
1815 {
1816         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1817         u32 active_seg_mask = 0, tm_offset, rt_reg;
1818         struct ecore_tm_iids tm_iids;
1819         u64 cfg_word;
1820         u8 i;
1821
1822         OSAL_MEM_ZERO(&tm_iids, sizeof(tm_iids));
1823         ecore_cxt_tm_iids(p_mngr, &tm_iids);
1824
1825         /* @@@TBD No pre-scan for now */
1826
1827         /* Note: We assume consecutive VFs for a PF */
1828         for (i = 0; i < p_mngr->vf_count; i++) {
1829                 cfg_word = 0;
1830                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_cids);
1831                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1832                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1833                 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all */
1834
1835                 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1836                          (sizeof(cfg_word) / sizeof(u32)) *
1837                          (p_hwfn->p_dev->p_iov_info->first_vf_in_pf + i);
1838                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1839         }
1840
1841         cfg_word = 0;
1842         SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_cids);
1843         SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1844         SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0);         /* n/a for PF */
1845         SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all   */
1846
1847         rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1848                  (sizeof(cfg_word) / sizeof(u32)) *
1849                  (NUM_OF_VFS(p_hwfn->p_dev) + p_hwfn->rel_pf_id);
1850         STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1851
1852         /* enale scan */
1853         STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_CONN_RT_OFFSET,
1854                      tm_iids.pf_cids  ? 0x1 : 0x0);
1855
1856         /* @@@TBD how to enable the scan for the VFs */
1857
1858         tm_offset = tm_iids.per_vf_cids;
1859
1860         /* Note: We assume consecutive VFs for a PF */
1861         for (i = 0; i < p_mngr->vf_count; i++) {
1862                 cfg_word = 0;
1863                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_tids);
1864                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1865                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1866                 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1867                 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64)0);
1868
1869                 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1870                          (sizeof(cfg_word) / sizeof(u32)) *
1871                          (p_hwfn->p_dev->p_iov_info->first_vf_in_pf + i);
1872
1873                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1874         }
1875
1876         tm_offset = tm_iids.pf_cids;
1877         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1878                 cfg_word = 0;
1879                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_tids[i]);
1880                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1881                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0);
1882                 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1883                 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64)0);
1884
1885                 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1886                          (sizeof(cfg_word) / sizeof(u32)) *
1887                          (NUM_OF_VFS(p_hwfn->p_dev) +
1888                          p_hwfn->rel_pf_id * NUM_TASK_PF_SEGMENTS + i);
1889
1890                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1891                 active_seg_mask |= (tm_iids.pf_tids[i] ? (1 << i) : 0);
1892
1893                 tm_offset += tm_iids.pf_tids[i];
1894         }
1895
1896         if (ECORE_IS_RDMA_PERSONALITY(p_hwfn))
1897                 active_seg_mask = 0;
1898
1899         STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_TASK_RT_OFFSET, active_seg_mask);
1900
1901         /* @@@TBD how to enable the scan for the VFs */
1902 }
1903
1904 static void ecore_prs_init_common(struct ecore_hwfn *p_hwfn)
1905 {
1906         if ((p_hwfn->hw_info.personality == ECORE_PCI_FCOE) &&
1907             p_hwfn->pf_params.fcoe_pf_params.is_target)
1908                 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET, 0);
1909 }
1910
1911 static void ecore_prs_init_pf(struct ecore_hwfn *p_hwfn)
1912 {
1913         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1914         struct ecore_conn_type_cfg *p_fcoe;
1915         struct ecore_tid_seg *p_tid;
1916
1917         p_fcoe = &p_mngr->conn_cfg[PROTOCOLID_FCOE];
1918
1919         /* If FCoE is active set the MAX OX_ID (tid) in the Parser */
1920         if (!p_fcoe->cid_count)
1921                 return;
1922
1923         p_tid = &p_fcoe->tid_seg[ECORE_CXT_FCOE_TID_SEG];
1924         if (p_hwfn->pf_params.fcoe_pf_params.is_target) {
1925                 STORE_RT_REG_AGG(p_hwfn,
1926                                  PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET,
1927                                  p_tid->count);
1928         } else {
1929                 STORE_RT_REG_AGG(p_hwfn,
1930                                 PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET,
1931                                 p_tid->count);
1932         }
1933 }
1934
1935 void ecore_cxt_hw_init_common(struct ecore_hwfn *p_hwfn)
1936 {
1937         /* CDU configuration */
1938         ecore_cdu_init_common(p_hwfn);
1939         ecore_prs_init_common(p_hwfn);
1940 }
1941
1942 void ecore_cxt_hw_init_pf(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1943 {
1944         ecore_qm_init_pf(p_hwfn, p_ptt);
1945         ecore_cm_init_pf(p_hwfn);
1946         ecore_dq_init_pf(p_hwfn);
1947         ecore_cdu_init_pf(p_hwfn);
1948         ecore_ilt_init_pf(p_hwfn);
1949         ecore_src_init_pf(p_hwfn);
1950         ecore_tm_init_pf(p_hwfn);
1951         ecore_prs_init_pf(p_hwfn);
1952 }
1953
1954 enum _ecore_status_t _ecore_cxt_acquire_cid(struct ecore_hwfn *p_hwfn,
1955                                             enum protocol_type type,
1956                                             u32 *p_cid, u8 vfid)
1957 {
1958         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1959         struct ecore_cid_acquired_map *p_map;
1960         u32 rel_cid;
1961
1962         if (type >= MAX_CONN_TYPES) {
1963                 DP_NOTICE(p_hwfn, true, "Invalid protocol type %d", type);
1964                 return ECORE_INVAL;
1965         }
1966
1967         if (vfid >= COMMON_MAX_NUM_VFS && vfid != ECORE_CXT_PF_CID) {
1968                 DP_NOTICE(p_hwfn, true, "VF [%02x] is out of range\n", vfid);
1969                 return ECORE_INVAL;
1970         }
1971
1972         /* Determine the right map to take this CID from */
1973         if (vfid == ECORE_CXT_PF_CID)
1974                 p_map = &p_mngr->acquired[type];
1975         else
1976                 p_map = &p_mngr->acquired_vf[type][vfid];
1977
1978         if (p_map->cid_map == OSAL_NULL) {
1979                 DP_NOTICE(p_hwfn, true, "Invalid protocol type %d", type);
1980                 return ECORE_INVAL;
1981         }
1982
1983         rel_cid = OSAL_FIND_FIRST_ZERO_BIT(p_map->cid_map,
1984                                            p_map->max_count);
1985
1986         if (rel_cid >= p_map->max_count) {
1987                 DP_NOTICE(p_hwfn, false, "no CID available for protocol %d\n",
1988                           type);
1989                 return ECORE_NORESOURCES;
1990         }
1991
1992         OSAL_SET_BIT(rel_cid, p_map->cid_map);
1993
1994         *p_cid = rel_cid + p_map->start_cid;
1995
1996         DP_VERBOSE(p_hwfn, ECORE_MSG_CXT,
1997                    "Acquired cid 0x%08x [rel. %08x] vfid %02x type %d\n",
1998                    *p_cid, rel_cid, vfid, type);
1999
2000         return ECORE_SUCCESS;
2001 }
2002
2003 enum _ecore_status_t ecore_cxt_acquire_cid(struct ecore_hwfn *p_hwfn,
2004                                            enum protocol_type type,
2005                                            u32 *p_cid)
2006 {
2007         return _ecore_cxt_acquire_cid(p_hwfn, type, p_cid, ECORE_CXT_PF_CID);
2008 }
2009
2010 static bool ecore_cxt_test_cid_acquired(struct ecore_hwfn *p_hwfn,
2011                                         u32 cid, u8 vfid,
2012                                         enum protocol_type *p_type,
2013                                         struct ecore_cid_acquired_map **pp_map)
2014 {
2015         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
2016         u32 rel_cid;
2017
2018         /* Iterate over protocols and find matching cid range */
2019         for (*p_type = 0; *p_type < MAX_CONN_TYPES; (*p_type)++) {
2020                 if (vfid == ECORE_CXT_PF_CID)
2021                         *pp_map = &p_mngr->acquired[*p_type];
2022                 else
2023                         *pp_map = &p_mngr->acquired_vf[*p_type][vfid];
2024
2025                 if (!((*pp_map)->cid_map))
2026                         continue;
2027                 if (cid >= (*pp_map)->start_cid &&
2028                     cid < (*pp_map)->start_cid + (*pp_map)->max_count) {
2029                         break;
2030                 }
2031         }
2032
2033         if (*p_type == MAX_CONN_TYPES) {
2034                 DP_NOTICE(p_hwfn, true, "Invalid CID %d vfid %02x", cid, vfid);
2035                 goto fail;
2036         }
2037
2038         rel_cid = cid - (*pp_map)->start_cid;
2039         if (!OSAL_TEST_BIT(rel_cid, (*pp_map)->cid_map)) {
2040                 DP_NOTICE(p_hwfn, true,
2041                           "CID %d [vifd %02x] not acquired", cid, vfid);
2042                 goto fail;
2043         }
2044
2045         return true;
2046 fail:
2047         *p_type = MAX_CONN_TYPES;
2048         *pp_map = OSAL_NULL;
2049         return false;
2050 }
2051
2052 void _ecore_cxt_release_cid(struct ecore_hwfn *p_hwfn, u32 cid, u8 vfid)
2053 {
2054         struct ecore_cid_acquired_map *p_map = OSAL_NULL;
2055         enum protocol_type type;
2056         bool b_acquired;
2057         u32 rel_cid;
2058
2059         if (vfid != ECORE_CXT_PF_CID && vfid > COMMON_MAX_NUM_VFS) {
2060                 DP_NOTICE(p_hwfn, true,
2061                           "Trying to return incorrect CID belonging to VF %02x\n",
2062                           vfid);
2063                 return;
2064         }
2065
2066         /* Test acquired and find matching per-protocol map */
2067         b_acquired = ecore_cxt_test_cid_acquired(p_hwfn, cid, vfid,
2068                                                  &type, &p_map);
2069
2070         if (!b_acquired)
2071                 return;
2072
2073         rel_cid = cid - p_map->start_cid;
2074         OSAL_CLEAR_BIT(rel_cid, p_map->cid_map);
2075
2076         DP_VERBOSE(p_hwfn, ECORE_MSG_CXT,
2077                    "Released CID 0x%08x [rel. %08x] vfid %02x type %d\n",
2078                    cid, rel_cid, vfid, type);
2079 }
2080
2081 void ecore_cxt_release_cid(struct ecore_hwfn *p_hwfn, u32 cid)
2082 {
2083         _ecore_cxt_release_cid(p_hwfn, cid, ECORE_CXT_PF_CID);
2084 }
2085
2086 enum _ecore_status_t ecore_cxt_get_cid_info(struct ecore_hwfn *p_hwfn,
2087                                             struct ecore_cxt_info *p_info)
2088 {
2089         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
2090         struct ecore_cid_acquired_map *p_map = OSAL_NULL;
2091         u32 conn_cxt_size, hw_p_size, cxts_per_p, line;
2092         enum protocol_type type;
2093         bool b_acquired;
2094
2095         /* Test acquired and find matching per-protocol map */
2096         b_acquired = ecore_cxt_test_cid_acquired(p_hwfn, p_info->iid,
2097                                                  ECORE_CXT_PF_CID,
2098                                                  &type, &p_map);
2099
2100         if (!b_acquired)
2101                 return ECORE_INVAL;
2102
2103         /* set the protocl type */
2104         p_info->type = type;
2105
2106         /* compute context virtual pointer */
2107         hw_p_size = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
2108
2109         conn_cxt_size = CONN_CXT_SIZE(p_hwfn);
2110         cxts_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / conn_cxt_size;
2111         line = p_info->iid / cxts_per_p;
2112
2113         /* Make sure context is allocated (dynamic allocation) */
2114         if (!p_mngr->ilt_shadow[line].p_virt)
2115                 return ECORE_INVAL;
2116
2117         p_info->p_cxt = (u8 *)p_mngr->ilt_shadow[line].p_virt +
2118                               p_info->iid % cxts_per_p * conn_cxt_size;
2119
2120         DP_VERBOSE(p_hwfn, (ECORE_MSG_ILT | ECORE_MSG_CXT),
2121                    "Accessing ILT shadow[%d]: CXT pointer is at %p (for iid %d)\n",
2122                    (p_info->iid / cxts_per_p), p_info->p_cxt, p_info->iid);
2123
2124         return ECORE_SUCCESS;
2125 }
2126
2127 static void ecore_rdma_set_pf_params(struct ecore_hwfn *p_hwfn,
2128                                      struct ecore_rdma_pf_params *p_params,
2129                                      u32 num_tasks)
2130 {
2131         u32 num_cons, num_qps, num_srqs;
2132         enum protocol_type proto;
2133
2134         /* Override personality with rdma flavor */
2135         num_srqs = OSAL_MIN_T(u32, ECORE_RDMA_MAX_SRQS, p_params->num_srqs);
2136
2137         /* The only case RDMA personality can be overriden is if NVRAM is
2138          * configured with ETH_RDMA or if no rdma protocol was requested
2139          */
2140         switch (p_params->rdma_protocol) {
2141         case ECORE_RDMA_PROTOCOL_DEFAULT:
2142                 if (p_hwfn->mcp_info->func_info.protocol ==
2143                     ECORE_PCI_ETH_RDMA) {
2144                         DP_NOTICE(p_hwfn, false,
2145                                   "Current day drivers don't support RoCE & iWARP. Default to RoCE-only\n");
2146                         p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
2147                 }
2148                 break;
2149         case ECORE_RDMA_PROTOCOL_NONE:
2150                 p_hwfn->hw_info.personality = ECORE_PCI_ETH;
2151                 return; /* intentional... nothing left to do... */
2152         case ECORE_RDMA_PROTOCOL_ROCE:
2153                 if (p_hwfn->mcp_info->func_info.protocol == ECORE_PCI_ETH_RDMA)
2154                         p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
2155                 break;
2156         case ECORE_RDMA_PROTOCOL_IWARP:
2157                 if (p_hwfn->mcp_info->func_info.protocol == ECORE_PCI_ETH_RDMA)
2158                         p_hwfn->hw_info.personality = ECORE_PCI_ETH_IWARP;
2159                 break;
2160         }
2161
2162         switch (p_hwfn->hw_info.personality) {
2163         case ECORE_PCI_ETH_IWARP:
2164                 /* Each QP requires one connection */
2165                 num_cons = OSAL_MIN_T(u32, IWARP_MAX_QPS, p_params->num_qps);
2166 #ifdef CONFIG_ECORE_IWARP /* required for the define */
2167                 /* additional connections required for passive tcp handling */
2168                 num_cons += ECORE_IWARP_PREALLOC_CNT;
2169 #endif
2170                 proto = PROTOCOLID_IWARP;
2171                 p_params->roce_edpm_mode = false;
2172                 break;
2173         case ECORE_PCI_ETH_ROCE:
2174                 num_qps = OSAL_MIN_T(u32, ROCE_MAX_QPS, p_params->num_qps);
2175                 num_cons = num_qps * 2; /* each QP requires two connections */
2176                 proto = PROTOCOLID_ROCE;
2177                 break;
2178         default:
2179                 return;
2180         }
2181
2182         if (num_cons && num_tasks) {
2183                 ecore_cxt_set_proto_cid_count(p_hwfn, proto,
2184                                               num_cons, 0);
2185
2186                 /* Deliberatly passing ROCE for tasks id. This is because
2187                  * iWARP / RoCE share the task id.
2188                  */
2189                 ecore_cxt_set_proto_tid_count(p_hwfn, PROTOCOLID_ROCE,
2190                                               ECORE_CXT_ROCE_TID_SEG,
2191                                               1, /* RoCE segment type */
2192                                               num_tasks,
2193                                               false); /* !force load */
2194                 ecore_cxt_set_srq_count(p_hwfn, num_srqs);
2195
2196         } else {
2197                 DP_INFO(p_hwfn->p_dev,
2198                         "RDMA personality used without setting params!\n");
2199         }
2200 }
2201
2202 enum _ecore_status_t ecore_cxt_set_pf_params(struct ecore_hwfn *p_hwfn,
2203                                              u32 rdma_tasks)
2204 {
2205         /* Set the number of required CORE connections */
2206         u32 core_cids = 1; /* SPQ */
2207
2208         if (p_hwfn->using_ll2)
2209                 core_cids += 4; /* @@@TBD Use the proper #define */
2210
2211         ecore_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_CORE, core_cids, 0);
2212
2213         switch (p_hwfn->hw_info.personality) {
2214         case ECORE_PCI_ETH_RDMA:
2215         case ECORE_PCI_ETH_IWARP:
2216         case ECORE_PCI_ETH_ROCE:
2217         {
2218                 ecore_rdma_set_pf_params(p_hwfn,
2219                                          &p_hwfn->pf_params.rdma_pf_params,
2220                                          rdma_tasks);
2221
2222                 /* no need for break since RoCE coexist with Ethernet */
2223         }
2224         case ECORE_PCI_ETH:
2225         {
2226                 struct ecore_eth_pf_params *p_params =
2227                                         &p_hwfn->pf_params.eth_pf_params;
2228
2229                 if (!p_params->num_vf_cons)
2230                         p_params->num_vf_cons = ETH_PF_PARAMS_VF_CONS_DEFAULT;
2231                 ecore_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
2232                                               p_params->num_cons,
2233                                               p_params->num_vf_cons);
2234                 p_hwfn->p_cxt_mngr->arfs_count = p_params->num_arfs_filters;
2235
2236                 break;
2237         }
2238         case ECORE_PCI_FCOE:
2239         {
2240                 struct ecore_fcoe_pf_params *p_params;
2241
2242                 p_params = &p_hwfn->pf_params.fcoe_pf_params;
2243
2244                 if (p_params->num_cons && p_params->num_tasks) {
2245                         ecore_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_FCOE,
2246                                                       p_params->num_cons, 0);
2247
2248                         ecore_cxt_set_proto_tid_count(p_hwfn, PROTOCOLID_FCOE,
2249                                                       ECORE_CXT_FCOE_TID_SEG,
2250                                                       0, /* segment type */
2251                                                       p_params->num_tasks,
2252                                                       true);
2253                 } else {
2254                         DP_INFO(p_hwfn->p_dev,
2255                                 "Fcoe personality used without setting params!\n");
2256                 }
2257                 break;
2258         }
2259         case ECORE_PCI_ISCSI:
2260         {
2261                 struct ecore_iscsi_pf_params *p_params;
2262
2263                 p_params = &p_hwfn->pf_params.iscsi_pf_params;
2264
2265                 if (p_params->num_cons && p_params->num_tasks) {
2266                         ecore_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_ISCSI,
2267                                                       p_params->num_cons, 0);
2268
2269                         ecore_cxt_set_proto_tid_count(p_hwfn, PROTOCOLID_ISCSI,
2270                                                       ECORE_CXT_ISCSI_TID_SEG,
2271                                                       0, /* segment type */
2272                                                       p_params->num_tasks,
2273                                                       true);
2274                 } else {
2275                         DP_INFO(p_hwfn->p_dev,
2276                                 "Iscsi personality used without setting params!\n");
2277                 }
2278                 break;
2279         }
2280         default:
2281                 return ECORE_INVAL;
2282         }
2283
2284         return ECORE_SUCCESS;
2285 }
2286
2287 enum _ecore_status_t ecore_cxt_get_tid_mem_info(struct ecore_hwfn *p_hwfn,
2288                                                 struct ecore_tid_mem *p_info)
2289 {
2290         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
2291         u32 proto, seg, total_lines, i, shadow_line;
2292         struct ecore_ilt_client_cfg *p_cli;
2293         struct ecore_ilt_cli_blk *p_fl_seg;
2294         struct ecore_tid_seg *p_seg_info;
2295
2296         /* Verify the personality */
2297         switch (p_hwfn->hw_info.personality) {
2298         case ECORE_PCI_FCOE:
2299                 proto = PROTOCOLID_FCOE;
2300                 seg = ECORE_CXT_FCOE_TID_SEG;
2301                 break;
2302         case ECORE_PCI_ISCSI:
2303                 proto = PROTOCOLID_ISCSI;
2304                 seg = ECORE_CXT_ISCSI_TID_SEG;
2305                 break;
2306         default:
2307                 return ECORE_INVAL;
2308         }
2309
2310         p_cli = &p_mngr->clients[ILT_CLI_CDUT];
2311         if (!p_cli->active) {
2312                 return ECORE_INVAL;
2313         }
2314
2315         p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg];
2316         if (!p_seg_info->has_fl_mem)
2317                 return ECORE_INVAL;
2318
2319         p_fl_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)];
2320         total_lines = DIV_ROUND_UP(p_fl_seg->total_size,
2321                                    p_fl_seg->real_size_in_page);
2322
2323         for (i = 0; i < total_lines; i++) {
2324                 shadow_line = i + p_fl_seg->start_line -
2325                               p_hwfn->p_cxt_mngr->pf_start_line;
2326                 p_info->blocks[i] = p_mngr->ilt_shadow[shadow_line].p_virt;
2327         }
2328         p_info->waste = ILT_PAGE_IN_BYTES(p_cli->p_size.val) -
2329                         p_fl_seg->real_size_in_page;
2330         p_info->tid_size = p_mngr->task_type_size[p_seg_info->type];
2331         p_info->num_tids_per_block = p_fl_seg->real_size_in_page /
2332                                      p_info->tid_size;
2333
2334         return ECORE_SUCCESS;
2335 }
2336
2337 /* This function is very RoCE oriented, if another protocol in the future
2338  * will want this feature we'll need to modify the function to be more generic
2339  */
2340 enum _ecore_status_t
2341 ecore_cxt_dynamic_ilt_alloc(struct ecore_hwfn *p_hwfn,
2342                             enum ecore_cxt_elem_type elem_type,
2343                             u32 iid)
2344 {
2345         u32 reg_offset, shadow_line, elem_size, hw_p_size, elems_per_p, line;
2346         struct ecore_ilt_client_cfg *p_cli;
2347         struct ecore_ilt_cli_blk *p_blk;
2348         struct ecore_ptt *p_ptt;
2349         dma_addr_t p_phys;
2350         u64 ilt_hw_entry;
2351         void *p_virt;
2352         enum _ecore_status_t rc = ECORE_SUCCESS;
2353
2354         switch (elem_type) {
2355         case ECORE_ELEM_CXT:
2356                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
2357                 elem_size = CONN_CXT_SIZE(p_hwfn);
2358                 p_blk = &p_cli->pf_blks[CDUC_BLK];
2359                 break;
2360         case ECORE_ELEM_SRQ:
2361                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
2362                 elem_size = SRQ_CXT_SIZE;
2363                 p_blk = &p_cli->pf_blks[SRQ_BLK];
2364                 break;
2365         case ECORE_ELEM_TASK:
2366                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
2367                 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
2368                 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(ECORE_CXT_ROCE_TID_SEG)];
2369                 break;
2370         default:
2371                 DP_NOTICE(p_hwfn, false,
2372                           "ECORE_INVALID elem type = %d", elem_type);
2373                 return ECORE_INVAL;
2374         }
2375
2376         /* Calculate line in ilt */
2377         hw_p_size = p_cli->p_size.val;
2378         elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
2379         line = p_blk->start_line + (iid / elems_per_p);
2380         shadow_line = line - p_hwfn->p_cxt_mngr->pf_start_line;
2381
2382         /* If line is already allocated, do nothing, otherwise allocate it and
2383          * write it to the PSWRQ2 registers.
2384          * This section can be run in parallel from different contexts and thus
2385          * a mutex protection is needed.
2386          */
2387
2388         OSAL_MUTEX_ACQUIRE(&p_hwfn->p_cxt_mngr->mutex);
2389
2390         if (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt)
2391                 goto out0;
2392
2393         p_ptt = ecore_ptt_acquire(p_hwfn);
2394         if (!p_ptt) {
2395                 DP_NOTICE(p_hwfn, false,
2396                           "ECORE_TIME_OUT on ptt acquire - dynamic allocation");
2397                 rc = ECORE_TIMEOUT;
2398                 goto out0;
2399         }
2400
2401         p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
2402                                          &p_phys,
2403                                          p_blk->real_size_in_page);
2404         if (!p_virt) {
2405                 rc = ECORE_NOMEM;
2406                 goto out1;
2407         }
2408         OSAL_MEM_ZERO(p_virt, p_blk->real_size_in_page);
2409
2410         /* configuration of refTagMask to 0xF is required for RoCE DIF MR only,
2411          * to compensate for a HW bug, but it is configured even if DIF is not
2412          * enabled. This is harmless and allows us to avoid a dedicated API. We
2413          * configure the field for all of the contexts on the newly allocated
2414          * page.
2415          */
2416         if (elem_type == ECORE_ELEM_TASK) {
2417                 u32 elem_i;
2418                 u8 *elem_start = (u8 *)p_virt;
2419                 union type1_task_context *elem;
2420
2421                 for (elem_i = 0; elem_i < elems_per_p; elem_i++) {
2422                         elem = (union type1_task_context *)elem_start;
2423                         SET_FIELD(elem->roce_ctx.tdif_context.flags1,
2424                                   TDIF_TASK_CONTEXT_REFTAGMASK , 0xf);
2425                         elem_start += TYPE1_TASK_CXT_SIZE(p_hwfn);
2426                 }
2427         }
2428
2429         p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt = p_virt;
2430         p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys = p_phys;
2431         p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].size =
2432                 p_blk->real_size_in_page;
2433
2434         /* compute absolute offset */
2435         reg_offset = PSWRQ2_REG_ILT_MEMORY +
2436                      (line * ILT_REG_SIZE_IN_BYTES * ILT_ENTRY_IN_REGS);
2437
2438         ilt_hw_entry = 0;
2439         SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
2440         SET_FIELD(ilt_hw_entry,
2441                   ILT_ENTRY_PHY_ADDR,
2442                   (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys >> 12));
2443
2444         /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a wide-bus */
2445         ecore_dmae_host2grc(p_hwfn, p_ptt, (u64)(osal_uintptr_t)&ilt_hw_entry,
2446                             reg_offset, sizeof(ilt_hw_entry) / sizeof(u32),
2447                             0 /* no flags */);
2448
2449         if (elem_type == ECORE_ELEM_CXT) {
2450                 u32 last_cid_allocated = (1 + (iid / elems_per_p)) *
2451                                          elems_per_p;
2452
2453                 /* Update the relevant register in the parser */
2454                 ecore_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF,
2455                          last_cid_allocated - 1);
2456
2457                 /* RoCE w/a -> we don't write to the prs search reg until first
2458                  * cid is allocated. This is because the prs checks
2459                  * last_cid-1 >=0 making 0 a valid value... this will cause
2460                  * the a context load to occur on a RoCE packet received with
2461                  * cid=0 even before context was initialized, can happen with a
2462                  * stray packet from switch or a packet with crc-error
2463                  */
2464
2465                 if (!p_hwfn->b_rdma_enabled_in_prs) {
2466                         /* Enable Rdma search */
2467                         ecore_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 1);
2468                         p_hwfn->b_rdma_enabled_in_prs = true;
2469                 }
2470         }
2471
2472 out1:
2473         ecore_ptt_release(p_hwfn, p_ptt);
2474 out0:
2475         OSAL_MUTEX_RELEASE(&p_hwfn->p_cxt_mngr->mutex);
2476
2477         return rc;
2478 }
2479
2480 /* This function is very RoCE oriented, if another protocol in the future
2481  * will want this feature we'll need to modify the function to be more generic
2482  */
2483 enum _ecore_status_t
2484 ecore_cxt_free_ilt_range(struct ecore_hwfn *p_hwfn,
2485                          enum ecore_cxt_elem_type elem_type,
2486                          u32 start_iid, u32 count)
2487 {
2488         u32 start_line, end_line, shadow_start_line, shadow_end_line;
2489         u32 reg_offset, elem_size, hw_p_size, elems_per_p;
2490         struct ecore_ilt_client_cfg *p_cli;
2491         struct ecore_ilt_cli_blk *p_blk;
2492         u32 end_iid = start_iid + count;
2493         struct ecore_ptt *p_ptt;
2494         u64 ilt_hw_entry = 0;
2495         u32 i;
2496
2497         switch (elem_type) {
2498         case ECORE_ELEM_CXT:
2499                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
2500                 elem_size = CONN_CXT_SIZE(p_hwfn);
2501                 p_blk = &p_cli->pf_blks[CDUC_BLK];
2502                 break;
2503         case ECORE_ELEM_SRQ:
2504                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
2505                 elem_size = SRQ_CXT_SIZE;
2506                 p_blk = &p_cli->pf_blks[SRQ_BLK];
2507                 break;
2508         case ECORE_ELEM_TASK:
2509                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
2510                 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
2511                 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(ECORE_CXT_ROCE_TID_SEG)];
2512                 break;
2513         default:
2514                 DP_NOTICE(p_hwfn, false,
2515                           "ECORE_INVALID elem type = %d", elem_type);
2516                 return ECORE_INVAL;
2517         }
2518
2519         /* Calculate line in ilt */
2520         hw_p_size = p_cli->p_size.val;
2521         elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
2522         start_line = p_blk->start_line + (start_iid / elems_per_p);
2523         end_line = p_blk->start_line + (end_iid / elems_per_p);
2524         if (((end_iid + 1) / elems_per_p) != (end_iid / elems_per_p))
2525                 end_line--;
2526
2527         shadow_start_line = start_line - p_hwfn->p_cxt_mngr->pf_start_line;
2528         shadow_end_line = end_line - p_hwfn->p_cxt_mngr->pf_start_line;
2529
2530         p_ptt = ecore_ptt_acquire(p_hwfn);
2531         if (!p_ptt) {
2532                 DP_NOTICE(p_hwfn, false, "ECORE_TIME_OUT on ptt acquire - dynamic allocation");
2533                 return ECORE_TIMEOUT;
2534         }
2535
2536         for (i = shadow_start_line; i < shadow_end_line; i++) {
2537                 if (!p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt)
2538                         continue;
2539
2540                 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
2541                                        p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt,
2542                                        p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys,
2543                                        p_hwfn->p_cxt_mngr->ilt_shadow[i].size);
2544
2545                 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt = OSAL_NULL;
2546                 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys = 0;
2547                 p_hwfn->p_cxt_mngr->ilt_shadow[i].size = 0;
2548
2549                 /* compute absolute offset */
2550                 reg_offset = PSWRQ2_REG_ILT_MEMORY +
2551                              ((start_line++) * ILT_REG_SIZE_IN_BYTES *
2552                               ILT_ENTRY_IN_REGS);
2553
2554                 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a
2555                  * wide-bus.
2556                  */
2557                 ecore_dmae_host2grc(p_hwfn, p_ptt,
2558                                     (u64)(osal_uintptr_t)&ilt_hw_entry,
2559                                     reg_offset,
2560                                     sizeof(ilt_hw_entry) / sizeof(u32),
2561                                     0 /* no flags */);
2562         }
2563
2564         ecore_ptt_release(p_hwfn, p_ptt);
2565
2566         return ECORE_SUCCESS;
2567 }
2568
2569 enum _ecore_status_t ecore_cxt_get_task_ctx(struct ecore_hwfn *p_hwfn,
2570                                             u32 tid,
2571                                             u8 ctx_type,
2572                                             void **pp_task_ctx)
2573 {
2574         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
2575         struct ecore_ilt_client_cfg *p_cli;
2576         struct ecore_tid_seg *p_seg_info;
2577         struct ecore_ilt_cli_blk *p_seg;
2578         u32 num_tids_per_block;
2579         u32 tid_size, ilt_idx;
2580         u32 total_lines;
2581         u32 proto, seg;
2582
2583         /* Verify the personality */
2584         switch (p_hwfn->hw_info.personality) {
2585         case ECORE_PCI_FCOE:
2586                 proto = PROTOCOLID_FCOE;
2587                 seg = ECORE_CXT_FCOE_TID_SEG;
2588                 break;
2589         case ECORE_PCI_ISCSI:
2590                 proto = PROTOCOLID_ISCSI;
2591                 seg = ECORE_CXT_ISCSI_TID_SEG;
2592                 break;
2593         default:
2594                 return ECORE_INVAL;
2595         }
2596
2597         p_cli = &p_mngr->clients[ILT_CLI_CDUT];
2598         if (!p_cli->active) {
2599                 return ECORE_INVAL;
2600         }
2601
2602         p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg];
2603
2604         if (ctx_type == ECORE_CTX_WORKING_MEM) {
2605                 p_seg = &p_cli->pf_blks[CDUT_SEG_BLK(seg)];
2606         } else if (ctx_type == ECORE_CTX_FL_MEM) {
2607                 if (!p_seg_info->has_fl_mem) {
2608                         return ECORE_INVAL;
2609                 }
2610                 p_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)];
2611         } else {
2612                 return ECORE_INVAL;
2613         }
2614         total_lines = DIV_ROUND_UP(p_seg->total_size,
2615                                    p_seg->real_size_in_page);
2616         tid_size = p_mngr->task_type_size[p_seg_info->type];
2617         num_tids_per_block = p_seg->real_size_in_page / tid_size;
2618
2619         if (total_lines < tid/num_tids_per_block)
2620                 return ECORE_INVAL;
2621
2622         ilt_idx = tid / num_tids_per_block + p_seg->start_line -
2623                   p_mngr->pf_start_line;
2624         *pp_task_ctx = (u8 *)p_mngr->ilt_shadow[ilt_idx].p_virt +
2625                              (tid % num_tids_per_block) * tid_size;
2626
2627         return ECORE_SUCCESS;
2628 }