sys/dev/qlxgb/qla_hw.c

   1 /*
   2  * Copyright (c) 2010-2011 Qlogic Corporation
   3  * All rights reserved.
   4  *
   5  *  Redistribution and use in source and binary forms, with or without
   6  *  modification, are permitted provided that the following conditions
   7  *  are met:
   8  *
   9  *  1. Redistributions of source code must retain the above copyright
  10  *     notice, this list of conditions and the following disclaimer.
  11  *  2. Redistributions in binary form must reproduce the above copyright
  12  *     notice, this list of conditions and the following disclaimer in the
  13  *     documentation and/or other materials provided with the distribution.
  14  *
  15  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  16  *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  19  *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  20  *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  21  *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  22  *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  23  *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  24  *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  25  *  POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 /*
  29  * File: qla_hw.c
  30  * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
  31  * Content: Contains Hardware dependant functions
  32  */
  33
  34 #include <sys/cdefs.h>
  35 __FBSDID("$FreeBSD$");
  36
  37 #include "qla_os.h"
  38 #include "qla_reg.h"
  39 #include "qla_hw.h"
  40 #include "qla_def.h"
  41 #include "qla_inline.h"
  42 #include "qla_ver.h"
  43 #include "qla_glbl.h"
  44 #include "qla_dbg.h"
  45
  46 static uint32_t sysctl_num_rds_rings = 2;
  47 static uint32_t sysctl_num_sds_rings = 4;
  48
  49 /*
  50  * Static Functions
  51  */
  52
  53 static void qla_init_cntxt_regions(qla_host_t *ha);
  54 static int qla_issue_cmd(qla_host_t *ha, qla_cdrp_t *cdrp);
  55 static int qla_fw_cmd(qla_host_t *ha, void *fw_cmd, uint32_t size);
  56 static int qla_config_mac_addr(qla_host_t *ha, uint8_t *mac_addr,
  57                 uint16_t cntxt_id, uint32_t add_multi);
  58 static void qla_del_rcv_cntxt(qla_host_t *ha);
  59 static int qla_init_rcv_cntxt(qla_host_t *ha);
  60 static void qla_del_xmt_cntxt(qla_host_t *ha);
  61 static int qla_init_xmt_cntxt(qla_host_t *ha);
  62 static int qla_get_max_rds(qla_host_t *ha);
  63 static int qla_get_max_sds(qla_host_t *ha);
  64 static int qla_get_max_rules(qla_host_t *ha);
  65 static int qla_get_max_rcv_cntxts(qla_host_t *ha);
  66 static int qla_get_max_tx_cntxts(qla_host_t *ha);
  67 static int qla_get_max_mtu(qla_host_t *ha);
  68 static int qla_get_max_lro(qla_host_t *ha);
  69 static int qla_get_flow_control(qla_host_t *ha);
  70 static void qla_hw_tx_done_locked(qla_host_t *ha);
  71
  72 int
  73 qla_get_msix_count(qla_host_t *ha)
  74 {
  75         return (sysctl_num_sds_rings);
  76 }
  77
  78 /*
  79  * Name: qla_hw_add_sysctls
  80  * Function: Add P3Plus specific sysctls
  81  */
  82 void
  83 qla_hw_add_sysctls(qla_host_t *ha)
  84 {
  85         device_t        dev;
  86
  87         dev = ha->pci_dev;
  88
  89         SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
  90                 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
  91                 OID_AUTO, "num_rds_rings", CTLFLAG_RD, &sysctl_num_rds_rings,
  92                 sysctl_num_rds_rings, "Number of Rcv Descriptor Rings");
  93
  94         SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
  95                 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
  96                 OID_AUTO, "num_sds_rings", CTLFLAG_RD, &sysctl_num_sds_rings,
  97                 sysctl_num_sds_rings, "Number of Status Descriptor Rings");
  98 }
  99
 100 /*
 101  * Name: qla_free_dma
 102  * Function: Frees the DMA'able memory allocated in qla_alloc_dma()
 103  */
 104 void
 105 qla_free_dma(qla_host_t *ha)
 106 {
 107         uint32_t i;
 108
 109         if (ha->hw.dma_buf.flags.context) {
 110                 qla_free_dmabuf(ha, &ha->hw.dma_buf.context);
 111                 ha->hw.dma_buf.flags.context = 0;
 112         }
 113
 114         if (ha->hw.dma_buf.flags.sds_ring) {
 115                 for (i = 0; i < ha->hw.num_sds_rings; i++)
 116                         qla_free_dmabuf(ha, &ha->hw.dma_buf.sds_ring[i]);
 117                 ha->hw.dma_buf.flags.sds_ring = 0;
 118         }
 119
 120         if (ha->hw.dma_buf.flags.rds_ring) {
 121                 for (i = 0; i < ha->hw.num_rds_rings; i++)
 122                         qla_free_dmabuf(ha, &ha->hw.dma_buf.rds_ring[i]);
 123                 ha->hw.dma_buf.flags.rds_ring = 0;
 124         }
 125
 126         if (ha->hw.dma_buf.flags.tx_ring) {
 127                 qla_free_dmabuf(ha, &ha->hw.dma_buf.tx_ring);
 128                 ha->hw.dma_buf.flags.tx_ring = 0;
 129         }
 130 }
 131
 132 /*
 133  * Name: qla_alloc_dma
 134  * Function: Allocates DMA'able memory for Tx/Rx Rings, Tx/Rx Contexts.
 135  */
 136 int
 137 qla_alloc_dma(qla_host_t *ha)
 138 {
 139         device_t                dev;
 140         uint32_t                i, j, size;
 141
 142         dev = ha->pci_dev;
 143
 144         QL_DPRINT2((dev, "%s: enter\n", __func__));
 145
 146         ha->hw.num_rds_rings = (uint16_t)sysctl_num_rds_rings;
 147         ha->hw.num_sds_rings = (uint16_t)sysctl_num_sds_rings;
 148
 149         /*
 150          * Allocate Transmit Ring
 151          */
 152
 153         ha->hw.dma_buf.tx_ring.alignment = 8;
 154         ha->hw.dma_buf.tx_ring.size =
 155                 (sizeof(q80_tx_cmd_t)) * NUM_TX_DESCRIPTORS;
 156
 157         if (qla_alloc_dmabuf(ha, &ha->hw.dma_buf.tx_ring)) {
 158                 device_printf(dev, "%s: tx ring alloc failed\n", __func__);
 159                 goto qla_alloc_dma_exit;
 160         }
 161         ha->hw.dma_buf.flags.tx_ring = 1;
 162
 163         QL_DPRINT2((dev, "%s: tx_ring phys %p virt %p\n",
 164                 __func__, (void *)(ha->hw.dma_buf.tx_ring.dma_addr),
 165                 ha->hw.dma_buf.tx_ring.dma_b));
 166         /*
 167          * Allocate Receive Descriptor Rings
 168          */
 169
 170         for (i = 0; i < ha->hw.num_rds_rings; i++) {
 171                 ha->hw.dma_buf.rds_ring[i].alignment = 8;
 172
 173                 if (i == RDS_RING_INDEX_NORMAL) {
 174                         ha->hw.dma_buf.rds_ring[i].size =
 175                                 (sizeof(q80_recv_desc_t)) * NUM_RX_DESCRIPTORS;
 176                 } else if (i == RDS_RING_INDEX_JUMBO) {
 177                         ha->hw.dma_buf.rds_ring[i].size =
 178                                 (sizeof(q80_recv_desc_t)) *
 179                                         NUM_RX_JUMBO_DESCRIPTORS;
 180                 } else
 181                         break;
 182
 183                 if (qla_alloc_dmabuf(ha, &ha->hw.dma_buf.rds_ring[i])) {
 184                         QL_DPRINT4((dev, "%s: rds ring alloc failed\n",
 185                                 __func__));
 186
 187                         for (j = 0; j < i; j++)
 188                                 qla_free_dmabuf(ha,
 189                                         &ha->hw.dma_buf.rds_ring[j]);
 190
 191                         goto qla_alloc_dma_exit;
 192                 }
 193                 QL_DPRINT4((dev, "%s: rx_ring[%d] phys %p virt %p\n",
 194                         __func__, i,
 195                         (void *)(ha->hw.dma_buf.rds_ring[i].dma_addr),
 196                         ha->hw.dma_buf.rds_ring[i].dma_b));
 197         }
 198         ha->hw.dma_buf.flags.rds_ring = 1;
 199
 200         /*
 201          * Allocate Status Descriptor Rings
 202          */
 203
 204         for (i = 0; i < ha->hw.num_sds_rings; i++) {
 205                 ha->hw.dma_buf.sds_ring[i].alignment = 8;
 206                 ha->hw.dma_buf.sds_ring[i].size =
 207                         (sizeof(q80_stat_desc_t)) * NUM_STATUS_DESCRIPTORS;
 208
 209                 if (qla_alloc_dmabuf(ha, &ha->hw.dma_buf.sds_ring[i])) {
 210                         device_printf(dev, "%s: sds ring alloc failed\n",
 211                                 __func__);
 212
 213                         for (j = 0; j < i; j++)
 214                                 qla_free_dmabuf(ha,
 215                                         &ha->hw.dma_buf.sds_ring[j]);
 216
 217                         goto qla_alloc_dma_exit;
 218                 }
 219                 QL_DPRINT4((dev, "%s: sds_ring[%d] phys %p virt %p\n",
 220                         __func__, i,
 221                         (void *)(ha->hw.dma_buf.sds_ring[i].dma_addr),
 222                         ha->hw.dma_buf.sds_ring[i].dma_b));
 223         }
 224         ha->hw.dma_buf.flags.sds_ring = 1;
 225
 226         /*
 227          * Allocate Context Area
 228          */
 229         size = QL_ALIGN((sizeof (q80_tx_cntxt_req_t)), QL_BUFFER_ALIGN);
 230
 231         size += QL_ALIGN((sizeof (q80_tx_cntxt_rsp_t)), QL_BUFFER_ALIGN);
 232
 233         size += QL_ALIGN((sizeof (q80_rcv_cntxt_req_t)), QL_BUFFER_ALIGN);
 234
 235         size += QL_ALIGN((sizeof (q80_rcv_cntxt_rsp_t)), QL_BUFFER_ALIGN);
 236
 237         size += sizeof (uint32_t); /* for tx consumer index */
 238
 239         size = QL_ALIGN(size, PAGE_SIZE);
 240
 241         ha->hw.dma_buf.context.alignment = 8;
 242         ha->hw.dma_buf.context.size = size;
 243
 244         if (qla_alloc_dmabuf(ha, &ha->hw.dma_buf.context)) {
 245                 device_printf(dev, "%s: context alloc failed\n", __func__);
 246                 goto qla_alloc_dma_exit;
 247         }
 248         ha->hw.dma_buf.flags.context = 1;
 249         QL_DPRINT2((dev, "%s: context phys %p virt %p\n",
 250                 __func__, (void *)(ha->hw.dma_buf.context.dma_addr),
 251                 ha->hw.dma_buf.context.dma_b));
 252
 253         qla_init_cntxt_regions(ha);
 254
 255         return 0;
 256
 257 qla_alloc_dma_exit:
 258         qla_free_dma(ha);
 259         return -1;
 260 }
 261
 262 /*
 263  * Name: qla_init_cntxt_regions
 264  * Function: Initializes Tx/Rx Contexts.
 265  */
 266 static void
 267 qla_init_cntxt_regions(qla_host_t *ha)
 268 {
 269         qla_hw_t                *hw;
 270         q80_tx_cntxt_req_t      *tx_cntxt_req;
 271         q80_rcv_cntxt_req_t     *rx_cntxt_req;
 272         bus_addr_t              phys_addr;
 273         uint32_t                i;
 274         device_t                dev;
 275         uint32_t                size;
 276
 277         dev = ha->pci_dev;
 278
 279         hw = &ha->hw;
 280
 281         hw->tx_ring_base = hw->dma_buf.tx_ring.dma_b;
 282
 283         for (i = 0; i < ha->hw.num_sds_rings; i++)
 284                 hw->sds[i].sds_ring_base =
 285                         (q80_stat_desc_t *)hw->dma_buf.sds_ring[i].dma_b;
 286
 287
 288         phys_addr = hw->dma_buf.context.dma_addr;
 289
 290         memset((void *)hw->dma_buf.context.dma_b, 0,
 291                 ha->hw.dma_buf.context.size);
 292
 293         hw->tx_cntxt_req        =
 294                 (q80_tx_cntxt_req_t *)hw->dma_buf.context.dma_b;
 295         hw->tx_cntxt_req_paddr  = phys_addr;
 296
 297         size = QL_ALIGN((sizeof (q80_tx_cntxt_req_t)), QL_BUFFER_ALIGN);
 298
 299         hw->tx_cntxt_rsp        =
 300                 (q80_tx_cntxt_rsp_t *)((uint8_t *)hw->tx_cntxt_req + size);
 301         hw->tx_cntxt_rsp_paddr  = hw->tx_cntxt_req_paddr + size;
 302
 303         size = QL_ALIGN((sizeof (q80_tx_cntxt_rsp_t)), QL_BUFFER_ALIGN);
 304
 305         hw->rx_cntxt_req =
 306                 (q80_rcv_cntxt_req_t *)((uint8_t *)hw->tx_cntxt_rsp + size);
 307         hw->rx_cntxt_req_paddr = hw->tx_cntxt_rsp_paddr + size;
 308
 309         size = QL_ALIGN((sizeof (q80_rcv_cntxt_req_t)), QL_BUFFER_ALIGN);
 310
 311         hw->rx_cntxt_rsp =
 312                 (q80_rcv_cntxt_rsp_t *)((uint8_t *)hw->rx_cntxt_req + size);
 313         hw->rx_cntxt_rsp_paddr = hw->rx_cntxt_req_paddr + size;
 314
 315         size = QL_ALIGN((sizeof (q80_rcv_cntxt_rsp_t)), QL_BUFFER_ALIGN);
 316
 317         hw->tx_cons = (uint32_t *)((uint8_t *)hw->rx_cntxt_rsp + size);
 318         hw->tx_cons_paddr = hw->rx_cntxt_rsp_paddr + size;
 319
 320         /*
 321          * Initialize the Transmit Context Request so that we don't need to
 322          * do it everytime we need to create a context
 323          */
 324         tx_cntxt_req = hw->tx_cntxt_req;
 325
 326         tx_cntxt_req->rsp_dma_addr = qla_host_to_le64(hw->tx_cntxt_rsp_paddr);
 327
 328         tx_cntxt_req->cmd_cons_dma_addr = qla_host_to_le64(hw->tx_cons_paddr);
 329
 330         tx_cntxt_req->caps[0] = qla_host_to_le32((CNTXT_CAP0_BASEFW |
 331                                         CNTXT_CAP0_LEGACY_MN | CNTXT_CAP0_LSO));
 332
 333         tx_cntxt_req->intr_mode = qla_host_to_le32(CNTXT_INTR_MODE_SHARED);
 334
 335         tx_cntxt_req->phys_addr =
 336                 qla_host_to_le64(hw->dma_buf.tx_ring.dma_addr);
 337
 338         tx_cntxt_req->num_entries = qla_host_to_le32(NUM_TX_DESCRIPTORS);
 339
 340         /*
 341          * Initialize the Receive Context Request
 342          */
 343
 344         rx_cntxt_req = hw->rx_cntxt_req;
 345
 346         rx_cntxt_req->rx_req.rsp_dma_addr =
 347                 qla_host_to_le64(hw->rx_cntxt_rsp_paddr);
 348
 349         rx_cntxt_req->rx_req.caps[0] = qla_host_to_le32(CNTXT_CAP0_BASEFW |
 350                                                 CNTXT_CAP0_LEGACY_MN |
 351                                                 CNTXT_CAP0_JUMBO |
 352                                                 CNTXT_CAP0_LRO|
 353                                                 CNTXT_CAP0_HW_LRO);
 354
 355         rx_cntxt_req->rx_req.intr_mode =
 356                 qla_host_to_le32(CNTXT_INTR_MODE_SHARED);
 357
 358         rx_cntxt_req->rx_req.rds_intr_mode =
 359                 qla_host_to_le32(CNTXT_INTR_MODE_UNIQUE);
 360
 361         rx_cntxt_req->rx_req.rds_ring_offset = 0;
 362         rx_cntxt_req->rx_req.sds_ring_offset = qla_host_to_le32(
 363                 (hw->num_rds_rings * sizeof(q80_rq_rds_ring_t)));
 364         rx_cntxt_req->rx_req.num_rds_rings =
 365                 qla_host_to_le16(hw->num_rds_rings);
 366         rx_cntxt_req->rx_req.num_sds_rings =
 367                 qla_host_to_le16(hw->num_sds_rings);
 368
 369         for (i = 0; i < hw->num_rds_rings; i++) {
 370                 rx_cntxt_req->rds_req[i].phys_addr =
 371                         qla_host_to_le64(hw->dma_buf.rds_ring[i].dma_addr);
 372
 373                 if (i == RDS_RING_INDEX_NORMAL) {
 374                         rx_cntxt_req->rds_req[i].buf_size =
 375                                 qla_host_to_le64(MCLBYTES);
 376                         rx_cntxt_req->rds_req[i].size =
 377                                 qla_host_to_le32(NUM_RX_DESCRIPTORS);
 378                 } else {
 379                         rx_cntxt_req->rds_req[i].buf_size =
 380                                 qla_host_to_le64(MJUM9BYTES);
 381                         rx_cntxt_req->rds_req[i].size =
 382                                 qla_host_to_le32(NUM_RX_JUMBO_DESCRIPTORS);
 383                 }
 384         }
 385
 386         for (i = 0; i < hw->num_sds_rings; i++) {
 387                 rx_cntxt_req->sds_req[i].phys_addr =
 388                         qla_host_to_le64(hw->dma_buf.sds_ring[i].dma_addr);
 389                 rx_cntxt_req->sds_req[i].size =
 390                         qla_host_to_le32(NUM_STATUS_DESCRIPTORS);
 391                 rx_cntxt_req->sds_req[i].msi_index = qla_host_to_le16(i);
 392         }
 393
 394         QL_DPRINT2((ha->pci_dev, "%s: tx_cntxt_req = %p paddr %p\n",
 395                 __func__, hw->tx_cntxt_req, (void *)hw->tx_cntxt_req_paddr));
 396         QL_DPRINT2((ha->pci_dev, "%s: tx_cntxt_rsp = %p paddr %p\n",
 397                 __func__, hw->tx_cntxt_rsp, (void *)hw->tx_cntxt_rsp_paddr));
 398         QL_DPRINT2((ha->pci_dev, "%s: rx_cntxt_req = %p paddr %p\n",
 399                 __func__, hw->rx_cntxt_req, (void *)hw->rx_cntxt_req_paddr));
 400         QL_DPRINT2((ha->pci_dev, "%s: rx_cntxt_rsp = %p paddr %p\n",
 401                 __func__, hw->rx_cntxt_rsp, (void *)hw->rx_cntxt_rsp_paddr));
 402         QL_DPRINT2((ha->pci_dev, "%s: tx_cons      = %p paddr %p\n",
 403                 __func__, hw->tx_cons, (void *)hw->tx_cons_paddr));
 404 }
 405
 406 /*
 407  * Name: qla_issue_cmd
 408  * Function: Issues commands on the CDRP interface and returns responses.
 409  */
 410 static int
 411 qla_issue_cmd(qla_host_t *ha, qla_cdrp_t *cdrp)
 412 {
 413         int     ret = 0;
 414         uint32_t signature;
 415         uint32_t count = 400; /* 4 seconds or 400 10ms intervals */
 416         uint32_t data;
 417         device_t dev;
 418
 419         dev = ha->pci_dev;
 420
 421         signature = 0xcafe0000 | 0x0100 | ha->pci_func;
 422
 423         ret = qla_sem_lock(ha, Q8_SEM5_LOCK, 0, (uint32_t)ha->pci_func);
 424
 425         if (ret) {
 426                 device_printf(dev, "%s: SEM5_LOCK lock failed\n", __func__);
 427                 return (ret);
 428         }
 429
 430         WRITE_OFFSET32(ha, Q8_NX_CDRP_SIGNATURE, signature);
 431
 432         WRITE_OFFSET32(ha, Q8_NX_CDRP_ARG1, (cdrp->cmd_arg1));
 433         WRITE_OFFSET32(ha, Q8_NX_CDRP_ARG2, (cdrp->cmd_arg2));
 434         WRITE_OFFSET32(ha, Q8_NX_CDRP_ARG3, (cdrp->cmd_arg3));
 435
 436         WRITE_OFFSET32(ha, Q8_NX_CDRP_CMD_RSP, cdrp->cmd);
 437
 438         while (count) {
 439                 qla_mdelay(__func__, 10);
 440
 441                 data = READ_REG32(ha, Q8_NX_CDRP_CMD_RSP);
 442
 443                 if ((!(data & 0x80000000)))
 444                         break;
 445                 count--;
 446         }
 447         if ((!count) || (data != 1))
 448                 ret = -1;
 449
 450         cdrp->rsp = READ_REG32(ha, Q8_NX_CDRP_CMD_RSP);
 451         cdrp->rsp_arg1 = READ_REG32(ha, Q8_NX_CDRP_ARG1);
 452         cdrp->rsp_arg2 = READ_REG32(ha, Q8_NX_CDRP_ARG2);
 453         cdrp->rsp_arg3 = READ_REG32(ha, Q8_NX_CDRP_ARG3);
 454
 455         qla_sem_unlock(ha, Q8_SEM5_UNLOCK);
 456
 457         if (ret) {
 458                 device_printf(dev, "%s: "
 459                         "cmd[0x%08x] = 0x%08x\n"
 460                         "\tsig[0x%08x] = 0x%08x\n"
 461                         "\targ1[0x%08x] = 0x%08x\n"
 462                         "\targ2[0x%08x] = 0x%08x\n"
 463                         "\targ3[0x%08x] = 0x%08x\n",
 464                         __func__, Q8_NX_CDRP_CMD_RSP, cdrp->cmd,
 465                         Q8_NX_CDRP_SIGNATURE, signature,
 466                         Q8_NX_CDRP_ARG1, cdrp->cmd_arg1,
 467                         Q8_NX_CDRP_ARG2, cdrp->cmd_arg2,
 468                         Q8_NX_CDRP_ARG3, cdrp->cmd_arg3);
 469
 470                 device_printf(dev, "%s: exit (ret = 0x%x)\n"
 471                         "\t\t rsp = 0x%08x\n"
 472                         "\t\t arg1 = 0x%08x\n"
 473                         "\t\t arg2 = 0x%08x\n"
 474                         "\t\t arg3 = 0x%08x\n",
 475                         __func__, ret, cdrp->rsp,
 476                         cdrp->rsp_arg1, cdrp->rsp_arg2, cdrp->rsp_arg3);
 477         }
 478
 479         return (ret);
 480 }
 481
 482 #define QLA_TX_MIN_FREE 2
 483
 484 /*
 485  * Name: qla_fw_cmd
 486  * Function: Issues firmware control commands on the Tx Ring.
 487  */
 488 static int
 489 qla_fw_cmd(qla_host_t *ha, void *fw_cmd, uint32_t size)
 490 {
 491         device_t dev;
 492         q80_tx_cmd_t *tx_cmd;
 493         qla_hw_t *hw = &ha->hw;
 494         int count = 100;
 495
 496         dev = ha->pci_dev;
 497
 498         QLA_TX_LOCK(ha);
 499
 500         if (hw->txr_free <= QLA_TX_MIN_FREE) {
 501                 while (count--) {
 502                         qla_hw_tx_done_locked(ha);
 503                         if (hw->txr_free > QLA_TX_MIN_FREE)
 504                                 break;
 505
 506                         QLA_TX_UNLOCK(ha);
 507                         qla_mdelay(__func__, 10);
 508                         QLA_TX_LOCK(ha);
 509                 }
 510                 if (hw->txr_free <= QLA_TX_MIN_FREE) {
 511                         QLA_TX_UNLOCK(ha);
 512                         device_printf(dev, "%s: xmit queue full\n", __func__);
 513                         return (-1);
 514                 }
 515         }
 516         tx_cmd = &hw->tx_ring_base[hw->txr_next];
 517
 518         bzero((void *)tx_cmd, sizeof(q80_tx_cmd_t));
 519
 520         bcopy(fw_cmd, tx_cmd, size);
 521
 522         hw->txr_next = (hw->txr_next + 1) & (NUM_TX_DESCRIPTORS - 1);
 523         hw->txr_free--;
 524
 525         QL_UPDATE_TX_PRODUCER_INDEX(ha, hw->txr_next);
 526
 527         QLA_TX_UNLOCK(ha);
 528
 529         return (0);
 530 }
 531
 532 /*
 533  * Name: qla_config_rss
 534  * Function: Configure RSS for the context/interface.
 535  */
 536 const uint64_t rss_key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
 537                         0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
 538                         0x255b0ec26d5a56daULL };
 539
 540 static int
 541 qla_config_rss(qla_host_t *ha, uint16_t cntxt_id)
 542 {
 543         qla_fw_cds_config_rss_t rss_config;
 544         int ret, i;
 545
 546         bzero(&rss_config, sizeof(qla_fw_cds_config_rss_t));
 547
 548         rss_config.hdr.cmd = Q8_FWCD_CNTRL_REQ;
 549         rss_config.hdr.opcode = Q8_FWCD_OPCODE_CONFIG_RSS;
 550         rss_config.hdr.cntxt_id = cntxt_id;
 551
 552         rss_config.hash_type = (Q8_FWCD_RSS_HASH_TYPE_IPV4_TCP_IP |
 553                                         Q8_FWCD_RSS_HASH_TYPE_IPV6_TCP_IP);
 554         rss_config.flags = Q8_FWCD_RSS_FLAGS_ENABLE_RSS;
 555
 556         rss_config.ind_tbl_mask = 0x7;
 557
 558         for (i = 0; i < 5; i++)
 559                 rss_config.rss_key[i] = rss_key[i];
 560
 561         ret = qla_fw_cmd(ha, &rss_config, sizeof(qla_fw_cds_config_rss_t));
 562
 563         return ret;
 564 }
 565
 566 /*
 567  * Name: qla_config_intr_coalesce
 568  * Function: Configure Interrupt Coalescing.
 569  */
 570 static int
 571 qla_config_intr_coalesce(qla_host_t *ha, uint16_t cntxt_id, int tenable)
 572 {
 573         qla_fw_cds_config_intr_coalesc_t intr_coalesce;
 574         int ret;
 575
 576         bzero(&intr_coalesce, sizeof(qla_fw_cds_config_intr_coalesc_t));
 577
 578         intr_coalesce.hdr.cmd = Q8_FWCD_CNTRL_REQ;
 579         intr_coalesce.hdr.opcode = Q8_FWCD_OPCODE_CONFIG_INTR_COALESCING;
 580         intr_coalesce.hdr.cntxt_id = cntxt_id;
 581
 582         intr_coalesce.flags = 0x04;
 583         intr_coalesce.max_rcv_pkts = 256;
 584         intr_coalesce.max_rcv_usecs = 3;
 585         intr_coalesce.max_snd_pkts = 64;
 586         intr_coalesce.max_snd_usecs = 4;
 587
 588         if (tenable) {
 589                 intr_coalesce.usecs_to = 1000; /* 1 millisecond */
 590                 intr_coalesce.timer_type = Q8_FWCMD_INTR_COALESC_TIMER_PERIODIC;
 591                 intr_coalesce.sds_ring_bitmask =
 592                         Q8_FWCMD_INTR_COALESC_SDS_RING_0;
 593         }
 594
 595         ret = qla_fw_cmd(ha, &intr_coalesce,
 596                         sizeof(qla_fw_cds_config_intr_coalesc_t));
 597
 598         return ret;
 599 }
 600
 601
 602 /*
 603  * Name: qla_config_mac_addr
 604  * Function: binds a MAC address to the context/interface.
 605  *      Can be unicast, multicast or broadcast.
 606  */
 607 static int
 608 qla_config_mac_addr(qla_host_t *ha, uint8_t *mac_addr, uint16_t cntxt_id,
 609         uint32_t add_multi)
 610 {
 611         qla_fw_cds_config_mac_addr_t mac_config;
 612         int ret;
 613
 614 //      device_printf(ha->pci_dev,
 615 //              "%s: mac_addr %02x:%02x:%02x:%02x:%02x:%02x\n", __func__,
 616 //              mac_addr[0], mac_addr[1], mac_addr[2],
 617 //              mac_addr[3], mac_addr[4], mac_addr[5]);
 618
 619         bzero(&mac_config, sizeof(qla_fw_cds_config_mac_addr_t));
 620
 621         mac_config.hdr.cmd = Q8_FWCD_CNTRL_REQ;
 622         mac_config.hdr.opcode = Q8_FWCD_OPCODE_CONFIG_MAC_ADDR;
 623         mac_config.hdr.cntxt_id = cntxt_id;
 624
 625         if (add_multi)
 626                 mac_config.cmd = Q8_FWCD_ADD_MAC_ADDR;
 627         else
 628                 mac_config.cmd = Q8_FWCD_DEL_MAC_ADDR;
 629         bcopy(mac_addr, mac_config.mac_addr,6);
 630
 631         ret = qla_fw_cmd(ha, &mac_config, sizeof(qla_fw_cds_config_mac_addr_t));
 632
 633         return ret;
 634 }
 635
 636
 637 /*
 638  * Name: qla_set_mac_rcv_mode
 639  * Function: Enable/Disable AllMulticast and Promiscous Modes.
 640  */
 641 static int
 642 qla_set_mac_rcv_mode(qla_host_t *ha, uint16_t cntxt_id, uint32_t mode)
 643 {
 644         qla_set_mac_rcv_mode_t rcv_mode;
 645         int ret;
 646
 647         bzero(&rcv_mode, sizeof(qla_set_mac_rcv_mode_t));
 648
 649         rcv_mode.hdr.cmd = Q8_FWCD_CNTRL_REQ;
 650         rcv_mode.hdr.opcode = Q8_FWCD_OPCODE_CONFIG_MAC_RCV_MODE;
 651         rcv_mode.hdr.cntxt_id = cntxt_id;
 652
 653         rcv_mode.mode = mode;
 654
 655         ret = qla_fw_cmd(ha, &rcv_mode, sizeof(qla_set_mac_rcv_mode_t));
 656
 657         return ret;
 658 }
 659
 660 void
 661 qla_set_promisc(qla_host_t *ha)
 662 {
 663         (void)qla_set_mac_rcv_mode(ha,
 664                 (ha->hw.rx_cntxt_rsp)->rx_rsp.cntxt_id,
 665                 Q8_MAC_RCV_ENABLE_PROMISCUOUS);
 666 }
 667
 668 void
 669 qla_set_allmulti(qla_host_t *ha)
 670 {
 671         (void)qla_set_mac_rcv_mode(ha,
 672                 (ha->hw.rx_cntxt_rsp)->rx_rsp.cntxt_id,
 673                 Q8_MAC_RCV_ENABLE_ALLMULTI);
 674 }
 675
 676 void
 677 qla_reset_promisc_allmulti(qla_host_t *ha)
 678 {
 679         (void)qla_set_mac_rcv_mode(ha,
 680                 (ha->hw.rx_cntxt_rsp)->rx_rsp.cntxt_id,
 681                 Q8_MAC_RCV_RESET_PROMISC_ALLMULTI);
 682 }
 683
 684 /*
 685  * Name: qla_config_ipv4_addr
 686  * Function: Configures the Destination IP Addr for LRO.
 687  */
 688 void
 689 qla_config_ipv4_addr(qla_host_t *ha, uint32_t ipv4_addr)
 690 {
 691         qla_config_ipv4_t ip_conf;
 692
 693         bzero(&ip_conf, sizeof(qla_config_ipv4_t));
 694
 695         ip_conf.hdr.cmd = Q8_FWCD_CNTRL_REQ;
 696         ip_conf.hdr.opcode = Q8_FWCD_OPCODE_CONFIG_IPADDR;
 697         ip_conf.hdr.cntxt_id = (ha->hw.rx_cntxt_rsp)->rx_rsp.cntxt_id;
 698
 699         ip_conf.cmd = (uint64_t)Q8_CONFIG_CMD_IP_ENABLE;
 700         ip_conf.ipv4_addr = (uint64_t)ipv4_addr;
 701
 702         (void)qla_fw_cmd(ha, &ip_conf, sizeof(qla_config_ipv4_t));
 703
 704         return;
 705 }
 706
 707 /*
 708  * Name: qla_tx_tso
 709  * Function: Checks if the packet to be transmitted is a candidate for
 710  *      Large TCP Segment Offload. If yes, the appropriate fields in the Tx
 711  *      Ring Structure are plugged in.
 712  */
 713 static int
 714 qla_tx_tso(qla_host_t *ha, struct mbuf *mp, q80_tx_cmd_t *tx_cmd)
 715 {
 716         struct ether_vlan_header *eh;
 717         struct ip *ip = NULL;
 718         struct tcphdr *th = NULL;
 719         uint32_t ehdrlen,  hdrlen, ip_hlen, tcp_hlen;
 720         uint16_t etype, opcode, offload = 1;
 721         device_t dev;
 722
 723         dev = ha->pci_dev;
 724
 725         if (mp->m_pkthdr.len <= ha->max_frame_size)
 726                 return (-1);
 727
 728         eh = mtod(mp, struct ether_vlan_header *);
 729
 730         if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
 731                 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
 732                 etype = ntohs(eh->evl_proto);
 733         } else {
 734                 ehdrlen = ETHER_HDR_LEN;
 735                 etype = ntohs(eh->evl_encap_proto);
 736         }
 737
 738         switch (etype) {
 739                 case ETHERTYPE_IP:
 740                         ip = (struct ip *)(mp->m_data + ehdrlen);
 741                         ip_hlen = ip->ip_hl << 2;
 742                         opcode = Q8_TX_CMD_OP_XMT_TCP_LSO;
 743
 744                         if (ip->ip_p != IPPROTO_TCP) {
 745                                 offload = 0;
 746                         } else
 747                                 th = (struct tcphdr *)((caddr_t)ip + ip_hlen);
 748                 break;
 749
 750                 default:
 751                         QL_DPRINT8((dev, "%s: type!=ip\n", __func__));
 752                         offload = 0;
 753                 break;
 754         }
 755
 756         if (!offload)
 757                 return (-1);
 758
 759         tcp_hlen = th->th_off << 2;
 760
 761         hdrlen = ehdrlen + ip_hlen + tcp_hlen;
 762
 763         if (mp->m_len < hdrlen) {
 764                 device_printf(dev, "%s: (mp->m_len < hdrlen)\n", __func__);
 765                 return (-1);
 766         }
 767
 768         tx_cmd->flags_opcode = opcode ;
 769         tx_cmd->tcp_hdr_off = ip_hlen + ehdrlen;
 770         tx_cmd->ip_hdr_off = ehdrlen;
 771         tx_cmd->mss = mp->m_pkthdr.tso_segsz;
 772         tx_cmd->total_hdr_len = hdrlen;
 773
 774         /* Check for Multicast least significant bit of MSB == 1 */
 775         if (eh->evl_dhost[0] & 0x01) {
 776                 tx_cmd->flags_opcode = Q8_TX_CMD_FLAGS_MULTICAST;
 777         }
 778
 779         return (0);
 780 }
 781
 782 /*
 783  * Name: qla_tx_chksum
 784  * Function: Checks if the packet to be transmitted is a candidate for
 785  *      TCP/UDP Checksum offload. If yes, the appropriate fields in the Tx
 786  *      Ring Structure are plugged in.
 787  */
 788 static int
 789 qla_tx_chksum(qla_host_t *ha, struct mbuf *mp, q80_tx_cmd_t *tx_cmd)
 790 {
 791         struct ether_vlan_header *eh;
 792         struct ip *ip;
 793         struct ip6_hdr *ip6;
 794         uint32_t ehdrlen, ip_hlen;
 795         uint16_t etype, opcode, offload = 1;
 796         device_t dev;
 797
 798         dev = ha->pci_dev;
 799
 800         if ((mp->m_pkthdr.csum_flags & (CSUM_TCP|CSUM_UDP)) == 0)
 801                 return (-1);
 802
 803         eh = mtod(mp, struct ether_vlan_header *);
 804
 805         if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
 806                 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
 807                 etype = ntohs(eh->evl_proto);
 808         } else {
 809                 ehdrlen = ETHER_HDR_LEN;
 810                 etype = ntohs(eh->evl_encap_proto);
 811         }
 812
 813
 814         switch (etype) {
 815                 case ETHERTYPE_IP:
 816                         ip = (struct ip *)(mp->m_data + ehdrlen);
 817
 818                         ip_hlen = ip->ip_hl << 2;
 819
 820                         if (mp->m_len < (ehdrlen + ip_hlen)) {
 821                                 device_printf(dev, "%s: ipv4 mlen\n", __func__);
 822                                 offload = 0;
 823                                 break;
 824                         }
 825
 826                         if (ip->ip_p == IPPROTO_TCP)
 827                                 opcode = Q8_TX_CMD_OP_XMT_TCP_CHKSUM;
 828                         else if (ip->ip_p == IPPROTO_UDP)
 829                                 opcode = Q8_TX_CMD_OP_XMT_UDP_CHKSUM;
 830                         else {
 831                                 device_printf(dev, "%s: ipv4\n", __func__);
 832                                 offload = 0;
 833                         }
 834                 break;
 835
 836                 case ETHERTYPE_IPV6:
 837                         ip6 = (struct ip6_hdr *)(mp->m_data + ehdrlen);
 838
 839                         ip_hlen = sizeof(struct ip6_hdr);
 840
 841                         if (mp->m_len < (ehdrlen + ip_hlen)) {
 842                                 device_printf(dev, "%s: ipv6 mlen\n", __func__);
 843                                 offload = 0;
 844                                 break;
 845                         }
 846
 847                         if (ip6->ip6_nxt == IPPROTO_TCP)
 848                                 opcode = Q8_TX_CMD_OP_XMT_TCP_CHKSUM_IPV6;
 849                         else if (ip6->ip6_nxt == IPPROTO_UDP)
 850                                 opcode = Q8_TX_CMD_OP_XMT_UDP_CHKSUM_IPV6;
 851                         else {
 852                                 device_printf(dev, "%s: ipv6\n", __func__);
 853                                 offload = 0;
 854                         }
 855                 break;
 856
 857                 default:
 858                         offload = 0;
 859                 break;
 860         }
 861         if (!offload)
 862                 return (-1);
 863
 864         tx_cmd->flags_opcode = opcode;
 865
 866         tx_cmd->tcp_hdr_off = ip_hlen + ehdrlen;
 867
 868         return (0);
 869 }
 870
 871 /*
 872  * Name: qla_hw_send
 873  * Function: Transmits a packet. It first checks if the packet is a
 874  *      candidate for Large TCP Segment Offload and then for UDP/TCP checksum
 875  *      offload. If either of these creteria are not met, it is transmitted
 876  *      as a regular ethernet frame.
 877  */
 878 int
 879 qla_hw_send(qla_host_t *ha, bus_dma_segment_t *segs, int nsegs,
 880         uint32_t *tx_idx,  struct mbuf *mp)
 881 {
 882         struct ether_vlan_header *eh;
 883         qla_hw_t *hw = &ha->hw;
 884         q80_tx_cmd_t *tx_cmd, tso_cmd;
 885         bus_dma_segment_t *c_seg;
 886         uint32_t num_tx_cmds, hdr_len = 0;
 887         uint32_t total_length = 0, bytes, tx_cmd_count = 0;
 888         device_t dev;
 889         int i;
 890
 891         dev = ha->pci_dev;
 892
 893         /*
 894          * Always make sure there is atleast one empty slot in the tx_ring
 895          * tx_ring is considered full when there only one entry available
 896          */
 897         num_tx_cmds = (nsegs + (Q8_TX_CMD_MAX_SEGMENTS - 1)) >> 2;
 898
 899         total_length = mp->m_pkthdr.len;
 900         if (total_length > QLA_MAX_TSO_FRAME_SIZE) {
 901                 device_printf(dev, "%s: total length exceeds maxlen(%d)\n",
 902                         __func__, total_length);
 903                 return (-1);
 904         }
 905
 906         bzero((void *)&tso_cmd, sizeof(q80_tx_cmd_t));
 907
 908         if (qla_tx_tso(ha, mp, &tso_cmd) == 0) {
 909                 /* find the additional tx_cmd descriptors required */
 910
 911                 hdr_len = tso_cmd.total_hdr_len;
 912
 913                 bytes = sizeof(q80_tx_cmd_t) - Q8_TX_CMD_TSO_ALIGN;
 914                 bytes = QL_MIN(bytes, hdr_len);
 915
 916                 num_tx_cmds++;
 917                 hdr_len -= bytes;
 918
 919                 while (hdr_len) {
 920                         bytes = QL_MIN((sizeof(q80_tx_cmd_t)), hdr_len);
 921                         hdr_len -= bytes;
 922                         num_tx_cmds++;
 923                 }
 924                 hdr_len = tso_cmd.total_hdr_len;
 925         }
 926
 927         if (hw->txr_free <= (num_tx_cmds + QLA_TX_MIN_FREE)) {
 928                 qla_hw_tx_done_locked(ha);
 929                 if (hw->txr_free <= (num_tx_cmds + QLA_TX_MIN_FREE)) {
 930                         QL_DPRINT8((dev, "%s: (hw->txr_free <= "
 931                                 "(num_tx_cmds + QLA_TX_MIN_FREE))\n",
 932                                 __func__));
 933                         return (-1);
 934                 }
 935         }
 936
 937         *tx_idx = hw->txr_next;
 938
 939         tx_cmd = &hw->tx_ring_base[hw->txr_next];
 940
 941         if (hdr_len == 0) {
 942                 if ((nsegs > Q8_TX_MAX_SEGMENTS) ||
 943                         (mp->m_pkthdr.len > ha->max_frame_size)){
 944                         device_printf(dev,
 945                                 "%s: (nsegs[%d, %d, 0x%x] > Q8_TX_MAX_SEGMENTS)\n",
 946                                 __func__, nsegs, mp->m_pkthdr.len,
 947                                 mp->m_pkthdr.csum_flags);
 948                         qla_dump_buf8(ha, "qla_hw_send: wrong pkt",
 949                                 mtod(mp, char *), mp->m_len);
 950                         return (EINVAL);
 951                 }
 952                 bzero((void *)tx_cmd, sizeof(q80_tx_cmd_t));
 953                 if (qla_tx_chksum(ha, mp, tx_cmd) != 0)
 954                         tx_cmd->flags_opcode = Q8_TX_CMD_OP_XMT_ETHER;
 955         } else {
 956                 bcopy(&tso_cmd, tx_cmd, sizeof(q80_tx_cmd_t));
 957         }
 958
 959         eh = mtod(mp, struct ether_vlan_header *);
 960         if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN))
 961                 tx_cmd->flags_opcode |= Q8_TX_CMD_FLAGS_VLAN_TAGGED;
 962         else if (mp->m_flags & M_VLANTAG) {
 963                 tx_cmd->flags_opcode |= (Q8_TX_CMD_FLAGS_VLAN_TAGGED |
 964                                                 Q8_TX_CMD_FLAGS_HW_VLAN_ID);
 965                 tx_cmd->vlan_tci = mp->m_pkthdr.ether_vtag;
 966         }
 967
 968
 969         tx_cmd->n_bufs = (uint8_t)nsegs;
 970         tx_cmd->data_len_lo = (uint8_t)(total_length & 0xFF);
 971         tx_cmd->data_len_hi = qla_host_to_le16(((uint16_t)(total_length >> 8)));
 972         tx_cmd->port_cntxtid = Q8_TX_CMD_PORT_CNXTID(ha->pci_func);
 973
 974         c_seg = segs;
 975
 976         while (1) {
 977                 for (i = 0; ((i < Q8_TX_CMD_MAX_SEGMENTS) && nsegs); i++) {
 978
 979                         switch (i) {
 980                         case 0:
 981                                 tx_cmd->buf1_addr = c_seg->ds_addr;
 982                                 tx_cmd->buf1_len = c_seg->ds_len;
 983                                 break;
 984
 985                         case 1:
 986                                 tx_cmd->buf2_addr = c_seg->ds_addr;
 987                                 tx_cmd->buf2_len = c_seg->ds_len;
 988                                 break;
 989
 990                         case 2:
 991                                 tx_cmd->buf3_addr = c_seg->ds_addr;
 992                                 tx_cmd->buf3_len = c_seg->ds_len;
 993                                 break;
 994
 995                         case 3:
 996                                 tx_cmd->buf4_addr = c_seg->ds_addr;
 997                                 tx_cmd->buf4_len = c_seg->ds_len;
 998                                 break;
 999                         }
1000
1001                         c_seg++;
1002                         nsegs--;
1003                 }
1004
1005                 hw->txr_next = (hw->txr_next + 1) & (NUM_TX_DESCRIPTORS - 1);
1006                 tx_cmd_count++;
1007
1008                 if (!nsegs)
1009                         break;
1010
1011                 tx_cmd = &hw->tx_ring_base[hw->txr_next];
1012                 bzero((void *)tx_cmd, sizeof(q80_tx_cmd_t));
1013         }
1014
1015         if (hdr_len) {
1016                 /* TSO : Copy the header in the following tx cmd descriptors */
1017                 uint8_t *src, *dst;
1018
1019                 src = (uint8_t *)eh;
1020
1021                 tx_cmd = &hw->tx_ring_base[hw->txr_next];
1022                 bzero((void *)tx_cmd, sizeof(q80_tx_cmd_t));
1023
1024                 bytes = sizeof(q80_tx_cmd_t) - Q8_TX_CMD_TSO_ALIGN;
1025                 bytes = QL_MIN(bytes, hdr_len);
1026
1027                 dst = (uint8_t *)tx_cmd + Q8_TX_CMD_TSO_ALIGN;
1028
1029                 if (mp->m_flags & M_VLANTAG) {
1030                         /* first copy the src/dst MAC addresses */
1031                         bcopy(src, dst, (ETHER_ADDR_LEN * 2));
1032                         dst += (ETHER_ADDR_LEN * 2);
1033                         src += (ETHER_ADDR_LEN * 2);
1034
1035                         hdr_len -= (ETHER_ADDR_LEN * 2);
1036
1037                         *((uint16_t *)dst) = htons(ETHERTYPE_VLAN);
1038                         dst += 2;
1039                         *((uint16_t *)dst) = mp->m_pkthdr.ether_vtag;
1040                         dst += 2;
1041
1042                         bytes -= ((ETHER_ADDR_LEN * 2) + 4);
1043
1044                         bcopy(src, dst, bytes);
1045                         src += bytes;
1046                         hdr_len -= bytes;
1047                 } else {
1048                         bcopy(src, dst, bytes);
1049                         src += bytes;
1050                         hdr_len -= bytes;
1051                 }
1052
1053                 hw->txr_next = (hw->txr_next + 1) & (NUM_TX_DESCRIPTORS - 1);
1054                 tx_cmd_count++;
1055
1056                 while (hdr_len) {
1057                         tx_cmd = &hw->tx_ring_base[hw->txr_next];
1058                         bzero((void *)tx_cmd, sizeof(q80_tx_cmd_t));
1059
1060                         bytes = QL_MIN((sizeof(q80_tx_cmd_t)), hdr_len);
1061
1062                         bcopy(src, tx_cmd, bytes);
1063                         src += bytes;
1064                         hdr_len -= bytes;
1065                         hw->txr_next =
1066                                 (hw->txr_next + 1) & (NUM_TX_DESCRIPTORS - 1);
1067                         tx_cmd_count++;
1068                 }
1069         }
1070
1071         hw->txr_free = hw->txr_free - tx_cmd_count;
1072
1073         QL_UPDATE_TX_PRODUCER_INDEX(ha, hw->txr_next);
1074         QL_DPRINT8((dev, "%s: return\n", __func__));
1075         return (0);
1076 }
1077
1078 /*
1079  * Name: qla_del_hw_if
1080  * Function: Destroys the hardware specific entities corresponding to an
1081  *      Ethernet Interface
1082  */
1083 void
1084 qla_del_hw_if(qla_host_t *ha)
1085 {
1086         int     i;
1087
1088         for (i = 0; i < ha->hw.num_sds_rings; i++)
1089                 QL_DISABLE_INTERRUPTS(ha, i);
1090
1091         qla_del_rcv_cntxt(ha);
1092         qla_del_xmt_cntxt(ha);
1093
1094         ha->hw.flags.lro = 0;
1095 }
1096
1097 /*
1098  * Name: qla_init_hw_if
1099  * Function: Creates the hardware specific entities corresponding to an
1100  *      Ethernet Interface - Transmit and Receive Contexts. Sets the MAC Address
1101  *      corresponding to the interface. Enables LRO if allowed.
1102  */
1103 int
1104 qla_init_hw_if(qla_host_t *ha)
1105 {
1106         device_t        dev;
1107         int             i;
1108         uint8_t         bcast_mac[6];
1109
1110         qla_get_hw_caps(ha);
1111
1112         dev = ha->pci_dev;
1113
1114         for (i = 0; i < ha->hw.num_sds_rings; i++) {
1115                 bzero(ha->hw.dma_buf.sds_ring[i].dma_b,
1116                         ha->hw.dma_buf.sds_ring[i].size);
1117         }
1118         /*
1119          * Create Receive Context
1120          */
1121         if (qla_init_rcv_cntxt(ha)) {
1122                 return (-1);
1123         }
1124
1125         ha->hw.rx_next = NUM_RX_DESCRIPTORS - 2;
1126         ha->hw.rxj_next = NUM_RX_JUMBO_DESCRIPTORS - 2;
1127         ha->hw.rx_in = ha->hw.rxj_in = 0;
1128
1129         /* Update the RDS Producer Indices */
1130         QL_UPDATE_RDS_PRODUCER_INDEX(ha, 0, ha->hw.rx_next);
1131         QL_UPDATE_RDS_PRODUCER_INDEX(ha, 1, ha->hw.rxj_next);
1132
1133         /*
1134          * Create Transmit Context
1135          */
1136         if (qla_init_xmt_cntxt(ha)) {
1137                 qla_del_rcv_cntxt(ha);
1138                 return (-1);
1139         }
1140
1141         qla_config_mac_addr(ha, ha->hw.mac_addr,
1142                 (ha->hw.rx_cntxt_rsp)->rx_rsp.cntxt_id, 1);
1143
1144         bcast_mac[0] = 0xFF; bcast_mac[1] = 0xFF; bcast_mac[2] = 0xFF;
1145         bcast_mac[3] = 0xFF; bcast_mac[4] = 0xFF; bcast_mac[5] = 0xFF;
1146         qla_config_mac_addr(ha, bcast_mac,
1147                 (ha->hw.rx_cntxt_rsp)->rx_rsp.cntxt_id, 1);
1148
1149         qla_config_rss(ha, (ha->hw.rx_cntxt_rsp)->rx_rsp.cntxt_id);
1150
1151         qla_config_intr_coalesce(ha, (ha->hw.rx_cntxt_rsp)->rx_rsp.cntxt_id, 0);
1152
1153         for (i = 0; i < ha->hw.num_sds_rings; i++)
1154                 QL_ENABLE_INTERRUPTS(ha, i);
1155
1156         return (0);
1157 }
1158
1159 /*
1160  * Name: qla_init_rcv_cntxt
1161  * Function: Creates the Receive Context.
1162  */
1163 static int
1164 qla_init_rcv_cntxt(qla_host_t *ha)
1165 {
1166         device_t                dev;
1167         qla_cdrp_t              cdrp;
1168         q80_rcv_cntxt_rsp_t     *rsp;
1169         q80_stat_desc_t         *sdesc;
1170         bus_addr_t              phys_addr;
1171         int                     i, j;
1172         qla_hw_t                *hw = &ha->hw;
1173
1174         dev = ha->pci_dev;
1175
1176         /*
1177          * Create Receive Context
1178          */
1179
1180         for (i = 0; i < hw->num_sds_rings; i++) {
1181                 sdesc = (q80_stat_desc_t *)&hw->sds[i].sds_ring_base[0];
1182                 for (j = 0; j < NUM_STATUS_DESCRIPTORS; j++) {
1183                         sdesc->data[0] =
1184                                 Q8_STAT_DESC_SET_OWNER(Q8_STAT_DESC_OWNER_FW);
1185                 }
1186         }
1187
1188         phys_addr = ha->hw.rx_cntxt_req_paddr;
1189
1190         bzero(&cdrp, sizeof(qla_cdrp_t));
1191
1192         cdrp.cmd = Q8_CMD_CREATE_RX_CNTXT;
1193         cdrp.cmd_arg1 = (uint32_t)(phys_addr >> 32);
1194         cdrp.cmd_arg2 = (uint32_t)(phys_addr);
1195         cdrp.cmd_arg3 = (uint32_t)(sizeof (q80_rcv_cntxt_req_t));
1196
1197         if (qla_issue_cmd(ha, &cdrp)) {
1198                 device_printf(dev, "%s: Q8_CMD_CREATE_RX_CNTXT failed\n",
1199                         __func__);
1200                 return (-1);
1201         } else {
1202                 rsp = ha->hw.rx_cntxt_rsp;
1203
1204                 QL_DPRINT2((dev, "%s: rcv cntxt successful"
1205                         " rds_ring_offset = 0x%08x"
1206                         " sds_ring_offset = 0x%08x"
1207                         " cntxt_state = 0x%08x"
1208                         " funcs_per_port = 0x%08x"
1209                         " num_rds_rings = 0x%04x"
1210                         " num_sds_rings = 0x%04x"
1211                         " cntxt_id = 0x%04x"
1212                         " phys_port = 0x%02x"
1213                         " virt_port = 0x%02x\n",
1214                         __func__,
1215                         rsp->rx_rsp.rds_ring_offset,
1216                         rsp->rx_rsp.sds_ring_offset,
1217                         rsp->rx_rsp.cntxt_state,
1218                         rsp->rx_rsp.funcs_per_port,
1219                         rsp->rx_rsp.num_rds_rings,
1220                         rsp->rx_rsp.num_sds_rings,
1221                         rsp->rx_rsp.cntxt_id,
1222                         rsp->rx_rsp.phys_port,
1223                         rsp->rx_rsp.virt_port));
1224
1225                 for (i = 0; i < ha->hw.num_rds_rings; i++) {
1226                         QL_DPRINT2((dev,
1227                                 "%s: rcv cntxt rds[%i].producer_reg = 0x%08x\n",
1228                                 __func__, i, rsp->rds_rsp[i].producer_reg));
1229                 }
1230                 for (i = 0; i < ha->hw.num_sds_rings; i++) {
1231                         QL_DPRINT2((dev,
1232                                 "%s: rcv cntxt sds[%i].consumer_reg = 0x%08x"
1233                                 " sds[%i].intr_mask_reg = 0x%08x\n",
1234                                 __func__, i, rsp->sds_rsp[i].consumer_reg,
1235                                 i, rsp->sds_rsp[i].intr_mask_reg));
1236                 }
1237         }
1238         ha->hw.flags.init_rx_cnxt = 1;
1239         return (0);
1240 }
1241
1242 /*
1243  * Name: qla_del_rcv_cntxt
1244  * Function: Destroys the Receive Context.
1245  */
1246 void
1247 qla_del_rcv_cntxt(qla_host_t *ha)
1248 {
1249         qla_cdrp_t      cdrp;
1250         device_t        dev = ha->pci_dev;
1251
1252         if (!ha->hw.flags.init_rx_cnxt)
1253                 return;
1254
1255         bzero(&cdrp, sizeof(qla_cdrp_t));
1256
1257         cdrp.cmd = Q8_CMD_DESTROY_RX_CNTXT;
1258         cdrp.cmd_arg1 = (uint32_t) (ha->hw.rx_cntxt_rsp)->rx_rsp.cntxt_id;
1259
1260         if (qla_issue_cmd(ha, &cdrp)) {
1261                 device_printf(dev, "%s: Q8_CMD_DESTROY_RX_CNTXT failed\n",
1262                         __func__);
1263         }
1264         ha->hw.flags.init_rx_cnxt = 0;
1265 }
1266
1267 /*
1268  * Name: qla_init_xmt_cntxt
1269  * Function: Creates the Transmit Context.
1270  */
1271 static int
1272 qla_init_xmt_cntxt(qla_host_t *ha)
1273 {
1274         bus_addr_t              phys_addr;
1275         device_t                dev;
1276         q80_tx_cntxt_rsp_t      *tx_rsp;
1277         qla_cdrp_t              cdrp;
1278         qla_hw_t                *hw = &ha->hw;
1279
1280         dev = ha->pci_dev;
1281
1282         /*
1283          * Create Transmit Context
1284          */
1285         phys_addr = ha->hw.tx_cntxt_req_paddr;
1286         tx_rsp = ha->hw.tx_cntxt_rsp;
1287
1288         hw->txr_comp = hw->txr_next = 0;
1289         *(hw->tx_cons) = 0;
1290
1291         bzero(&cdrp, sizeof(qla_cdrp_t));
1292
1293         cdrp.cmd = Q8_CMD_CREATE_TX_CNTXT;
1294         cdrp.cmd_arg1 = (uint32_t)(phys_addr >> 32);
1295         cdrp.cmd_arg2 = (uint32_t)(phys_addr);
1296         cdrp.cmd_arg3 = (uint32_t)(sizeof (q80_tx_cntxt_req_t));
1297
1298         if (qla_issue_cmd(ha, &cdrp)) {
1299                 device_printf(dev, "%s: Q8_CMD_CREATE_TX_CNTXT failed\n",
1300                         __func__);
1301                 return (-1);
1302         } else {
1303                 ha->hw.tx_prod_reg = tx_rsp->producer_reg;
1304
1305                 QL_DPRINT2((dev, "%s: tx cntxt successful"
1306                         " cntxt_state = 0x%08x "
1307                         " cntxt_id = 0x%04x "
1308                         " phys_port_id = 0x%02x "
1309                         " virt_port_id = 0x%02x "
1310                         " producer_reg = 0x%08x "
1311                         " intr_mask_reg = 0x%08x\n",
1312                         __func__, tx_rsp->cntxt_state, tx_rsp->cntxt_id,
1313                         tx_rsp->phys_port_id, tx_rsp->virt_port_id,
1314                         tx_rsp->producer_reg, tx_rsp->intr_mask_reg));
1315         }
1316         ha->hw.txr_free = NUM_TX_DESCRIPTORS;
1317
1318         ha->hw.flags.init_tx_cnxt = 1;
1319         return (0);
1320 }
1321
1322 /*
1323  * Name: qla_del_xmt_cntxt
1324  * Function: Destroys the Transmit Context.
1325  */
1326 static void
1327 qla_del_xmt_cntxt(qla_host_t *ha)
1328 {
1329         qla_cdrp_t      cdrp;
1330         device_t        dev = ha->pci_dev;
1331
1332         if (!ha->hw.flags.init_tx_cnxt)
1333                 return;
1334
1335         bzero(&cdrp, sizeof(qla_cdrp_t));
1336
1337         cdrp.cmd = Q8_CMD_DESTROY_TX_CNTXT;
1338         cdrp.cmd_arg1 = (uint32_t) (ha->hw.tx_cntxt_rsp)->cntxt_id;
1339
1340         if (qla_issue_cmd(ha, &cdrp)) {
1341                 device_printf(dev, "%s: Q8_CMD_DESTROY_TX_CNTXT failed\n",
1342                         __func__);
1343         }
1344         ha->hw.flags.init_tx_cnxt = 0;
1345 }
1346
1347 /*
1348  * Name: qla_get_max_rds
1349  * Function: Returns the maximum number of Receive Descriptor Rings per context.
1350  */
1351 static int
1352 qla_get_max_rds(qla_host_t *ha)
1353 {
1354         qla_cdrp_t      cdrp;
1355         device_t        dev;
1356
1357         dev = ha->pci_dev;
1358
1359         bzero(&cdrp, sizeof(qla_cdrp_t));
1360
1361         cdrp.cmd = Q8_CMD_RD_MAX_RDS_PER_CNTXT;
1362
1363         if (qla_issue_cmd(ha, &cdrp)) {
1364                 device_printf(dev, "%s: Q8_CMD_RD_MAX_RDS_PER_CNTXT failed\n",
1365                         __func__);
1366                 return (-1);
1367         } else {
1368                 ha->hw.max_rds_per_cntxt = cdrp.rsp_arg1;
1369                 QL_DPRINT2((dev, "%s: max_rds_per_context 0x%08x\n",
1370                         __func__, ha->hw.max_rds_per_cntxt));
1371         }
1372         return 0;
1373 }
1374
1375 /*
1376  * Name: qla_get_max_sds
1377  * Function: Returns the maximum number of Status Descriptor Rings per context.
1378  */
1379 static int
1380 qla_get_max_sds(qla_host_t *ha)
1381 {
1382         qla_cdrp_t      cdrp;
1383         device_t        dev;
1384
1385         dev = ha->pci_dev;
1386
1387         bzero(&cdrp, sizeof(qla_cdrp_t));
1388
1389         cdrp.cmd = Q8_CMD_RD_MAX_SDS_PER_CNTXT;
1390
1391         if (qla_issue_cmd(ha, &cdrp)) {
1392                 device_printf(dev, "%s: Q8_CMD_RD_MAX_RDS_PER_CNTXT failed\n",
1393                         __func__);
1394                 return (-1);
1395         } else {
1396                 ha->hw.max_sds_per_cntxt = cdrp.rsp_arg1;
1397                 QL_DPRINT2((dev, "%s: max_sds_per_context 0x%08x\n",
1398                         __func__, ha->hw.max_sds_per_cntxt));
1399         }
1400         return 0;
1401 }
1402
1403 /*
1404  * Name: qla_get_max_rules
1405  * Function: Returns the maximum number of Rules per context.
1406  */
1407 static int
1408 qla_get_max_rules(qla_host_t *ha)
1409 {
1410         qla_cdrp_t      cdrp;
1411         device_t        dev;
1412
1413         dev = ha->pci_dev;
1414
1415         bzero(&cdrp, sizeof(qla_cdrp_t));
1416
1417         cdrp.cmd = Q8_CMD_RD_MAX_RULES_PER_CNTXT;
1418
1419         if (qla_issue_cmd(ha, &cdrp)) {
1420                 device_printf(dev, "%s: Q8_CMD_RD_MAX_RULES_PER_CNTXT failed\n",
1421                         __func__);
1422                 return (-1);
1423         } else {
1424                 ha->hw.max_rules_per_cntxt = cdrp.rsp_arg1;
1425                 QL_DPRINT2((dev, "%s: max_rules_per_cntxt 0x%08x\n",
1426                         __func__, ha->hw.max_rules_per_cntxt));
1427         }
1428         return 0;
1429 }
1430
1431 /*
1432  * Name: qla_get_max_rcv_cntxts
1433  * Function: Returns the maximum number of Receive Contexts supported.
1434  */
1435 static int
1436 qla_get_max_rcv_cntxts(qla_host_t *ha)
1437 {
1438         qla_cdrp_t      cdrp;
1439         device_t        dev;
1440
1441         dev = ha->pci_dev;
1442
1443         bzero(&cdrp, sizeof(qla_cdrp_t));
1444
1445         cdrp.cmd = Q8_CMD_RD_MAX_RX_CNTXT;
1446
1447         if (qla_issue_cmd(ha, &cdrp)) {
1448                 device_printf(dev, "%s: Q8_CMD_RD_MAX_RX_CNTXT failed\n",
1449                         __func__);
1450                 return (-1);
1451         } else {
1452                 ha->hw.max_rcv_cntxts = cdrp.rsp_arg1;
1453                 QL_DPRINT2((dev, "%s: max_rcv_cntxts 0x%08x\n",
1454                         __func__, ha->hw.max_rcv_cntxts));
1455         }
1456         return 0;
1457 }
1458
1459 /*
1460  * Name: qla_get_max_tx_cntxts
1461  * Function: Returns the maximum number of Transmit Contexts supported.
1462  */
1463 static int
1464 qla_get_max_tx_cntxts(qla_host_t *ha)
1465 {
1466         qla_cdrp_t      cdrp;
1467         device_t        dev;
1468
1469         dev = ha->pci_dev;
1470
1471         bzero(&cdrp, sizeof(qla_cdrp_t));
1472
1473         cdrp.cmd = Q8_CMD_RD_MAX_TX_CNTXT;
1474
1475         if (qla_issue_cmd(ha, &cdrp)) {
1476                 device_printf(dev, "%s: Q8_CMD_RD_MAX_TX_CNTXT failed\n",
1477                         __func__);
1478                 return (-1);
1479         } else {
1480                 ha->hw.max_xmt_cntxts = cdrp.rsp_arg1;
1481                 QL_DPRINT2((dev, "%s: max_xmt_cntxts 0x%08x\n",
1482                         __func__, ha->hw.max_xmt_cntxts));
1483         }
1484         return 0;
1485 }
1486
1487 /*
1488  * Name: qla_get_max_mtu
1489  * Function: Returns the MTU supported for a context.
1490  */
1491 static int
1492 qla_get_max_mtu(qla_host_t *ha)
1493 {
1494         qla_cdrp_t      cdrp;
1495         device_t        dev;
1496
1497         dev = ha->pci_dev;
1498
1499         bzero(&cdrp, sizeof(qla_cdrp_t));
1500
1501         cdrp.cmd = Q8_CMD_RD_MAX_MTU;
1502
1503         if (qla_issue_cmd(ha, &cdrp)) {
1504                 device_printf(dev, "%s: Q8_CMD_RD_MAX_MTU failed\n", __func__);
1505                 return (-1);
1506         } else {
1507                 ha->hw.max_mtu = cdrp.rsp_arg1;
1508                 QL_DPRINT2((dev, "%s: max_mtu 0x%08x\n", __func__,
1509                         ha->hw.max_mtu));
1510         }
1511         return 0;
1512 }
1513
1514 /*
1515  * Name: qla_set_max_mtu
1516  * Function:
1517  *      Sets the maximum transfer unit size for the specified rcv context.
1518  */
1519 int
1520 qla_set_max_mtu(qla_host_t *ha, uint32_t mtu, uint16_t cntxt_id)
1521 {
1522         qla_cdrp_t      cdrp;
1523         device_t        dev;
1524
1525         dev = ha->pci_dev;
1526
1527         bzero(&cdrp, sizeof(qla_cdrp_t));
1528
1529         cdrp.cmd = Q8_CMD_SET_MTU;
1530         cdrp.cmd_arg1 = (uint32_t)cntxt_id;
1531         cdrp.cmd_arg2 = mtu;
1532
1533         if (qla_issue_cmd(ha, &cdrp)) {
1534                 device_printf(dev, "%s: Q8_CMD_RD_MAX_MTU failed\n", __func__);
1535                 return (-1);
1536         } else {
1537                 ha->hw.max_mtu = cdrp.rsp_arg1;
1538         }
1539         return 0;
1540 }
1541
1542 /*
1543  * Name: qla_get_max_lro
1544  * Function: Returns the maximum number of TCP Connection which can be supported
1545  *      with LRO.
1546  */
1547 static int
1548 qla_get_max_lro(qla_host_t *ha)
1549 {
1550         qla_cdrp_t      cdrp;
1551         device_t        dev;
1552
1553         dev = ha->pci_dev;
1554
1555         bzero(&cdrp, sizeof(qla_cdrp_t));
1556
1557         cdrp.cmd = Q8_CMD_RD_MAX_LRO;
1558
1559         if (qla_issue_cmd(ha, &cdrp)) {
1560                 device_printf(dev, "%s: Q8_CMD_RD_MAX_LRO failed\n", __func__);
1561                 return (-1);
1562         } else {
1563                 ha->hw.max_lro = cdrp.rsp_arg1;
1564                 QL_DPRINT2((dev, "%s: max_lro 0x%08x\n", __func__,
1565                         ha->hw.max_lro));
1566         }
1567         return 0;
1568 }
1569
1570 /*
1571  * Name: qla_get_flow_control
1572  * Function: Returns the Receive/Transmit Flow Control (PAUSE) settings for
1573  *      PCI function.
1574  */
1575 static int
1576 qla_get_flow_control(qla_host_t *ha)
1577 {
1578         qla_cdrp_t      cdrp;
1579         device_t        dev;
1580
1581         dev = ha->pci_dev;
1582
1583         bzero(&cdrp, sizeof(qla_cdrp_t));
1584
1585         cdrp.cmd = Q8_CMD_GET_FLOW_CNTRL;
1586
1587         if (qla_issue_cmd(ha, &cdrp)) {
1588                 device_printf(dev, "%s: Q8_CMD_GET_FLOW_CNTRL failed\n",
1589                         __func__);
1590                 return (-1);
1591         } else {
1592                 QL_DPRINT2((dev, "%s: flow control 0x%08x\n", __func__,
1593                         cdrp.rsp_arg1));
1594         }
1595         return 0;
1596 }
1597
1598 /*
1599  * Name: qla_get_flow_control
1600  * Function: Retrieves hardware capabilities
1601  */
1602 void
1603 qla_get_hw_caps(qla_host_t *ha)
1604 {
1605         //qla_read_mac_addr(ha);
1606         qla_get_max_rds(ha);
1607         qla_get_max_sds(ha);
1608         qla_get_max_rules(ha);
1609         qla_get_max_rcv_cntxts(ha);
1610         qla_get_max_tx_cntxts(ha);
1611         qla_get_max_mtu(ha);
1612         qla_get_max_lro(ha);
1613         qla_get_flow_control(ha);
1614         return;
1615 }
1616
1617 /*
1618  * Name: qla_hw_set_multi
1619  * Function: Sets the Multicast Addresses provided the host O.S into the
1620  *      hardware (for the given interface)
1621  */
1622 void
1623 qla_hw_set_multi(qla_host_t *ha, uint8_t *mta, uint32_t mcnt,
1624         uint32_t add_multi)
1625 {
1626         q80_rcv_cntxt_rsp_t     *rsp;
1627         int i;
1628
1629         rsp = ha->hw.rx_cntxt_rsp;
1630         for (i = 0; i < mcnt; i++) {
1631                 qla_config_mac_addr(ha, mta, rsp->rx_rsp.cntxt_id, add_multi);
1632                 mta += Q8_MAC_ADDR_LEN;
1633         }
1634         return;
1635 }
1636
1637 /*
1638  * Name: qla_hw_tx_done_locked
1639  * Function: Handle Transmit Completions
1640  */
1641 static void
1642 qla_hw_tx_done_locked(qla_host_t *ha)
1643 {
1644         qla_tx_buf_t *txb;
1645         qla_hw_t *hw = &ha->hw;
1646         uint32_t comp_idx, comp_count = 0;
1647
1648         /* retrieve index of last entry in tx ring completed */
1649         comp_idx = qla_le32_to_host(*(hw->tx_cons));
1650
1651         while (comp_idx != hw->txr_comp) {
1652
1653                 txb = &ha->tx_buf[hw->txr_comp];
1654
1655                 hw->txr_comp++;
1656                 if (hw->txr_comp == NUM_TX_DESCRIPTORS)
1657                         hw->txr_comp = 0;
1658
1659                 comp_count++;
1660
1661                 if (txb->m_head) {
1662                         bus_dmamap_sync(ha->tx_tag, txb->map,
1663                                 BUS_DMASYNC_POSTWRITE);
1664                         bus_dmamap_unload(ha->tx_tag, txb->map);
1665                         bus_dmamap_destroy(ha->tx_tag, txb->map);
1666                         m_freem(txb->m_head);
1667
1668                         txb->map = (bus_dmamap_t)0;
1669                         txb->m_head = NULL;
1670                 }
1671         }
1672
1673         hw->txr_free += comp_count;
1674
1675         QL_DPRINT8((ha->pci_dev, "%s: return [c,f, p, pn][%d, %d, %d, %d]\n", __func__,
1676                 hw->txr_comp, hw->txr_free, hw->txr_next, READ_REG32(ha, (ha->hw.tx_prod_reg + 0x1b2000))));
1677
1678         return;
1679 }
1680
1681 /*
1682  * Name: qla_hw_tx_done
1683  * Function: Handle Transmit Completions
1684  */
1685 void
1686 qla_hw_tx_done(qla_host_t *ha)
1687 {
1688         if (!mtx_trylock(&ha->tx_lock)) {
1689                 QL_DPRINT8((ha->pci_dev,
1690                         "%s: !mtx_trylock(&ha->tx_lock)\n", __func__));
1691                 return;
1692         }
1693         qla_hw_tx_done_locked(ha);
1694
1695         if (ha->hw.txr_free > free_pkt_thres)
1696                 ha->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1697
1698         mtx_unlock(&ha->tx_lock);
1699         return;
1700 }
1701
1702 void
1703 qla_update_link_state(qla_host_t *ha)
1704 {
1705         uint32_t link_state;
1706
1707         if (!(ha->ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1708                 ha->hw.flags.link_up = 0;
1709                 return;
1710         }
1711         link_state = READ_REG32(ha, Q8_LINK_STATE);
1712
1713         if (ha->pci_func == 0)
1714                 ha->hw.flags.link_up = (((link_state & 0xF) == 1)? 1 : 0);
1715         else
1716                 ha->hw.flags.link_up = ((((link_state >> 4)& 0xF) == 1)? 1 : 0);
1717 }
1718
1719 int
1720 qla_config_lro(qla_host_t *ha)
1721 {
1722         int i;
1723         qla_hw_t *hw = &ha->hw;
1724         struct lro_ctrl *lro;
1725
1726         for (i = 0; i < hw->num_sds_rings; i++) {
1727                 lro = &hw->sds[i].lro;
1728                 if (tcp_lro_init(lro)) {
1729                         device_printf(ha->pci_dev, "%s: tcp_lro_init failed\n",
1730                                 __func__);
1731                         return (-1);
1732                 }
1733                 lro->ifp = ha->ifp;
1734         }
1735         ha->flags.lro_init = 1;
1736
1737         QL_DPRINT2((ha->pci_dev, "%s: LRO initialized\n", __func__));
1738         return (0);
1739 }
1740
1741 void
1742 qla_free_lro(qla_host_t *ha)
1743 {
1744         int i;
1745         qla_hw_t *hw = &ha->hw;
1746         struct lro_ctrl *lro;
1747
1748         if (!ha->flags.lro_init)
1749                 return;
1750
1751         for (i = 0; i < hw->num_sds_rings; i++) {
1752                 lro = &hw->sds[i].lro;
1753                 tcp_lro_free(lro);
1754         }
1755         ha->flags.lro_init = 0;
1756 }
1757
1758 void
1759 qla_hw_stop_rcv(qla_host_t *ha)
1760 {
1761         int i, done, count = 100;
1762
1763         while (count--) {
1764                 done = 1;
1765                 for (i = 0; i < ha->hw.num_sds_rings; i++) {
1766                         if (ha->hw.sds[i].rcv_active)
1767                                 done = 0;
1768                 }
1769                 if (done)
1770                         break;
1771                 else
1772                         qla_mdelay(__func__, 10);
1773         }
1774 }
1775