2 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr>
3 * Copyright (c) 2012 Bernhard Schmidt <bschmidt@FreeBSD.org>
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 * $OpenBSD: rt2860.c,v 1.65 2010/10/23 14:24:54 damien Exp $
20 #include <sys/cdefs.h>
21 __FBSDID("$FreeBSD$");
24 * Ralink Technology RT2860/RT3090/RT3390/RT3562/RT5390/RT5392 chipset driver
25 * http://www.ralinktech.com/
28 #include <sys/param.h>
29 #include <sys/sysctl.h>
30 #include <sys/sockio.h>
32 #include <sys/kernel.h>
33 #include <sys/socket.h>
34 #include <sys/systm.h>
35 #include <sys/malloc.h>
37 #include <sys/mutex.h>
38 #include <sys/module.h>
40 #include <sys/endian.h>
41 #include <sys/firmware.h>
43 #include <machine/bus.h>
44 #include <machine/resource.h>
49 #include <net/if_arp.h>
50 #include <net/ethernet.h>
51 #include <net/if_dl.h>
52 #include <net/if_media.h>
53 #include <net/if_types.h>
55 #include <net80211/ieee80211_var.h>
56 #include <net80211/ieee80211_radiotap.h>
57 #include <net80211/ieee80211_regdomain.h>
58 #include <net80211/ieee80211_ratectl.h>
60 #include <netinet/in.h>
61 #include <netinet/in_systm.h>
62 #include <netinet/in_var.h>
63 #include <netinet/ip.h>
64 #include <netinet/if_ether.h>
66 #include <dev/ral/rt2860reg.h>
67 #include <dev/ral/rt2860var.h>
71 #define DPRINTF(x) do { if (sc->sc_debug > 0) printf x; } while (0)
72 #define DPRINTFN(n, x) do { if (sc->sc_debug >= (n)) printf x; } while (0)
75 #define DPRINTFN(n, x)
78 static struct ieee80211vap *rt2860_vap_create(struct ieee80211com *,
79 const char [IFNAMSIZ], int, enum ieee80211_opmode,
80 int, const uint8_t [IEEE80211_ADDR_LEN],
81 const uint8_t [IEEE80211_ADDR_LEN]);
82 static void rt2860_vap_delete(struct ieee80211vap *);
83 static void rt2860_dma_map_addr(void *, bus_dma_segment_t *, int, int);
84 static int rt2860_alloc_tx_ring(struct rt2860_softc *,
85 struct rt2860_tx_ring *);
86 static void rt2860_reset_tx_ring(struct rt2860_softc *,
87 struct rt2860_tx_ring *);
88 static void rt2860_free_tx_ring(struct rt2860_softc *,
89 struct rt2860_tx_ring *);
90 static int rt2860_alloc_tx_pool(struct rt2860_softc *);
91 static void rt2860_free_tx_pool(struct rt2860_softc *);
92 static int rt2860_alloc_rx_ring(struct rt2860_softc *,
93 struct rt2860_rx_ring *);
94 static void rt2860_reset_rx_ring(struct rt2860_softc *,
95 struct rt2860_rx_ring *);
96 static void rt2860_free_rx_ring(struct rt2860_softc *,
97 struct rt2860_rx_ring *);
98 static void rt2860_updatestats(struct rt2860_softc *);
99 static void rt2860_newassoc(struct ieee80211_node *, int);
100 static void rt2860_node_free(struct ieee80211_node *);
102 static int rt2860_ampdu_rx_start(struct ieee80211com *,
103 struct ieee80211_node *, uint8_t);
104 static void rt2860_ampdu_rx_stop(struct ieee80211com *,
105 struct ieee80211_node *, uint8_t);
107 static int rt2860_newstate(struct ieee80211vap *, enum ieee80211_state,
109 static uint16_t rt3090_efuse_read_2(struct rt2860_softc *, uint16_t);
110 static uint16_t rt2860_eeprom_read_2(struct rt2860_softc *, uint16_t);
111 static void rt2860_intr_coherent(struct rt2860_softc *);
112 static void rt2860_drain_stats_fifo(struct rt2860_softc *);
113 static void rt2860_tx_intr(struct rt2860_softc *, int);
114 static void rt2860_rx_intr(struct rt2860_softc *);
115 static void rt2860_tbtt_intr(struct rt2860_softc *);
116 static void rt2860_gp_intr(struct rt2860_softc *);
117 static int rt2860_tx(struct rt2860_softc *, struct mbuf *,
118 struct ieee80211_node *);
119 static int rt2860_raw_xmit(struct ieee80211_node *, struct mbuf *,
120 const struct ieee80211_bpf_params *);
121 static int rt2860_tx_raw(struct rt2860_softc *, struct mbuf *,
122 struct ieee80211_node *,
123 const struct ieee80211_bpf_params *params);
124 static void rt2860_start(struct ifnet *);
125 static void rt2860_start_locked(struct ifnet *);
126 static void rt2860_watchdog(void *);
127 static int rt2860_ioctl(struct ifnet *, u_long, caddr_t);
128 static void rt2860_mcu_bbp_write(struct rt2860_softc *, uint8_t, uint8_t);
129 static uint8_t rt2860_mcu_bbp_read(struct rt2860_softc *, uint8_t);
130 static void rt2860_rf_write(struct rt2860_softc *, uint8_t, uint32_t);
131 static uint8_t rt3090_rf_read(struct rt2860_softc *, uint8_t);
132 static void rt3090_rf_write(struct rt2860_softc *, uint8_t, uint8_t);
133 static int rt2860_mcu_cmd(struct rt2860_softc *, uint8_t, uint16_t, int);
134 static void rt2860_enable_mrr(struct rt2860_softc *);
135 static void rt2860_set_txpreamble(struct rt2860_softc *);
136 static void rt2860_set_basicrates(struct rt2860_softc *,
137 const struct ieee80211_rateset *);
138 static void rt2860_scan_start(struct ieee80211com *);
139 static void rt2860_scan_end(struct ieee80211com *);
140 static void rt2860_set_channel(struct ieee80211com *);
141 static void rt2860_select_chan_group(struct rt2860_softc *, int);
142 static void rt2860_set_chan(struct rt2860_softc *, u_int);
143 static void rt3090_set_chan(struct rt2860_softc *, u_int);
144 static void rt5390_set_chan(struct rt2860_softc *, u_int);
145 static int rt3090_rf_init(struct rt2860_softc *);
146 static void rt5390_rf_init(struct rt2860_softc *);
147 static void rt3090_rf_wakeup(struct rt2860_softc *);
148 static void rt5390_rf_wakeup(struct rt2860_softc *);
149 static int rt3090_filter_calib(struct rt2860_softc *, uint8_t, uint8_t,
151 static void rt3090_rf_setup(struct rt2860_softc *);
152 static void rt2860_set_leds(struct rt2860_softc *, uint16_t);
153 static void rt2860_set_gp_timer(struct rt2860_softc *, int);
154 static void rt2860_set_bssid(struct rt2860_softc *, const uint8_t *);
155 static void rt2860_set_macaddr(struct rt2860_softc *, const uint8_t *);
156 static void rt2860_update_promisc(struct ifnet *);
157 static void rt2860_updateslot(struct ifnet *);
158 static void rt2860_updateprot(struct ifnet *);
159 static int rt2860_updateedca(struct ieee80211com *);
161 static int rt2860_set_key(struct ieee80211com *, struct ieee80211_node *,
162 struct ieee80211_key *);
163 static void rt2860_delete_key(struct ieee80211com *,
164 struct ieee80211_node *, struct ieee80211_key *);
166 static int8_t rt2860_rssi2dbm(struct rt2860_softc *, uint8_t, uint8_t);
167 static const char *rt2860_get_rf(uint8_t);
168 static int rt2860_read_eeprom(struct rt2860_softc *,
169 uint8_t macaddr[IEEE80211_ADDR_LEN]);
170 static int rt2860_bbp_init(struct rt2860_softc *);
171 static void rt5390_bbp_init(struct rt2860_softc *);
172 static int rt2860_txrx_enable(struct rt2860_softc *);
173 static void rt2860_init(void *);
174 static void rt2860_init_locked(struct rt2860_softc *);
175 static void rt2860_stop(void *);
176 static void rt2860_stop_locked(struct rt2860_softc *);
177 static int rt2860_load_microcode(struct rt2860_softc *);
179 static void rt2860_calib(struct rt2860_softc *);
181 static void rt3090_set_rx_antenna(struct rt2860_softc *, int);
182 static void rt2860_switch_chan(struct rt2860_softc *,
183 struct ieee80211_channel *);
184 static int rt2860_setup_beacon(struct rt2860_softc *,
185 struct ieee80211vap *);
186 static void rt2860_enable_tsf_sync(struct rt2860_softc *);
188 static const struct {
191 } rt2860_def_mac[] = {
195 static const struct {
198 } rt2860_def_bbp[] = {
200 }, rt5390_def_bbp[] = {
204 static const struct rfprog {
206 uint32_t r1, r2, r3, r4;
207 } rt2860_rf2850[] = {
217 static const struct {
220 } rt3090_def_rf[] = {
222 }, rt5390_def_rf[] = {
224 }, rt5392_def_rf[] = {
229 rt2860_attach(device_t dev, int id)
231 struct rt2860_softc *sc = device_get_softc(dev);
232 struct ieee80211com *ic;
235 int error, ntries, qid;
237 uint8_t macaddr[IEEE80211_ADDR_LEN];
242 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211);
244 device_printf(sc->sc_dev, "can not if_alloc()\n");
249 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
250 MTX_DEF | MTX_RECURSE);
252 callout_init_mtx(&sc->watchdog_ch, &sc->sc_mtx, 0);
254 /* wait for NIC to initialize */
255 for (ntries = 0; ntries < 100; ntries++) {
256 tmp = RAL_READ(sc, RT2860_ASIC_VER_ID);
257 if (tmp != 0 && tmp != 0xffffffff)
262 device_printf(sc->sc_dev,
263 "timeout waiting for NIC to initialize\n");
267 sc->mac_ver = tmp >> 16;
268 sc->mac_rev = tmp & 0xffff;
270 if (sc->mac_ver != 0x2860 &&
271 (id == 0x0681 || id == 0x0781 || id == 0x1059))
272 sc->sc_flags |= RT2860_ADVANCED_PS;
274 /* retrieve RF rev. no and various other things from EEPROM */
275 rt2860_read_eeprom(sc, macaddr);
276 device_printf(sc->sc_dev, "MAC/BBP RT%X (rev 0x%04X), "
277 "RF %s (MIMO %dT%dR), address %6D\n",
278 sc->mac_ver, sc->mac_rev, rt2860_get_rf(sc->rf_rev),
279 sc->ntxchains, sc->nrxchains, macaddr, ":");
282 * Allocate Tx (4 EDCAs + HCCA + Mgt) and Rx rings.
284 for (qid = 0; qid < 6; qid++) {
285 if ((error = rt2860_alloc_tx_ring(sc, &sc->txq[qid])) != 0) {
286 device_printf(sc->sc_dev,
287 "could not allocate Tx ring %d\n", qid);
292 if ((error = rt2860_alloc_rx_ring(sc, &sc->rxq)) != 0) {
293 device_printf(sc->sc_dev, "could not allocate Rx ring\n");
297 if ((error = rt2860_alloc_tx_pool(sc)) != 0) {
298 device_printf(sc->sc_dev, "could not allocate Tx pool\n");
302 /* mgmt ring is broken on RT2860C, use EDCA AC VO ring instead */
303 sc->mgtqid = (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) ?
307 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
308 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
309 ifp->if_init = rt2860_init;
310 ifp->if_ioctl = rt2860_ioctl;
311 ifp->if_start = rt2860_start;
312 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
313 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
314 IFQ_SET_READY(&ifp->if_snd);
317 ic->ic_opmode = IEEE80211_M_STA;
318 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
320 /* set device capabilities */
322 IEEE80211_C_STA /* station mode */
323 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */
324 | IEEE80211_C_HOSTAP /* hostap mode */
325 | IEEE80211_C_MONITOR /* monitor mode */
326 | IEEE80211_C_AHDEMO /* adhoc demo mode */
327 | IEEE80211_C_WDS /* 4-address traffic works */
328 | IEEE80211_C_MBSS /* mesh point link mode */
329 | IEEE80211_C_SHPREAMBLE /* short preamble supported */
330 | IEEE80211_C_SHSLOT /* short slot time supported */
331 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */
333 | IEEE80211_C_BGSCAN /* capable of bg scanning */
335 | IEEE80211_C_WME /* 802.11e */
339 setbit(&bands, IEEE80211_MODE_11B);
340 setbit(&bands, IEEE80211_MODE_11G);
341 if (sc->rf_rev == RT2860_RF_2750 || sc->rf_rev == RT2860_RF_2850)
342 setbit(&bands, IEEE80211_MODE_11A);
343 ieee80211_init_channels(ic, NULL, &bands);
345 ieee80211_ifattach(ic, macaddr);
347 ic->ic_wme.wme_update = rt2860_updateedca;
348 ic->ic_scan_start = rt2860_scan_start;
349 ic->ic_scan_end = rt2860_scan_end;
350 ic->ic_set_channel = rt2860_set_channel;
351 ic->ic_updateslot = rt2860_updateslot;
352 ic->ic_update_promisc = rt2860_update_promisc;
353 ic->ic_raw_xmit = rt2860_raw_xmit;
354 sc->sc_node_free = ic->ic_node_free;
355 ic->ic_node_free = rt2860_node_free;
356 ic->ic_newassoc = rt2860_newassoc;
358 ic->ic_vap_create = rt2860_vap_create;
359 ic->ic_vap_delete = rt2860_vap_delete;
361 ieee80211_radiotap_attach(ic,
362 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap),
363 RT2860_TX_RADIOTAP_PRESENT,
364 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap),
365 RT2860_RX_RADIOTAP_PRESENT);
368 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
369 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
370 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "debug msgs");
373 ieee80211_announce(ic);
377 fail3: rt2860_free_rx_ring(sc, &sc->rxq);
378 fail2: while (--qid >= 0)
379 rt2860_free_tx_ring(sc, &sc->txq[qid]);
380 fail1: mtx_destroy(&sc->sc_mtx);
386 rt2860_detach(void *xsc)
388 struct rt2860_softc *sc = xsc;
389 struct ifnet *ifp = sc->sc_ifp;
390 struct ieee80211com *ic = ifp->if_l2com;
394 rt2860_stop_locked(sc);
397 ieee80211_ifdetach(ic);
399 for (qid = 0; qid < 6; qid++)
400 rt2860_free_tx_ring(sc, &sc->txq[qid]);
401 rt2860_free_rx_ring(sc, &sc->rxq);
402 rt2860_free_tx_pool(sc);
406 mtx_destroy(&sc->sc_mtx);
412 rt2860_shutdown(void *xsc)
414 struct rt2860_softc *sc = xsc;
420 rt2860_suspend(void *xsc)
422 struct rt2860_softc *sc = xsc;
428 rt2860_resume(void *xsc)
430 struct rt2860_softc *sc = xsc;
431 struct ifnet *ifp = sc->sc_ifp;
433 if (ifp->if_flags & IFF_UP)
437 static struct ieee80211vap *
438 rt2860_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
439 enum ieee80211_opmode opmode, int flags,
440 const uint8_t bssid[IEEE80211_ADDR_LEN],
441 const uint8_t mac[IEEE80211_ADDR_LEN])
443 struct ifnet *ifp = ic->ic_ifp;
444 struct rt2860_vap *rvp;
445 struct ieee80211vap *vap;
448 case IEEE80211_M_STA:
449 case IEEE80211_M_IBSS:
450 case IEEE80211_M_AHDEMO:
451 case IEEE80211_M_MONITOR:
452 case IEEE80211_M_HOSTAP:
453 case IEEE80211_M_MBSS:
455 if (!TAILQ_EMPTY(&ic->ic_vaps)) {
456 if_printf(ifp, "only 1 vap supported\n");
459 if (opmode == IEEE80211_M_STA)
460 flags |= IEEE80211_CLONE_NOBEACONS;
462 case IEEE80211_M_WDS:
463 if (TAILQ_EMPTY(&ic->ic_vaps) ||
464 ic->ic_opmode != IEEE80211_M_HOSTAP) {
465 if_printf(ifp, "wds only supported in ap mode\n");
469 * Silently remove any request for a unique
470 * bssid; WDS vap's always share the local
473 flags &= ~IEEE80211_CLONE_BSSID;
476 if_printf(ifp, "unknown opmode %d\n", opmode);
479 rvp = malloc(sizeof(struct rt2860_vap), M_80211_VAP, M_NOWAIT | M_ZERO);
483 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid, mac);
485 /* override state transition machine */
486 rvp->ral_newstate = vap->iv_newstate;
487 vap->iv_newstate = rt2860_newstate;
489 vap->iv_update_beacon = rt2860_beacon_update;
492 /* HW supports up to 255 STAs (0-254) in HostAP and IBSS modes */
493 vap->iv_max_aid = min(IEEE80211_AID_MAX, RT2860_WCID_MAX);
495 ieee80211_ratectl_init(vap);
497 ieee80211_vap_attach(vap, ieee80211_media_change, ieee80211_media_status);
498 if (TAILQ_FIRST(&ic->ic_vaps) == vap)
499 ic->ic_opmode = opmode;
504 rt2860_vap_delete(struct ieee80211vap *vap)
506 struct rt2860_vap *rvp = RT2860_VAP(vap);
508 ieee80211_ratectl_deinit(vap);
509 ieee80211_vap_detach(vap);
510 free(rvp, M_80211_VAP);
514 rt2860_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
519 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
521 *(bus_addr_t *)arg = segs[0].ds_addr;
526 rt2860_alloc_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring)
530 size = RT2860_TX_RING_COUNT * sizeof (struct rt2860_txd);
532 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 16, 0,
533 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
534 size, 1, size, 0, NULL, NULL, &ring->desc_dmat);
536 device_printf(sc->sc_dev, "could not create desc DMA map\n");
540 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->txd,
541 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map);
543 device_printf(sc->sc_dev, "could not allocate DMA memory\n");
547 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->txd,
548 size, rt2860_dma_map_addr, &ring->paddr, 0);
550 device_printf(sc->sc_dev, "could not load desc DMA map\n");
554 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
558 fail: rt2860_free_tx_ring(sc, ring);
563 rt2860_reset_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring)
565 struct rt2860_tx_data *data;
568 for (i = 0; i < RT2860_TX_RING_COUNT; i++) {
569 if ((data = ring->data[i]) == NULL)
570 continue; /* nothing mapped in this slot */
572 if (data->m != NULL) {
573 bus_dmamap_sync(sc->txwi_dmat, data->map,
574 BUS_DMASYNC_POSTWRITE);
575 bus_dmamap_unload(sc->txwi_dmat, data->map);
579 if (data->ni != NULL) {
580 ieee80211_free_node(data->ni);
584 SLIST_INSERT_HEAD(&sc->data_pool, data, next);
585 ring->data[i] = NULL;
589 ring->cur = ring->next = 0;
593 rt2860_free_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring)
595 struct rt2860_tx_data *data;
598 if (ring->txd != NULL) {
599 bus_dmamap_sync(ring->desc_dmat, ring->desc_map,
600 BUS_DMASYNC_POSTWRITE);
601 bus_dmamap_unload(ring->desc_dmat, ring->desc_map);
602 bus_dmamem_free(ring->desc_dmat, ring->txd, ring->desc_map);
604 if (ring->desc_dmat != NULL)
605 bus_dma_tag_destroy(ring->desc_dmat);
607 for (i = 0; i < RT2860_TX_RING_COUNT; i++) {
608 if ((data = ring->data[i]) == NULL)
609 continue; /* nothing mapped in this slot */
611 if (data->m != NULL) {
612 bus_dmamap_sync(sc->txwi_dmat, data->map,
613 BUS_DMASYNC_POSTWRITE);
614 bus_dmamap_unload(sc->txwi_dmat, data->map);
617 if (data->ni != NULL)
618 ieee80211_free_node(data->ni);
620 SLIST_INSERT_HEAD(&sc->data_pool, data, next);
625 * Allocate a pool of TX Wireless Information blocks.
628 rt2860_alloc_tx_pool(struct rt2860_softc *sc)
634 size = RT2860_TX_POOL_COUNT * RT2860_TXWI_DMASZ;
636 /* init data_pool early in case of failure.. */
637 SLIST_INIT(&sc->data_pool);
639 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
640 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
641 size, 1, size, 0, NULL, NULL, &sc->txwi_dmat);
643 device_printf(sc->sc_dev, "could not create txwi DMA tag\n");
647 error = bus_dmamem_alloc(sc->txwi_dmat, (void **)&sc->txwi_vaddr,
648 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->txwi_map);
650 device_printf(sc->sc_dev, "could not allocate DMA memory\n");
654 error = bus_dmamap_load(sc->txwi_dmat, sc->txwi_map,
655 sc->txwi_vaddr, size, rt2860_dma_map_addr, &paddr, 0);
657 device_printf(sc->sc_dev, "could not load txwi DMA map\n");
661 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE);
663 vaddr = sc->txwi_vaddr;
664 for (i = 0; i < RT2860_TX_POOL_COUNT; i++) {
665 struct rt2860_tx_data *data = &sc->data[i];
667 error = bus_dmamap_create(sc->txwi_dmat, 0, &data->map);
669 device_printf(sc->sc_dev, "could not create DMA map\n");
672 data->txwi = (struct rt2860_txwi *)vaddr;
674 vaddr += RT2860_TXWI_DMASZ;
675 paddr += RT2860_TXWI_DMASZ;
677 SLIST_INSERT_HEAD(&sc->data_pool, data, next);
682 fail: rt2860_free_tx_pool(sc);
687 rt2860_free_tx_pool(struct rt2860_softc *sc)
689 if (sc->txwi_vaddr != NULL) {
690 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map,
691 BUS_DMASYNC_POSTWRITE);
692 bus_dmamap_unload(sc->txwi_dmat, sc->txwi_map);
693 bus_dmamem_free(sc->txwi_dmat, sc->txwi_vaddr, sc->txwi_map);
695 if (sc->txwi_dmat != NULL)
696 bus_dma_tag_destroy(sc->txwi_dmat);
698 while (!SLIST_EMPTY(&sc->data_pool)) {
699 struct rt2860_tx_data *data;
700 data = SLIST_FIRST(&sc->data_pool);
701 bus_dmamap_destroy(sc->txwi_dmat, data->map);
702 SLIST_REMOVE_HEAD(&sc->data_pool, next);
707 rt2860_alloc_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring)
712 size = RT2860_RX_RING_COUNT * sizeof (struct rt2860_rxd);
714 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 16, 0,
715 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
716 size, 1, size, 0, NULL, NULL, &ring->desc_dmat);
718 device_printf(sc->sc_dev, "could not create desc DMA tag\n");
722 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->rxd,
723 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map);
725 device_printf(sc->sc_dev, "could not allocate DMA memory\n");
729 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->rxd,
730 size, rt2860_dma_map_addr, &ring->paddr, 0);
732 device_printf(sc->sc_dev, "could not load desc DMA map\n");
736 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
737 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES,
738 1, MCLBYTES, 0, NULL, NULL, &ring->data_dmat);
740 device_printf(sc->sc_dev, "could not create data DMA tag\n");
744 for (i = 0; i < RT2860_RX_RING_COUNT; i++) {
745 struct rt2860_rx_data *data = &ring->data[i];
746 struct rt2860_rxd *rxd = &ring->rxd[i];
748 error = bus_dmamap_create(ring->data_dmat, 0, &data->map);
750 device_printf(sc->sc_dev, "could not create DMA map\n");
754 data->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
755 if (data->m == NULL) {
756 device_printf(sc->sc_dev,
757 "could not allocate rx mbuf\n");
762 error = bus_dmamap_load(ring->data_dmat, data->map,
763 mtod(data->m, void *), MCLBYTES, rt2860_dma_map_addr,
766 device_printf(sc->sc_dev,
767 "could not load rx buf DMA map");
771 rxd->sdp0 = htole32(physaddr);
772 rxd->sdl0 = htole16(MCLBYTES);
775 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
779 fail: rt2860_free_rx_ring(sc, ring);
784 rt2860_reset_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring)
788 for (i = 0; i < RT2860_RX_RING_COUNT; i++)
789 ring->rxd[i].sdl0 &= ~htole16(RT2860_RX_DDONE);
791 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
797 rt2860_free_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring)
801 if (ring->rxd != NULL) {
802 bus_dmamap_sync(ring->desc_dmat, ring->desc_map,
803 BUS_DMASYNC_POSTWRITE);
804 bus_dmamap_unload(ring->desc_dmat, ring->desc_map);
805 bus_dmamem_free(ring->desc_dmat, ring->rxd, ring->desc_map);
807 if (ring->desc_dmat != NULL)
808 bus_dma_tag_destroy(ring->desc_dmat);
810 for (i = 0; i < RT2860_RX_RING_COUNT; i++) {
811 struct rt2860_rx_data *data = &ring->data[i];
813 if (data->m != NULL) {
814 bus_dmamap_sync(ring->data_dmat, data->map,
815 BUS_DMASYNC_POSTREAD);
816 bus_dmamap_unload(ring->data_dmat, data->map);
819 if (data->map != NULL)
820 bus_dmamap_destroy(ring->data_dmat, data->map);
822 if (ring->data_dmat != NULL)
823 bus_dma_tag_destroy(ring->data_dmat);
827 rt2860_updatestats(struct rt2860_softc *sc)
829 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
832 * In IBSS or HostAP modes (when the hardware sends beacons), the
833 * MAC can run into a livelock and start sending CTS-to-self frames
834 * like crazy if protection is enabled. Fortunately, we can detect
835 * when such a situation occurs and reset the MAC.
837 if (ic->ic_curmode != IEEE80211_M_STA) {
838 /* check if we're in a livelock situation.. */
839 uint32_t tmp = RAL_READ(sc, RT2860_DEBUG);
840 if ((tmp & (1 << 29)) && (tmp & (1 << 7 | 1 << 5))) {
841 /* ..and reset MAC/BBP for a while.. */
842 DPRINTF(("CTS-to-self livelock detected\n"));
843 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_SRST);
844 RAL_BARRIER_WRITE(sc);
846 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL,
847 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN);
853 rt2860_newassoc(struct ieee80211_node *ni, int isnew)
855 struct ieee80211com *ic = ni->ni_ic;
856 struct rt2860_softc *sc = ic->ic_ifp->if_softc;
859 wcid = IEEE80211_AID(ni->ni_associd);
860 if (isnew && ni->ni_associd != 0) {
861 sc->wcid2ni[wcid] = ni;
863 /* init WCID table entry */
864 RAL_WRITE_REGION_1(sc, RT2860_WCID_ENTRY(wcid),
865 ni->ni_macaddr, IEEE80211_ADDR_LEN);
867 DPRINTF(("new assoc isnew=%d addr=%s WCID=%d\n",
868 isnew, ether_sprintf(ni->ni_macaddr), wcid));
872 rt2860_node_free(struct ieee80211_node *ni)
874 struct ieee80211com *ic = ni->ni_ic;
875 struct rt2860_softc *sc = ic->ic_ifp->if_softc;
878 if (ni->ni_associd != 0) {
879 wcid = IEEE80211_AID(ni->ni_associd);
881 /* clear Rx WCID search table entry */
882 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(wcid), 0, 2);
884 sc->sc_node_free(ni);
889 rt2860_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni,
892 struct rt2860_softc *sc = ic->ic_softc;
893 uint8_t wcid = ((struct rt2860_node *)ni)->wcid;
896 /* update BA session mask */
897 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4);
898 tmp |= (1 << tid) << 16;
899 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp);
904 rt2860_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni,
907 struct rt2860_softc *sc = ic->ic_softc;
908 uint8_t wcid = ((struct rt2860_node *)ni)->wcid;
911 /* update BA session mask */
912 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4);
913 tmp &= ~((1 << tid) << 16);
914 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp);
919 rt2860_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
921 struct rt2860_vap *rvp = RT2860_VAP(vap);
922 struct ieee80211com *ic = vap->iv_ic;
923 struct rt2860_softc *sc = ic->ic_ifp->if_softc;
927 if (vap->iv_state == IEEE80211_S_RUN) {
928 /* turn link LED off */
929 rt2860_set_leds(sc, RT2860_LED_RADIO);
932 if (nstate == IEEE80211_S_INIT && vap->iv_state == IEEE80211_S_RUN) {
933 /* abort TSF synchronization */
934 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG);
935 RAL_WRITE(sc, RT2860_BCN_TIME_CFG,
936 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN |
937 RT2860_TBTT_TIMER_EN));
940 rt2860_set_gp_timer(sc, 0);
942 error = rvp->ral_newstate(vap, nstate, arg);
946 if (nstate == IEEE80211_S_RUN) {
947 struct ieee80211_node *ni = vap->iv_bss;
949 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
950 rt2860_enable_mrr(sc);
951 rt2860_set_txpreamble(sc);
952 rt2860_set_basicrates(sc, &ni->ni_rates);
953 rt2860_set_bssid(sc, ni->ni_bssid);
956 if (vap->iv_opmode == IEEE80211_M_HOSTAP ||
957 vap->iv_opmode == IEEE80211_M_IBSS ||
958 vap->iv_opmode == IEEE80211_M_MBSS) {
959 error = rt2860_setup_beacon(sc, vap);
964 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
965 rt2860_enable_tsf_sync(sc);
966 rt2860_set_gp_timer(sc, 500);
969 /* turn link LED on */
970 rt2860_set_leds(sc, RT2860_LED_RADIO |
971 (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan) ?
972 RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ));
977 /* Read 16-bit from eFUSE ROM (>=RT3071 only.) */
979 rt3090_efuse_read_2(struct rt2860_softc *sc, uint16_t addr)
987 * Read one 16-byte block into registers EFUSE_DATA[0-3]:
993 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL);
994 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK);
995 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK;
996 RAL_WRITE(sc, RT3070_EFUSE_CTRL, tmp);
997 for (ntries = 0; ntries < 500; ntries++) {
998 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL);
999 if (!(tmp & RT3070_EFSROM_KICK))
1006 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK)
1007 return 0xffff; /* address not found */
1009 /* determine to which 32-bit register our 16-bit word belongs */
1010 reg = RT3070_EFUSE_DATA3 - (addr & 0xc);
1011 tmp = RAL_READ(sc, reg);
1013 return (addr & 2) ? tmp >> 16 : tmp & 0xffff;
1017 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46,
1021 rt2860_eeprom_read_2(struct rt2860_softc *sc, uint16_t addr)
1027 /* clock C once before the first command */
1028 RT2860_EEPROM_CTL(sc, 0);
1030 RT2860_EEPROM_CTL(sc, RT2860_S);
1031 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C);
1032 RT2860_EEPROM_CTL(sc, RT2860_S);
1034 /* write start bit (1) */
1035 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D);
1036 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C);
1038 /* write READ opcode (10) */
1039 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D);
1040 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C);
1041 RT2860_EEPROM_CTL(sc, RT2860_S);
1042 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C);
1044 /* write address (A5-A0 or A7-A0) */
1045 n = ((RAL_READ(sc, RT2860_PCI_EECTRL) & 0x30) == 0) ? 5 : 7;
1046 for (; n >= 0; n--) {
1047 RT2860_EEPROM_CTL(sc, RT2860_S |
1048 (((addr >> n) & 1) << RT2860_SHIFT_D));
1049 RT2860_EEPROM_CTL(sc, RT2860_S |
1050 (((addr >> n) & 1) << RT2860_SHIFT_D) | RT2860_C);
1053 RT2860_EEPROM_CTL(sc, RT2860_S);
1055 /* read data Q15-Q0 */
1057 for (n = 15; n >= 0; n--) {
1058 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C);
1059 tmp = RAL_READ(sc, RT2860_PCI_EECTRL);
1060 val |= ((tmp & RT2860_Q) >> RT2860_SHIFT_Q) << n;
1061 RT2860_EEPROM_CTL(sc, RT2860_S);
1064 RT2860_EEPROM_CTL(sc, 0);
1066 /* clear Chip Select and clock C */
1067 RT2860_EEPROM_CTL(sc, RT2860_S);
1068 RT2860_EEPROM_CTL(sc, 0);
1069 RT2860_EEPROM_CTL(sc, RT2860_C);
1074 static __inline uint16_t
1075 rt2860_srom_read(struct rt2860_softc *sc, uint8_t addr)
1077 /* either eFUSE ROM or EEPROM */
1078 return sc->sc_srom_read(sc, addr);
1082 rt2860_intr_coherent(struct rt2860_softc *sc)
1086 /* DMA finds data coherent event when checking the DDONE bit */
1088 DPRINTF(("Tx/Rx Coherent interrupt\n"));
1090 /* restart DMA engine */
1091 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG);
1092 tmp &= ~(RT2860_TX_WB_DDONE | RT2860_RX_DMA_EN | RT2860_TX_DMA_EN);
1093 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp);
1095 (void)rt2860_txrx_enable(sc);
1099 rt2860_drain_stats_fifo(struct rt2860_softc *sc)
1101 struct ifnet *ifp = sc->sc_ifp;
1102 struct ieee80211_node *ni;
1105 uint8_t wcid, mcs, pid;
1107 /* drain Tx status FIFO (maxsize = 16) */
1108 while ((stat = RAL_READ(sc, RT2860_TX_STAT_FIFO)) & RT2860_TXQ_VLD) {
1109 DPRINTFN(4, ("tx stat 0x%08x\n", stat));
1111 wcid = (stat >> RT2860_TXQ_WCID_SHIFT) & 0xff;
1112 ni = sc->wcid2ni[wcid];
1114 /* if no ACK was requested, no feedback is available */
1115 if (!(stat & RT2860_TXQ_ACKREQ) || wcid == 0xff || ni == NULL)
1118 /* update per-STA AMRR stats */
1119 if (stat & RT2860_TXQ_OK) {
1121 * Check if there were retries, ie if the Tx success
1122 * rate is different from the requested rate. Note
1123 * that it works only because we do not allow rate
1124 * fallback from OFDM to CCK.
1126 mcs = (stat >> RT2860_TXQ_MCS_SHIFT) & 0x7f;
1127 pid = (stat >> RT2860_TXQ_PID_SHIFT) & 0xf;
1132 ieee80211_ratectl_tx_complete(ni->ni_vap, ni,
1133 IEEE80211_RATECTL_TX_SUCCESS, &retrycnt, NULL);
1135 ieee80211_ratectl_tx_complete(ni->ni_vap, ni,
1136 IEEE80211_RATECTL_TX_FAILURE, &retrycnt, NULL);
1143 rt2860_tx_intr(struct rt2860_softc *sc, int qid)
1145 struct ifnet *ifp = sc->sc_ifp;
1146 struct rt2860_tx_ring *ring = &sc->txq[qid];
1149 rt2860_drain_stats_fifo(sc);
1151 hw = RAL_READ(sc, RT2860_TX_DTX_IDX(qid));
1152 while (ring->next != hw) {
1153 struct rt2860_tx_data *data = ring->data[ring->next];
1156 bus_dmamap_sync(sc->txwi_dmat, data->map,
1157 BUS_DMASYNC_POSTWRITE);
1158 bus_dmamap_unload(sc->txwi_dmat, data->map);
1159 if (data->m->m_flags & M_TXCB) {
1160 ieee80211_process_callback(data->ni, data->m,
1164 ieee80211_free_node(data->ni);
1168 SLIST_INSERT_HEAD(&sc->data_pool, data, next);
1169 ring->data[ring->next] = NULL;
1174 ring->next = (ring->next + 1) % RT2860_TX_RING_COUNT;
1177 sc->sc_tx_timer = 0;
1178 if (ring->queued < RT2860_TX_RING_COUNT)
1179 sc->qfullmsk &= ~(1 << qid);
1180 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1181 rt2860_start_locked(ifp);
1185 * Return the Rx chain with the highest RSSI for a given frame.
1187 static __inline uint8_t
1188 rt2860_maxrssi_chain(struct rt2860_softc *sc, const struct rt2860_rxwi *rxwi)
1190 uint8_t rxchain = 0;
1192 if (sc->nrxchains > 1) {
1193 if (rxwi->rssi[1] > rxwi->rssi[rxchain])
1195 if (sc->nrxchains > 2)
1196 if (rxwi->rssi[2] > rxwi->rssi[rxchain])
1203 rt2860_rx_intr(struct rt2860_softc *sc)
1205 struct rt2860_rx_radiotap_header *tap;
1206 struct ifnet *ifp = sc->sc_ifp;
1207 struct ieee80211com *ic = ifp->if_l2com;
1208 struct ieee80211_frame *wh;
1209 struct ieee80211_node *ni;
1210 struct mbuf *m, *m1;
1211 bus_addr_t physaddr;
1218 hw = RAL_READ(sc, RT2860_FS_DRX_IDX) & 0xfff;
1219 while (sc->rxq.cur != hw) {
1220 struct rt2860_rx_data *data = &sc->rxq.data[sc->rxq.cur];
1221 struct rt2860_rxd *rxd = &sc->rxq.rxd[sc->rxq.cur];
1222 struct rt2860_rxwi *rxwi;
1224 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map,
1225 BUS_DMASYNC_POSTREAD);
1227 if (__predict_false(!(rxd->sdl0 & htole16(RT2860_RX_DDONE)))) {
1228 DPRINTF(("RXD DDONE bit not set!\n"));
1229 break; /* should not happen */
1232 if (__predict_false(rxd->flags &
1233 htole32(RT2860_RX_CRCERR | RT2860_RX_ICVERR))) {
1239 if (__predict_false(rxd->flags & htole32(RT2860_RX_MICERR))) {
1240 /* report MIC failures to net80211 for TKIP */
1241 ic->ic_stats.is_rx_locmicfail++;
1242 ieee80211_michael_mic_failure(ic, 0/* XXX */);
1248 m1 = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1249 if (__predict_false(m1 == NULL)) {
1254 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
1255 BUS_DMASYNC_POSTREAD);
1256 bus_dmamap_unload(sc->rxq.data_dmat, data->map);
1258 error = bus_dmamap_load(sc->rxq.data_dmat, data->map,
1259 mtod(m1, void *), MCLBYTES, rt2860_dma_map_addr,
1261 if (__predict_false(error != 0)) {
1264 /* try to reload the old mbuf */
1265 error = bus_dmamap_load(sc->rxq.data_dmat, data->map,
1266 mtod(data->m, void *), MCLBYTES,
1267 rt2860_dma_map_addr, &physaddr, 0);
1268 if (__predict_false(error != 0)) {
1269 panic("%s: could not load old rx mbuf",
1270 device_get_name(sc->sc_dev));
1272 /* physical address may have changed */
1273 rxd->sdp0 = htole32(physaddr);
1279 * New mbuf successfully loaded, update Rx ring and continue
1284 rxd->sdp0 = htole32(physaddr);
1286 rxwi = mtod(m, struct rt2860_rxwi *);
1289 m->m_pkthdr.rcvif = ifp;
1290 m->m_data = (caddr_t)(rxwi + 1);
1291 m->m_pkthdr.len = m->m_len = le16toh(rxwi->len) & 0xfff;
1293 wh = mtod(m, struct ieee80211_frame *);
1295 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
1296 /* frame is decrypted by hardware */
1297 wh->i_fc[1] &= ~IEEE80211_FC1_PROTECTED;
1301 /* HW may insert 2 padding bytes after 802.11 header */
1302 if (rxd->flags & htole32(RT2860_RX_L2PAD)) {
1303 u_int hdrlen = ieee80211_hdrsize(wh);
1304 ovbcopy(wh, (caddr_t)wh + 2, hdrlen);
1306 wh = mtod(m, struct ieee80211_frame *);
1309 ant = rt2860_maxrssi_chain(sc, rxwi);
1310 rssi = rt2860_rssi2dbm(sc, rxwi->rssi[ant], ant);
1311 nf = RT2860_NOISE_FLOOR;
1313 if (ieee80211_radiotap_active(ic)) {
1314 tap = &sc->sc_rxtap;
1316 tap->wr_antenna = ant;
1317 tap->wr_antsignal = nf + rssi;
1318 tap->wr_antnoise = nf;
1319 /* in case it can't be found below */
1321 phy = le16toh(rxwi->phy);
1322 switch (phy & RT2860_PHY_MODE) {
1323 case RT2860_PHY_CCK:
1324 switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) {
1325 case 0: tap->wr_rate = 2; break;
1326 case 1: tap->wr_rate = 4; break;
1327 case 2: tap->wr_rate = 11; break;
1328 case 3: tap->wr_rate = 22; break;
1330 if (phy & RT2860_PHY_SHPRE)
1331 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
1333 case RT2860_PHY_OFDM:
1334 switch (phy & RT2860_PHY_MCS) {
1335 case 0: tap->wr_rate = 12; break;
1336 case 1: tap->wr_rate = 18; break;
1337 case 2: tap->wr_rate = 24; break;
1338 case 3: tap->wr_rate = 36; break;
1339 case 4: tap->wr_rate = 48; break;
1340 case 5: tap->wr_rate = 72; break;
1341 case 6: tap->wr_rate = 96; break;
1342 case 7: tap->wr_rate = 108; break;
1349 wh = mtod(m, struct ieee80211_frame *);
1351 /* send the frame to the 802.11 layer */
1352 ni = ieee80211_find_rxnode(ic,
1353 (struct ieee80211_frame_min *)wh);
1355 (void)ieee80211_input(ni, m, rssi - nf, nf);
1356 ieee80211_free_node(ni);
1358 (void)ieee80211_input_all(ic, m, rssi - nf, nf);
1362 skip: rxd->sdl0 &= ~htole16(RT2860_RX_DDONE);
1364 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map,
1365 BUS_DMASYNC_PREWRITE);
1367 sc->rxq.cur = (sc->rxq.cur + 1) % RT2860_RX_RING_COUNT;
1370 /* tell HW what we have processed */
1371 RAL_WRITE(sc, RT2860_RX_CALC_IDX,
1372 (sc->rxq.cur - 1) % RT2860_RX_RING_COUNT);
1376 rt2860_tbtt_intr(struct rt2860_softc *sc)
1379 struct ieee80211com *ic = &sc->sc_ic;
1381 #ifndef IEEE80211_STA_ONLY
1382 if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
1383 /* one less beacon until next DTIM */
1384 if (ic->ic_dtim_count == 0)
1385 ic->ic_dtim_count = ic->ic_dtim_period - 1;
1387 ic->ic_dtim_count--;
1389 /* update dynamic parts of beacon */
1390 rt2860_setup_beacon(sc);
1392 /* flush buffered multicast frames */
1393 if (ic->ic_dtim_count == 0)
1394 ieee80211_notify_dtim(ic);
1397 /* check if protection mode has changed */
1398 if ((sc->sc_ic_flags ^ ic->ic_flags) & IEEE80211_F_USEPROT) {
1399 rt2860_updateprot(ic);
1400 sc->sc_ic_flags = ic->ic_flags;
1406 rt2860_gp_intr(struct rt2860_softc *sc)
1408 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
1409 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
1411 DPRINTFN(2, ("GP timeout state=%d\n", vap->iv_state));
1413 if (vap->iv_state == IEEE80211_S_RUN)
1414 rt2860_updatestats(sc);
1418 rt2860_intr(void *arg)
1420 struct rt2860_softc *sc = arg;
1425 r = RAL_READ(sc, RT2860_INT_STATUS);
1426 if (__predict_false(r == 0xffffffff)) {
1428 return; /* device likely went away */
1432 return; /* not for us */
1435 /* acknowledge interrupts */
1436 RAL_WRITE(sc, RT2860_INT_STATUS, r);
1438 if (r & RT2860_TX_RX_COHERENT)
1439 rt2860_intr_coherent(sc);
1441 if (r & RT2860_MAC_INT_2) /* TX status */
1442 rt2860_drain_stats_fifo(sc);
1444 if (r & RT2860_TX_DONE_INT5)
1445 rt2860_tx_intr(sc, 5);
1447 if (r & RT2860_RX_DONE_INT)
1450 if (r & RT2860_TX_DONE_INT4)
1451 rt2860_tx_intr(sc, 4);
1453 if (r & RT2860_TX_DONE_INT3)
1454 rt2860_tx_intr(sc, 3);
1456 if (r & RT2860_TX_DONE_INT2)
1457 rt2860_tx_intr(sc, 2);
1459 if (r & RT2860_TX_DONE_INT1)
1460 rt2860_tx_intr(sc, 1);
1462 if (r & RT2860_TX_DONE_INT0)
1463 rt2860_tx_intr(sc, 0);
1465 if (r & RT2860_MAC_INT_0) /* TBTT */
1466 rt2860_tbtt_intr(sc);
1468 if (r & RT2860_MAC_INT_3) /* Auto wakeup */
1471 if (r & RT2860_MAC_INT_4) /* GP timer */
1478 rt2860_tx(struct rt2860_softc *sc, struct mbuf *m, struct ieee80211_node *ni)
1480 struct ifnet *ifp = sc->sc_ifp;
1481 struct ieee80211com *ic = ifp->if_l2com;
1482 struct ieee80211vap *vap = ni->ni_vap;
1483 struct rt2860_tx_ring *ring;
1484 struct rt2860_tx_data *data;
1485 struct rt2860_txd *txd;
1486 struct rt2860_txwi *txwi;
1487 struct ieee80211_frame *wh;
1488 const struct ieee80211_txparam *tp;
1489 struct ieee80211_key *k;
1491 bus_dma_segment_t segs[RT2860_MAX_SCATTER];
1492 bus_dma_segment_t *seg;
1495 uint8_t type, qsel, mcs, pid, tid, qid;
1496 int i, nsegs, ntxds, pad, rate, ridx, error;
1498 /* the data pool contains at least one element, pick the first */
1499 data = SLIST_FIRST(&sc->data_pool);
1501 wh = mtod(m, struct ieee80211_frame *);
1503 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
1504 k = ieee80211_crypto_encap(ni, m);
1510 /* packet header may have moved, reset our local pointer */
1511 wh = mtod(m, struct ieee80211_frame *);
1514 hdrlen = ieee80211_anyhdrsize(wh);
1515 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
1517 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)];
1518 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1519 rate = tp->mcastrate;
1520 } else if (m->m_flags & M_EAPOL) {
1521 rate = tp->mgmtrate;
1522 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) {
1523 rate = tp->ucastrate;
1525 (void) ieee80211_ratectl_rate(ni, NULL, 0);
1526 rate = ni->ni_txrate;
1528 rate &= IEEE80211_RATE_VAL;
1530 qid = M_WME_GETAC(m);
1531 if (IEEE80211_QOS_HAS_SEQ(wh)) {
1532 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0];
1533 tid = qos & IEEE80211_QOS_TID;
1538 ring = &sc->txq[qid];
1539 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt, rate);
1541 /* get MCS code from rate index */
1542 mcs = rt2860_rates[ridx].mcs;
1544 /* setup TX Wireless Information */
1547 /* let HW generate seq numbers for non-QoS frames */
1548 txwi->xflags = qos ? 0 : RT2860_TX_NSEQ;
1549 if (type == IEEE80211_FC0_TYPE_DATA)
1550 txwi->wcid = IEEE80211_AID(ni->ni_associd);
1553 txwi->len = htole16(m->m_pkthdr.len);
1554 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) {
1555 txwi->phy = htole16(RT2860_PHY_CCK);
1556 if (ridx != RT2860_RIDX_CCK1 &&
1557 (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
1558 mcs |= RT2860_PHY_SHPRE;
1560 txwi->phy = htole16(RT2860_PHY_OFDM);
1561 txwi->phy |= htole16(mcs);
1564 * We store the MCS code into the driver-private PacketID field.
1565 * The PacketID is latched into TX_STAT_FIFO when Tx completes so
1566 * that we know at which initial rate the frame was transmitted.
1567 * We add 1 to the MCS code because setting the PacketID field to
1568 * 0 means that we don't want feedback in TX_STAT_FIFO.
1570 pid = (mcs + 1) & 0xf;
1571 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT);
1573 /* check if RTS/CTS or CTS-to-self protection is required */
1574 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) &&
1575 (m->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold ||
1576 ((ic->ic_flags & IEEE80211_F_USEPROT) &&
1577 rt2860_rates[ridx].phy == IEEE80211_T_OFDM)))
1578 txwi->txop = RT2860_TX_TXOP_HT;
1580 txwi->txop = RT2860_TX_TXOP_BACKOFF;
1582 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) &&
1583 (!qos || (qos & IEEE80211_QOS_ACKPOLICY) !=
1584 IEEE80211_QOS_ACKPOLICY_NOACK)) {
1585 txwi->xflags |= RT2860_TX_ACK;
1587 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
1588 dur = rt2860_rates[ridx].sp_ack_dur;
1590 dur = rt2860_rates[ridx].lp_ack_dur;
1591 *(uint16_t *)wh->i_dur = htole16(dur);
1593 /* ask MAC to insert timestamp into probe responses */
1595 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==
1596 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP))
1597 /* NOTE: beacons do not pass through tx_data() */
1598 txwi->flags |= RT2860_TX_TS;
1600 if (ieee80211_radiotap_active_vap(vap)) {
1601 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap;
1604 tap->wt_rate = rate;
1605 if (mcs & RT2860_PHY_SHPRE)
1606 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
1608 ieee80211_radiotap_tx(vap, m);
1611 pad = (hdrlen + 3) & ~3;
1613 /* copy and trim 802.11 header */
1614 memcpy(txwi + 1, wh, hdrlen);
1617 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, segs,
1619 if (__predict_false(error != 0 && error != EFBIG)) {
1620 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n",
1625 if (__predict_true(error == 0)) {
1626 /* determine how many TXDs are required */
1627 ntxds = 1 + (nsegs / 2);
1629 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) {
1630 /* not enough free TXDs, force mbuf defrag */
1631 bus_dmamap_unload(sc->txwi_dmat, data->map);
1635 if (__predict_false(error != 0)) {
1636 m1 = m_defrag(m, M_NOWAIT);
1638 device_printf(sc->sc_dev,
1639 "could not defragment mbuf\n");
1645 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m,
1647 if (__predict_false(error != 0)) {
1648 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n",
1654 /* determine how many TXDs are now required */
1655 ntxds = 1 + (nsegs / 2);
1657 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) {
1658 /* this is a hopeless case, drop the mbuf! */
1659 bus_dmamap_unload(sc->txwi_dmat, data->map);
1665 qsel = (qid < WME_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT;
1667 /* first segment is TXWI + 802.11 header */
1668 txd = &ring->txd[ring->cur];
1669 txd->sdp0 = htole32(data->paddr);
1670 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + pad);
1673 /* setup payload segments */
1675 for (i = nsegs; i >= 2; i -= 2) {
1676 txd->sdp1 = htole32(seg->ds_addr);
1677 txd->sdl1 = htole16(seg->ds_len);
1679 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT;
1680 /* grab a new Tx descriptor */
1681 txd = &ring->txd[ring->cur];
1682 txd->sdp0 = htole32(seg->ds_addr);
1683 txd->sdl0 = htole16(seg->ds_len);
1687 /* finalize last segment */
1689 txd->sdp1 = htole32(seg->ds_addr);
1690 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1);
1692 txd->sdl0 |= htole16(RT2860_TX_LS0);
1696 /* remove from the free pool and link it into the SW Tx slot */
1697 SLIST_REMOVE_HEAD(&sc->data_pool, next);
1700 ring->data[ring->cur] = data;
1702 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE);
1703 bus_dmamap_sync(sc->txwi_dmat, data->map, BUS_DMASYNC_PREWRITE);
1704 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
1706 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n",
1707 qid, txwi->wcid, nsegs, ridx));
1709 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT;
1710 ring->queued += ntxds;
1711 if (ring->queued >= RT2860_TX_RING_COUNT)
1712 sc->qfullmsk |= 1 << qid;
1715 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur);
1721 rt2860_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
1722 const struct ieee80211_bpf_params *params)
1724 struct ieee80211com *ic = ni->ni_ic;
1725 struct ifnet *ifp = ic->ic_ifp;
1726 struct rt2860_softc *sc = ifp->if_softc;
1731 /* prevent management frames from being sent if we're not ready */
1732 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1735 ieee80211_free_node(ni);
1738 if (params == NULL) {
1740 * Legacy path; interpret frame contents to decide
1741 * precisely how to send the frame.
1743 error = rt2860_tx(sc, m, ni);
1746 * Caller supplied explicit parameters to use in
1747 * sending the frame.
1749 error = rt2860_tx_raw(sc, m, ni, params);
1752 /* NB: m is reclaimed on tx failure */
1753 ieee80211_free_node(ni);
1756 sc->sc_tx_timer = 5;
1762 rt2860_tx_raw(struct rt2860_softc *sc, struct mbuf *m,
1763 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params)
1765 struct ifnet *ifp = sc->sc_ifp;
1766 struct ieee80211com *ic = ifp->if_l2com;
1767 struct ieee80211vap *vap = ni->ni_vap;
1768 struct rt2860_tx_ring *ring;
1769 struct rt2860_tx_data *data;
1770 struct rt2860_txd *txd;
1771 struct rt2860_txwi *txwi;
1772 struct ieee80211_frame *wh;
1774 bus_dma_segment_t segs[RT2860_MAX_SCATTER];
1775 bus_dma_segment_t *seg;
1778 uint8_t type, qsel, mcs, pid, tid, qid;
1779 int i, nsegs, ntxds, pad, rate, ridx, error;
1781 /* the data pool contains at least one element, pick the first */
1782 data = SLIST_FIRST(&sc->data_pool);
1784 wh = mtod(m, struct ieee80211_frame *);
1785 hdrlen = ieee80211_hdrsize(wh);
1786 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
1788 /* Choose a TX rate index. */
1789 rate = params->ibp_rate0;
1790 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt,
1791 rate & IEEE80211_RATE_VAL);
1792 if (ridx == (uint8_t)-1) {
1793 /* XXX fall back to mcast/mgmt rate? */
1798 qid = params->ibp_pri & 3;
1800 ring = &sc->txq[qid];
1802 /* get MCS code from rate index */
1803 mcs = rt2860_rates[ridx].mcs;
1805 /* setup TX Wireless Information */
1808 /* let HW generate seq numbers for non-QoS frames */
1809 txwi->xflags = params->ibp_pri & 3 ? 0 : RT2860_TX_NSEQ;
1811 txwi->len = htole16(m->m_pkthdr.len);
1812 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) {
1813 txwi->phy = htole16(RT2860_PHY_CCK);
1814 if (ridx != RT2860_RIDX_CCK1 &&
1815 (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
1816 mcs |= RT2860_PHY_SHPRE;
1818 txwi->phy = htole16(RT2860_PHY_OFDM);
1819 txwi->phy |= htole16(mcs);
1822 * We store the MCS code into the driver-private PacketID field.
1823 * The PacketID is latched into TX_STAT_FIFO when Tx completes so
1824 * that we know at which initial rate the frame was transmitted.
1825 * We add 1 to the MCS code because setting the PacketID field to
1826 * 0 means that we don't want feedback in TX_STAT_FIFO.
1828 pid = (mcs + 1) & 0xf;
1829 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT);
1831 /* check if RTS/CTS or CTS-to-self protection is required */
1832 if (params->ibp_flags & IEEE80211_BPF_RTS ||
1833 params->ibp_flags & IEEE80211_BPF_CTS)
1834 txwi->txop = RT2860_TX_TXOP_HT;
1836 txwi->txop = RT2860_TX_TXOP_BACKOFF;
1837 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) {
1838 txwi->xflags |= RT2860_TX_ACK;
1840 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
1841 dur = rt2860_rates[ridx].sp_ack_dur;
1843 dur = rt2860_rates[ridx].lp_ack_dur;
1844 *(uint16_t *)wh->i_dur = htole16(dur);
1846 /* ask MAC to insert timestamp into probe responses */
1848 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==
1849 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP))
1850 /* NOTE: beacons do not pass through tx_data() */
1851 txwi->flags |= RT2860_TX_TS;
1853 if (ieee80211_radiotap_active_vap(vap)) {
1854 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap;
1857 tap->wt_rate = rate;
1858 if (mcs & RT2860_PHY_SHPRE)
1859 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
1861 ieee80211_radiotap_tx(vap, m);
1864 pad = (hdrlen + 3) & ~3;
1866 /* copy and trim 802.11 header */
1867 memcpy(txwi + 1, wh, hdrlen);
1870 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, segs,
1872 if (__predict_false(error != 0 && error != EFBIG)) {
1873 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n",
1878 if (__predict_true(error == 0)) {
1879 /* determine how many TXDs are required */
1880 ntxds = 1 + (nsegs / 2);
1882 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) {
1883 /* not enough free TXDs, force mbuf defrag */
1884 bus_dmamap_unload(sc->txwi_dmat, data->map);
1888 if (__predict_false(error != 0)) {
1889 m1 = m_defrag(m, M_NOWAIT);
1891 device_printf(sc->sc_dev,
1892 "could not defragment mbuf\n");
1898 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m,
1900 if (__predict_false(error != 0)) {
1901 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n",
1907 /* determine how many TXDs are now required */
1908 ntxds = 1 + (nsegs / 2);
1910 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) {
1911 /* this is a hopeless case, drop the mbuf! */
1912 bus_dmamap_unload(sc->txwi_dmat, data->map);
1918 qsel = (qid < WME_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT;
1920 /* first segment is TXWI + 802.11 header */
1921 txd = &ring->txd[ring->cur];
1922 txd->sdp0 = htole32(data->paddr);
1923 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + pad);
1926 /* setup payload segments */
1928 for (i = nsegs; i >= 2; i -= 2) {
1929 txd->sdp1 = htole32(seg->ds_addr);
1930 txd->sdl1 = htole16(seg->ds_len);
1932 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT;
1933 /* grab a new Tx descriptor */
1934 txd = &ring->txd[ring->cur];
1935 txd->sdp0 = htole32(seg->ds_addr);
1936 txd->sdl0 = htole16(seg->ds_len);
1940 /* finalize last segment */
1942 txd->sdp1 = htole32(seg->ds_addr);
1943 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1);
1945 txd->sdl0 |= htole16(RT2860_TX_LS0);
1949 /* remove from the free pool and link it into the SW Tx slot */
1950 SLIST_REMOVE_HEAD(&sc->data_pool, next);
1953 ring->data[ring->cur] = data;
1955 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE);
1956 bus_dmamap_sync(sc->txwi_dmat, data->map, BUS_DMASYNC_PREWRITE);
1957 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
1959 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n",
1960 qid, txwi->wcid, nsegs, ridx));
1962 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT;
1963 ring->queued += ntxds;
1964 if (ring->queued >= RT2860_TX_RING_COUNT)
1965 sc->qfullmsk |= 1 << qid;
1968 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur);
1974 rt2860_start(struct ifnet *ifp)
1976 struct rt2860_softc *sc = ifp->if_softc;
1979 rt2860_start_locked(ifp);
1984 rt2860_start_locked(struct ifnet *ifp)
1986 struct rt2860_softc *sc = ifp->if_softc;
1987 struct ieee80211_node *ni;
1990 RAL_LOCK_ASSERT(sc);
1992 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 ||
1993 (ifp->if_drv_flags & IFF_DRV_OACTIVE))
1997 if (SLIST_EMPTY(&sc->data_pool) || sc->qfullmsk != 0) {
1998 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2001 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
2004 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
2005 if (rt2860_tx(sc, m, ni) != 0) {
2006 ieee80211_free_node(ni);
2010 sc->sc_tx_timer = 5;
2015 rt2860_watchdog(void *arg)
2017 struct rt2860_softc *sc = arg;
2018 struct ifnet *ifp = sc->sc_ifp;
2020 RAL_LOCK_ASSERT(sc);
2022 KASSERT(ifp->if_drv_flags & IFF_DRV_RUNNING, ("not running"));
2024 if (sc->sc_invalid) /* card ejected */
2027 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) {
2028 if_printf(ifp, "device timeout\n");
2029 rt2860_stop_locked(sc);
2030 rt2860_init_locked(sc);
2034 callout_reset(&sc->watchdog_ch, hz, rt2860_watchdog, sc);
2038 rt2860_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
2040 struct rt2860_softc *sc = ifp->if_softc;
2041 struct ieee80211com *ic = ifp->if_l2com;
2042 struct ifreq *ifr = (struct ifreq *)data;
2043 int error = 0, startall = 0;
2048 if (ifp->if_flags & IFF_UP) {
2049 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
2050 rt2860_init_locked(sc);
2053 rt2860_update_promisc(ifp);
2055 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2056 rt2860_stop_locked(sc);
2060 ieee80211_start_all(ic);
2063 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd);
2066 error = ether_ioctl(ifp, cmd, data);
2076 * Reading and writing from/to the BBP is different from RT2560 and RT2661.
2077 * We access the BBP through the 8051 microcontroller unit which means that
2078 * the microcode must be loaded first.
2081 rt2860_mcu_bbp_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val)
2085 for (ntries = 0; ntries < 100; ntries++) {
2086 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK))
2090 if (ntries == 100) {
2091 device_printf(sc->sc_dev,
2092 "could not write to BBP through MCU\n");
2096 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL |
2097 RT2860_BBP_CSR_KICK | reg << 8 | val);
2098 RAL_BARRIER_WRITE(sc);
2100 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0);
2105 rt2860_mcu_bbp_read(struct rt2860_softc *sc, uint8_t reg)
2110 for (ntries = 0; ntries < 100; ntries++) {
2111 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK))
2115 if (ntries == 100) {
2116 device_printf(sc->sc_dev,
2117 "could not read from BBP through MCU\n");
2121 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL |
2122 RT2860_BBP_CSR_KICK | RT2860_BBP_CSR_READ | reg << 8);
2123 RAL_BARRIER_WRITE(sc);
2125 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0);
2128 for (ntries = 0; ntries < 100; ntries++) {
2129 val = RAL_READ(sc, RT2860_H2M_BBPAGENT);
2130 if (!(val & RT2860_BBP_CSR_KICK))
2134 device_printf(sc->sc_dev, "could not read from BBP through MCU\n");
2140 * Write to one of the 4 programmable 24-bit RF registers.
2143 rt2860_rf_write(struct rt2860_softc *sc, uint8_t reg, uint32_t val)
2148 for (ntries = 0; ntries < 100; ntries++) {
2149 if (!(RAL_READ(sc, RT2860_RF_CSR_CFG0) & RT2860_RF_REG_CTRL))
2153 if (ntries == 100) {
2154 device_printf(sc->sc_dev, "could not write to RF\n");
2158 /* RF registers are 24-bit on the RT2860 */
2159 tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT |
2160 (val & 0x3fffff) << 2 | (reg & 3);
2161 RAL_WRITE(sc, RT2860_RF_CSR_CFG0, tmp);
2165 rt3090_rf_read(struct rt2860_softc *sc, uint8_t reg)
2170 for (ntries = 0; ntries < 100; ntries++) {
2171 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK))
2175 if (ntries == 100) {
2176 device_printf(sc->sc_dev, "could not read RF register\n");
2179 tmp = RT3070_RF_KICK | reg << 8;
2180 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp);
2182 for (ntries = 0; ntries < 100; ntries++) {
2183 tmp = RAL_READ(sc, RT3070_RF_CSR_CFG);
2184 if (!(tmp & RT3070_RF_KICK))
2188 if (ntries == 100) {
2189 device_printf(sc->sc_dev, "could not read RF register\n");
2196 rt3090_rf_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val)
2201 for (ntries = 0; ntries < 10; ntries++) {
2202 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK))
2207 device_printf(sc->sc_dev, "could not write to RF\n");
2211 tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val;
2212 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp);
2216 * Send a command to the 8051 microcontroller unit.
2219 rt2860_mcu_cmd(struct rt2860_softc *sc, uint8_t cmd, uint16_t arg, int wait)
2225 for (ntries = 0; ntries < 100; ntries++) {
2226 if (!(RAL_READ(sc, RT2860_H2M_MAILBOX) & RT2860_H2M_BUSY))
2233 cid = wait ? cmd : RT2860_TOKEN_NO_INTR;
2234 RAL_WRITE(sc, RT2860_H2M_MAILBOX, RT2860_H2M_BUSY | cid << 16 | arg);
2235 RAL_BARRIER_WRITE(sc);
2236 RAL_WRITE(sc, RT2860_HOST_CMD, cmd);
2240 /* wait for the command to complete */
2241 for (ntries = 0; ntries < 200; ntries++) {
2242 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_CID);
2243 /* find the command slot */
2244 for (slot = 0; slot < 4; slot++, tmp >>= 8)
2245 if ((tmp & 0xff) == cid)
2251 if (ntries == 200) {
2252 /* clear command and status */
2253 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff);
2254 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff);
2257 /* get command status (1 means success) */
2258 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_STATUS);
2259 tmp = (tmp >> (slot * 8)) & 0xff;
2260 DPRINTF(("MCU command=0x%02x slot=%d status=0x%02x\n",
2262 /* clear command and status */
2263 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff);
2264 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff);
2265 return (tmp == 1) ? 0 : EIO;
2269 rt2860_enable_mrr(struct rt2860_softc *sc)
2271 #define CCK(mcs) (mcs)
2272 #define OFDM(mcs) (1 << 3 | (mcs))
2273 RAL_WRITE(sc, RT2860_LG_FBK_CFG0,
2274 OFDM(6) << 28 | /* 54->48 */
2275 OFDM(5) << 24 | /* 48->36 */
2276 OFDM(4) << 20 | /* 36->24 */
2277 OFDM(3) << 16 | /* 24->18 */
2278 OFDM(2) << 12 | /* 18->12 */
2279 OFDM(1) << 8 | /* 12-> 9 */
2280 OFDM(0) << 4 | /* 9-> 6 */
2281 OFDM(0)); /* 6-> 6 */
2283 RAL_WRITE(sc, RT2860_LG_FBK_CFG1,
2284 CCK(2) << 12 | /* 11->5.5 */
2285 CCK(1) << 8 | /* 5.5-> 2 */
2286 CCK(0) << 4 | /* 2-> 1 */
2287 CCK(0)); /* 1-> 1 */
2293 rt2860_set_txpreamble(struct rt2860_softc *sc)
2295 struct ifnet *ifp = sc->sc_ifp;
2296 struct ieee80211com *ic = ifp->if_l2com;
2299 tmp = RAL_READ(sc, RT2860_AUTO_RSP_CFG);
2300 tmp &= ~RT2860_CCK_SHORT_EN;
2301 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
2302 tmp |= RT2860_CCK_SHORT_EN;
2303 RAL_WRITE(sc, RT2860_AUTO_RSP_CFG, tmp);
2307 rt2860_set_basicrates(struct rt2860_softc *sc,
2308 const struct ieee80211_rateset *rs)
2310 #define RV(r) ((r) & IEEE80211_RATE_VAL)
2311 struct ifnet *ifp = sc->sc_ifp;
2312 struct ieee80211com *ic = ifp->if_l2com;
2317 for (i = 0; i < rs->rs_nrates; i++) {
2318 rate = rs->rs_rates[i];
2320 if (!(rate & IEEE80211_RATE_BASIC))
2323 mask |= 1 << ieee80211_legacy_rate_lookup(ic->ic_rt, RV(rate));
2326 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, mask);
2331 rt2860_scan_start(struct ieee80211com *ic)
2333 struct ifnet *ifp = ic->ic_ifp;
2334 struct rt2860_softc *sc = ifp->if_softc;
2337 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG);
2338 RAL_WRITE(sc, RT2860_BCN_TIME_CFG,
2339 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN |
2340 RT2860_TBTT_TIMER_EN));
2341 rt2860_set_gp_timer(sc, 0);
2345 rt2860_scan_end(struct ieee80211com *ic)
2347 struct ifnet *ifp = ic->ic_ifp;
2348 struct rt2860_softc *sc = ifp->if_softc;
2349 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
2351 if (vap->iv_state == IEEE80211_S_RUN) {
2352 rt2860_enable_tsf_sync(sc);
2353 rt2860_set_gp_timer(sc, 500);
2358 rt2860_set_channel(struct ieee80211com *ic)
2360 struct ifnet *ifp = ic->ic_ifp;
2361 struct rt2860_softc *sc = ifp->if_softc;
2364 rt2860_switch_chan(sc, ic->ic_curchan);
2369 rt2860_select_chan_group(struct rt2860_softc *sc, int group)
2374 rt2860_mcu_bbp_write(sc, 62, 0x37 - sc->lna[group]);
2375 rt2860_mcu_bbp_write(sc, 63, 0x37 - sc->lna[group]);
2376 rt2860_mcu_bbp_write(sc, 64, 0x37 - sc->lna[group]);
2377 rt2860_mcu_bbp_write(sc, 86, 0x00);
2380 if (sc->ext_2ghz_lna) {
2381 rt2860_mcu_bbp_write(sc, 82, 0x62);
2382 rt2860_mcu_bbp_write(sc, 75, 0x46);
2384 rt2860_mcu_bbp_write(sc, 82, 0x84);
2385 rt2860_mcu_bbp_write(sc, 75, 0x50);
2388 if (sc->ext_5ghz_lna) {
2389 rt2860_mcu_bbp_write(sc, 82, 0xf2);
2390 rt2860_mcu_bbp_write(sc, 75, 0x46);
2392 rt2860_mcu_bbp_write(sc, 82, 0xf2);
2393 rt2860_mcu_bbp_write(sc, 75, 0x50);
2397 tmp = RAL_READ(sc, RT2860_TX_BAND_CFG);
2398 tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P);
2399 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P;
2400 RAL_WRITE(sc, RT2860_TX_BAND_CFG, tmp);
2402 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */
2403 tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN;
2404 if (sc->nrxchains > 1)
2405 tmp |= RT2860_LNA_PE1_EN;
2406 if (sc->mac_ver == 0x3593 && sc->nrxchains > 2)
2407 tmp |= RT3593_LNA_PE2_EN;
2408 if (group == 0) { /* 2GHz */
2409 tmp |= RT2860_PA_PE_G0_EN;
2410 if (sc->ntxchains > 1)
2411 tmp |= RT2860_PA_PE_G1_EN;
2412 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2)
2413 tmp |= RT3593_PA_PE_G2_EN;
2415 tmp |= RT2860_PA_PE_A0_EN;
2416 if (sc->ntxchains > 1)
2417 tmp |= RT2860_PA_PE_A1_EN;
2418 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2)
2419 tmp |= RT3593_PA_PE_A2_EN;
2421 RAL_WRITE(sc, RT2860_TX_PIN_CFG, tmp);
2423 if (sc->mac_ver == 0x3593) {
2424 tmp = RAL_READ(sc, RT2860_GPIO_CTRL);
2425 if (sc->sc_flags & RT2860_PCIE) {
2434 tmp = (tmp & ~0x00001000) | 0x00000010;
2435 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp);
2438 /* set initial AGC value */
2439 if (group == 0) { /* 2GHz band */
2440 if (sc->mac_ver >= 0x3071)
2441 agc = 0x1c + sc->lna[0] * 2;
2443 agc = 0x2e + sc->lna[0];
2444 } else { /* 5GHz band */
2445 agc = 0x32 + (sc->lna[group] * 5) / 3;
2447 rt2860_mcu_bbp_write(sc, 66, agc);
2453 rt2860_set_chan(struct rt2860_softc *sc, u_int chan)
2455 const struct rfprog *rfprog = rt2860_rf2850;
2456 uint32_t r2, r3, r4;
2457 int8_t txpow1, txpow2;
2460 /* find the settings for this channel (we know it exists) */
2461 for (i = 0; rfprog[i].chan != chan; i++);
2464 if (sc->ntxchains == 1)
2465 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */
2466 if (sc->nrxchains == 1)
2467 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */
2468 else if (sc->nrxchains == 2)
2469 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */
2471 /* use Tx power values from EEPROM */
2472 txpow1 = sc->txpow1[i];
2473 txpow2 = sc->txpow2[i];
2476 txpow1 = txpow1 << 1 | 1;
2478 txpow1 = (7 + txpow1) << 1;
2480 txpow2 = txpow2 << 1 | 1;
2482 txpow2 = (7 + txpow2) << 1;
2484 r3 = rfprog[i].r3 | txpow1 << 7;
2485 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4;
2487 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1);
2488 rt2860_rf_write(sc, RT2860_RF2, r2);
2489 rt2860_rf_write(sc, RT2860_RF3, r3);
2490 rt2860_rf_write(sc, RT2860_RF4, r4);
2494 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1);
2495 rt2860_rf_write(sc, RT2860_RF2, r2);
2496 rt2860_rf_write(sc, RT2860_RF3, r3 | 1);
2497 rt2860_rf_write(sc, RT2860_RF4, r4);
2501 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1);
2502 rt2860_rf_write(sc, RT2860_RF2, r2);
2503 rt2860_rf_write(sc, RT2860_RF3, r3);
2504 rt2860_rf_write(sc, RT2860_RF4, r4);
2508 rt3090_set_chan(struct rt2860_softc *sc, u_int chan)
2510 int8_t txpow1, txpow2;
2514 /* RT3090 is 2GHz only */
2515 KASSERT(chan >= 1 && chan <= 14, ("chan %d not support", chan));
2517 /* find the settings for this channel (we know it exists) */
2518 for (i = 0; rt2860_rf2850[i].chan != chan; i++);
2520 /* use Tx power values from EEPROM */
2521 txpow1 = sc->txpow1[i];
2522 txpow2 = sc->txpow2[i];
2524 rt3090_rf_write(sc, 2, rt3090_freqs[i].n);
2525 rf = rt3090_rf_read(sc, 3);
2526 rf = (rf & ~0x0f) | rt3090_freqs[i].k;
2527 rt3090_rf_write(sc, 3, rf);
2528 rf = rt3090_rf_read(sc, 6);
2529 rf = (rf & ~0x03) | rt3090_freqs[i].r;
2530 rt3090_rf_write(sc, 6, rf);
2533 rf = rt3090_rf_read(sc, 12);
2534 rf = (rf & ~0x1f) | txpow1;
2535 rt3090_rf_write(sc, 12, rf);
2538 rf = rt3090_rf_read(sc, 13);
2539 rf = (rf & ~0x1f) | txpow2;
2540 rt3090_rf_write(sc, 13, rf);
2542 rf = rt3090_rf_read(sc, 1);
2544 if (sc->ntxchains == 1)
2545 rf |= RT3070_TX1_PD | RT3070_TX2_PD;
2546 else if (sc->ntxchains == 2)
2547 rf |= RT3070_TX2_PD;
2548 if (sc->nrxchains == 1)
2549 rf |= RT3070_RX1_PD | RT3070_RX2_PD;
2550 else if (sc->nrxchains == 2)
2551 rf |= RT3070_RX2_PD;
2552 rt3090_rf_write(sc, 1, rf);
2555 rf = rt3090_rf_read(sc, 23);
2556 rf = (rf & ~0x7f) | sc->freq;
2557 rt3090_rf_write(sc, 23, rf);
2559 /* program RF filter */
2560 rf = rt3090_rf_read(sc, 24); /* Tx */
2561 rf = (rf & ~0x3f) | sc->rf24_20mhz;
2562 rt3090_rf_write(sc, 24, rf);
2563 rf = rt3090_rf_read(sc, 31); /* Rx */
2564 rf = (rf & ~0x3f) | sc->rf24_20mhz;
2565 rt3090_rf_write(sc, 31, rf);
2567 /* enable RF tuning */
2568 rf = rt3090_rf_read(sc, 7);
2569 rt3090_rf_write(sc, 7, rf | RT3070_TUNE);
2573 rt5390_set_chan(struct rt2860_softc *sc, u_int chan)
2575 uint8_t h20mhz, rf, tmp;
2576 int8_t txpow1, txpow2;
2579 /* RT5390 is 2GHz only */
2580 KASSERT(chan >= 1 && chan <= 14, ("chan %d not support", chan));
2582 /* find the settings for this channel (we know it exists) */
2583 for (i = 0; rt2860_rf2850[i].chan != chan; i++);
2585 /* use Tx power values from EEPROM */
2586 txpow1 = sc->txpow1[i];
2587 txpow2 = sc->txpow2[i];
2589 rt3090_rf_write(sc, 8, rt3090_freqs[i].n);
2590 rt3090_rf_write(sc, 9, rt3090_freqs[i].k & 0x0f);
2591 rf = rt3090_rf_read(sc, 11);
2592 rf = (rf & ~0x03) | (rt3090_freqs[i].r & 0x03);
2593 rt3090_rf_write(sc, 11, rf);
2595 rf = rt3090_rf_read(sc, 49);
2596 rf = (rf & ~0x3f) | (txpow1 & 0x3f);
2597 /* the valid range of the RF R49 is 0x00~0x27 */
2598 if ((rf & 0x3f) > 0x27)
2599 rf = (rf & ~0x3f) | 0x27;
2600 rt3090_rf_write(sc, 49, rf);
2601 if (sc->mac_ver == 0x5392) {
2602 rf = rt3090_rf_read(sc, 50);
2603 rf = (rf & ~0x3f) | (txpow2 & 0x3f);
2604 /* the valid range of the RF R50 is 0x00~0x27 */
2605 if ((rf & 0x3f) > 0x27)
2606 rf = (rf & ~0x3f) | 0x27;
2607 rt3090_rf_write(sc, 50, rf);
2610 rf = rt3090_rf_read(sc, 1);
2611 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD;
2612 if (sc->mac_ver == 0x5392)
2613 rf |= RT3070_RX1_PD | RT3070_TX1_PD;
2614 rt3090_rf_write(sc, 1, rf);
2616 rf = rt3090_rf_read(sc, 2);
2617 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL);
2619 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL);
2621 rf = rt3090_rf_read(sc, 17);
2623 rf = (rf & ~0x7f) | (sc->freq & 0x7f);
2626 rt2860_mcu_cmd(sc, 0x74, (tmp << 8 ) | rf, 0);
2628 if (sc->mac_ver == 0x5390) {
2631 else if (chan >= 5 && chan <= 6)
2633 else if (chan >= 7 && chan <= 10)
2637 rt3090_rf_write(sc, 55, rf);
2645 else if (chan >= 4 && chan <= 6)
2647 else if (chan >= 7 && chan <= 12)
2649 else if (chan == 13)
2653 rt3090_rf_write(sc, 59, rf);
2657 h20mhz = (sc->rf24_20mhz & 0x20) >> 5;
2658 rf = rt3090_rf_read(sc, 30);
2659 rf = (rf & ~0x06) | (h20mhz << 1) | (h20mhz << 2);
2660 rt3090_rf_write(sc, 30, rf);
2662 /* Rx BB filter VCM */
2663 rf = rt3090_rf_read(sc, 30);
2664 rf = (rf & ~0x18) | 0x10;
2665 rt3090_rf_write(sc, 30, rf);
2667 /* Initiate VCO calibration. */
2668 rf = rt3090_rf_read(sc, 3);
2669 rf |= RT3593_VCOCAL;
2670 rt3090_rf_write(sc, 3, rf);
2674 rt3090_rf_init(struct rt2860_softc *sc)
2680 rf = rt3090_rf_read(sc, 30);
2681 /* toggle RF R30 bit 7 */
2682 rt3090_rf_write(sc, 30, rf | 0x80);
2684 rt3090_rf_write(sc, 30, rf & ~0x80);
2686 tmp = RAL_READ(sc, RT3070_LDO_CFG0);
2688 if (sc->patch_dac && sc->mac_rev < 0x0211)
2689 tmp |= 0x0d000000; /* 1.35V */
2691 tmp |= 0x01000000; /* 1.2V */
2692 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp);
2694 /* patch LNA_PE_G1 */
2695 tmp = RAL_READ(sc, RT3070_GPIO_SWITCH);
2696 RAL_WRITE(sc, RT3070_GPIO_SWITCH, tmp & ~0x20);
2698 /* initialize RF registers to default value */
2699 for (i = 0; i < nitems(rt3090_def_rf); i++) {
2700 rt3090_rf_write(sc, rt3090_def_rf[i].reg,
2701 rt3090_def_rf[i].val);
2704 /* select 20MHz bandwidth */
2705 rt3090_rf_write(sc, 31, 0x14);
2707 rf = rt3090_rf_read(sc, 6);
2708 rt3090_rf_write(sc, 6, rf | 0x40);
2710 if (sc->mac_ver != 0x3593) {
2711 /* calibrate filter for 20MHz bandwidth */
2712 sc->rf24_20mhz = 0x1f; /* default value */
2713 rt3090_filter_calib(sc, 0x07, 0x16, &sc->rf24_20mhz);
2715 /* select 40MHz bandwidth */
2716 bbp = rt2860_mcu_bbp_read(sc, 4);
2717 rt2860_mcu_bbp_write(sc, 4, (bbp & ~0x08) | 0x10);
2718 rf = rt3090_rf_read(sc, 31);
2719 rt3090_rf_write(sc, 31, rf | 0x20);
2721 /* calibrate filter for 40MHz bandwidth */
2722 sc->rf24_40mhz = 0x2f; /* default value */
2723 rt3090_filter_calib(sc, 0x27, 0x19, &sc->rf24_40mhz);
2725 /* go back to 20MHz bandwidth */
2726 bbp = rt2860_mcu_bbp_read(sc, 4);
2727 rt2860_mcu_bbp_write(sc, 4, bbp & ~0x18);
2729 if (sc->mac_rev < 0x0211)
2730 rt3090_rf_write(sc, 27, 0x03);
2732 tmp = RAL_READ(sc, RT3070_OPT_14);
2733 RAL_WRITE(sc, RT3070_OPT_14, tmp | 1);
2735 if (sc->rf_rev == RT3070_RF_3020)
2736 rt3090_set_rx_antenna(sc, 0);
2738 bbp = rt2860_mcu_bbp_read(sc, 138);
2739 if (sc->mac_ver == 0x3593) {
2740 if (sc->ntxchains == 1)
2741 bbp |= 0x60; /* turn off DAC1 and DAC2 */
2742 else if (sc->ntxchains == 2)
2743 bbp |= 0x40; /* turn off DAC2 */
2744 if (sc->nrxchains == 1)
2745 bbp &= ~0x06; /* turn off ADC1 and ADC2 */
2746 else if (sc->nrxchains == 2)
2747 bbp &= ~0x04; /* turn off ADC2 */
2749 if (sc->ntxchains == 1)
2750 bbp |= 0x20; /* turn off DAC1 */
2751 if (sc->nrxchains == 1)
2752 bbp &= ~0x02; /* turn off ADC1 */
2754 rt2860_mcu_bbp_write(sc, 138, bbp);
2756 rf = rt3090_rf_read(sc, 1);
2757 rf &= ~(RT3070_RX0_PD | RT3070_TX0_PD);
2758 rf |= RT3070_RF_BLOCK | RT3070_RX1_PD | RT3070_TX1_PD;
2759 rt3090_rf_write(sc, 1, rf);
2761 rf = rt3090_rf_read(sc, 15);
2762 rt3090_rf_write(sc, 15, rf & ~RT3070_TX_LO2);
2764 rf = rt3090_rf_read(sc, 17);
2765 rf &= ~RT3070_TX_LO1;
2766 if (sc->mac_rev >= 0x0211 && !sc->ext_2ghz_lna)
2767 rf |= 0x20; /* fix for long range Rx issue */
2768 if (sc->txmixgain_2ghz >= 2)
2769 rf = (rf & ~0x7) | sc->txmixgain_2ghz;
2770 rt3090_rf_write(sc, 17, rf);
2772 rf = rt3090_rf_read(sc, 20);
2773 rt3090_rf_write(sc, 20, rf & ~RT3070_RX_LO1);
2775 rf = rt3090_rf_read(sc, 21);
2776 rt3090_rf_write(sc, 21, rf & ~RT3070_RX_LO2);
2782 rt5390_rf_init(struct rt2860_softc *sc)
2787 rf = rt3090_rf_read(sc, 2);
2788 /* Toggle RF R2 bit 7. */
2789 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL);
2791 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL);
2793 /* Initialize RF registers to default value. */
2794 if (sc->mac_ver == 0x5392) {
2795 for (i = 0; i < nitems(rt5392_def_rf); i++) {
2796 rt3090_rf_write(sc, rt5392_def_rf[i].reg,
2797 rt5392_def_rf[i].val);
2800 for (i = 0; i < nitems(rt5390_def_rf); i++) {
2801 rt3090_rf_write(sc, rt5390_def_rf[i].reg,
2802 rt5390_def_rf[i].val);
2806 sc->rf24_20mhz = 0x1f;
2807 sc->rf24_40mhz = 0x2f;
2809 if (sc->mac_rev < 0x0211)
2810 rt3090_rf_write(sc, 27, 0x03);
2812 /* Set led open drain enable. */
2813 RAL_WRITE(sc, RT3070_OPT_14, RAL_READ(sc, RT3070_OPT_14) | 1);
2815 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0);
2816 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0);
2818 if (sc->mac_ver == 0x5390)
2819 rt3090_set_rx_antenna(sc, 0);
2821 /* Patch RSSI inaccurate issue. */
2822 rt2860_mcu_bbp_write(sc, 79, 0x13);
2823 rt2860_mcu_bbp_write(sc, 80, 0x05);
2824 rt2860_mcu_bbp_write(sc, 81, 0x33);
2826 /* Enable DC filter. */
2827 if (sc->mac_rev >= 0x0211)
2828 rt2860_mcu_bbp_write(sc, 103, 0xc0);
2830 bbp = rt2860_mcu_bbp_read(sc, 138);
2831 if (sc->ntxchains == 1)
2832 bbp |= 0x20; /* Turn off DAC1. */
2833 if (sc->nrxchains == 1)
2834 bbp &= ~0x02; /* Turn off ADC1. */
2835 rt2860_mcu_bbp_write(sc, 138, bbp);
2837 /* Enable RX LO1 and LO2. */
2838 rt3090_rf_write(sc, 38, rt3090_rf_read(sc, 38) & ~RT5390_RX_LO1);
2839 rt3090_rf_write(sc, 39, rt3090_rf_read(sc, 39) & ~RT5390_RX_LO2);
2841 /* Avoid data lost and CRC error. */
2842 rt2860_mcu_bbp_write(sc, 4,
2843 rt2860_mcu_bbp_read(sc, 4) | RT5390_MAC_IF_CTRL);
2845 rf = rt3090_rf_read(sc, 30);
2846 rf = (rf & ~0x18) | 0x10;
2847 rt3090_rf_write(sc, 30, rf);
2851 rt3090_rf_wakeup(struct rt2860_softc *sc)
2856 if (sc->mac_ver == 0x3593) {
2858 rf = rt3090_rf_read(sc, 1);
2859 rt3090_rf_write(sc, 1, rf | RT3593_VCO);
2861 /* initiate VCO calibration */
2862 rf = rt3090_rf_read(sc, 3);
2863 rt3090_rf_write(sc, 3, rf | RT3593_VCOCAL);
2865 /* enable VCO bias current control */
2866 rf = rt3090_rf_read(sc, 6);
2867 rt3090_rf_write(sc, 6, rf | RT3593_VCO_IC);
2869 /* initiate res calibration */
2870 rf = rt3090_rf_read(sc, 2);
2871 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL);
2873 /* set reference current control to 0.33 mA */
2874 rf = rt3090_rf_read(sc, 22);
2875 rf &= ~RT3593_CP_IC_MASK;
2876 rf |= 1 << RT3593_CP_IC_SHIFT;
2877 rt3090_rf_write(sc, 22, rf);
2880 rf = rt3090_rf_read(sc, 46);
2881 rt3090_rf_write(sc, 46, rf | RT3593_RX_CTB);
2883 rf = rt3090_rf_read(sc, 20);
2884 rf &= ~(RT3593_LDO_RF_VC_MASK | RT3593_LDO_PLL_VC_MASK);
2885 rt3090_rf_write(sc, 20, rf);
2887 /* enable RF block */
2888 rf = rt3090_rf_read(sc, 1);
2889 rt3090_rf_write(sc, 1, rf | RT3070_RF_BLOCK);
2891 /* enable VCO bias current control */
2892 rf = rt3090_rf_read(sc, 7);
2893 rt3090_rf_write(sc, 7, rf | 0x30);
2895 rf = rt3090_rf_read(sc, 9);
2896 rt3090_rf_write(sc, 9, rf | 0x0e);
2899 rf = rt3090_rf_read(sc, 21);
2900 rt3090_rf_write(sc, 21, rf | RT3070_RX_CTB);
2902 /* fix Tx to Rx IQ glitch by raising RF voltage */
2903 rf = rt3090_rf_read(sc, 27);
2905 if (sc->mac_rev < 0x0211)
2907 rt3090_rf_write(sc, 27, rf);
2909 if (sc->patch_dac && sc->mac_rev < 0x0211) {
2910 tmp = RAL_READ(sc, RT3070_LDO_CFG0);
2911 tmp = (tmp & ~0x1f000000) | 0x0d000000;
2912 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp);
2917 rt5390_rf_wakeup(struct rt2860_softc *sc)
2922 rf = rt3090_rf_read(sc, 1);
2923 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD |
2925 if (sc->mac_ver == 0x5392)
2926 rf |= RT3070_RX1_PD | RT3070_TX1_PD;
2927 rt3090_rf_write(sc, 1, rf);
2929 rf = rt3090_rf_read(sc, 6);
2930 rf |= RT3593_VCO_IC | RT3593_VCOCAL;
2931 if (sc->mac_ver == 0x5390)
2932 rf &= ~RT3593_VCO_IC;
2933 rt3090_rf_write(sc, 6, rf);
2935 rt3090_rf_write(sc, 2, rt3090_rf_read(sc, 2) | RT3593_RESCAL);
2937 rf = rt3090_rf_read(sc, 22);
2938 rf = (rf & ~0xe0) | 0x20;
2939 rt3090_rf_write(sc, 22, rf);
2941 rt3090_rf_write(sc, 42, rt3090_rf_read(sc, 42) | RT5390_RX_CTB);
2942 rt3090_rf_write(sc, 20, rt3090_rf_read(sc, 20) & ~0x77);
2943 rt3090_rf_write(sc, 3, rt3090_rf_read(sc, 3) | RT3593_VCOCAL);
2945 if (sc->patch_dac && sc->mac_rev < 0x0211) {
2946 tmp = RAL_READ(sc, RT3070_LDO_CFG0);
2947 tmp = (tmp & ~0x1f000000) | 0x0d000000;
2948 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp);
2953 rt3090_filter_calib(struct rt2860_softc *sc, uint8_t init, uint8_t target,
2957 uint8_t bbp55_pb, bbp55_sb, delta;
2960 /* program filter */
2961 rf24 = rt3090_rf_read(sc, 24);
2962 rf24 = (rf24 & 0xc0) | init; /* initial filter value */
2963 rt3090_rf_write(sc, 24, rf24);
2965 /* enable baseband loopback mode */
2966 rf22 = rt3090_rf_read(sc, 22);
2967 rt3090_rf_write(sc, 22, rf22 | RT3070_BB_LOOPBACK);
2969 /* set power and frequency of passband test tone */
2970 rt2860_mcu_bbp_write(sc, 24, 0x00);
2971 for (ntries = 0; ntries < 100; ntries++) {
2972 /* transmit test tone */
2973 rt2860_mcu_bbp_write(sc, 25, 0x90);
2975 /* read received power */
2976 bbp55_pb = rt2860_mcu_bbp_read(sc, 55);
2983 /* set power and frequency of stopband test tone */
2984 rt2860_mcu_bbp_write(sc, 24, 0x06);
2985 for (ntries = 0; ntries < 100; ntries++) {
2986 /* transmit test tone */
2987 rt2860_mcu_bbp_write(sc, 25, 0x90);
2989 /* read received power */
2990 bbp55_sb = rt2860_mcu_bbp_read(sc, 55);
2992 delta = bbp55_pb - bbp55_sb;
2996 /* reprogram filter */
2998 rt3090_rf_write(sc, 24, rf24);
3002 rf24--; /* backtrack */
3004 rt3090_rf_write(sc, 24, rf24);
3007 /* restore initial state */
3008 rt2860_mcu_bbp_write(sc, 24, 0x00);
3010 /* disable baseband loopback mode */
3011 rf22 = rt3090_rf_read(sc, 22);
3012 rt3090_rf_write(sc, 22, rf22 & ~RT3070_BB_LOOPBACK);
3018 rt3090_rf_setup(struct rt2860_softc *sc)
3023 if (sc->mac_rev >= 0x0211) {
3024 /* enable DC filter */
3025 rt2860_mcu_bbp_write(sc, 103, 0xc0);
3027 /* improve power consumption */
3028 bbp = rt2860_mcu_bbp_read(sc, 31);
3029 rt2860_mcu_bbp_write(sc, 31, bbp & ~0x03);
3032 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0);
3033 if (sc->mac_rev < 0x0211) {
3034 RAL_WRITE(sc, RT2860_TX_SW_CFG2,
3035 sc->patch_dac ? 0x2c : 0x0f);
3037 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0);
3039 /* initialize RF registers from ROM */
3040 if (sc->mac_ver < 0x5390) {
3041 for (i = 0; i < 10; i++) {
3042 if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff)
3044 rt3090_rf_write(sc, sc->rf[i].reg, sc->rf[i].val);
3050 rt2860_set_leds(struct rt2860_softc *sc, uint16_t which)
3052 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LEDS,
3053 which | (sc->leds & 0x7f), 0);
3057 * Hardware has a general-purpose programmable timer interrupt that can
3058 * periodically raise MAC_INT_4.
3061 rt2860_set_gp_timer(struct rt2860_softc *sc, int ms)
3065 /* disable GP timer before reprogramming it */
3066 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN);
3067 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp & ~RT2860_GP_TIMER_EN);
3072 tmp = RAL_READ(sc, RT2860_INT_TIMER_CFG);
3073 ms *= 16; /* Unit: 64us */
3074 tmp = (tmp & 0xffff) | ms << RT2860_GP_TIMER_SHIFT;
3075 RAL_WRITE(sc, RT2860_INT_TIMER_CFG, tmp);
3077 /* enable GP timer */
3078 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN);
3079 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp | RT2860_GP_TIMER_EN);
3083 rt2860_set_bssid(struct rt2860_softc *sc, const uint8_t *bssid)
3085 RAL_WRITE(sc, RT2860_MAC_BSSID_DW0,
3086 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24);
3087 RAL_WRITE(sc, RT2860_MAC_BSSID_DW1,
3088 bssid[4] | bssid[5] << 8);
3092 rt2860_set_macaddr(struct rt2860_softc *sc, const uint8_t *addr)
3094 RAL_WRITE(sc, RT2860_MAC_ADDR_DW0,
3095 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
3096 RAL_WRITE(sc, RT2860_MAC_ADDR_DW1,
3097 addr[4] | addr[5] << 8 | 0xff << 16);
3101 rt2860_updateslot(struct ifnet *ifp)
3103 struct rt2860_softc *sc = ifp->if_softc;
3104 struct ieee80211com *ic = ifp->if_l2com;
3107 tmp = RAL_READ(sc, RT2860_BKOFF_SLOT_CFG);
3109 tmp |= (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20;
3110 RAL_WRITE(sc, RT2860_BKOFF_SLOT_CFG, tmp);
3114 rt2860_updateprot(struct ifnet *ifp)
3116 struct rt2860_softc *sc = ifp->if_softc;
3117 struct ieee80211com *ic = ifp->if_l2com;
3120 tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL;
3121 /* setup protection frame rate (MCS code) */
3122 tmp |= IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ?
3123 rt2860_rates[RT2860_RIDX_OFDM6].mcs :
3124 rt2860_rates[RT2860_RIDX_CCK11].mcs;
3126 /* CCK frames don't require protection */
3127 RAL_WRITE(sc, RT2860_CCK_PROT_CFG, tmp);
3129 if (ic->ic_flags & IEEE80211_F_USEPROT) {
3130 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS)
3131 tmp |= RT2860_PROT_CTRL_RTS_CTS;
3132 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY)
3133 tmp |= RT2860_PROT_CTRL_CTS;
3135 RAL_WRITE(sc, RT2860_OFDM_PROT_CFG, tmp);
3139 rt2860_update_promisc(struct ifnet *ifp)
3141 struct rt2860_softc *sc = ifp->if_softc;
3144 tmp = RAL_READ(sc, RT2860_RX_FILTR_CFG);
3145 tmp &= ~RT2860_DROP_NOT_MYBSS;
3146 if (!(ifp->if_flags & IFF_PROMISC))
3147 tmp |= RT2860_DROP_NOT_MYBSS;
3148 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp);
3152 rt2860_updateedca(struct ieee80211com *ic)
3154 struct rt2860_softc *sc = ic->ic_ifp->if_softc;
3155 const struct wmeParams *wmep;
3158 wmep = ic->ic_wme.wme_chanParams.cap_wmeParams;
3160 /* update MAC TX configuration registers */
3161 for (aci = 0; aci < WME_NUM_AC; aci++) {
3162 RAL_WRITE(sc, RT2860_EDCA_AC_CFG(aci),
3163 wmep[aci].wmep_logcwmax << 16 |
3164 wmep[aci].wmep_logcwmin << 12 |
3165 wmep[aci].wmep_aifsn << 8 |
3166 wmep[aci].wmep_txopLimit);
3169 /* update SCH/DMA registers too */
3170 RAL_WRITE(sc, RT2860_WMM_AIFSN_CFG,
3171 wmep[WME_AC_VO].wmep_aifsn << 12 |
3172 wmep[WME_AC_VI].wmep_aifsn << 8 |
3173 wmep[WME_AC_BK].wmep_aifsn << 4 |
3174 wmep[WME_AC_BE].wmep_aifsn);
3175 RAL_WRITE(sc, RT2860_WMM_CWMIN_CFG,
3176 wmep[WME_AC_VO].wmep_logcwmin << 12 |
3177 wmep[WME_AC_VI].wmep_logcwmin << 8 |
3178 wmep[WME_AC_BK].wmep_logcwmin << 4 |
3179 wmep[WME_AC_BE].wmep_logcwmin);
3180 RAL_WRITE(sc, RT2860_WMM_CWMAX_CFG,
3181 wmep[WME_AC_VO].wmep_logcwmax << 12 |
3182 wmep[WME_AC_VI].wmep_logcwmax << 8 |
3183 wmep[WME_AC_BK].wmep_logcwmax << 4 |
3184 wmep[WME_AC_BE].wmep_logcwmax);
3185 RAL_WRITE(sc, RT2860_WMM_TXOP0_CFG,
3186 wmep[WME_AC_BK].wmep_txopLimit << 16 |
3187 wmep[WME_AC_BE].wmep_txopLimit);
3188 RAL_WRITE(sc, RT2860_WMM_TXOP1_CFG,
3189 wmep[WME_AC_VO].wmep_txopLimit << 16 |
3190 wmep[WME_AC_VI].wmep_txopLimit);
3197 rt2860_set_key(struct ieee80211com *ic, struct ieee80211_node *ni,
3198 struct ieee80211_key *k)
3200 struct rt2860_softc *sc = ic->ic_softc;
3203 uint8_t mode, wcid, iv[8];
3205 /* defer setting of WEP keys until interface is brought up */
3206 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) !=
3207 (IFF_UP | IFF_RUNNING))
3210 /* map net80211 cipher to RT2860 security mode */
3211 switch (k->k_cipher) {
3212 case IEEE80211_CIPHER_WEP40:
3213 mode = RT2860_MODE_WEP40;
3215 case IEEE80211_CIPHER_WEP104:
3216 mode = RT2860_MODE_WEP104;
3218 case IEEE80211_CIPHER_TKIP:
3219 mode = RT2860_MODE_TKIP;
3221 case IEEE80211_CIPHER_CCMP:
3222 mode = RT2860_MODE_AES_CCMP;
3228 if (k->k_flags & IEEE80211_KEY_GROUP) {
3229 wcid = 0; /* NB: update WCID0 for group keys */
3230 base = RT2860_SKEY(0, k->k_id);
3232 wcid = ((struct rt2860_node *)ni)->wcid;
3233 base = RT2860_PKEY(wcid);
3236 if (k->k_cipher == IEEE80211_CIPHER_TKIP) {
3237 RAL_WRITE_REGION_1(sc, base, k->k_key, 16);
3238 #ifndef IEEE80211_STA_ONLY
3239 if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
3240 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[16], 8);
3241 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[24], 8);
3245 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[24], 8);
3246 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[16], 8);
3249 RAL_WRITE_REGION_1(sc, base, k->k_key, k->k_len);
3251 if (!(k->k_flags & IEEE80211_KEY_GROUP) ||
3252 (k->k_flags & IEEE80211_KEY_TX)) {
3253 /* set initial packet number in IV+EIV */
3254 if (k->k_cipher == IEEE80211_CIPHER_WEP40 ||
3255 k->k_cipher == IEEE80211_CIPHER_WEP104) {
3256 uint32_t val = arc4random();
3257 /* skip weak IVs from Fluhrer/Mantin/Shamir */
3258 if (val >= 0x03ff00 && (val & 0xf8ff00) == 0x00ff00)
3263 iv[3] = k->k_id << 6;
3264 iv[4] = iv[5] = iv[6] = iv[7] = 0;
3266 if (k->k_cipher == IEEE80211_CIPHER_TKIP) {
3267 iv[0] = k->k_tsc >> 8;
3268 iv[1] = (iv[0] | 0x20) & 0x7f;
3272 iv[1] = k->k_tsc >> 8;
3275 iv[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV;
3276 iv[4] = k->k_tsc >> 16;
3277 iv[5] = k->k_tsc >> 24;
3278 iv[6] = k->k_tsc >> 32;
3279 iv[7] = k->k_tsc >> 40;
3281 RAL_WRITE_REGION_1(sc, RT2860_IVEIV(wcid), iv, 8);
3284 if (k->k_flags & IEEE80211_KEY_GROUP) {
3285 /* install group key */
3286 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7);
3287 attr &= ~(0xf << (k->k_id * 4));
3288 attr |= mode << (k->k_id * 4);
3289 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr);
3291 /* install pairwise key */
3292 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid));
3293 attr = (attr & ~0xf) | (mode << 1) | RT2860_RX_PKEY_EN;
3294 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr);
3300 rt2860_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni,
3301 struct ieee80211_key *k)
3303 struct rt2860_softc *sc = ic->ic_softc;
3307 if (k->k_flags & IEEE80211_KEY_GROUP) {
3308 /* remove group key */
3309 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7);
3310 attr &= ~(0xf << (k->k_id * 4));
3311 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr);
3314 /* remove pairwise key */
3315 wcid = ((struct rt2860_node *)ni)->wcid;
3316 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid));
3318 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr);
3324 rt2860_rssi2dbm(struct rt2860_softc *sc, uint8_t rssi, uint8_t rxchain)
3326 struct ifnet *ifp = sc->sc_ifp;
3327 struct ieee80211com *ic = ifp->if_l2com;
3328 struct ieee80211_channel *c = ic->ic_curchan;
3331 if (IEEE80211_IS_CHAN_5GHZ(c)) {
3332 u_int chan = ieee80211_chan2ieee(ic, c);
3333 delta = sc->rssi_5ghz[rxchain];
3335 /* determine channel group */
3337 delta -= sc->lna[1];
3338 else if (chan <= 128)
3339 delta -= sc->lna[2];
3341 delta -= sc->lna[3];
3343 delta = sc->rssi_2ghz[rxchain] - sc->lna[0];
3345 return -12 - delta - rssi;
3349 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word.
3350 * Used to adjust per-rate Tx power registers.
3352 static __inline uint32_t
3353 b4inc(uint32_t b32, int8_t delta)
3357 for (i = 0; i < 8; i++) {
3364 b32 = b32 >> 4 | b4 << 28;
3370 rt2860_get_rf(uint8_t rev)
3373 case RT2860_RF_2820: return "RT2820";
3374 case RT2860_RF_2850: return "RT2850";
3375 case RT2860_RF_2720: return "RT2720";
3376 case RT2860_RF_2750: return "RT2750";
3377 case RT3070_RF_3020: return "RT3020";
3378 case RT3070_RF_2020: return "RT2020";
3379 case RT3070_RF_3021: return "RT3021";
3380 case RT3070_RF_3022: return "RT3022";
3381 case RT3070_RF_3052: return "RT3052";
3382 case RT3070_RF_3320: return "RT3320";
3383 case RT3070_RF_3053: return "RT3053";
3384 case RT5390_RF_5390: return "RT5390";
3385 default: return "unknown";
3390 rt2860_read_eeprom(struct rt2860_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN])
3392 int8_t delta_2ghz, delta_5ghz;
3397 /* check whether the ROM is eFUSE ROM or EEPROM */
3398 sc->sc_srom_read = rt2860_eeprom_read_2;
3399 if (sc->mac_ver >= 0x3071) {
3400 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL);
3401 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp));
3402 if (tmp & RT3070_SEL_EFUSE)
3403 sc->sc_srom_read = rt3090_efuse_read_2;
3406 /* read EEPROM version */
3407 val = rt2860_srom_read(sc, RT2860_EEPROM_VERSION);
3408 DPRINTF(("EEPROM rev=%d, FAE=%d\n", val & 0xff, val >> 8));
3410 /* read MAC address */
3411 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC01);
3412 macaddr[0] = val & 0xff;
3413 macaddr[1] = val >> 8;
3414 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC23);
3415 macaddr[2] = val & 0xff;
3416 macaddr[3] = val >> 8;
3417 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC45);
3418 macaddr[4] = val & 0xff;
3419 macaddr[5] = val >> 8;
3421 /* read country code */
3422 val = rt2860_srom_read(sc, RT2860_EEPROM_COUNTRY);
3423 DPRINTF(("EEPROM region code=0x%04x\n", val));
3425 /* read vendor BBP settings */
3426 for (i = 0; i < 8; i++) {
3427 val = rt2860_srom_read(sc, RT2860_EEPROM_BBP_BASE + i);
3428 sc->bbp[i].val = val & 0xff;
3429 sc->bbp[i].reg = val >> 8;
3430 DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, sc->bbp[i].val));
3432 if (sc->mac_ver >= 0x3071) {
3433 /* read vendor RF settings */
3434 for (i = 0; i < 10; i++) {
3435 val = rt2860_srom_read(sc, RT3071_EEPROM_RF_BASE + i);
3436 sc->rf[i].val = val & 0xff;
3437 sc->rf[i].reg = val >> 8;
3438 DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg,
3443 /* read RF frequency offset from EEPROM */
3444 val = rt2860_srom_read(sc, RT2860_EEPROM_FREQ_LEDS);
3445 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0;
3446 DPRINTF(("EEPROM freq offset %d\n", sc->freq & 0xff));
3447 if ((val >> 8) != 0xff) {
3448 /* read LEDs operating mode */
3449 sc->leds = val >> 8;
3450 sc->led[0] = rt2860_srom_read(sc, RT2860_EEPROM_LED1);
3451 sc->led[1] = rt2860_srom_read(sc, RT2860_EEPROM_LED2);
3452 sc->led[2] = rt2860_srom_read(sc, RT2860_EEPROM_LED3);
3454 /* broken EEPROM, use default settings */
3456 sc->led[0] = 0x5555;
3457 sc->led[1] = 0x2221;
3458 sc->led[2] = 0xa9f8;
3460 DPRINTF(("EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n",
3461 sc->leds, sc->led[0], sc->led[1], sc->led[2]));
3463 /* read RF information */
3464 val = rt2860_srom_read(sc, RT2860_EEPROM_ANTENNA);
3465 if (val == 0xffff) {
3466 DPRINTF(("invalid EEPROM antenna info, using default\n"));
3467 if (sc->mac_ver >= 0x5390) {
3468 /* default to RF5390 */
3469 sc->rf_rev = RT5390_RF_5390;
3470 sc->ntxchains = (sc->mac_ver == 0x5392) ? 2 : 1;
3471 sc->nrxchains = (sc->mac_ver == 0x5392) ? 2 : 1;
3472 } else if (sc->mac_ver == 0x3593) {
3473 /* default to RF3053 3T3R */
3474 sc->rf_rev = RT3070_RF_3053;
3477 } else if (sc->mac_ver >= 0x3071) {
3478 /* default to RF3020 1T1R */
3479 sc->rf_rev = RT3070_RF_3020;
3483 /* default to RF2820 1T2R */
3484 sc->rf_rev = RT2860_RF_2820;
3489 sc->rf_rev = (val >> 8) & 0xf;
3490 if (sc->mac_ver >= 0x5390) {
3491 sc->ntxchains = (sc->mac_ver == 0x5392) ? 2 : 1;
3492 sc->nrxchains = (sc->mac_ver == 0x5392) ? 2 : 1;
3494 sc->ntxchains = (val >> 4) & 0xf;
3495 sc->nrxchains = val & 0xf;
3498 DPRINTF(("EEPROM RF rev=0x%02x chains=%dT%dR\n",
3499 sc->rf_rev, sc->ntxchains, sc->nrxchains));
3501 /* check if RF supports automatic Tx access gain control */
3502 val = rt2860_srom_read(sc, RT2860_EEPROM_CONFIG);
3503 DPRINTF(("EEPROM CFG 0x%04x\n", val));
3504 /* check if driver should patch the DAC issue */
3505 if ((val >> 8) != 0xff)
3506 sc->patch_dac = (val >> 15) & 1;
3507 if ((val & 0xff) != 0xff) {
3508 sc->ext_5ghz_lna = (val >> 3) & 1;
3509 sc->ext_2ghz_lna = (val >> 2) & 1;
3510 /* check if RF supports automatic Tx access gain control */
3511 sc->calib_2ghz = sc->calib_5ghz = 0; /* XXX (val >> 1) & 1 */;
3512 /* check if we have a hardware radio switch */
3513 sc->rfswitch = val & 1;
3515 if (sc->sc_flags & RT2860_ADVANCED_PS) {
3516 /* read PCIe power save level */
3517 val = rt2860_srom_read(sc, RT2860_EEPROM_PCIE_PSLEVEL);
3518 if ((val & 0xff) != 0xff) {
3519 sc->pslevel = val & 0x3;
3520 val = rt2860_srom_read(sc, RT2860_EEPROM_REV);
3521 if ((val & 0xff80) != 0x9280)
3522 sc->pslevel = MIN(sc->pslevel, 1);
3523 DPRINTF(("EEPROM PCIe PS Level=%d\n", sc->pslevel));
3527 /* read power settings for 2GHz channels */
3528 for (i = 0; i < 14; i += 2) {
3529 val = rt2860_srom_read(sc,
3530 RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2);
3531 sc->txpow1[i + 0] = (int8_t)(val & 0xff);
3532 sc->txpow1[i + 1] = (int8_t)(val >> 8);
3534 if (sc->mac_ver != 0x5390) {
3535 val = rt2860_srom_read(sc,
3536 RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2);
3537 sc->txpow2[i + 0] = (int8_t)(val & 0xff);
3538 sc->txpow2[i + 1] = (int8_t)(val >> 8);
3541 /* fix broken Tx power entries */
3542 for (i = 0; i < 14; i++) {
3543 if (sc->txpow1[i] < 0 ||
3544 sc->txpow1[i] > ((sc->mac_ver >= 0x5390) ? 39 : 31))
3546 if (sc->mac_ver != 0x5390) {
3547 if (sc->txpow2[i] < 0 ||
3548 sc->txpow2[i] > ((sc->mac_ver == 0x5392) ? 39 : 31))
3551 DPRINTF(("chan %d: power1=%d, power2=%d\n",
3552 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i]));
3554 /* read power settings for 5GHz channels */
3555 for (i = 0; i < 40; i += 2) {
3556 val = rt2860_srom_read(sc,
3557 RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2);
3558 sc->txpow1[i + 14] = (int8_t)(val & 0xff);
3559 sc->txpow1[i + 15] = (int8_t)(val >> 8);
3561 val = rt2860_srom_read(sc,
3562 RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2);
3563 sc->txpow2[i + 14] = (int8_t)(val & 0xff);
3564 sc->txpow2[i + 15] = (int8_t)(val >> 8);
3566 /* fix broken Tx power entries */
3567 for (i = 0; i < 40; i++) {
3568 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15)
3569 sc->txpow1[14 + i] = 5;
3570 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15)
3571 sc->txpow2[14 + i] = 5;
3572 DPRINTF(("chan %d: power1=%d, power2=%d\n",
3573 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i],
3574 sc->txpow2[14 + i]));
3577 /* read Tx power compensation for each Tx rate */
3578 val = rt2860_srom_read(sc, RT2860_EEPROM_DELTAPWR);
3579 delta_2ghz = delta_5ghz = 0;
3580 if ((val & 0xff) != 0xff && (val & 0x80)) {
3581 delta_2ghz = val & 0xf;
3582 if (!(val & 0x40)) /* negative number */
3583 delta_2ghz = -delta_2ghz;
3586 if ((val & 0xff) != 0xff && (val & 0x80)) {
3587 delta_5ghz = val & 0xf;
3588 if (!(val & 0x40)) /* negative number */
3589 delta_5ghz = -delta_5ghz;
3591 DPRINTF(("power compensation=%d (2GHz), %d (5GHz)\n",
3592 delta_2ghz, delta_5ghz));
3594 for (ridx = 0; ridx < 5; ridx++) {
3597 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2);
3599 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2 + 1);
3600 reg |= (uint32_t)val << 16;
3602 sc->txpow20mhz[ridx] = reg;
3603 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz);
3604 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz);
3606 DPRINTF(("ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, "
3607 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx],
3608 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx]));
3611 /* read factory-calibrated samples for temperature compensation */
3612 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_2GHZ);
3613 sc->tssi_2ghz[0] = val & 0xff; /* [-4] */
3614 sc->tssi_2ghz[1] = val >> 8; /* [-3] */
3615 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_2GHZ);
3616 sc->tssi_2ghz[2] = val & 0xff; /* [-2] */
3617 sc->tssi_2ghz[3] = val >> 8; /* [-1] */
3618 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_2GHZ);
3619 sc->tssi_2ghz[4] = val & 0xff; /* [+0] */
3620 sc->tssi_2ghz[5] = val >> 8; /* [+1] */
3621 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_2GHZ);
3622 sc->tssi_2ghz[6] = val & 0xff; /* [+2] */
3623 sc->tssi_2ghz[7] = val >> 8; /* [+3] */
3624 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_2GHZ);
3625 sc->tssi_2ghz[8] = val & 0xff; /* [+4] */
3626 sc->step_2ghz = val >> 8;
3627 DPRINTF(("TSSI 2GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x "
3628 "0x%02x 0x%02x step=%d\n", sc->tssi_2ghz[0], sc->tssi_2ghz[1],
3629 sc->tssi_2ghz[2], sc->tssi_2ghz[3], sc->tssi_2ghz[4],
3630 sc->tssi_2ghz[5], sc->tssi_2ghz[6], sc->tssi_2ghz[7],
3631 sc->tssi_2ghz[8], sc->step_2ghz));
3632 /* check that ref value is correct, otherwise disable calibration */
3633 if (sc->tssi_2ghz[4] == 0xff)
3636 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_5GHZ);
3637 sc->tssi_5ghz[0] = val & 0xff; /* [-4] */
3638 sc->tssi_5ghz[1] = val >> 8; /* [-3] */
3639 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_5GHZ);
3640 sc->tssi_5ghz[2] = val & 0xff; /* [-2] */
3641 sc->tssi_5ghz[3] = val >> 8; /* [-1] */
3642 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_5GHZ);
3643 sc->tssi_5ghz[4] = val & 0xff; /* [+0] */
3644 sc->tssi_5ghz[5] = val >> 8; /* [+1] */
3645 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_5GHZ);
3646 sc->tssi_5ghz[6] = val & 0xff; /* [+2] */
3647 sc->tssi_5ghz[7] = val >> 8; /* [+3] */
3648 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_5GHZ);
3649 sc->tssi_5ghz[8] = val & 0xff; /* [+4] */
3650 sc->step_5ghz = val >> 8;
3651 DPRINTF(("TSSI 5GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x "
3652 "0x%02x 0x%02x step=%d\n", sc->tssi_5ghz[0], sc->tssi_5ghz[1],
3653 sc->tssi_5ghz[2], sc->tssi_5ghz[3], sc->tssi_5ghz[4],
3654 sc->tssi_5ghz[5], sc->tssi_5ghz[6], sc->tssi_5ghz[7],
3655 sc->tssi_5ghz[8], sc->step_5ghz));
3656 /* check that ref value is correct, otherwise disable calibration */
3657 if (sc->tssi_5ghz[4] == 0xff)
3660 /* read RSSI offsets and LNA gains from EEPROM */
3661 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_2GHZ);
3662 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */
3663 sc->rssi_2ghz[1] = val >> 8; /* Ant B */
3664 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_2GHZ);
3665 if (sc->mac_ver >= 0x3071) {
3667 * On RT3090 chips (limited to 2 Rx chains), this ROM
3668 * field contains the Tx mixer gain for the 2GHz band.
3670 if ((val & 0xff) != 0xff)
3671 sc->txmixgain_2ghz = val & 0x7;
3672 DPRINTF(("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz));
3674 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */
3675 sc->lna[2] = val >> 8; /* channel group 2 */
3677 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_5GHZ);
3678 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */
3679 sc->rssi_5ghz[1] = val >> 8; /* Ant B */
3680 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_5GHZ);
3681 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */
3682 sc->lna[3] = val >> 8; /* channel group 3 */
3684 val = rt2860_srom_read(sc, RT2860_EEPROM_LNA);
3685 if (sc->mac_ver >= 0x3071)
3686 sc->lna[0] = RT3090_DEF_LNA;
3687 else /* channel group 0 */
3688 sc->lna[0] = val & 0xff;
3689 sc->lna[1] = val >> 8; /* channel group 1 */
3691 /* fix broken 5GHz LNA entries */
3692 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) {
3693 DPRINTF(("invalid LNA for channel group %d\n", 2));
3694 sc->lna[2] = sc->lna[1];
3696 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) {
3697 DPRINTF(("invalid LNA for channel group %d\n", 3));
3698 sc->lna[3] = sc->lna[1];
3701 /* fix broken RSSI offset entries */
3702 for (ant = 0; ant < 3; ant++) {
3703 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) {
3704 DPRINTF(("invalid RSSI%d offset: %d (2GHz)\n",
3705 ant + 1, sc->rssi_2ghz[ant]));
3706 sc->rssi_2ghz[ant] = 0;
3708 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) {
3709 DPRINTF(("invalid RSSI%d offset: %d (5GHz)\n",
3710 ant + 1, sc->rssi_5ghz[ant]));
3711 sc->rssi_5ghz[ant] = 0;
3719 rt2860_bbp_init(struct rt2860_softc *sc)
3723 /* wait for BBP to wake up */
3724 for (ntries = 0; ntries < 20; ntries++) {
3725 uint8_t bbp0 = rt2860_mcu_bbp_read(sc, 0);
3726 if (bbp0 != 0 && bbp0 != 0xff)
3730 device_printf(sc->sc_dev,
3731 "timeout waiting for BBP to wake up\n");
3735 /* initialize BBP registers to default values */
3736 if (sc->mac_ver >= 0x5390)
3737 rt5390_bbp_init(sc);
3739 for (i = 0; i < nitems(rt2860_def_bbp); i++) {
3740 rt2860_mcu_bbp_write(sc, rt2860_def_bbp[i].reg,
3741 rt2860_def_bbp[i].val);
3745 /* fix BBP84 for RT2860E */
3746 if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101)
3747 rt2860_mcu_bbp_write(sc, 84, 0x19);
3749 if (sc->mac_ver >= 0x3071) {
3750 rt2860_mcu_bbp_write(sc, 79, 0x13);
3751 rt2860_mcu_bbp_write(sc, 80, 0x05);
3752 rt2860_mcu_bbp_write(sc, 81, 0x33);
3753 } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) {
3754 rt2860_mcu_bbp_write(sc, 69, 0x16);
3755 rt2860_mcu_bbp_write(sc, 73, 0x12);
3762 rt5390_bbp_init(struct rt2860_softc *sc)
3767 /* Apply maximum likelihood detection for 2 stream case. */
3768 if (sc->nrxchains > 1) {
3769 bbp = rt2860_mcu_bbp_read(sc, 105);
3770 rt2860_mcu_bbp_write(sc, 105, bbp | RT5390_MLD);
3773 /* Avoid data lost and CRC error. */
3774 bbp = rt2860_mcu_bbp_read(sc, 4);
3775 rt2860_mcu_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL);
3777 for (i = 0; i < nitems(rt5390_def_bbp); i++) {
3778 rt2860_mcu_bbp_write(sc, rt5390_def_bbp[i].reg,
3779 rt5390_def_bbp[i].val);
3782 if (sc->mac_ver == 0x5392) {
3783 rt2860_mcu_bbp_write(sc, 84, 0x9a);
3784 rt2860_mcu_bbp_write(sc, 95, 0x9a);
3785 rt2860_mcu_bbp_write(sc, 98, 0x12);
3786 rt2860_mcu_bbp_write(sc, 106, 0x05);
3787 rt2860_mcu_bbp_write(sc, 134, 0xd0);
3788 rt2860_mcu_bbp_write(sc, 135, 0xf6);
3791 bbp = rt2860_mcu_bbp_read(sc, 152);
3792 rt2860_mcu_bbp_write(sc, 152, bbp | 0x80);
3794 /* Disable hardware antenna diversity. */
3795 if (sc->mac_ver == 0x5390)
3796 rt2860_mcu_bbp_write(sc, 154, 0);
3800 rt2860_txrx_enable(struct rt2860_softc *sc)
3802 struct ifnet *ifp = sc->sc_ifp;
3803 struct ieee80211com *ic = ifp->if_l2com;
3807 /* enable Tx/Rx DMA engine */
3808 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN);
3809 RAL_BARRIER_READ_WRITE(sc);
3810 for (ntries = 0; ntries < 200; ntries++) {
3811 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG);
3812 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0)
3816 if (ntries == 200) {
3817 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n");
3823 tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN |
3824 RT2860_WPDMA_BT_SIZE64 << RT2860_WPDMA_BT_SIZE_SHIFT;
3825 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp);
3828 tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR;
3829 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
3830 tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL |
3831 RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK |
3832 RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV |
3833 RT2860_DROP_CFACK | RT2860_DROP_CFEND;
3834 if (ic->ic_opmode == IEEE80211_M_STA)
3835 tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL;
3837 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp);
3839 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL,
3840 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN);
3846 rt2860_init(void *arg)
3848 struct rt2860_softc *sc = arg;
3849 struct ifnet *ifp = sc->sc_ifp;
3850 struct ieee80211com *ic = ifp->if_l2com;
3853 rt2860_init_locked(sc);
3856 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3857 ieee80211_start_all(ic);
3861 rt2860_init_locked(struct rt2860_softc *sc)
3863 struct ifnet *ifp = sc->sc_ifp;
3864 struct ieee80211com *ic = ifp->if_l2com;
3867 int i, qid, ridx, ntries, error;
3869 RAL_LOCK_ASSERT(sc);
3872 /* hardware has a radio switch on GPIO pin 2 */
3873 if (!(RAL_READ(sc, RT2860_GPIO_CTRL) & (1 << 2))) {
3874 device_printf(sc->sc_dev,
3875 "radio is disabled by hardware switch\n");
3877 rt2860_stop_locked(sc);
3882 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE);
3885 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG);
3887 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp);
3889 /* PBF hardware reset */
3890 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f);
3891 RAL_BARRIER_WRITE(sc);
3892 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00);
3894 if ((error = rt2860_load_microcode(sc)) != 0) {
3895 device_printf(sc->sc_dev, "could not load 8051 microcode\n");
3896 rt2860_stop_locked(sc);
3900 rt2860_set_macaddr(sc, IF_LLADDR(ifp));
3902 /* init Tx power for all Tx rates (from EEPROM) */
3903 for (ridx = 0; ridx < 5; ridx++) {
3904 if (sc->txpow20mhz[ridx] == 0xffffffff)
3906 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]);
3909 for (ntries = 0; ntries < 100; ntries++) {
3910 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG);
3911 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0)
3915 if (ntries == 100) {
3916 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n");
3917 rt2860_stop_locked(sc);
3921 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp);
3923 /* reset Rx ring and all 6 Tx rings */
3924 RAL_WRITE(sc, RT2860_WPDMA_RST_IDX, 0x1003f);
3926 /* PBF hardware reset */
3927 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f);
3928 RAL_BARRIER_WRITE(sc);
3929 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00);
3931 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE | RT2860_IO_RF_PE);
3933 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST);
3934 RAL_BARRIER_WRITE(sc);
3935 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0);
3937 for (i = 0; i < nitems(rt2860_def_mac); i++)
3938 RAL_WRITE(sc, rt2860_def_mac[i].reg, rt2860_def_mac[i].val);
3939 if (sc->mac_ver >= 0x5390)
3940 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 0x00000404);
3941 else if (sc->mac_ver >= 0x3071) {
3942 /* set delay of PA_PE assertion to 1us (unit of 0.25us) */
3943 RAL_WRITE(sc, RT2860_TX_SW_CFG0,
3944 4 << RT2860_DLY_PAPE_EN_SHIFT);
3947 if (!(RAL_READ(sc, RT2860_PCI_CFG) & RT2860_PCI_CFG_PCI)) {
3948 sc->sc_flags |= RT2860_PCIE;
3949 /* PCIe has different clock cycle count than PCI */
3950 tmp = RAL_READ(sc, RT2860_US_CYC_CNT);
3951 tmp = (tmp & ~0xff) | 0x7d;
3952 RAL_WRITE(sc, RT2860_US_CYC_CNT, tmp);
3955 /* wait while MAC is busy */
3956 for (ntries = 0; ntries < 100; ntries++) {
3957 if (!(RAL_READ(sc, RT2860_MAC_STATUS_REG) &
3958 (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY)))
3962 if (ntries == 100) {
3963 device_printf(sc->sc_dev, "timeout waiting for MAC\n");
3964 rt2860_stop_locked(sc);
3968 /* clear Host to MCU mailbox */
3969 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0);
3970 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0);
3972 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0);
3975 if ((error = rt2860_bbp_init(sc)) != 0) {
3976 rt2860_stop_locked(sc);
3980 /* clear RX WCID search table */
3981 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(0), 0, 512);
3982 /* clear pairwise key table */
3983 RAL_SET_REGION_4(sc, RT2860_PKEY(0), 0, 2048);
3984 /* clear IV/EIV table */
3985 RAL_SET_REGION_4(sc, RT2860_IVEIV(0), 0, 512);
3986 /* clear WCID attribute table */
3987 RAL_SET_REGION_4(sc, RT2860_WCID_ATTR(0), 0, 256);
3988 /* clear shared key table */
3989 RAL_SET_REGION_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32);
3990 /* clear shared key mode */
3991 RAL_SET_REGION_4(sc, RT2860_SKEY_MODE_0_7, 0, 4);
3993 /* init Tx rings (4 EDCAs + HCCA + Mgt) */
3994 for (qid = 0; qid < 6; qid++) {
3995 RAL_WRITE(sc, RT2860_TX_BASE_PTR(qid), sc->txq[qid].paddr);
3996 RAL_WRITE(sc, RT2860_TX_MAX_CNT(qid), RT2860_TX_RING_COUNT);
3997 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), 0);
4001 RAL_WRITE(sc, RT2860_RX_BASE_PTR, sc->rxq.paddr);
4002 RAL_WRITE(sc, RT2860_RX_MAX_CNT, RT2860_RX_RING_COUNT);
4003 RAL_WRITE(sc, RT2860_RX_CALC_IDX, RT2860_RX_RING_COUNT - 1);
4005 /* setup maximum buffer sizes */
4006 RAL_WRITE(sc, RT2860_MAX_LEN_CFG, 1 << 12 |
4007 (MCLBYTES - sizeof (struct rt2860_rxwi) - 2));
4009 for (ntries = 0; ntries < 100; ntries++) {
4010 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG);
4011 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0)
4015 if (ntries == 100) {
4016 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n");
4017 rt2860_stop_locked(sc);
4021 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp);
4023 /* disable interrupts mitigation */
4024 RAL_WRITE(sc, RT2860_DELAY_INT_CFG, 0);
4026 /* write vendor-specific BBP values (from EEPROM) */
4027 for (i = 0; i < 8; i++) {
4028 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff)
4030 rt2860_mcu_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val);
4033 /* select Main antenna for 1T1R devices */
4034 if (sc->rf_rev == RT3070_RF_2020 ||
4035 sc->rf_rev == RT3070_RF_3020 ||
4036 sc->rf_rev == RT3070_RF_3320 ||
4037 sc->mac_ver == 0x5390)
4038 rt3090_set_rx_antenna(sc, 0);
4040 /* send LEDs operating mode to microcontroller */
4041 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0], 0);
4042 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1], 0);
4043 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2], 0);
4045 if (sc->mac_ver >= 0x5390)
4047 else if (sc->mac_ver >= 0x3071) {
4048 if ((error = rt3090_rf_init(sc)) != 0) {
4049 rt2860_stop_locked(sc);
4054 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_SLEEP, 0x02ff, 1);
4055 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_WAKEUP, 0, 1);
4057 if (sc->mac_ver >= 0x5390)
4058 rt5390_rf_wakeup(sc);
4059 else if (sc->mac_ver >= 0x3071)
4060 rt3090_rf_wakeup(sc);
4062 /* disable non-existing Rx chains */
4063 bbp3 = rt2860_mcu_bbp_read(sc, 3);
4064 bbp3 &= ~(1 << 3 | 1 << 4);
4065 if (sc->nrxchains == 2)
4067 else if (sc->nrxchains == 3)
4069 rt2860_mcu_bbp_write(sc, 3, bbp3);
4071 /* disable non-existing Tx chains */
4072 bbp1 = rt2860_mcu_bbp_read(sc, 1);
4073 if (sc->ntxchains == 1)
4074 bbp1 = (bbp1 & ~(1 << 3 | 1 << 4));
4075 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 2)
4076 bbp1 = (bbp1 & ~(1 << 4)) | 1 << 3;
4077 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 3)
4078 bbp1 = (bbp1 & ~(1 << 3)) | 1 << 4;
4079 rt2860_mcu_bbp_write(sc, 1, bbp1);
4081 if (sc->mac_ver >= 0x3071)
4082 rt3090_rf_setup(sc);
4084 /* select default channel */
4085 rt2860_switch_chan(sc, ic->ic_curchan);
4087 /* reset RF from MCU */
4088 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0);
4090 /* set RTS threshold */
4091 tmp = RAL_READ(sc, RT2860_TX_RTS_CFG);
4093 tmp |= IEEE80211_RTS_DEFAULT << 8;
4094 RAL_WRITE(sc, RT2860_TX_RTS_CFG, tmp);
4096 /* setup initial protection mode */
4097 rt2860_updateprot(ifp);
4099 /* turn radio LED on */
4100 rt2860_set_leds(sc, RT2860_LED_RADIO);
4102 /* enable Tx/Rx DMA engine */
4103 if ((error = rt2860_txrx_enable(sc)) != 0) {
4104 rt2860_stop_locked(sc);
4108 /* clear pending interrupts */
4109 RAL_WRITE(sc, RT2860_INT_STATUS, 0xffffffff);
4110 /* enable interrupts */
4111 RAL_WRITE(sc, RT2860_INT_MASK, 0x3fffc);
4113 if (sc->sc_flags & RT2860_ADVANCED_PS)
4114 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_PSLEVEL, sc->pslevel, 0);
4116 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4117 ifp->if_drv_flags |= IFF_DRV_RUNNING;
4119 callout_reset(&sc->watchdog_ch, hz, rt2860_watchdog, sc);
4123 rt2860_stop(void *arg)
4125 struct rt2860_softc *sc = arg;
4128 rt2860_stop_locked(sc);
4133 rt2860_stop_locked(struct rt2860_softc *sc)
4135 struct ifnet *ifp = sc->sc_ifp;
4139 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
4140 rt2860_set_leds(sc, 0); /* turn all LEDs off */
4142 callout_stop(&sc->watchdog_ch);
4143 sc->sc_tx_timer = 0;
4144 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
4146 /* disable interrupts */
4147 RAL_WRITE(sc, RT2860_INT_MASK, 0);
4149 /* disable GP timer */
4150 rt2860_set_gp_timer(sc, 0);
4153 tmp = RAL_READ(sc, RT2860_MAC_SYS_CTRL);
4154 tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN);
4155 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, tmp);
4158 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST);
4159 RAL_BARRIER_WRITE(sc);
4160 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0);
4162 /* reset Tx and Rx rings (and reclaim TXWIs) */
4164 for (qid = 0; qid < 6; qid++)
4165 rt2860_reset_tx_ring(sc, &sc->txq[qid]);
4166 rt2860_reset_rx_ring(sc, &sc->rxq);
4170 rt2860_load_microcode(struct rt2860_softc *sc)
4172 const struct firmware *fp;
4175 RAL_LOCK_ASSERT(sc);
4178 fp = firmware_get("rt2860fw");
4181 device_printf(sc->sc_dev,
4182 "unable to receive rt2860fw firmware image\n");
4186 /* set "host program ram write selection" bit */
4187 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_HST_PM_SEL);
4188 /* write microcode image */
4189 RAL_WRITE_REGION_1(sc, RT2860_FW_BASE, fp->data, fp->datasize);
4190 /* kick microcontroller unit */
4191 RAL_WRITE(sc, RT2860_SYS_CTRL, 0);
4192 RAL_BARRIER_WRITE(sc);
4193 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_MCU_RESET);
4195 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0);
4196 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0);
4198 /* wait until microcontroller is ready */
4199 RAL_BARRIER_READ_WRITE(sc);
4200 for (ntries = 0; ntries < 1000; ntries++) {
4201 if (RAL_READ(sc, RT2860_SYS_CTRL) & RT2860_MCU_READY)
4205 if (ntries == 1000) {
4206 device_printf(sc->sc_dev,
4207 "timeout waiting for MCU to initialize\n");
4212 firmware_put(fp, FIRMWARE_UNLOAD);
4217 * This function is called periodically to adjust Tx power based on
4218 * temperature variation.
4222 rt2860_calib(struct rt2860_softc *sc)
4224 struct ieee80211com *ic = &sc->sc_ic;
4225 const uint8_t *tssi;
4226 uint8_t step, bbp49;
4229 /* read current temperature */
4230 bbp49 = rt2860_mcu_bbp_read(sc, 49);
4232 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan)) {
4233 tssi = &sc->tssi_2ghz[4];
4234 step = sc->step_2ghz;
4236 tssi = &sc->tssi_5ghz[4];
4237 step = sc->step_5ghz;
4240 if (bbp49 < tssi[0]) { /* lower than reference */
4241 /* use higher Tx power than default */
4242 for (d = 0; d > -4 && bbp49 <= tssi[d - 1]; d--);
4243 } else if (bbp49 > tssi[0]) { /* greater than reference */
4244 /* use lower Tx power than default */
4245 for (d = 0; d < +4 && bbp49 >= tssi[d + 1]; d++);
4247 /* use default Tx power */
4252 DPRINTF(("BBP49=0x%02x, adjusting Tx power by %d\n", bbp49, d));
4254 /* write adjusted Tx power values for each Tx rate */
4255 for (ridx = 0; ridx < 5; ridx++) {
4256 if (sc->txpow20mhz[ridx] == 0xffffffff)
4258 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx),
4259 b4inc(sc->txpow20mhz[ridx], d));
4265 rt3090_set_rx_antenna(struct rt2860_softc *sc, int aux)
4270 if (sc->mac_ver == 0x5390) {
4271 rt2860_mcu_bbp_write(sc, 152,
4272 rt2860_mcu_bbp_read(sc, 152) & ~0x80);
4274 tmp = RAL_READ(sc, RT2860_PCI_EECTRL);
4275 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp & ~RT2860_C);
4276 tmp = RAL_READ(sc, RT2860_GPIO_CTRL);
4277 RAL_WRITE(sc, RT2860_GPIO_CTRL, (tmp & ~0x0808) | 0x08);
4280 if (sc->mac_ver == 0x5390) {
4281 rt2860_mcu_bbp_write(sc, 152,
4282 rt2860_mcu_bbp_read(sc, 152) | 0x80);
4284 tmp = RAL_READ(sc, RT2860_PCI_EECTRL);
4285 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp | RT2860_C);
4286 tmp = RAL_READ(sc, RT2860_GPIO_CTRL);
4287 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp & ~0x0808);
4293 rt2860_switch_chan(struct rt2860_softc *sc, struct ieee80211_channel *c)
4295 struct ifnet *ifp = sc->sc_ifp;
4296 struct ieee80211com *ic = ifp->if_l2com;
4299 chan = ieee80211_chan2ieee(ic, c);
4300 if (chan == 0 || chan == IEEE80211_CHAN_ANY)
4303 if (sc->mac_ver >= 0x5390)
4304 rt5390_set_chan(sc, chan);
4305 else if (sc->mac_ver >= 0x3071)
4306 rt3090_set_chan(sc, chan);
4308 rt2860_set_chan(sc, chan);
4310 /* determine channel group */
4313 else if (chan <= 64)
4315 else if (chan <= 128)
4320 /* XXX necessary only when group has changed! */
4321 if (sc->mac_ver < 0x5390)
4322 rt2860_select_chan_group(sc, group);
4328 rt2860_setup_beacon(struct rt2860_softc *sc, struct ieee80211vap *vap)
4330 struct ieee80211com *ic = vap->iv_ic;
4331 struct ieee80211_beacon_offsets bo;
4332 struct rt2860_txwi txwi;
4336 if ((m = ieee80211_beacon_alloc(vap->iv_bss, &bo)) == NULL)
4339 memset(&txwi, 0, sizeof txwi);
4341 txwi.len = htole16(m->m_pkthdr.len);
4342 /* send beacons at the lowest available rate */
4343 ridx = IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan) ?
4344 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1;
4345 txwi.phy = htole16(rt2860_rates[ridx].mcs);
4346 if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM)
4347 txwi.phy |= htole16(RT2860_PHY_OFDM);
4348 txwi.txop = RT2860_TX_TXOP_HT;
4349 txwi.flags = RT2860_TX_TS;
4350 txwi.xflags = RT2860_TX_NSEQ;
4352 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0),
4353 (uint8_t *)&txwi, sizeof txwi);
4354 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0) + sizeof txwi,
4355 mtod(m, uint8_t *), m->m_pkthdr.len);
4363 rt2860_enable_tsf_sync(struct rt2860_softc *sc)
4365 struct ifnet *ifp = sc->sc_ifp;
4366 struct ieee80211com *ic = ifp->if_l2com;
4367 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
4370 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG);
4373 tmp |= vap->iv_bss->ni_intval * 16;
4374 tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN;
4375 if (vap->iv_opmode == IEEE80211_M_STA) {
4377 * Local TSF is always updated with remote TSF on beacon
4380 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT;
4382 else if (vap->iv_opmode == IEEE80211_M_IBSS ||
4383 vap->iv_opmode == IEEE80211_M_MBSS) {
4384 tmp |= RT2860_BCN_TX_EN;
4386 * Local TSF is updated with remote TSF on beacon reception
4387 * only if the remote TSF is greater than local TSF.
4389 tmp |= 2 << RT2860_TSF_SYNC_MODE_SHIFT;
4390 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP) {
4391 tmp |= RT2860_BCN_TX_EN;
4392 /* SYNC with nobody */
4393 tmp |= 3 << RT2860_TSF_SYNC_MODE_SHIFT;
4396 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, tmp);