2 * Copyright (c) 1997, 1998-2003
3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver
39 * Written by Bill Paul <wpaul@windriver.com>
40 * Senior Networking Software Engineer
45 * This driver is designed to support RealTek's next generation of
46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S,
48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E.
50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
51 * with the older 8139 family, however it also supports a special
52 * C+ mode of operation that provides several new performance enhancing
53 * features. These include:
55 * o Descriptor based DMA mechanism. Each descriptor represents
56 * a single packet fragment. Data buffers may be aligned on
61 * o TCP/IP checksum offload for both RX and TX
63 * o High and normal priority transmit DMA rings
65 * o VLAN tag insertion and extraction
67 * o TCP large send (segmentation offload)
69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
70 * programming API is fairly straightforward. The RX filtering, EEPROM
71 * access and PHY access is the same as it is on the older 8139 series
74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
75 * same programming API and feature set as the 8139C+ with the following
76 * differences and additions:
82 * o GMII and TBI ports/registers for interfacing with copper
85 * o RX and TX DMA rings can have up to 1024 descriptors
86 * (the 8139C+ allows a maximum of 64)
88 * o Slight differences in register layout from the 8139C+
90 * The TX start and timer interrupt registers are at different locations
91 * on the 8169 than they are on the 8139C+. Also, the status word in the
92 * RX descriptor has a slightly different bit layout. The 8169 does not
93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
97 * (the 'S' stands for 'single-chip'). These devices have the same
98 * programming API as the older 8169, but also have some vendor-specific
99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
102 * This driver takes advantage of the RX and TX checksum offload and
103 * VLAN tag insertion/extraction features. It also implements TX
104 * interrupt moderation using the timer interrupt registers, which
105 * significantly reduces TX interrupt load. There is also support
106 * for jumbo frames, however the 8169/8169S/8110S can not transmit
107 * jumbo frames larger than 7440, so the max MTU possible with this
108 * driver is 7422 bytes.
111 #ifdef HAVE_KERNEL_OPTION_HEADERS
112 #include "opt_device_polling.h"
115 #include <sys/param.h>
116 #include <sys/endian.h>
117 #include <sys/systm.h>
118 #include <sys/sockio.h>
119 #include <sys/mbuf.h>
120 #include <sys/malloc.h>
121 #include <sys/module.h>
122 #include <sys/kernel.h>
123 #include <sys/socket.h>
124 #include <sys/lock.h>
125 #include <sys/mutex.h>
126 #include <sys/sysctl.h>
127 #include <sys/taskqueue.h>
130 #include <net/if_arp.h>
131 #include <net/ethernet.h>
132 #include <net/if_dl.h>
133 #include <net/if_media.h>
134 #include <net/if_types.h>
135 #include <net/if_vlan_var.h>
139 #include <machine/bus.h>
140 #include <machine/resource.h>
142 #include <sys/rman.h>
144 #include <dev/mii/mii.h>
145 #include <dev/mii/miivar.h>
147 #include <dev/pci/pcireg.h>
148 #include <dev/pci/pcivar.h>
150 #include <pci/if_rlreg.h>
152 MODULE_DEPEND(re, pci, 1, 1, 1);
153 MODULE_DEPEND(re, ether, 1, 1, 1);
154 MODULE_DEPEND(re, miibus, 1, 1, 1);
156 /* "device miibus" required. See GENERIC if you get errors here. */
157 #include "miibus_if.h"
160 static int intr_filter = 0;
161 TUNABLE_INT("hw.re.intr_filter", &intr_filter);
162 static int msi_disable = 0;
163 TUNABLE_INT("hw.re.msi_disable", &msi_disable);
164 static int msix_disable = 0;
165 TUNABLE_INT("hw.re.msix_disable", &msix_disable);
166 static int prefer_iomap = 0;
167 TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap);
169 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
172 * Various supported device vendors/types and their names.
174 static const struct rl_type re_devs[] = {
175 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0,
176 "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
177 { DLINK_VENDORID, DLINK_DEVICEID_530T_REVC, 0,
178 "D-Link DGE-530(T) Gigabit Ethernet Adapter" },
179 { RT_VENDORID, RT_DEVICEID_8139, 0,
180 "RealTek 8139C+ 10/100BaseTX" },
181 { RT_VENDORID, RT_DEVICEID_8101E, 0,
182 "RealTek 810xE PCIe 10/100baseTX" },
183 { RT_VENDORID, RT_DEVICEID_8168, 0,
184 "RealTek 8168/8111 B/C/CP/D/DP/E/F PCIe Gigabit Ethernet" },
185 { RT_VENDORID, RT_DEVICEID_8169, 0,
186 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" },
187 { RT_VENDORID, RT_DEVICEID_8169SC, 0,
188 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
189 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0,
190 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" },
191 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0,
192 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" },
193 { USR_VENDORID, USR_DEVICEID_997902, 0,
194 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" }
197 static const struct rl_hwrev re_hwrevs[] = {
198 { RL_HWREV_8139, RL_8139, "", RL_MTU },
199 { RL_HWREV_8139A, RL_8139, "A", RL_MTU },
200 { RL_HWREV_8139AG, RL_8139, "A-G", RL_MTU },
201 { RL_HWREV_8139B, RL_8139, "B", RL_MTU },
202 { RL_HWREV_8130, RL_8139, "8130", RL_MTU },
203 { RL_HWREV_8139C, RL_8139, "C", RL_MTU },
204 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C", RL_MTU },
205 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+", RL_MTU },
206 { RL_HWREV_8168B_SPIN1, RL_8169, "8168", RL_JUMBO_MTU },
207 { RL_HWREV_8169, RL_8169, "8169", RL_JUMBO_MTU },
208 { RL_HWREV_8169S, RL_8169, "8169S", RL_JUMBO_MTU },
209 { RL_HWREV_8110S, RL_8169, "8110S", RL_JUMBO_MTU },
210 { RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB", RL_JUMBO_MTU },
211 { RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU },
212 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL", RL_JUMBO_MTU },
213 { RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU },
214 { RL_HWREV_8100, RL_8139, "8100", RL_MTU },
215 { RL_HWREV_8101, RL_8139, "8101", RL_MTU },
216 { RL_HWREV_8100E, RL_8169, "8100E", RL_MTU },
217 { RL_HWREV_8101E, RL_8169, "8101E", RL_MTU },
218 { RL_HWREV_8102E, RL_8169, "8102E", RL_MTU },
219 { RL_HWREV_8102EL, RL_8169, "8102EL", RL_MTU },
220 { RL_HWREV_8102EL_SPIN1, RL_8169, "8102EL", RL_MTU },
221 { RL_HWREV_8103E, RL_8169, "8103E", RL_MTU },
222 { RL_HWREV_8401E, RL_8169, "8401E", RL_MTU },
223 { RL_HWREV_8402, RL_8169, "8402", RL_MTU },
224 { RL_HWREV_8105E, RL_8169, "8105E", RL_MTU },
225 { RL_HWREV_8105E_SPIN1, RL_8169, "8105E", RL_MTU },
226 { RL_HWREV_8168B_SPIN2, RL_8169, "8168", RL_JUMBO_MTU },
227 { RL_HWREV_8168B_SPIN3, RL_8169, "8168", RL_JUMBO_MTU },
228 { RL_HWREV_8168C, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K },
229 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K },
230 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP", RL_JUMBO_MTU_6K },
231 { RL_HWREV_8168D, RL_8169, "8168D/8111D", RL_JUMBO_MTU_9K },
232 { RL_HWREV_8168DP, RL_8169, "8168DP/8111DP", RL_JUMBO_MTU_9K },
233 { RL_HWREV_8168E, RL_8169, "8168E/8111E", RL_JUMBO_MTU_9K},
234 { RL_HWREV_8168E_VL, RL_8169, "8168E/8111E-VL", RL_JUMBO_MTU_6K},
235 { RL_HWREV_8168F, RL_8169, "8168F/8111F", RL_JUMBO_MTU_9K},
236 { RL_HWREV_8411, RL_8169, "8411", RL_JUMBO_MTU_9K},
240 static int re_probe (device_t);
241 static int re_attach (device_t);
242 static int re_detach (device_t);
244 static int re_encap (struct rl_softc *, struct mbuf **);
246 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int);
247 static int re_allocmem (device_t, struct rl_softc *);
248 static __inline void re_discard_rxbuf
249 (struct rl_softc *, int);
250 static int re_newbuf (struct rl_softc *, int);
251 static int re_jumbo_newbuf (struct rl_softc *, int);
252 static int re_rx_list_init (struct rl_softc *);
253 static int re_jrx_list_init (struct rl_softc *);
254 static int re_tx_list_init (struct rl_softc *);
256 static __inline void re_fixup_rx
259 static int re_rxeof (struct rl_softc *, int *);
260 static void re_txeof (struct rl_softc *);
261 #ifdef DEVICE_POLLING
262 static int re_poll (struct ifnet *, enum poll_cmd, int);
263 static int re_poll_locked (struct ifnet *, enum poll_cmd, int);
265 static int re_intr (void *);
266 static void re_intr_msi (void *);
267 static void re_tick (void *);
268 static void re_int_task (void *, int);
269 static void re_start (struct ifnet *);
270 static void re_start_locked (struct ifnet *);
271 static int re_ioctl (struct ifnet *, u_long, caddr_t);
272 static void re_init (void *);
273 static void re_init_locked (struct rl_softc *);
274 static void re_stop (struct rl_softc *);
275 static void re_watchdog (struct rl_softc *);
276 static int re_suspend (device_t);
277 static int re_resume (device_t);
278 static int re_shutdown (device_t);
279 static int re_ifmedia_upd (struct ifnet *);
280 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *);
282 static void re_eeprom_putbyte (struct rl_softc *, int);
283 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *);
284 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int);
285 static int re_gmii_readreg (device_t, int, int);
286 static int re_gmii_writereg (device_t, int, int, int);
288 static int re_miibus_readreg (device_t, int, int);
289 static int re_miibus_writereg (device_t, int, int, int);
290 static void re_miibus_statchg (device_t);
292 static void re_set_jumbo (struct rl_softc *, int);
293 static void re_set_rxmode (struct rl_softc *);
294 static void re_reset (struct rl_softc *);
295 static void re_setwol (struct rl_softc *);
296 static void re_clrwol (struct rl_softc *);
297 static void re_set_linkspeed (struct rl_softc *);
299 #ifdef DEV_NETMAP /* see ixgbe.c for details */
300 #include <dev/netmap/if_re_netmap.h>
301 #endif /* !DEV_NETMAP */
304 static int re_diag (struct rl_softc *);
307 static void re_add_sysctls (struct rl_softc *);
308 static int re_sysctl_stats (SYSCTL_HANDLER_ARGS);
309 static int sysctl_int_range (SYSCTL_HANDLER_ARGS, int, int);
310 static int sysctl_hw_re_int_mod (SYSCTL_HANDLER_ARGS);
312 static device_method_t re_methods[] = {
313 /* Device interface */
314 DEVMETHOD(device_probe, re_probe),
315 DEVMETHOD(device_attach, re_attach),
316 DEVMETHOD(device_detach, re_detach),
317 DEVMETHOD(device_suspend, re_suspend),
318 DEVMETHOD(device_resume, re_resume),
319 DEVMETHOD(device_shutdown, re_shutdown),
322 DEVMETHOD(miibus_readreg, re_miibus_readreg),
323 DEVMETHOD(miibus_writereg, re_miibus_writereg),
324 DEVMETHOD(miibus_statchg, re_miibus_statchg),
329 static driver_t re_driver = {
332 sizeof(struct rl_softc)
335 static devclass_t re_devclass;
337 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0);
338 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0);
341 CSR_WRITE_1(sc, RL_EECMD, \
342 CSR_READ_1(sc, RL_EECMD) | x)
345 CSR_WRITE_1(sc, RL_EECMD, \
346 CSR_READ_1(sc, RL_EECMD) & ~x)
349 * Send a read command and address to the EEPROM, check for ACK.
352 re_eeprom_putbyte(struct rl_softc *sc, int addr)
356 d = addr | (RL_9346_READ << sc->rl_eewidth);
359 * Feed in each bit and strobe the clock.
362 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) {
364 EE_SET(RL_EE_DATAIN);
366 EE_CLR(RL_EE_DATAIN);
377 * Read a word of data stored in the EEPROM at address 'addr.'
380 re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest)
386 * Send address of word we want to read.
388 re_eeprom_putbyte(sc, addr);
391 * Start reading bits from EEPROM.
393 for (i = 0x8000; i; i >>= 1) {
396 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
406 * Read a sequence of words from the EEPROM.
409 re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt)
412 u_int16_t word = 0, *ptr;
414 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM);
418 for (i = 0; i < cnt; i++) {
419 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL);
420 re_eeprom_getword(sc, off + i, &word);
421 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL);
422 ptr = (u_int16_t *)(dest + (i * 2));
426 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM);
430 re_gmii_readreg(device_t dev, int phy, int reg)
436 sc = device_get_softc(dev);
438 /* Let the rgephy driver read the GMEDIASTAT register */
440 if (reg == RL_GMEDIASTAT) {
441 rval = CSR_READ_1(sc, RL_GMEDIASTAT);
445 CSR_WRITE_4(sc, RL_PHYAR, reg << 16);
447 for (i = 0; i < RL_PHY_TIMEOUT; i++) {
448 rval = CSR_READ_4(sc, RL_PHYAR);
449 if (rval & RL_PHYAR_BUSY)
454 if (i == RL_PHY_TIMEOUT) {
455 device_printf(sc->rl_dev, "PHY read failed\n");
460 * Controller requires a 20us delay to process next MDIO request.
464 return (rval & RL_PHYAR_PHYDATA);
468 re_gmii_writereg(device_t dev, int phy, int reg, int data)
474 sc = device_get_softc(dev);
476 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) |
477 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY);
479 for (i = 0; i < RL_PHY_TIMEOUT; i++) {
480 rval = CSR_READ_4(sc, RL_PHYAR);
481 if (!(rval & RL_PHYAR_BUSY))
486 if (i == RL_PHY_TIMEOUT) {
487 device_printf(sc->rl_dev, "PHY write failed\n");
492 * Controller requires a 20us delay to process next MDIO request.
500 re_miibus_readreg(device_t dev, int phy, int reg)
504 u_int16_t re8139_reg = 0;
506 sc = device_get_softc(dev);
508 if (sc->rl_type == RL_8169) {
509 rval = re_gmii_readreg(dev, phy, reg);
515 re8139_reg = RL_BMCR;
518 re8139_reg = RL_BMSR;
521 re8139_reg = RL_ANAR;
524 re8139_reg = RL_ANER;
527 re8139_reg = RL_LPAR;
533 * Allow the rlphy driver to read the media status
534 * register. If we have a link partner which does not
535 * support NWAY, this is the register which will tell
536 * us the results of parallel detection.
539 rval = CSR_READ_1(sc, RL_MEDIASTAT);
542 device_printf(sc->rl_dev, "bad phy register\n");
545 rval = CSR_READ_2(sc, re8139_reg);
546 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) {
547 /* 8139C+ has different bit layout. */
548 rval &= ~(BMCR_LOOP | BMCR_ISO);
554 re_miibus_writereg(device_t dev, int phy, int reg, int data)
557 u_int16_t re8139_reg = 0;
560 sc = device_get_softc(dev);
562 if (sc->rl_type == RL_8169) {
563 rval = re_gmii_writereg(dev, phy, reg, data);
569 re8139_reg = RL_BMCR;
570 if (sc->rl_type == RL_8139CPLUS) {
571 /* 8139C+ has different bit layout. */
572 data &= ~(BMCR_LOOP | BMCR_ISO);
576 re8139_reg = RL_BMSR;
579 re8139_reg = RL_ANAR;
582 re8139_reg = RL_ANER;
585 re8139_reg = RL_LPAR;
592 device_printf(sc->rl_dev, "bad phy register\n");
595 CSR_WRITE_2(sc, re8139_reg, data);
600 re_miibus_statchg(device_t dev)
604 struct mii_data *mii;
606 sc = device_get_softc(dev);
607 mii = device_get_softc(sc->rl_miibus);
609 if (mii == NULL || ifp == NULL ||
610 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
613 sc->rl_flags &= ~RL_FLAG_LINK;
614 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
615 (IFM_ACTIVE | IFM_AVALID)) {
616 switch (IFM_SUBTYPE(mii->mii_media_active)) {
619 sc->rl_flags |= RL_FLAG_LINK;
622 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0)
624 sc->rl_flags |= RL_FLAG_LINK;
631 * RealTek controllers does not provide any interface to
632 * Tx/Rx MACs for resolved speed, duplex and flow-control
638 * Set the RX configuration and 64-bit multicast hash filter.
641 re_set_rxmode(struct rl_softc *sc)
644 struct ifmultiaddr *ifma;
645 uint32_t hashes[2] = { 0, 0 };
652 rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD;
654 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
655 if (ifp->if_flags & IFF_PROMISC)
656 rxfilt |= RL_RXCFG_RX_ALLPHYS;
658 * Unlike other hardwares, we have to explicitly set
659 * RL_RXCFG_RX_MULTI to receive multicast frames in
662 rxfilt |= RL_RXCFG_RX_MULTI;
663 hashes[0] = hashes[1] = 0xffffffff;
668 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
669 if (ifma->ifma_addr->sa_family != AF_LINK)
671 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
672 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
674 hashes[0] |= (1 << h);
676 hashes[1] |= (1 << (h - 32));
678 if_maddr_runlock(ifp);
680 if (hashes[0] != 0 || hashes[1] != 0) {
682 * For some unfathomable reason, RealTek decided to
683 * reverse the order of the multicast hash registers
684 * in the PCI Express parts. This means we have to
685 * write the hash pattern in reverse order for those
688 if ((sc->rl_flags & RL_FLAG_PCIE) != 0) {
689 h = bswap32(hashes[0]);
690 hashes[0] = bswap32(hashes[1]);
693 rxfilt |= RL_RXCFG_RX_MULTI;
697 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
698 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
699 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
703 re_reset(struct rl_softc *sc)
709 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
711 for (i = 0; i < RL_TIMEOUT; i++) {
713 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
717 device_printf(sc->rl_dev, "reset never completed!\n");
719 if ((sc->rl_flags & RL_FLAG_MACRESET) != 0)
720 CSR_WRITE_1(sc, 0x82, 1);
721 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169S)
722 re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0);
728 * The following routine is designed to test for a defect on some
729 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
730 * lines connected to the bus, however for a 32-bit only card, they
731 * should be pulled high. The result of this defect is that the
732 * NIC will not work right if you plug it into a 64-bit slot: DMA
733 * operations will be done with 64-bit transfers, which will fail
734 * because the 64-bit data lines aren't connected.
736 * There's no way to work around this (short of talking a soldering
737 * iron to the board), however we can detect it. The method we use
738 * here is to put the NIC into digital loopback mode, set the receiver
739 * to promiscuous mode, and then try to send a frame. We then compare
740 * the frame data we sent to what was received. If the data matches,
741 * then the NIC is working correctly, otherwise we know the user has
742 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
743 * slot. In the latter case, there's no way the NIC can work correctly,
744 * so we print out a message on the console and abort the device attach.
748 re_diag(struct rl_softc *sc)
750 struct ifnet *ifp = sc->rl_ifp;
752 struct ether_header *eh;
753 struct rl_desc *cur_rx;
756 int total_len, i, error = 0, phyaddr;
757 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
758 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
760 /* Allocate a single mbuf */
761 MGETHDR(m0, M_NOWAIT, MT_DATA);
768 * Initialize the NIC in test mode. This sets the chip up
769 * so that it can send and receive frames, but performs the
770 * following special functions:
771 * - Puts receiver in promiscuous mode
772 * - Enables digital loopback mode
773 * - Leaves interrupts turned off
776 ifp->if_flags |= IFF_PROMISC;
778 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
780 sc->rl_flags |= RL_FLAG_LINK;
781 if (sc->rl_type == RL_8169)
786 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET);
787 for (i = 0; i < RL_TIMEOUT; i++) {
788 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR);
789 if (!(status & BMCR_RESET))
793 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP);
794 CSR_WRITE_2(sc, RL_ISR, RL_INTRS);
798 /* Put some data in the mbuf */
800 eh = mtod(m0, struct ether_header *);
801 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN);
802 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN);
803 eh->ether_type = htons(ETHERTYPE_IP);
804 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
807 * Queue the packet, start transmission.
808 * Note: IF_HANDOFF() ultimately calls re_start() for us.
811 CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
813 /* XXX: re_diag must not be called when in ALTQ mode */
814 IF_HANDOFF(&ifp->if_snd, m0, ifp);
818 /* Wait for it to propagate through the chip */
821 for (i = 0; i < RL_TIMEOUT; i++) {
822 status = CSR_READ_2(sc, RL_ISR);
823 CSR_WRITE_2(sc, RL_ISR, status);
824 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) ==
825 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK))
830 if (i == RL_TIMEOUT) {
831 device_printf(sc->rl_dev,
832 "diagnostic failed, failed to receive packet in"
839 * The packet should have been dumped into the first
840 * entry in the RX DMA ring. Grab it from there.
843 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
844 sc->rl_ldata.rl_rx_list_map,
845 BUS_DMASYNC_POSTREAD);
846 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag,
847 sc->rl_ldata.rl_rx_desc[0].rx_dmamap,
848 BUS_DMASYNC_POSTREAD);
849 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag,
850 sc->rl_ldata.rl_rx_desc[0].rx_dmamap);
852 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m;
853 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL;
854 eh = mtod(m0, struct ether_header *);
856 cur_rx = &sc->rl_ldata.rl_rx_list[0];
857 total_len = RL_RXBYTES(cur_rx);
858 rxstat = le32toh(cur_rx->rl_cmdstat);
860 if (total_len != ETHER_MIN_LEN) {
861 device_printf(sc->rl_dev,
862 "diagnostic failed, received short packet\n");
867 /* Test that the received packet data matches what we sent. */
869 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) ||
870 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) ||
871 ntohs(eh->ether_type) != ETHERTYPE_IP) {
872 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n");
873 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n",
874 dst, ":", src, ":", ETHERTYPE_IP);
875 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n",
876 eh->ether_dhost, ":", eh->ether_shost, ":",
877 ntohs(eh->ether_type));
878 device_printf(sc->rl_dev, "You may have a defective 32-bit "
879 "NIC plugged into a 64-bit PCI slot.\n");
880 device_printf(sc->rl_dev, "Please re-install the NIC in a "
881 "32-bit slot for proper operation.\n");
882 device_printf(sc->rl_dev, "Read the re(4) man page for more "
888 /* Turn interface off, release resources */
891 sc->rl_flags &= ~RL_FLAG_LINK;
892 ifp->if_flags &= ~IFF_PROMISC;
905 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
906 * IDs against our list and return a device name if we find a match.
909 re_probe(device_t dev)
911 const struct rl_type *t;
912 uint16_t devid, vendor;
913 uint16_t revid, sdevid;
916 vendor = pci_get_vendor(dev);
917 devid = pci_get_device(dev);
918 revid = pci_get_revid(dev);
919 sdevid = pci_get_subdevice(dev);
921 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) {
922 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) {
924 * Only attach to rev. 3 of the Linksys EG1032 adapter.
925 * Rev. 2 is supported by sk(4).
931 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) {
933 /* 8139, let rl(4) take care of this device. */
939 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) {
940 if (vendor == t->rl_vid && devid == t->rl_did) {
941 device_set_desc(dev, t->rl_name);
942 return (BUS_PROBE_DEFAULT);
950 * Map a single buffer address.
954 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
961 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
963 *addr = segs->ds_addr;
967 re_allocmem(device_t dev, struct rl_softc *sc)
970 bus_size_t rx_list_size, tx_list_size;
974 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc);
975 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc);
978 * Allocate the parent bus DMA tag appropriate for PCI.
979 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD
980 * register should be set. However some RealTek chips are known
981 * to be buggy on DAC handling, therefore disable DAC by limiting
982 * DMA address space to 32bit. PCIe variants of RealTek chips
983 * may not have the limitation.
985 lowaddr = BUS_SPACE_MAXADDR;
986 if ((sc->rl_flags & RL_FLAG_PCIE) == 0)
987 lowaddr = BUS_SPACE_MAXADDR_32BIT;
988 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
989 lowaddr, BUS_SPACE_MAXADDR, NULL, NULL,
990 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
991 NULL, NULL, &sc->rl_parent_tag);
993 device_printf(dev, "could not allocate parent DMA tag\n");
998 * Allocate map for TX mbufs.
1000 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0,
1001 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
1002 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0,
1003 NULL, NULL, &sc->rl_ldata.rl_tx_mtag);
1005 device_printf(dev, "could not allocate TX DMA tag\n");
1010 * Allocate map for RX mbufs.
1013 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
1014 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t),
1015 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1016 MJUM9BYTES, 1, MJUM9BYTES, 0, NULL, NULL,
1017 &sc->rl_ldata.rl_jrx_mtag);
1020 "could not allocate jumbo RX DMA tag\n");
1024 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0,
1025 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1026 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag);
1028 device_printf(dev, "could not allocate RX DMA tag\n");
1033 * Allocate map for TX descriptor list.
1035 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
1036 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1037 NULL, tx_list_size, 1, tx_list_size, 0,
1038 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag);
1040 device_printf(dev, "could not allocate TX DMA ring tag\n");
1044 /* Allocate DMA'able memory for the TX ring */
1046 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag,
1047 (void **)&sc->rl_ldata.rl_tx_list,
1048 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
1049 &sc->rl_ldata.rl_tx_list_map);
1051 device_printf(dev, "could not allocate TX DMA ring\n");
1055 /* Load the map for the TX ring. */
1057 sc->rl_ldata.rl_tx_list_addr = 0;
1058 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag,
1059 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list,
1060 tx_list_size, re_dma_map_addr,
1061 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT);
1062 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) {
1063 device_printf(dev, "could not load TX DMA ring\n");
1067 /* Create DMA maps for TX buffers */
1069 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
1070 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0,
1071 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap);
1073 device_printf(dev, "could not create DMA map for TX\n");
1079 * Allocate map for RX descriptor list.
1081 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
1082 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1083 NULL, rx_list_size, 1, rx_list_size, 0,
1084 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag);
1086 device_printf(dev, "could not create RX DMA ring tag\n");
1090 /* Allocate DMA'able memory for the RX ring */
1092 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag,
1093 (void **)&sc->rl_ldata.rl_rx_list,
1094 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
1095 &sc->rl_ldata.rl_rx_list_map);
1097 device_printf(dev, "could not allocate RX DMA ring\n");
1101 /* Load the map for the RX ring. */
1103 sc->rl_ldata.rl_rx_list_addr = 0;
1104 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag,
1105 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list,
1106 rx_list_size, re_dma_map_addr,
1107 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT);
1108 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) {
1109 device_printf(dev, "could not load RX DMA ring\n");
1113 /* Create DMA maps for RX buffers */
1115 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
1116 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0,
1117 &sc->rl_ldata.rl_jrx_sparemap);
1120 "could not create spare DMA map for jumbo RX\n");
1123 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
1124 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0,
1125 &sc->rl_ldata.rl_jrx_desc[i].rx_dmamap);
1128 "could not create DMA map for jumbo RX\n");
1133 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0,
1134 &sc->rl_ldata.rl_rx_sparemap);
1136 device_printf(dev, "could not create spare DMA map for RX\n");
1139 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
1140 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0,
1141 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap);
1143 device_printf(dev, "could not create DMA map for RX\n");
1148 /* Create DMA map for statistics. */
1149 error = bus_dma_tag_create(sc->rl_parent_tag, RL_DUMP_ALIGN, 0,
1150 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1151 sizeof(struct rl_stats), 1, sizeof(struct rl_stats), 0, NULL, NULL,
1152 &sc->rl_ldata.rl_stag);
1154 device_printf(dev, "could not create statistics DMA tag\n");
1157 /* Allocate DMA'able memory for statistics. */
1158 error = bus_dmamem_alloc(sc->rl_ldata.rl_stag,
1159 (void **)&sc->rl_ldata.rl_stats,
1160 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
1161 &sc->rl_ldata.rl_smap);
1164 "could not allocate statistics DMA memory\n");
1167 /* Load the map for statistics. */
1168 sc->rl_ldata.rl_stats_addr = 0;
1169 error = bus_dmamap_load(sc->rl_ldata.rl_stag, sc->rl_ldata.rl_smap,
1170 sc->rl_ldata.rl_stats, sizeof(struct rl_stats), re_dma_map_addr,
1171 &sc->rl_ldata.rl_stats_addr, BUS_DMA_NOWAIT);
1172 if (error != 0 || sc->rl_ldata.rl_stats_addr == 0) {
1173 device_printf(dev, "could not load statistics DMA memory\n");
1181 * Attach the interface. Allocate softc structures, do ifmedia
1182 * setup and ethernet/BPF attach.
1185 re_attach(device_t dev)
1187 u_char eaddr[ETHER_ADDR_LEN];
1188 u_int16_t as[ETHER_ADDR_LEN / 2];
1189 struct rl_softc *sc;
1191 const struct rl_hwrev *hw_rev;
1194 u_int16_t devid, re_did = 0;
1195 int error = 0, i, phy, rid;
1196 int msic, msixc, reg;
1199 sc = device_get_softc(dev);
1202 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1204 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
1207 * Map control/status registers.
1209 pci_enable_busmaster(dev);
1211 devid = pci_get_device(dev);
1213 * Prefer memory space register mapping over IO space.
1214 * Because RTL8169SC does not seem to work when memory mapping
1215 * is used always activate io mapping.
1217 if (devid == RT_DEVICEID_8169SC)
1219 if (prefer_iomap == 0) {
1220 sc->rl_res_id = PCIR_BAR(1);
1221 sc->rl_res_type = SYS_RES_MEMORY;
1222 /* RTL8168/8101E seems to use different BARs. */
1223 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E)
1224 sc->rl_res_id = PCIR_BAR(2);
1226 sc->rl_res_id = PCIR_BAR(0);
1227 sc->rl_res_type = SYS_RES_IOPORT;
1229 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
1230 &sc->rl_res_id, RF_ACTIVE);
1231 if (sc->rl_res == NULL && prefer_iomap == 0) {
1232 sc->rl_res_id = PCIR_BAR(0);
1233 sc->rl_res_type = SYS_RES_IOPORT;
1234 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
1235 &sc->rl_res_id, RF_ACTIVE);
1237 if (sc->rl_res == NULL) {
1238 device_printf(dev, "couldn't map ports/memory\n");
1243 sc->rl_btag = rman_get_bustag(sc->rl_res);
1244 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
1246 msic = pci_msi_count(dev);
1247 msixc = pci_msix_count(dev);
1248 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) {
1249 sc->rl_flags |= RL_FLAG_PCIE;
1250 sc->rl_expcap = reg;
1253 device_printf(dev, "MSI count : %d\n", msic);
1254 device_printf(dev, "MSI-X count : %d\n", msixc);
1256 if (msix_disable > 0)
1258 if (msi_disable > 0)
1260 /* Prefer MSI-X to MSI. */
1264 sc->rl_res_pba = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1266 if (sc->rl_res_pba == NULL) {
1267 device_printf(sc->rl_dev,
1268 "could not allocate MSI-X PBA resource\n");
1270 if (sc->rl_res_pba != NULL &&
1271 pci_alloc_msix(dev, &msixc) == 0) {
1273 device_printf(dev, "Using %d MSI-X message\n",
1275 sc->rl_flags |= RL_FLAG_MSIX;
1277 pci_release_msi(dev);
1279 if ((sc->rl_flags & RL_FLAG_MSIX) == 0) {
1280 if (sc->rl_res_pba != NULL)
1281 bus_release_resource(dev, SYS_RES_MEMORY, rid,
1283 sc->rl_res_pba = NULL;
1287 /* Prefer MSI to INTx. */
1288 if (msixc == 0 && msic > 0) {
1290 if (pci_alloc_msi(dev, &msic) == 0) {
1291 if (msic == RL_MSI_MESSAGES) {
1292 device_printf(dev, "Using %d MSI message\n",
1294 sc->rl_flags |= RL_FLAG_MSI;
1295 /* Explicitly set MSI enable bit. */
1296 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
1297 cfg = CSR_READ_1(sc, RL_CFG2);
1299 CSR_WRITE_1(sc, RL_CFG2, cfg);
1300 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1302 pci_release_msi(dev);
1304 if ((sc->rl_flags & RL_FLAG_MSI) == 0)
1308 /* Allocate interrupt */
1309 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) {
1311 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1312 RF_SHAREABLE | RF_ACTIVE);
1313 if (sc->rl_irq[0] == NULL) {
1314 device_printf(dev, "couldn't allocate IRQ resources\n");
1319 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) {
1320 sc->rl_irq[i] = bus_alloc_resource_any(dev,
1321 SYS_RES_IRQ, &rid, RF_ACTIVE);
1322 if (sc->rl_irq[i] == NULL) {
1324 "couldn't llocate IRQ resources for "
1325 "message %d\n", rid);
1332 if ((sc->rl_flags & RL_FLAG_MSI) == 0) {
1333 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
1334 cfg = CSR_READ_1(sc, RL_CFG2);
1335 if ((cfg & RL_CFG2_MSI) != 0) {
1336 device_printf(dev, "turning off MSI enable bit.\n");
1337 cfg &= ~RL_CFG2_MSI;
1338 CSR_WRITE_1(sc, RL_CFG2, cfg);
1340 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1343 /* Disable ASPM L0S/L1. */
1344 if (sc->rl_expcap != 0) {
1345 cap = pci_read_config(dev, sc->rl_expcap +
1347 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) {
1348 ctl = pci_read_config(dev, sc->rl_expcap +
1350 if ((ctl & 0x0003) != 0) {
1352 pci_write_config(dev, sc->rl_expcap +
1353 PCIER_LINK_CTL, ctl, 2);
1354 device_printf(dev, "ASPM disabled\n");
1357 device_printf(dev, "no ASPM capability\n");
1361 hwrev = CSR_READ_4(sc, RL_TXCFG);
1362 switch (hwrev & 0x70000000) {
1365 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000);
1366 hwrev &= (RL_TXCFG_HWREV | 0x80000000);
1369 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000);
1370 hwrev &= RL_TXCFG_HWREV;
1373 device_printf(dev, "MAC rev. 0x%08x\n", hwrev & 0x00700000);
1374 while (hw_rev->rl_desc != NULL) {
1375 if (hw_rev->rl_rev == hwrev) {
1376 sc->rl_type = hw_rev->rl_type;
1377 sc->rl_hwrev = hw_rev;
1382 if (hw_rev->rl_desc == NULL) {
1383 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev);
1388 switch (hw_rev->rl_rev) {
1389 case RL_HWREV_8139CPLUS:
1390 sc->rl_flags |= RL_FLAG_FASTETHER | RL_FLAG_AUTOPAD;
1392 case RL_HWREV_8100E:
1393 case RL_HWREV_8101E:
1394 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_FASTETHER;
1396 case RL_HWREV_8102E:
1397 case RL_HWREV_8102EL:
1398 case RL_HWREV_8102EL_SPIN1:
1399 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 |
1400 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP |
1403 case RL_HWREV_8103E:
1404 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 |
1405 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP |
1406 RL_FLAG_AUTOPAD | RL_FLAG_MACSLEEP;
1408 case RL_HWREV_8401E:
1409 case RL_HWREV_8105E:
1410 case RL_HWREV_8105E_SPIN1:
1411 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
1412 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
1413 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD;
1416 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
1417 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
1418 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD |
1419 RL_FLAG_CMDSTOP_WAIT_TXQ;
1421 case RL_HWREV_8168B_SPIN1:
1422 case RL_HWREV_8168B_SPIN2:
1423 sc->rl_flags |= RL_FLAG_WOLRXENB;
1425 case RL_HWREV_8168B_SPIN3:
1426 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT;
1428 case RL_HWREV_8168C_SPIN2:
1429 sc->rl_flags |= RL_FLAG_MACSLEEP;
1431 case RL_HWREV_8168C:
1432 if ((hwrev & 0x00700000) == 0x00200000)
1433 sc->rl_flags |= RL_FLAG_MACSLEEP;
1435 case RL_HWREV_8168CP:
1436 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
1437 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP |
1438 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK;
1440 case RL_HWREV_8168D:
1441 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
1442 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
1443 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 |
1444 RL_FLAG_WOL_MANLINK;
1446 case RL_HWREV_8168DP:
1447 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
1448 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_AUTOPAD |
1449 RL_FLAG_JUMBOV2 | RL_FLAG_WAIT_TXPOLL | RL_FLAG_WOL_MANLINK;
1451 case RL_HWREV_8168E:
1452 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
1453 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
1454 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 |
1455 RL_FLAG_WOL_MANLINK;
1457 case RL_HWREV_8168E_VL:
1458 case RL_HWREV_8168F:
1460 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
1461 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP |
1462 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 |
1463 RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK;
1465 case RL_HWREV_8169_8110SB:
1466 case RL_HWREV_8169_8110SBL:
1467 case RL_HWREV_8169_8110SC:
1468 case RL_HWREV_8169_8110SCE:
1469 sc->rl_flags |= RL_FLAG_PHYWAKE;
1472 case RL_HWREV_8169S:
1473 case RL_HWREV_8110S:
1474 sc->rl_flags |= RL_FLAG_MACRESET;
1480 if (sc->rl_hwrev->rl_rev == RL_HWREV_8139CPLUS) {
1481 sc->rl_cfg0 = RL_8139_CFG0;
1482 sc->rl_cfg1 = RL_8139_CFG1;
1484 sc->rl_cfg3 = RL_8139_CFG3;
1485 sc->rl_cfg4 = RL_8139_CFG4;
1486 sc->rl_cfg5 = RL_8139_CFG5;
1488 sc->rl_cfg0 = RL_CFG0;
1489 sc->rl_cfg1 = RL_CFG1;
1490 sc->rl_cfg2 = RL_CFG2;
1491 sc->rl_cfg3 = RL_CFG3;
1492 sc->rl_cfg4 = RL_CFG4;
1493 sc->rl_cfg5 = RL_CFG5;
1496 /* Reset the adapter. */
1502 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
1503 cfg = CSR_READ_1(sc, sc->rl_cfg1);
1505 CSR_WRITE_1(sc, sc->rl_cfg1, cfg);
1506 cfg = CSR_READ_1(sc, sc->rl_cfg5);
1507 cfg &= RL_CFG5_PME_STS;
1508 CSR_WRITE_1(sc, sc->rl_cfg5, cfg);
1509 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1511 if ((sc->rl_flags & RL_FLAG_PAR) != 0) {
1513 * XXX Should have a better way to extract station
1514 * address from EEPROM.
1516 for (i = 0; i < ETHER_ADDR_LEN; i++)
1517 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i);
1519 sc->rl_eewidth = RL_9356_ADDR_LEN;
1520 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1);
1521 if (re_did != 0x8129)
1522 sc->rl_eewidth = RL_9346_ADDR_LEN;
1525 * Get station address from the EEPROM.
1527 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3);
1528 for (i = 0; i < ETHER_ADDR_LEN / 2; i++)
1529 as[i] = le16toh(as[i]);
1530 bcopy(as, eaddr, ETHER_ADDR_LEN);
1533 if (sc->rl_type == RL_8169) {
1534 /* Set RX length mask and number of descriptors. */
1535 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN;
1536 sc->rl_txstart = RL_GTXSTART;
1537 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT;
1538 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT;
1540 /* Set RX length mask and number of descriptors. */
1541 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN;
1542 sc->rl_txstart = RL_TXSTART;
1543 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT;
1544 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT;
1547 error = re_allocmem(dev, sc);
1552 ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
1554 device_printf(dev, "can not if_alloc()\n");
1559 /* Take controller out of deep sleep mode. */
1560 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) {
1561 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)
1562 CSR_WRITE_1(sc, RL_GPIO,
1563 CSR_READ_1(sc, RL_GPIO) | 0x01);
1565 CSR_WRITE_1(sc, RL_GPIO,
1566 CSR_READ_1(sc, RL_GPIO) & ~0x01);
1569 /* Take PHY out of power down mode. */
1570 if ((sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) {
1571 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80);
1572 if (hw_rev->rl_rev == RL_HWREV_8401E)
1573 CSR_WRITE_1(sc, 0xD1, CSR_READ_1(sc, 0xD1) & ~0x08);
1575 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) {
1576 re_gmii_writereg(dev, 1, 0x1f, 0);
1577 re_gmii_writereg(dev, 1, 0x0e, 0);
1581 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1582 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1583 ifp->if_ioctl = re_ioctl;
1584 ifp->if_start = re_start;
1586 * RTL8168/8111C generates wrong IP checksummed frame if the
1587 * packet has IP options so disable TX IP checksum offloading.
1589 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168C ||
1590 sc->rl_hwrev->rl_rev == RL_HWREV_8168C_SPIN2 ||
1591 sc->rl_hwrev->rl_rev == RL_HWREV_8168CP)
1592 ifp->if_hwassist = CSUM_TCP | CSUM_UDP;
1594 ifp->if_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP;
1595 ifp->if_hwassist |= CSUM_TSO;
1596 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4;
1597 ifp->if_capenable = ifp->if_capabilities;
1598 ifp->if_init = re_init;
1599 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN);
1600 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN;
1601 IFQ_SET_READY(&ifp->if_snd);
1603 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc);
1605 #define RE_PHYAD_INTERNAL 0
1608 phy = RE_PHYAD_INTERNAL;
1609 if (sc->rl_type == RL_8169)
1611 error = mii_attach(dev, &sc->rl_miibus, ifp, re_ifmedia_upd,
1612 re_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, MIIF_DOPAUSE);
1614 device_printf(dev, "attaching PHYs failed\n");
1619 * Call MI attach routine.
1621 ether_ifattach(ifp, eaddr);
1623 /* VLAN capability setup */
1624 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
1625 if (ifp->if_capabilities & IFCAP_HWCSUM)
1626 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
1627 /* Enable WOL if PM is supported. */
1628 if (pci_find_cap(sc->rl_dev, PCIY_PMG, ®) == 0)
1629 ifp->if_capabilities |= IFCAP_WOL;
1630 ifp->if_capenable = ifp->if_capabilities;
1631 ifp->if_capenable &= ~(IFCAP_WOL_UCAST | IFCAP_WOL_MCAST);
1633 * Don't enable TSO by default. It is known to generate
1634 * corrupted TCP segments(bad TCP options) under certain
1637 ifp->if_hwassist &= ~CSUM_TSO;
1638 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO);
1639 #ifdef DEVICE_POLLING
1640 ifp->if_capabilities |= IFCAP_POLLING;
1643 * Tell the upper layer(s) we support long frames.
1644 * Must appear after the call to ether_ifattach() because
1645 * ether_ifattach() sets ifi_hdrlen to the default value.
1647 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1650 re_netmap_attach(sc);
1651 #endif /* DEV_NETMAP */
1654 * Perform hardware diagnostic on the original RTL8169.
1655 * Some 32-bit cards were incorrectly wired and would
1656 * malfunction if plugged into a 64-bit slot.
1659 if (hwrev == RL_HWREV_8169) {
1660 error = re_diag(sc);
1663 "attach aborted due to hardware diag failure\n");
1664 ether_ifdetach(ifp);
1670 #ifdef RE_TX_MODERATION
1673 /* Hook interrupt last to avoid having to lock softc */
1674 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 &&
1676 error = bus_setup_intr(dev, sc->rl_irq[0],
1677 INTR_TYPE_NET | INTR_MPSAFE, NULL, re_intr_msi, sc,
1678 &sc->rl_intrhand[0]);
1680 error = bus_setup_intr(dev, sc->rl_irq[0],
1681 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc,
1682 &sc->rl_intrhand[0]);
1685 device_printf(dev, "couldn't set up irq\n");
1686 ether_ifdetach(ifp);
1698 * Shutdown hardware and free up resources. This can be called any
1699 * time after the mutex has been initialized. It is called in both
1700 * the error case in attach and the normal detach case so it needs
1701 * to be careful about only freeing resources that have actually been
1705 re_detach(device_t dev)
1707 struct rl_softc *sc;
1711 sc = device_get_softc(dev);
1713 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized"));
1715 /* These should only be active if attach succeeded */
1716 if (device_is_attached(dev)) {
1717 #ifdef DEVICE_POLLING
1718 if (ifp->if_capenable & IFCAP_POLLING)
1719 ether_poll_deregister(ifp);
1727 callout_drain(&sc->rl_stat_callout);
1728 taskqueue_drain(taskqueue_fast, &sc->rl_inttask);
1730 * Force off the IFF_UP flag here, in case someone
1731 * still had a BPF descriptor attached to this
1732 * interface. If they do, ether_ifdetach() will cause
1733 * the BPF code to try and clear the promisc mode
1734 * flag, which will bubble down to re_ioctl(),
1735 * which will try to call re_init() again. This will
1736 * turn the NIC back on and restart the MII ticker,
1737 * which will panic the system when the kernel tries
1738 * to invoke the re_tick() function that isn't there
1741 ifp->if_flags &= ~IFF_UP;
1742 ether_ifdetach(ifp);
1745 device_delete_child(dev, sc->rl_miibus);
1746 bus_generic_detach(dev);
1749 * The rest is resource deallocation, so we should already be
1753 if (sc->rl_intrhand[0] != NULL) {
1754 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]);
1755 sc->rl_intrhand[0] = NULL;
1760 #endif /* DEV_NETMAP */
1763 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0)
1767 if (sc->rl_irq[0] != NULL) {
1768 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->rl_irq[0]);
1769 sc->rl_irq[0] = NULL;
1771 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0)
1772 pci_release_msi(dev);
1773 if (sc->rl_res_pba) {
1775 bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->rl_res_pba);
1778 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id,
1781 /* Unload and free the RX DMA ring memory and map */
1783 if (sc->rl_ldata.rl_rx_list_tag) {
1784 if (sc->rl_ldata.rl_rx_list_map)
1785 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag,
1786 sc->rl_ldata.rl_rx_list_map);
1787 if (sc->rl_ldata.rl_rx_list_map && sc->rl_ldata.rl_rx_list)
1788 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag,
1789 sc->rl_ldata.rl_rx_list,
1790 sc->rl_ldata.rl_rx_list_map);
1791 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag);
1794 /* Unload and free the TX DMA ring memory and map */
1796 if (sc->rl_ldata.rl_tx_list_tag) {
1797 if (sc->rl_ldata.rl_tx_list_map)
1798 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag,
1799 sc->rl_ldata.rl_tx_list_map);
1800 if (sc->rl_ldata.rl_tx_list_map && sc->rl_ldata.rl_tx_list)
1801 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag,
1802 sc->rl_ldata.rl_tx_list,
1803 sc->rl_ldata.rl_tx_list_map);
1804 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag);
1807 /* Destroy all the RX and TX buffer maps */
1809 if (sc->rl_ldata.rl_tx_mtag) {
1810 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
1811 if (sc->rl_ldata.rl_tx_desc[i].tx_dmamap)
1812 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag,
1813 sc->rl_ldata.rl_tx_desc[i].tx_dmamap);
1815 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag);
1817 if (sc->rl_ldata.rl_rx_mtag) {
1818 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
1819 if (sc->rl_ldata.rl_rx_desc[i].rx_dmamap)
1820 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag,
1821 sc->rl_ldata.rl_rx_desc[i].rx_dmamap);
1823 if (sc->rl_ldata.rl_rx_sparemap)
1824 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag,
1825 sc->rl_ldata.rl_rx_sparemap);
1826 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag);
1828 if (sc->rl_ldata.rl_jrx_mtag) {
1829 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
1830 if (sc->rl_ldata.rl_jrx_desc[i].rx_dmamap)
1831 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag,
1832 sc->rl_ldata.rl_jrx_desc[i].rx_dmamap);
1834 if (sc->rl_ldata.rl_jrx_sparemap)
1835 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag,
1836 sc->rl_ldata.rl_jrx_sparemap);
1837 bus_dma_tag_destroy(sc->rl_ldata.rl_jrx_mtag);
1839 /* Unload and free the stats buffer and map */
1841 if (sc->rl_ldata.rl_stag) {
1842 if (sc->rl_ldata.rl_smap)
1843 bus_dmamap_unload(sc->rl_ldata.rl_stag,
1844 sc->rl_ldata.rl_smap);
1845 if (sc->rl_ldata.rl_smap && sc->rl_ldata.rl_stats)
1846 bus_dmamem_free(sc->rl_ldata.rl_stag,
1847 sc->rl_ldata.rl_stats, sc->rl_ldata.rl_smap);
1848 bus_dma_tag_destroy(sc->rl_ldata.rl_stag);
1851 if (sc->rl_parent_tag)
1852 bus_dma_tag_destroy(sc->rl_parent_tag);
1854 mtx_destroy(&sc->rl_mtx);
1859 static __inline void
1860 re_discard_rxbuf(struct rl_softc *sc, int idx)
1862 struct rl_desc *desc;
1863 struct rl_rxdesc *rxd;
1866 if (sc->rl_ifp->if_mtu > RL_MTU &&
1867 (sc->rl_flags & RL_FLAG_JUMBOV2) != 0)
1868 rxd = &sc->rl_ldata.rl_jrx_desc[idx];
1870 rxd = &sc->rl_ldata.rl_rx_desc[idx];
1871 desc = &sc->rl_ldata.rl_rx_list[idx];
1872 desc->rl_vlanctl = 0;
1873 cmdstat = rxd->rx_size;
1874 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1)
1875 cmdstat |= RL_RDESC_CMD_EOR;
1876 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN);
1880 re_newbuf(struct rl_softc *sc, int idx)
1883 struct rl_rxdesc *rxd;
1884 bus_dma_segment_t segs[1];
1886 struct rl_desc *desc;
1890 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1894 m->m_len = m->m_pkthdr.len = MCLBYTES;
1897 * This is part of an evil trick to deal with non-x86 platforms.
1898 * The RealTek chip requires RX buffers to be aligned on 64-bit
1899 * boundaries, but that will hose non-x86 machines. To get around
1900 * this, we leave some empty space at the start of each buffer
1901 * and for non-x86 hosts, we copy the buffer back six bytes
1902 * to achieve word alignment. This is slightly more efficient
1903 * than allocating a new buffer, copying the contents, and
1904 * discarding the old buffer.
1906 m_adj(m, RE_ETHER_ALIGN);
1908 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag,
1909 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT);
1914 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs));
1916 rxd = &sc->rl_ldata.rl_rx_desc[idx];
1917 if (rxd->rx_m != NULL) {
1918 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap,
1919 BUS_DMASYNC_POSTREAD);
1920 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap);
1924 map = rxd->rx_dmamap;
1925 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap;
1926 rxd->rx_size = segs[0].ds_len;
1927 sc->rl_ldata.rl_rx_sparemap = map;
1928 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap,
1929 BUS_DMASYNC_PREREAD);
1931 desc = &sc->rl_ldata.rl_rx_list[idx];
1932 desc->rl_vlanctl = 0;
1933 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr));
1934 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr));
1935 cmdstat = segs[0].ds_len;
1936 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1)
1937 cmdstat |= RL_RDESC_CMD_EOR;
1938 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN);
1944 re_jumbo_newbuf(struct rl_softc *sc, int idx)
1947 struct rl_rxdesc *rxd;
1948 bus_dma_segment_t segs[1];
1950 struct rl_desc *desc;
1954 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
1957 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1959 m_adj(m, RE_ETHER_ALIGN);
1961 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_jrx_mtag,
1962 sc->rl_ldata.rl_jrx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT);
1967 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs));
1969 rxd = &sc->rl_ldata.rl_jrx_desc[idx];
1970 if (rxd->rx_m != NULL) {
1971 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap,
1972 BUS_DMASYNC_POSTREAD);
1973 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap);
1977 map = rxd->rx_dmamap;
1978 rxd->rx_dmamap = sc->rl_ldata.rl_jrx_sparemap;
1979 rxd->rx_size = segs[0].ds_len;
1980 sc->rl_ldata.rl_jrx_sparemap = map;
1981 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap,
1982 BUS_DMASYNC_PREREAD);
1984 desc = &sc->rl_ldata.rl_rx_list[idx];
1985 desc->rl_vlanctl = 0;
1986 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr));
1987 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr));
1988 cmdstat = segs[0].ds_len;
1989 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1)
1990 cmdstat |= RL_RDESC_CMD_EOR;
1991 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN);
1997 static __inline void
1998 re_fixup_rx(struct mbuf *m)
2001 uint16_t *src, *dst;
2003 src = mtod(m, uint16_t *);
2004 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src;
2006 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
2009 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN;
2014 re_tx_list_init(struct rl_softc *sc)
2016 struct rl_desc *desc;
2021 bzero(sc->rl_ldata.rl_tx_list,
2022 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc));
2023 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++)
2024 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL;
2026 re_netmap_tx_init(sc);
2027 #endif /* DEV_NETMAP */
2029 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1];
2030 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR);
2032 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
2033 sc->rl_ldata.rl_tx_list_map,
2034 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2036 sc->rl_ldata.rl_tx_prodidx = 0;
2037 sc->rl_ldata.rl_tx_considx = 0;
2038 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt;
2044 re_rx_list_init(struct rl_softc *sc)
2048 bzero(sc->rl_ldata.rl_rx_list,
2049 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc));
2050 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
2051 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL;
2052 if ((error = re_newbuf(sc, i)) != 0)
2056 re_netmap_rx_init(sc);
2057 #endif /* DEV_NETMAP */
2059 /* Flush the RX descriptors */
2061 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
2062 sc->rl_ldata.rl_rx_list_map,
2063 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
2065 sc->rl_ldata.rl_rx_prodidx = 0;
2066 sc->rl_head = sc->rl_tail = NULL;
2067 sc->rl_int_rx_act = 0;
2073 re_jrx_list_init(struct rl_softc *sc)
2077 bzero(sc->rl_ldata.rl_rx_list,
2078 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc));
2079 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
2080 sc->rl_ldata.rl_jrx_desc[i].rx_m = NULL;
2081 if ((error = re_jumbo_newbuf(sc, i)) != 0)
2085 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
2086 sc->rl_ldata.rl_rx_list_map,
2087 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2089 sc->rl_ldata.rl_rx_prodidx = 0;
2090 sc->rl_head = sc->rl_tail = NULL;
2091 sc->rl_int_rx_act = 0;
2097 * RX handler for C+ and 8169. For the gigE chips, we support
2098 * the reception of jumbo frames that have been fragmented
2099 * across multiple 2K mbuf cluster buffers.
2102 re_rxeof(struct rl_softc *sc, int *rx_npktsp)
2106 int i, rxerr, total_len;
2107 struct rl_desc *cur_rx;
2108 u_int32_t rxstat, rxvlan;
2109 int jumbo, maxpkt = 16, rx_npkts = 0;
2115 if (netmap_rx_irq(ifp, 0 | (NETMAP_LOCKED_ENTER|NETMAP_LOCKED_EXIT),
2118 #endif /* DEV_NETMAP */
2119 if (ifp->if_mtu > RL_MTU && (sc->rl_flags & RL_FLAG_JUMBOV2) != 0)
2124 /* Invalidate the descriptor memory */
2126 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
2127 sc->rl_ldata.rl_rx_list_map,
2128 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2130 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0;
2131 i = RL_RX_DESC_NXT(sc, i)) {
2132 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
2134 cur_rx = &sc->rl_ldata.rl_rx_list[i];
2135 rxstat = le32toh(cur_rx->rl_cmdstat);
2136 if ((rxstat & RL_RDESC_STAT_OWN) != 0)
2138 total_len = rxstat & sc->rl_rxlenmask;
2139 rxvlan = le32toh(cur_rx->rl_vlanctl);
2141 m = sc->rl_ldata.rl_jrx_desc[i].rx_m;
2143 m = sc->rl_ldata.rl_rx_desc[i].rx_m;
2145 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 &&
2146 (rxstat & (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) !=
2147 (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) {
2149 * RTL8168C or later controllers do not
2150 * support multi-fragment packet.
2152 re_discard_rxbuf(sc, i);
2154 } else if ((rxstat & RL_RDESC_STAT_EOF) == 0) {
2155 if (re_newbuf(sc, i) != 0) {
2157 * If this is part of a multi-fragment packet,
2158 * discard all the pieces.
2160 if (sc->rl_head != NULL) {
2161 m_freem(sc->rl_head);
2162 sc->rl_head = sc->rl_tail = NULL;
2164 re_discard_rxbuf(sc, i);
2167 m->m_len = RE_RX_DESC_BUFLEN;
2168 if (sc->rl_head == NULL)
2169 sc->rl_head = sc->rl_tail = m;
2171 m->m_flags &= ~M_PKTHDR;
2172 sc->rl_tail->m_next = m;
2179 * NOTE: for the 8139C+, the frame length field
2180 * is always 12 bits in size, but for the gigE chips,
2181 * it is 13 bits (since the max RX frame length is 16K).
2182 * Unfortunately, all 32 bits in the status word
2183 * were already used, so to make room for the extra
2184 * length bit, RealTek took out the 'frame alignment
2185 * error' bit and shifted the other status bits
2186 * over one slot. The OWN, EOR, FS and LS bits are
2187 * still in the same places. We have already extracted
2188 * the frame length and checked the OWN bit, so rather
2189 * than using an alternate bit mapping, we shift the
2190 * status bits one space to the right so we can evaluate
2191 * them using the 8169 status as though it was in the
2192 * same format as that of the 8139C+.
2194 if (sc->rl_type == RL_8169)
2198 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be
2199 * set, but if CRC is clear, it will still be a valid frame.
2201 if ((rxstat & RL_RDESC_STAT_RXERRSUM) != 0) {
2203 if ((sc->rl_flags & RL_FLAG_JUMBOV2) == 0 &&
2205 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)
2210 * If this is part of a multi-fragment packet,
2211 * discard all the pieces.
2213 if (sc->rl_head != NULL) {
2214 m_freem(sc->rl_head);
2215 sc->rl_head = sc->rl_tail = NULL;
2217 re_discard_rxbuf(sc, i);
2223 * If allocating a replacement mbuf fails,
2224 * reload the current one.
2227 rxerr = re_jumbo_newbuf(sc, i);
2229 rxerr = re_newbuf(sc, i);
2232 if (sc->rl_head != NULL) {
2233 m_freem(sc->rl_head);
2234 sc->rl_head = sc->rl_tail = NULL;
2236 re_discard_rxbuf(sc, i);
2240 if (sc->rl_head != NULL) {
2242 m->m_len = total_len;
2244 m->m_len = total_len % RE_RX_DESC_BUFLEN;
2246 m->m_len = RE_RX_DESC_BUFLEN;
2249 * Special case: if there's 4 bytes or less
2250 * in this buffer, the mbuf can be discarded:
2251 * the last 4 bytes is the CRC, which we don't
2252 * care about anyway.
2254 if (m->m_len <= ETHER_CRC_LEN) {
2255 sc->rl_tail->m_len -=
2256 (ETHER_CRC_LEN - m->m_len);
2259 m->m_len -= ETHER_CRC_LEN;
2260 m->m_flags &= ~M_PKTHDR;
2261 sc->rl_tail->m_next = m;
2264 sc->rl_head = sc->rl_tail = NULL;
2265 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
2267 m->m_pkthdr.len = m->m_len =
2268 (total_len - ETHER_CRC_LEN);
2274 m->m_pkthdr.rcvif = ifp;
2276 /* Do RX checksumming if enabled */
2278 if (ifp->if_capenable & IFCAP_RXCSUM) {
2279 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) {
2280 /* Check IP header checksum */
2281 if (rxstat & RL_RDESC_STAT_PROTOID)
2282 m->m_pkthdr.csum_flags |=
2284 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD))
2285 m->m_pkthdr.csum_flags |=
2288 /* Check TCP/UDP checksum */
2289 if ((RL_TCPPKT(rxstat) &&
2290 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) ||
2291 (RL_UDPPKT(rxstat) &&
2292 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) {
2293 m->m_pkthdr.csum_flags |=
2294 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
2295 m->m_pkthdr.csum_data = 0xffff;
2299 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP
2301 if ((rxstat & RL_RDESC_STAT_PROTOID) &&
2302 (rxvlan & RL_RDESC_IPV4))
2303 m->m_pkthdr.csum_flags |=
2305 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) &&
2306 (rxvlan & RL_RDESC_IPV4))
2307 m->m_pkthdr.csum_flags |=
2309 if (((rxstat & RL_RDESC_STAT_TCP) &&
2310 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) ||
2311 ((rxstat & RL_RDESC_STAT_UDP) &&
2312 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) {
2313 m->m_pkthdr.csum_flags |=
2314 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
2315 m->m_pkthdr.csum_data = 0xffff;
2320 if (rxvlan & RL_RDESC_VLANCTL_TAG) {
2321 m->m_pkthdr.ether_vtag =
2322 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA));
2323 m->m_flags |= M_VLANTAG;
2326 (*ifp->if_input)(ifp, m);
2331 /* Flush the RX DMA ring */
2333 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
2334 sc->rl_ldata.rl_rx_list_map,
2335 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
2337 sc->rl_ldata.rl_rx_prodidx = i;
2339 if (rx_npktsp != NULL)
2340 *rx_npktsp = rx_npkts;
2348 re_txeof(struct rl_softc *sc)
2351 struct rl_txdesc *txd;
2355 cons = sc->rl_ldata.rl_tx_considx;
2356 if (cons == sc->rl_ldata.rl_tx_prodidx)
2361 if (netmap_tx_irq(ifp, 0 | (NETMAP_LOCKED_ENTER|NETMAP_LOCKED_EXIT)))
2363 #endif /* DEV_NETMAP */
2364 /* Invalidate the TX descriptor list */
2365 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
2366 sc->rl_ldata.rl_tx_list_map,
2367 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2369 for (; cons != sc->rl_ldata.rl_tx_prodidx;
2370 cons = RL_TX_DESC_NXT(sc, cons)) {
2371 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat);
2372 if (txstat & RL_TDESC_STAT_OWN)
2375 * We only stash mbufs in the last descriptor
2376 * in a fragment chain, which also happens to
2377 * be the only place where the TX status bits
2380 if (txstat & RL_TDESC_CMD_EOF) {
2381 txd = &sc->rl_ldata.rl_tx_desc[cons];
2382 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag,
2383 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2384 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag,
2386 KASSERT(txd->tx_m != NULL,
2387 ("%s: freeing NULL mbufs!", __func__));
2390 if (txstat & (RL_TDESC_STAT_EXCESSCOL|
2391 RL_TDESC_STAT_COLCNT))
2392 ifp->if_collisions++;
2393 if (txstat & RL_TDESC_STAT_TXERRSUM)
2398 sc->rl_ldata.rl_tx_free++;
2399 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2401 sc->rl_ldata.rl_tx_considx = cons;
2403 /* No changes made to the TX ring, so no flush needed */
2405 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) {
2406 #ifdef RE_TX_MODERATION
2408 * If not all descriptors have been reaped yet, reload
2409 * the timer so that we will eventually get another
2410 * interrupt that will cause us to re-enter this routine.
2411 * This is done in case the transmitter has gone idle.
2413 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2416 sc->rl_watchdog_timer = 0;
2422 struct rl_softc *sc;
2423 struct mii_data *mii;
2429 mii = device_get_softc(sc->rl_miibus);
2431 if ((sc->rl_flags & RL_FLAG_LINK) == 0)
2432 re_miibus_statchg(sc->rl_dev);
2434 * Reclaim transmitted frames here. Technically it is not
2435 * necessary to do here but it ensures periodic reclamation
2436 * regardless of Tx completion interrupt which seems to be
2437 * lost on PCIe based controllers under certain situations.
2441 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
2444 #ifdef DEVICE_POLLING
2446 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2448 struct rl_softc *sc = ifp->if_softc;
2452 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2453 rx_npkts = re_poll_locked(ifp, cmd, count);
2459 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
2461 struct rl_softc *sc = ifp->if_softc;
2466 sc->rxcycles = count;
2467 re_rxeof(sc, &rx_npkts);
2470 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2471 re_start_locked(ifp);
2473 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
2476 status = CSR_READ_2(sc, RL_ISR);
2477 if (status == 0xffff)
2480 CSR_WRITE_2(sc, RL_ISR, status);
2481 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) &&
2482 (sc->rl_flags & RL_FLAG_PCIE))
2483 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2486 * XXX check behaviour on receiver stalls.
2489 if (status & RL_ISR_SYSTEM_ERR) {
2490 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2496 #endif /* DEVICE_POLLING */
2501 struct rl_softc *sc;
2506 status = CSR_READ_2(sc, RL_ISR);
2507 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0)
2508 return (FILTER_STRAY);
2509 CSR_WRITE_2(sc, RL_IMR, 0);
2511 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask);
2513 return (FILTER_HANDLED);
2517 re_int_task(void *arg, int npending)
2519 struct rl_softc *sc;
2529 status = CSR_READ_2(sc, RL_ISR);
2530 CSR_WRITE_2(sc, RL_ISR, status);
2532 if (sc->suspended ||
2533 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2538 #ifdef DEVICE_POLLING
2539 if (ifp->if_capenable & IFCAP_POLLING) {
2545 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW))
2546 rval = re_rxeof(sc, NULL);
2549 * Some chips will ignore a second TX request issued
2550 * while an existing transmission is in progress. If
2551 * the transmitter goes idle but there are still
2552 * packets waiting to be sent, we need to restart the
2553 * channel here to flush them out. This only seems to
2554 * be required with the PCIe devices.
2556 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) &&
2557 (sc->rl_flags & RL_FLAG_PCIE))
2558 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2560 #ifdef RE_TX_MODERATION
2561 RL_ISR_TIMEOUT_EXPIRED|
2565 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL))
2568 if (status & RL_ISR_SYSTEM_ERR) {
2569 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2573 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2574 re_start_locked(ifp);
2578 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) {
2579 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask);
2583 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
2587 re_intr_msi(void *xsc)
2589 struct rl_softc *sc;
2591 uint16_t intrs, status;
2597 #ifdef DEVICE_POLLING
2598 if (ifp->if_capenable & IFCAP_POLLING) {
2603 /* Disable interrupts. */
2604 CSR_WRITE_2(sc, RL_IMR, 0);
2605 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2610 intrs = RL_INTRS_CPLUS;
2611 status = CSR_READ_2(sc, RL_ISR);
2612 CSR_WRITE_2(sc, RL_ISR, status);
2613 if (sc->rl_int_rx_act > 0) {
2614 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW |
2616 status &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW |
2620 if (status & (RL_ISR_TIMEOUT_EXPIRED | RL_ISR_RX_OK | RL_ISR_RX_ERR |
2621 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) {
2623 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2624 if (sc->rl_int_rx_mod != 0 &&
2625 (status & (RL_ISR_RX_OK | RL_ISR_RX_ERR |
2626 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) != 0) {
2627 /* Rearm one-shot timer. */
2628 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2629 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR |
2630 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN);
2631 sc->rl_int_rx_act = 1;
2633 intrs |= RL_ISR_RX_OK | RL_ISR_RX_ERR |
2634 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN;
2635 sc->rl_int_rx_act = 0;
2641 * Some chips will ignore a second TX request issued
2642 * while an existing transmission is in progress. If
2643 * the transmitter goes idle but there are still
2644 * packets waiting to be sent, we need to restart the
2645 * channel here to flush them out. This only seems to
2646 * be required with the PCIe devices.
2648 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) &&
2649 (sc->rl_flags & RL_FLAG_PCIE))
2650 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2651 if (status & (RL_ISR_TX_OK | RL_ISR_TX_ERR | RL_ISR_TX_DESC_UNAVAIL))
2654 if (status & RL_ISR_SYSTEM_ERR) {
2655 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2659 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2660 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2661 re_start_locked(ifp);
2662 CSR_WRITE_2(sc, RL_IMR, intrs);
2668 re_encap(struct rl_softc *sc, struct mbuf **m_head)
2670 struct rl_txdesc *txd, *txd_last;
2671 bus_dma_segment_t segs[RL_NTXSEGS];
2674 struct rl_desc *desc;
2676 int i, error, ei, si;
2678 uint32_t cmdstat, csum_flags, vlanctl;
2681 M_ASSERTPKTHDR((*m_head));
2684 * With some of the RealTek chips, using the checksum offload
2685 * support in conjunction with the autopadding feature results
2686 * in the transmission of corrupt frames. For example, if we
2687 * need to send a really small IP fragment that's less than 60
2688 * bytes in size, and IP header checksumming is enabled, the
2689 * resulting ethernet frame that appears on the wire will
2690 * have garbled payload. To work around this, if TX IP checksum
2691 * offload is enabled, we always manually pad short frames out
2692 * to the minimum ethernet frame size.
2694 if ((sc->rl_flags & RL_FLAG_AUTOPAD) == 0 &&
2695 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN &&
2696 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) {
2697 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len;
2698 if (M_WRITABLE(*m_head) == 0) {
2699 /* Get a writable copy. */
2700 m_new = m_dup(*m_head, M_NOWAIT);
2702 if (m_new == NULL) {
2708 if ((*m_head)->m_next != NULL ||
2709 M_TRAILINGSPACE(*m_head) < padlen) {
2710 m_new = m_defrag(*m_head, M_NOWAIT);
2711 if (m_new == NULL) {
2720 * Manually pad short frames, and zero the pad space
2721 * to avoid leaking data.
2723 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen);
2724 m_new->m_pkthdr.len += padlen;
2725 m_new->m_len = m_new->m_pkthdr.len;
2729 prod = sc->rl_ldata.rl_tx_prodidx;
2730 txd = &sc->rl_ldata.rl_tx_desc[prod];
2731 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap,
2732 *m_head, segs, &nsegs, BUS_DMA_NOWAIT);
2733 if (error == EFBIG) {
2734 m_new = m_collapse(*m_head, M_NOWAIT, RL_NTXSEGS);
2735 if (m_new == NULL) {
2741 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag,
2742 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT);
2748 } else if (error != 0)
2756 /* Check for number of available descriptors. */
2757 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) {
2758 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap);
2762 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap,
2763 BUS_DMASYNC_PREWRITE);
2766 * Set up checksum offload. Note: checksum offload bits must
2767 * appear in all descriptors of a multi-descriptor transmit
2768 * attempt. This is according to testing done with an 8169
2769 * chip. This is a requirement.
2773 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
2774 if ((sc->rl_flags & RL_FLAG_DESCV2) != 0) {
2775 csum_flags |= RL_TDESC_CMD_LGSEND;
2776 vlanctl |= ((uint32_t)(*m_head)->m_pkthdr.tso_segsz <<
2777 RL_TDESC_CMD_MSSVALV2_SHIFT);
2779 csum_flags |= RL_TDESC_CMD_LGSEND |
2780 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz <<
2781 RL_TDESC_CMD_MSSVAL_SHIFT);
2785 * Unconditionally enable IP checksum if TCP or UDP
2786 * checksum is required. Otherwise, TCP/UDP checksum
2787 * does't make effects.
2789 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) {
2790 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) {
2791 csum_flags |= RL_TDESC_CMD_IPCSUM;
2792 if (((*m_head)->m_pkthdr.csum_flags &
2794 csum_flags |= RL_TDESC_CMD_TCPCSUM;
2795 if (((*m_head)->m_pkthdr.csum_flags &
2797 csum_flags |= RL_TDESC_CMD_UDPCSUM;
2799 vlanctl |= RL_TDESC_CMD_IPCSUMV2;
2800 if (((*m_head)->m_pkthdr.csum_flags &
2802 vlanctl |= RL_TDESC_CMD_TCPCSUMV2;
2803 if (((*m_head)->m_pkthdr.csum_flags &
2805 vlanctl |= RL_TDESC_CMD_UDPCSUMV2;
2811 * Set up hardware VLAN tagging. Note: vlan tag info must
2812 * appear in all descriptors of a multi-descriptor
2813 * transmission attempt.
2815 if ((*m_head)->m_flags & M_VLANTAG)
2816 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) |
2817 RL_TDESC_VLANCTL_TAG;
2820 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) {
2821 desc = &sc->rl_ldata.rl_tx_list[prod];
2822 desc->rl_vlanctl = htole32(vlanctl);
2823 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr));
2824 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr));
2825 cmdstat = segs[i].ds_len;
2827 cmdstat |= RL_TDESC_CMD_OWN;
2828 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1)
2829 cmdstat |= RL_TDESC_CMD_EOR;
2830 desc->rl_cmdstat = htole32(cmdstat | csum_flags);
2831 sc->rl_ldata.rl_tx_free--;
2833 /* Update producer index. */
2834 sc->rl_ldata.rl_tx_prodidx = prod;
2836 /* Set EOF on the last descriptor. */
2837 ei = RL_TX_DESC_PRV(sc, prod);
2838 desc = &sc->rl_ldata.rl_tx_list[ei];
2839 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF);
2841 desc = &sc->rl_ldata.rl_tx_list[si];
2842 /* Set SOF and transfer ownership of packet to the chip. */
2843 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF);
2846 * Insure that the map for this transmission
2847 * is placed at the array index of the last descriptor
2848 * in this chain. (Swap last and first dmamaps.)
2850 txd_last = &sc->rl_ldata.rl_tx_desc[ei];
2851 map = txd->tx_dmamap;
2852 txd->tx_dmamap = txd_last->tx_dmamap;
2853 txd_last->tx_dmamap = map;
2854 txd_last->tx_m = *m_head;
2860 re_start(struct ifnet *ifp)
2862 struct rl_softc *sc;
2866 re_start_locked(ifp);
2871 * Main transmit routine for C+ and gigE NICs.
2874 re_start_locked(struct ifnet *ifp)
2876 struct rl_softc *sc;
2877 struct mbuf *m_head;
2883 /* XXX is this necessary ? */
2884 if (ifp->if_capenable & IFCAP_NETMAP) {
2885 struct netmap_kring *kring = &NA(ifp)->tx_rings[0];
2886 if (sc->rl_ldata.rl_tx_prodidx != kring->nr_hwcur) {
2887 /* kick the tx unit */
2888 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2889 #ifdef RE_TX_MODERATION
2890 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2892 sc->rl_watchdog_timer = 5;
2896 #endif /* DEV_NETMAP */
2897 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2898 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0)
2901 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2902 sc->rl_ldata.rl_tx_free > 1;) {
2903 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2907 if (re_encap(sc, &m_head) != 0) {
2910 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2911 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2916 * If there's a BPF listener, bounce a copy of this frame
2919 ETHER_BPF_MTAP(ifp, m_head);
2925 #ifdef RE_TX_MODERATION
2926 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt)
2927 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2932 /* Flush the TX descriptors */
2934 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
2935 sc->rl_ldata.rl_tx_list_map,
2936 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
2938 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2940 #ifdef RE_TX_MODERATION
2942 * Use the countdown timer for interrupt moderation.
2943 * 'TX done' interrupts are disabled. Instead, we reset the
2944 * countdown timer, which will begin counting until it hits
2945 * the value in the TIMERINT register, and then trigger an
2946 * interrupt. Each time we write to the TIMERCNT register,
2947 * the timer count is reset to 0.
2949 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2953 * Set a timeout in case the chip goes out to lunch.
2955 sc->rl_watchdog_timer = 5;
2959 re_set_jumbo(struct rl_softc *sc, int jumbo)
2962 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168E_VL) {
2963 pci_set_max_read_req(sc->rl_dev, 4096);
2967 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
2969 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) |
2971 switch (sc->rl_hwrev->rl_rev) {
2972 case RL_HWREV_8168DP:
2974 case RL_HWREV_8168E:
2975 CSR_WRITE_1(sc, sc->rl_cfg4,
2976 CSR_READ_1(sc, sc->rl_cfg4) | 0x01);
2979 CSR_WRITE_1(sc, sc->rl_cfg4,
2980 CSR_READ_1(sc, sc->rl_cfg4) | RL_CFG4_JUMBO_EN1);
2983 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) &
2984 ~RL_CFG3_JUMBO_EN0);
2985 switch (sc->rl_hwrev->rl_rev) {
2986 case RL_HWREV_8168DP:
2988 case RL_HWREV_8168E:
2989 CSR_WRITE_1(sc, sc->rl_cfg4,
2990 CSR_READ_1(sc, sc->rl_cfg4) & ~0x01);
2993 CSR_WRITE_1(sc, sc->rl_cfg4,
2994 CSR_READ_1(sc, sc->rl_cfg4) & ~RL_CFG4_JUMBO_EN1);
2997 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
2999 switch (sc->rl_hwrev->rl_rev) {
3000 case RL_HWREV_8168DP:
3001 pci_set_max_read_req(sc->rl_dev, 4096);
3005 pci_set_max_read_req(sc->rl_dev, 512);
3007 pci_set_max_read_req(sc->rl_dev, 4096);
3014 struct rl_softc *sc = xsc;
3022 re_init_locked(struct rl_softc *sc)
3024 struct ifnet *ifp = sc->rl_ifp;
3025 struct mii_data *mii;
3029 uint32_t align_dummy;
3030 u_char eaddr[ETHER_ADDR_LEN];
3035 mii = device_get_softc(sc->rl_miibus);
3037 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
3041 * Cancel pending I/O and free all RX/TX buffers.
3045 /* Put controller into known state. */
3049 * For C+ mode, initialize the RX descriptors and mbufs.
3051 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
3052 if (ifp->if_mtu > RL_MTU) {
3053 if (re_jrx_list_init(sc) != 0) {
3054 device_printf(sc->rl_dev,
3055 "no memory for jumbo RX buffers\n");
3059 /* Disable checksum offloading for jumbo frames. */
3060 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_TSO4);
3061 ifp->if_hwassist &= ~(RE_CSUM_FEATURES | CSUM_TSO);
3063 if (re_rx_list_init(sc) != 0) {
3064 device_printf(sc->rl_dev,
3065 "no memory for RX buffers\n");
3070 re_set_jumbo(sc, ifp->if_mtu > RL_MTU);
3072 if (re_rx_list_init(sc) != 0) {
3073 device_printf(sc->rl_dev, "no memory for RX buffers\n");
3077 if ((sc->rl_flags & RL_FLAG_PCIE) != 0 &&
3078 pci_get_device(sc->rl_dev) != RT_DEVICEID_8101E) {
3079 if (ifp->if_mtu > RL_MTU)
3080 pci_set_max_read_req(sc->rl_dev, 512);
3082 pci_set_max_read_req(sc->rl_dev, 4096);
3085 re_tx_list_init(sc);
3088 * Enable C+ RX and TX mode, as well as VLAN stripping and
3089 * RX checksum offload. We must configure the C+ register
3090 * before all others.
3092 cfg = RL_CPLUSCMD_PCI_MRW;
3093 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
3094 cfg |= RL_CPLUSCMD_RXCSUM_ENB;
3095 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
3096 cfg |= RL_CPLUSCMD_VLANSTRIP;
3097 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) {
3098 cfg |= RL_CPLUSCMD_MACSTAT_DIS;
3102 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB;
3103 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg);
3104 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SC ||
3105 sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) {
3107 if ((CSR_READ_1(sc, sc->rl_cfg2) & RL_CFG2_PCI66MHZ) != 0)
3109 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE)
3111 CSR_WRITE_4(sc, 0x7c, reg);
3112 /* Disable interrupt mitigation. */
3113 CSR_WRITE_2(sc, 0xe2, 0);
3116 * Disable TSO if interface MTU size is greater than MSS
3117 * allowed in controller.
3119 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) {
3120 ifp->if_capenable &= ~IFCAP_TSO4;
3121 ifp->if_hwassist &= ~CSUM_TSO;
3125 * Init our MAC address. Even though the chipset
3126 * documentation doesn't mention it, we need to enter "Config
3127 * register write enable" mode to modify the ID registers.
3129 /* Copy MAC address on stack to align. */
3130 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN);
3131 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
3132 CSR_WRITE_4(sc, RL_IDR0,
3133 htole32(*(u_int32_t *)(&eaddr.eaddr[0])));
3134 CSR_WRITE_4(sc, RL_IDR4,
3135 htole32(*(u_int32_t *)(&eaddr.eaddr[4])));
3136 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
3139 * Load the addresses of the RX and TX lists into the chip.
3142 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI,
3143 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr));
3144 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO,
3145 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr));
3147 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI,
3148 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr));
3149 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO,
3150 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr));
3153 * Enable transmit and receive.
3155 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
3158 * Set the initial TX configuration.
3160 if (sc->rl_testmode) {
3161 if (sc->rl_type == RL_8169)
3162 CSR_WRITE_4(sc, RL_TXCFG,
3163 RL_TXCFG_CONFIG|RL_LOOPTEST_ON);
3165 CSR_WRITE_4(sc, RL_TXCFG,
3166 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS);
3168 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
3170 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16);
3173 * Set the initial RX configuration.
3177 /* Configure interrupt moderation. */
3178 if (sc->rl_type == RL_8169) {
3179 /* Magic from vendor. */
3180 CSR_WRITE_2(sc, RL_INTRMOD, 0x5100);
3183 #ifdef DEVICE_POLLING
3185 * Disable interrupts if we are polling.
3187 if (ifp->if_capenable & IFCAP_POLLING)
3188 CSR_WRITE_2(sc, RL_IMR, 0);
3189 else /* otherwise ... */
3193 * Enable interrupts.
3195 if (sc->rl_testmode)
3196 CSR_WRITE_2(sc, RL_IMR, 0);
3198 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
3199 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS);
3201 /* Set initial TX threshold */
3202 sc->rl_txthresh = RL_TX_THRESH_INIT;
3204 /* Start RX/TX process. */
3205 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
3207 /* Enable receiver and transmitter. */
3208 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
3212 * Initialize the timer interrupt register so that
3213 * a timer interrupt will be generated once the timer
3214 * reaches a certain number of ticks. The timer is
3215 * reloaded on each transmit.
3217 #ifdef RE_TX_MODERATION
3219 * Use timer interrupt register to moderate TX interrupt
3220 * moderation, which dramatically improves TX frame rate.
3222 if (sc->rl_type == RL_8169)
3223 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800);
3225 CSR_WRITE_4(sc, RL_TIMERINT, 0x400);
3228 * Use timer interrupt register to moderate RX interrupt
3231 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 &&
3233 if (sc->rl_type == RL_8169)
3234 CSR_WRITE_4(sc, RL_TIMERINT_8169,
3235 RL_USECS(sc->rl_int_rx_mod));
3237 if (sc->rl_type == RL_8169)
3238 CSR_WRITE_4(sc, RL_TIMERINT_8169, RL_USECS(0));
3243 * For 8169 gigE NICs, set the max allowed RX packet
3244 * size so we can receive jumbo frames.
3246 if (sc->rl_type == RL_8169) {
3247 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
3249 * For controllers that use new jumbo frame scheme,
3250 * set maximum size of jumbo frame depedning on
3251 * controller revisions.
3253 if (ifp->if_mtu > RL_MTU)
3254 CSR_WRITE_2(sc, RL_MAXRXPKTLEN,
3255 sc->rl_hwrev->rl_max_mtu +
3256 ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN +
3259 CSR_WRITE_2(sc, RL_MAXRXPKTLEN,
3261 } else if ((sc->rl_flags & RL_FLAG_PCIE) != 0 &&
3262 sc->rl_hwrev->rl_max_mtu == RL_MTU) {
3263 /* RTL810x has no jumbo frame support. */
3264 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, RE_RX_DESC_BUFLEN);
3266 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383);
3269 if (sc->rl_testmode)
3272 CSR_WRITE_1(sc, sc->rl_cfg1, CSR_READ_1(sc, sc->rl_cfg1) |
3275 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3276 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3278 sc->rl_flags &= ~RL_FLAG_LINK;
3281 sc->rl_watchdog_timer = 0;
3282 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
3286 * Set media options.
3289 re_ifmedia_upd(struct ifnet *ifp)
3291 struct rl_softc *sc;
3292 struct mii_data *mii;
3296 mii = device_get_softc(sc->rl_miibus);
3298 error = mii_mediachg(mii);
3305 * Report current media status.
3308 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3310 struct rl_softc *sc;
3311 struct mii_data *mii;
3314 mii = device_get_softc(sc->rl_miibus);
3318 ifmr->ifm_active = mii->mii_media_active;
3319 ifmr->ifm_status = mii->mii_media_status;
3324 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3326 struct rl_softc *sc = ifp->if_softc;
3327 struct ifreq *ifr = (struct ifreq *) data;
3328 struct mii_data *mii;
3334 if (ifr->ifr_mtu < ETHERMIN ||
3335 ifr->ifr_mtu > sc->rl_hwrev->rl_max_mtu) {
3340 if (ifp->if_mtu != ifr->ifr_mtu) {
3341 ifp->if_mtu = ifr->ifr_mtu;
3342 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 &&
3343 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
3344 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3347 if (ifp->if_mtu > RL_TSO_MTU &&
3348 (ifp->if_capenable & IFCAP_TSO4) != 0) {
3349 ifp->if_capenable &= ~(IFCAP_TSO4 |
3351 ifp->if_hwassist &= ~CSUM_TSO;
3353 VLAN_CAPABILITIES(ifp);
3359 if ((ifp->if_flags & IFF_UP) != 0) {
3360 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
3361 if (((ifp->if_flags ^ sc->rl_if_flags)
3362 & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
3367 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
3370 sc->rl_if_flags = ifp->if_flags;
3376 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
3382 mii = device_get_softc(sc->rl_miibus);
3383 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
3389 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3391 #ifdef DEVICE_POLLING
3392 if (mask & IFCAP_POLLING) {
3393 if (ifr->ifr_reqcap & IFCAP_POLLING) {
3394 error = ether_poll_register(re_poll, ifp);
3398 /* Disable interrupts */
3399 CSR_WRITE_2(sc, RL_IMR, 0x0000);
3400 ifp->if_capenable |= IFCAP_POLLING;
3403 error = ether_poll_deregister(ifp);
3404 /* Enable interrupts. */
3406 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
3407 ifp->if_capenable &= ~IFCAP_POLLING;
3411 #endif /* DEVICE_POLLING */
3413 if ((mask & IFCAP_TXCSUM) != 0 &&
3414 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
3415 ifp->if_capenable ^= IFCAP_TXCSUM;
3416 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) {
3417 rev = sc->rl_hwrev->rl_rev;
3418 if (rev == RL_HWREV_8168C ||
3419 rev == RL_HWREV_8168C_SPIN2 ||
3420 rev == RL_HWREV_8168CP)
3421 ifp->if_hwassist |= CSUM_TCP | CSUM_UDP;
3423 ifp->if_hwassist |= RE_CSUM_FEATURES;
3425 ifp->if_hwassist &= ~RE_CSUM_FEATURES;
3428 if ((mask & IFCAP_RXCSUM) != 0 &&
3429 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) {
3430 ifp->if_capenable ^= IFCAP_RXCSUM;
3433 if ((mask & IFCAP_TSO4) != 0 &&
3434 (ifp->if_capabilities & IFCAP_TSO4) != 0) {
3435 ifp->if_capenable ^= IFCAP_TSO4;
3436 if ((IFCAP_TSO4 & ifp->if_capenable) != 0)
3437 ifp->if_hwassist |= CSUM_TSO;
3439 ifp->if_hwassist &= ~CSUM_TSO;
3440 if (ifp->if_mtu > RL_TSO_MTU &&
3441 (ifp->if_capenable & IFCAP_TSO4) != 0) {
3442 ifp->if_capenable &= ~IFCAP_TSO4;
3443 ifp->if_hwassist &= ~CSUM_TSO;
3446 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
3447 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
3448 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
3449 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
3450 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
3451 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
3452 /* TSO over VLAN requires VLAN hardware tagging. */
3453 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
3454 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
3457 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 &&
3458 (mask & (IFCAP_HWCSUM | IFCAP_TSO4 |
3459 IFCAP_VLAN_HWTSO)) != 0)
3461 if ((mask & IFCAP_WOL) != 0 &&
3462 (ifp->if_capabilities & IFCAP_WOL) != 0) {
3463 if ((mask & IFCAP_WOL_UCAST) != 0)
3464 ifp->if_capenable ^= IFCAP_WOL_UCAST;
3465 if ((mask & IFCAP_WOL_MCAST) != 0)
3466 ifp->if_capenable ^= IFCAP_WOL_MCAST;
3467 if ((mask & IFCAP_WOL_MAGIC) != 0)
3468 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
3470 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) {
3471 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3475 VLAN_CAPABILITIES(ifp);
3479 error = ether_ioctl(ifp, command, data);
3487 re_watchdog(struct rl_softc *sc)
3493 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0)
3498 if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) {
3499 if_printf(ifp, "watchdog timeout (missed Tx interrupts) "
3501 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3502 re_start_locked(ifp);
3506 if_printf(ifp, "watchdog timeout\n");
3510 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3512 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3513 re_start_locked(ifp);
3517 * Stop the adapter and free any mbufs allocated to the
3521 re_stop(struct rl_softc *sc)
3525 struct rl_txdesc *txd;
3526 struct rl_rxdesc *rxd;
3532 sc->rl_watchdog_timer = 0;
3533 callout_stop(&sc->rl_stat_callout);
3534 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3537 * Disable accepting frames to put RX MAC into idle state.
3538 * Otherwise it's possible to get frames while stop command
3539 * execution is in progress and controller can DMA the frame
3540 * to already freed RX buffer during that period.
3542 CSR_WRITE_4(sc, RL_RXCFG, CSR_READ_4(sc, RL_RXCFG) &
3543 ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_MULTI |
3544 RL_RXCFG_RX_BROAD));
3546 if ((sc->rl_flags & RL_FLAG_WAIT_TXPOLL) != 0) {
3547 for (i = RL_TIMEOUT; i > 0; i--) {
3548 if ((CSR_READ_1(sc, sc->rl_txstart) &
3549 RL_TXSTART_START) == 0)
3554 device_printf(sc->rl_dev,
3555 "stopping TX poll timed out!\n");
3556 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
3557 } else if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) {
3558 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB |
3560 if ((sc->rl_flags & RL_FLAG_CMDSTOP_WAIT_TXQ) != 0) {
3561 for (i = RL_TIMEOUT; i > 0; i--) {
3562 if ((CSR_READ_4(sc, RL_TXCFG) &
3563 RL_TXCFG_QUEUE_EMPTY) != 0)
3568 device_printf(sc->rl_dev,
3569 "stopping TXQ timed out!\n");
3572 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
3574 CSR_WRITE_2(sc, RL_IMR, 0x0000);
3575 CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
3577 if (sc->rl_head != NULL) {
3578 m_freem(sc->rl_head);
3579 sc->rl_head = sc->rl_tail = NULL;
3582 /* Free the TX list buffers. */
3583 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
3584 txd = &sc->rl_ldata.rl_tx_desc[i];
3585 if (txd->tx_m != NULL) {
3586 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag,
3587 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
3588 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag,
3595 /* Free the RX list buffers. */
3596 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
3597 rxd = &sc->rl_ldata.rl_rx_desc[i];
3598 if (rxd->rx_m != NULL) {
3599 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag,
3600 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3601 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag,
3608 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
3609 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
3610 rxd = &sc->rl_ldata.rl_jrx_desc[i];
3611 if (rxd->rx_m != NULL) {
3612 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag,
3613 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3614 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag,
3624 * Device suspend routine. Stop the interface and save some PCI
3625 * settings in case the BIOS doesn't restore them properly on
3629 re_suspend(device_t dev)
3631 struct rl_softc *sc;
3633 sc = device_get_softc(dev);
3645 * Device resume routine. Restore some PCI settings in case the BIOS
3646 * doesn't, re-enable busmastering, and restart the interface if
3650 re_resume(device_t dev)
3652 struct rl_softc *sc;
3655 sc = device_get_softc(dev);
3660 /* Take controller out of sleep mode. */
3661 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) {
3662 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)
3663 CSR_WRITE_1(sc, RL_GPIO,
3664 CSR_READ_1(sc, RL_GPIO) | 0x01);
3668 * Clear WOL matching such that normal Rx filtering
3669 * wouldn't interfere with WOL patterns.
3673 /* reinitialize interface if necessary */
3674 if (ifp->if_flags & IFF_UP)
3684 * Stop all chip I/O so that the kernel's probe routines don't
3685 * get confused by errant DMAs when rebooting.
3688 re_shutdown(device_t dev)
3690 struct rl_softc *sc;
3692 sc = device_get_softc(dev);
3697 * Mark interface as down since otherwise we will panic if
3698 * interrupt comes in later on, which can happen in some
3701 sc->rl_ifp->if_flags &= ~IFF_UP;
3709 re_set_linkspeed(struct rl_softc *sc)
3711 struct mii_softc *miisc;
3712 struct mii_data *mii;
3717 mii = device_get_softc(sc->rl_miibus);
3720 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
3721 (IFM_ACTIVE | IFM_AVALID)) {
3722 switch IFM_SUBTYPE(mii->mii_media_active) {
3733 miisc = LIST_FIRST(&mii->mii_phys);
3734 phyno = miisc->mii_phy;
3735 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3737 re_miibus_writereg(sc->rl_dev, phyno, MII_100T2CR, 0);
3738 re_miibus_writereg(sc->rl_dev, phyno,
3739 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
3740 re_miibus_writereg(sc->rl_dev, phyno,
3741 MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG);
3745 * Poll link state until re(4) get a 10/100Mbps link.
3747 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
3749 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID))
3750 == (IFM_ACTIVE | IFM_AVALID)) {
3751 switch (IFM_SUBTYPE(mii->mii_media_active)) {
3763 if (i == MII_ANEGTICKS_GIGE)
3764 device_printf(sc->rl_dev,
3765 "establishing a link failed, WOL may not work!");
3768 * No link, force MAC to have 100Mbps, full-duplex link.
3769 * MAC does not require reprogramming on resolved speed/duplex,
3770 * so this is just for completeness.
3772 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
3773 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
3777 re_setwol(struct rl_softc *sc)
3786 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
3790 /* Put controller into sleep mode. */
3791 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) {
3792 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)
3793 CSR_WRITE_1(sc, RL_GPIO,
3794 CSR_READ_1(sc, RL_GPIO) & ~0x01);
3796 if ((ifp->if_capenable & IFCAP_WOL) != 0) {
3798 if ((sc->rl_flags & RL_FLAG_WOL_MANLINK) != 0)
3799 re_set_linkspeed(sc);
3800 if ((sc->rl_flags & RL_FLAG_WOLRXENB) != 0)
3801 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB);
3803 /* Enable config register write. */
3804 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
3807 v = CSR_READ_1(sc, sc->rl_cfg1);
3809 if ((ifp->if_capenable & IFCAP_WOL) != 0)
3811 CSR_WRITE_1(sc, sc->rl_cfg1, v);
3813 v = CSR_READ_1(sc, sc->rl_cfg3);
3814 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
3815 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
3816 v |= RL_CFG3_WOL_MAGIC;
3817 CSR_WRITE_1(sc, sc->rl_cfg3, v);
3819 v = CSR_READ_1(sc, sc->rl_cfg5);
3820 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST |
3821 RL_CFG5_WOL_LANWAKE);
3822 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0)
3823 v |= RL_CFG5_WOL_UCAST;
3824 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
3825 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST;
3826 if ((ifp->if_capenable & IFCAP_WOL) != 0)
3827 v |= RL_CFG5_WOL_LANWAKE;
3828 CSR_WRITE_1(sc, sc->rl_cfg5, v);
3830 /* Config register write done. */
3831 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
3833 if ((ifp->if_capenable & IFCAP_WOL) == 0 &&
3834 (sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0)
3835 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80);
3837 * It seems that hardware resets its link speed to 100Mbps in
3838 * power down mode so switching to 100Mbps in driver is not
3842 /* Request PME if WOL is requested. */
3843 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2);
3844 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
3845 if ((ifp->if_capenable & IFCAP_WOL) != 0)
3846 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3847 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
3851 re_clrwol(struct rl_softc *sc)
3858 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
3861 /* Enable config register write. */
3862 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
3864 v = CSR_READ_1(sc, sc->rl_cfg3);
3865 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
3866 CSR_WRITE_1(sc, sc->rl_cfg3, v);
3868 /* Config register write done. */
3869 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
3871 v = CSR_READ_1(sc, sc->rl_cfg5);
3872 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
3873 v &= ~RL_CFG5_WOL_LANWAKE;
3874 CSR_WRITE_1(sc, sc->rl_cfg5, v);
3878 re_add_sysctls(struct rl_softc *sc)
3880 struct sysctl_ctx_list *ctx;
3881 struct sysctl_oid_list *children;
3884 ctx = device_get_sysctl_ctx(sc->rl_dev);
3885 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev));
3887 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "stats",
3888 CTLTYPE_INT | CTLFLAG_RW, sc, 0, re_sysctl_stats, "I",
3889 "Statistics Information");
3890 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0)
3893 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "int_rx_mod",
3894 CTLTYPE_INT | CTLFLAG_RW, &sc->rl_int_rx_mod, 0,
3895 sysctl_hw_re_int_mod, "I", "re RX interrupt moderation");
3896 /* Pull in device tunables. */
3897 sc->rl_int_rx_mod = RL_TIMER_DEFAULT;
3898 error = resource_int_value(device_get_name(sc->rl_dev),
3899 device_get_unit(sc->rl_dev), "int_rx_mod", &sc->rl_int_rx_mod);
3901 if (sc->rl_int_rx_mod < RL_TIMER_MIN ||
3902 sc->rl_int_rx_mod > RL_TIMER_MAX) {
3903 device_printf(sc->rl_dev, "int_rx_mod value out of "
3904 "range; using default: %d\n",
3906 sc->rl_int_rx_mod = RL_TIMER_DEFAULT;
3913 re_sysctl_stats(SYSCTL_HANDLER_ARGS)
3915 struct rl_softc *sc;
3916 struct rl_stats *stats;
3917 int error, i, result;
3920 error = sysctl_handle_int(oidp, &result, 0, req);
3921 if (error || req->newptr == NULL)
3925 sc = (struct rl_softc *)arg1;
3927 if ((sc->rl_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
3931 bus_dmamap_sync(sc->rl_ldata.rl_stag,
3932 sc->rl_ldata.rl_smap, BUS_DMASYNC_PREREAD);
3933 CSR_WRITE_4(sc, RL_DUMPSTATS_HI,
3934 RL_ADDR_HI(sc->rl_ldata.rl_stats_addr));
3935 CSR_WRITE_4(sc, RL_DUMPSTATS_LO,
3936 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr));
3937 CSR_WRITE_4(sc, RL_DUMPSTATS_LO,
3938 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr |
3939 RL_DUMPSTATS_START));
3940 for (i = RL_TIMEOUT; i > 0; i--) {
3941 if ((CSR_READ_4(sc, RL_DUMPSTATS_LO) &
3942 RL_DUMPSTATS_START) == 0)
3946 bus_dmamap_sync(sc->rl_ldata.rl_stag,
3947 sc->rl_ldata.rl_smap, BUS_DMASYNC_POSTREAD);
3950 device_printf(sc->rl_dev,
3951 "DUMP statistics request timedout\n");
3955 stats = sc->rl_ldata.rl_stats;
3956 printf("%s statistics:\n", device_get_nameunit(sc->rl_dev));
3957 printf("Tx frames : %ju\n",
3958 (uintmax_t)le64toh(stats->rl_tx_pkts));
3959 printf("Rx frames : %ju\n",
3960 (uintmax_t)le64toh(stats->rl_rx_pkts));
3961 printf("Tx errors : %ju\n",
3962 (uintmax_t)le64toh(stats->rl_tx_errs));
3963 printf("Rx errors : %u\n",
3964 le32toh(stats->rl_rx_errs));
3965 printf("Rx missed frames : %u\n",
3966 (uint32_t)le16toh(stats->rl_missed_pkts));
3967 printf("Rx frame alignment errs : %u\n",
3968 (uint32_t)le16toh(stats->rl_rx_framealign_errs));
3969 printf("Tx single collisions : %u\n",
3970 le32toh(stats->rl_tx_onecoll));
3971 printf("Tx multiple collisions : %u\n",
3972 le32toh(stats->rl_tx_multicolls));
3973 printf("Rx unicast frames : %ju\n",
3974 (uintmax_t)le64toh(stats->rl_rx_ucasts));
3975 printf("Rx broadcast frames : %ju\n",
3976 (uintmax_t)le64toh(stats->rl_rx_bcasts));
3977 printf("Rx multicast frames : %u\n",
3978 le32toh(stats->rl_rx_mcasts));
3979 printf("Tx aborts : %u\n",
3980 (uint32_t)le16toh(stats->rl_tx_aborts));
3981 printf("Tx underruns : %u\n",
3982 (uint32_t)le16toh(stats->rl_rx_underruns));
3989 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3995 value = *(int *)arg1;
3996 error = sysctl_handle_int(oidp, &value, 0, req);
3997 if (error || req->newptr == NULL)
3999 if (value < low || value > high)
4001 *(int *)arg1 = value;
4007 sysctl_hw_re_int_mod(SYSCTL_HANDLER_ARGS)
4010 return (sysctl_int_range(oidp, arg1, arg2, req, RL_TIMER_MIN,