2 * Copyright (c) 1997, 1998-2003
3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver
39 * Written by Bill Paul <wpaul@windriver.com>
40 * Senior Networking Software Engineer
45 * This driver is designed to support RealTek's next generation of
46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S,
48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E.
50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
51 * with the older 8139 family, however it also supports a special
52 * C+ mode of operation that provides several new performance enhancing
53 * features. These include:
55 * o Descriptor based DMA mechanism. Each descriptor represents
56 * a single packet fragment. Data buffers may be aligned on
61 * o TCP/IP checksum offload for both RX and TX
63 * o High and normal priority transmit DMA rings
65 * o VLAN tag insertion and extraction
67 * o TCP large send (segmentation offload)
69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
70 * programming API is fairly straightforward. The RX filtering, EEPROM
71 * access and PHY access is the same as it is on the older 8139 series
74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
75 * same programming API and feature set as the 8139C+ with the following
76 * differences and additions:
82 * o GMII and TBI ports/registers for interfacing with copper
85 * o RX and TX DMA rings can have up to 1024 descriptors
86 * (the 8139C+ allows a maximum of 64)
88 * o Slight differences in register layout from the 8139C+
90 * The TX start and timer interrupt registers are at different locations
91 * on the 8169 than they are on the 8139C+. Also, the status word in the
92 * RX descriptor has a slightly different bit layout. The 8169 does not
93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
97 * (the 'S' stands for 'single-chip'). These devices have the same
98 * programming API as the older 8169, but also have some vendor-specific
99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
102 * This driver takes advantage of the RX and TX checksum offload and
103 * VLAN tag insertion/extraction features. It also implements TX
104 * interrupt moderation using the timer interrupt registers, which
105 * significantly reduces TX interrupt load. There is also support
106 * for jumbo frames, however the 8169/8169S/8110S can not transmit
107 * jumbo frames larger than 7440, so the max MTU possible with this
108 * driver is 7422 bytes.
111 #ifdef HAVE_KERNEL_OPTION_HEADERS
112 #include "opt_device_polling.h"
115 #include <sys/param.h>
116 #include <sys/endian.h>
117 #include <sys/systm.h>
118 #include <sys/sockio.h>
119 #include <sys/mbuf.h>
120 #include <sys/malloc.h>
121 #include <sys/module.h>
122 #include <sys/kernel.h>
123 #include <sys/socket.h>
124 #include <sys/lock.h>
125 #include <sys/mutex.h>
126 #include <sys/sysctl.h>
127 #include <sys/taskqueue.h>
130 #include <net/if_arp.h>
131 #include <net/ethernet.h>
132 #include <net/if_dl.h>
133 #include <net/if_media.h>
134 #include <net/if_types.h>
135 #include <net/if_vlan_var.h>
139 #include <machine/bus.h>
140 #include <machine/resource.h>
142 #include <sys/rman.h>
144 #include <dev/mii/mii.h>
145 #include <dev/mii/miivar.h>
147 #include <dev/pci/pcireg.h>
148 #include <dev/pci/pcivar.h>
150 #include <pci/if_rlreg.h>
152 MODULE_DEPEND(re, pci, 1, 1, 1);
153 MODULE_DEPEND(re, ether, 1, 1, 1);
154 MODULE_DEPEND(re, miibus, 1, 1, 1);
156 /* "device miibus" required. See GENERIC if you get errors here. */
157 #include "miibus_if.h"
160 static int intr_filter = 0;
161 TUNABLE_INT("hw.re.intr_filter", &intr_filter);
162 static int msi_disable = 0;
163 TUNABLE_INT("hw.re.msi_disable", &msi_disable);
164 static int msix_disable = 0;
165 TUNABLE_INT("hw.re.msix_disable", &msix_disable);
166 static int prefer_iomap = 0;
167 TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap);
169 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
172 * Various supported device vendors/types and their names.
174 static const struct rl_type const re_devs[] = {
175 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0,
176 "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
177 { DLINK_VENDORID, DLINK_DEVICEID_530T_REVC, 0,
178 "D-Link DGE-530(T) Gigabit Ethernet Adapter" },
179 { RT_VENDORID, RT_DEVICEID_8139, 0,
180 "RealTek 8139C+ 10/100BaseTX" },
181 { RT_VENDORID, RT_DEVICEID_8101E, 0,
182 "RealTek 810xE PCIe 10/100baseTX" },
183 { RT_VENDORID, RT_DEVICEID_8168, 0,
184 "RealTek 8168/8111 B/C/CP/D/DP/E/F PCIe Gigabit Ethernet" },
185 { RT_VENDORID, RT_DEVICEID_8169, 0,
186 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" },
187 { RT_VENDORID, RT_DEVICEID_8169SC, 0,
188 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
189 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0,
190 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" },
191 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0,
192 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" },
193 { USR_VENDORID, USR_DEVICEID_997902, 0,
194 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" }
197 static const struct rl_hwrev const re_hwrevs[] = {
198 { RL_HWREV_8139, RL_8139, "", RL_MTU },
199 { RL_HWREV_8139A, RL_8139, "A", RL_MTU },
200 { RL_HWREV_8139AG, RL_8139, "A-G", RL_MTU },
201 { RL_HWREV_8139B, RL_8139, "B", RL_MTU },
202 { RL_HWREV_8130, RL_8139, "8130", RL_MTU },
203 { RL_HWREV_8139C, RL_8139, "C", RL_MTU },
204 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C", RL_MTU },
205 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+", RL_MTU },
206 { RL_HWREV_8168B_SPIN1, RL_8169, "8168", RL_JUMBO_MTU },
207 { RL_HWREV_8169, RL_8169, "8169", RL_JUMBO_MTU },
208 { RL_HWREV_8169S, RL_8169, "8169S", RL_JUMBO_MTU },
209 { RL_HWREV_8110S, RL_8169, "8110S", RL_JUMBO_MTU },
210 { RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB", RL_JUMBO_MTU },
211 { RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU },
212 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL", RL_JUMBO_MTU },
213 { RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU },
214 { RL_HWREV_8100, RL_8139, "8100", RL_MTU },
215 { RL_HWREV_8101, RL_8139, "8101", RL_MTU },
216 { RL_HWREV_8100E, RL_8169, "8100E", RL_MTU },
217 { RL_HWREV_8101E, RL_8169, "8101E", RL_MTU },
218 { RL_HWREV_8102E, RL_8169, "8102E", RL_MTU },
219 { RL_HWREV_8102EL, RL_8169, "8102EL", RL_MTU },
220 { RL_HWREV_8102EL_SPIN1, RL_8169, "8102EL", RL_MTU },
221 { RL_HWREV_8103E, RL_8169, "8103E", RL_MTU },
222 { RL_HWREV_8401E, RL_8169, "8401E", RL_MTU },
223 { RL_HWREV_8402, RL_8169, "8402", RL_MTU },
224 { RL_HWREV_8105E, RL_8169, "8105E", RL_MTU },
225 { RL_HWREV_8105E_SPIN1, RL_8169, "8105E", RL_MTU },
226 { RL_HWREV_8168B_SPIN2, RL_8169, "8168", RL_JUMBO_MTU },
227 { RL_HWREV_8168B_SPIN3, RL_8169, "8168", RL_JUMBO_MTU },
228 { RL_HWREV_8168C, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K },
229 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K },
230 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP", RL_JUMBO_MTU_6K },
231 { RL_HWREV_8168D, RL_8169, "8168D/8111D", RL_JUMBO_MTU_9K },
232 { RL_HWREV_8168DP, RL_8169, "8168DP/8111DP", RL_JUMBO_MTU_9K },
233 { RL_HWREV_8168E, RL_8169, "8168E/8111E", RL_JUMBO_MTU_9K},
234 { RL_HWREV_8168E_VL, RL_8169, "8168E/8111E-VL", RL_JUMBO_MTU_6K},
235 { RL_HWREV_8168F, RL_8169, "8168F/8111F", RL_JUMBO_MTU_9K},
236 { RL_HWREV_8411, RL_8169, "8411", RL_JUMBO_MTU_9K},
240 static int re_probe (device_t);
241 static int re_attach (device_t);
242 static int re_detach (device_t);
244 static int re_encap (struct rl_softc *, struct mbuf **);
246 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int);
247 static int re_allocmem (device_t, struct rl_softc *);
248 static __inline void re_discard_rxbuf
249 (struct rl_softc *, int);
250 static int re_newbuf (struct rl_softc *, int);
251 static int re_jumbo_newbuf (struct rl_softc *, int);
252 static int re_rx_list_init (struct rl_softc *);
253 static int re_jrx_list_init (struct rl_softc *);
254 static int re_tx_list_init (struct rl_softc *);
256 static __inline void re_fixup_rx
259 static int re_rxeof (struct rl_softc *, int *);
260 static void re_txeof (struct rl_softc *);
261 #ifdef DEVICE_POLLING
262 static int re_poll (struct ifnet *, enum poll_cmd, int);
263 static int re_poll_locked (struct ifnet *, enum poll_cmd, int);
265 static int re_intr (void *);
266 static void re_intr_msi (void *);
267 static void re_tick (void *);
268 static void re_int_task (void *, int);
269 static void re_start (struct ifnet *);
270 static void re_start_locked (struct ifnet *);
271 static int re_ioctl (struct ifnet *, u_long, caddr_t);
272 static void re_init (void *);
273 static void re_init_locked (struct rl_softc *);
274 static void re_stop (struct rl_softc *);
275 static void re_watchdog (struct rl_softc *);
276 static int re_suspend (device_t);
277 static int re_resume (device_t);
278 static int re_shutdown (device_t);
279 static int re_ifmedia_upd (struct ifnet *);
280 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *);
282 static void re_eeprom_putbyte (struct rl_softc *, int);
283 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *);
284 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int);
285 static int re_gmii_readreg (device_t, int, int);
286 static int re_gmii_writereg (device_t, int, int, int);
288 static int re_miibus_readreg (device_t, int, int);
289 static int re_miibus_writereg (device_t, int, int, int);
290 static void re_miibus_statchg (device_t);
292 static void re_set_jumbo (struct rl_softc *, int);
293 static void re_set_rxmode (struct rl_softc *);
294 static void re_reset (struct rl_softc *);
295 static void re_setwol (struct rl_softc *);
296 static void re_clrwol (struct rl_softc *);
297 static void re_set_linkspeed (struct rl_softc *);
300 static int re_diag (struct rl_softc *);
303 static void re_add_sysctls (struct rl_softc *);
304 static int re_sysctl_stats (SYSCTL_HANDLER_ARGS);
305 static int sysctl_int_range (SYSCTL_HANDLER_ARGS, int, int);
306 static int sysctl_hw_re_int_mod (SYSCTL_HANDLER_ARGS);
308 static device_method_t re_methods[] = {
309 /* Device interface */
310 DEVMETHOD(device_probe, re_probe),
311 DEVMETHOD(device_attach, re_attach),
312 DEVMETHOD(device_detach, re_detach),
313 DEVMETHOD(device_suspend, re_suspend),
314 DEVMETHOD(device_resume, re_resume),
315 DEVMETHOD(device_shutdown, re_shutdown),
318 DEVMETHOD(miibus_readreg, re_miibus_readreg),
319 DEVMETHOD(miibus_writereg, re_miibus_writereg),
320 DEVMETHOD(miibus_statchg, re_miibus_statchg),
325 static driver_t re_driver = {
328 sizeof(struct rl_softc)
331 static devclass_t re_devclass;
333 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0);
334 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0);
337 CSR_WRITE_1(sc, RL_EECMD, \
338 CSR_READ_1(sc, RL_EECMD) | x)
341 CSR_WRITE_1(sc, RL_EECMD, \
342 CSR_READ_1(sc, RL_EECMD) & ~x)
345 * Send a read command and address to the EEPROM, check for ACK.
348 re_eeprom_putbyte(struct rl_softc *sc, int addr)
352 d = addr | (RL_9346_READ << sc->rl_eewidth);
355 * Feed in each bit and strobe the clock.
358 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) {
360 EE_SET(RL_EE_DATAIN);
362 EE_CLR(RL_EE_DATAIN);
373 * Read a word of data stored in the EEPROM at address 'addr.'
376 re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest)
382 * Send address of word we want to read.
384 re_eeprom_putbyte(sc, addr);
387 * Start reading bits from EEPROM.
389 for (i = 0x8000; i; i >>= 1) {
392 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
402 * Read a sequence of words from the EEPROM.
405 re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt)
408 u_int16_t word = 0, *ptr;
410 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM);
414 for (i = 0; i < cnt; i++) {
415 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL);
416 re_eeprom_getword(sc, off + i, &word);
417 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL);
418 ptr = (u_int16_t *)(dest + (i * 2));
422 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM);
426 re_gmii_readreg(device_t dev, int phy, int reg)
432 sc = device_get_softc(dev);
434 /* Let the rgephy driver read the GMEDIASTAT register */
436 if (reg == RL_GMEDIASTAT) {
437 rval = CSR_READ_1(sc, RL_GMEDIASTAT);
441 CSR_WRITE_4(sc, RL_PHYAR, reg << 16);
443 for (i = 0; i < RL_PHY_TIMEOUT; i++) {
444 rval = CSR_READ_4(sc, RL_PHYAR);
445 if (rval & RL_PHYAR_BUSY)
450 if (i == RL_PHY_TIMEOUT) {
451 device_printf(sc->rl_dev, "PHY read failed\n");
456 * Controller requires a 20us delay to process next MDIO request.
460 return (rval & RL_PHYAR_PHYDATA);
464 re_gmii_writereg(device_t dev, int phy, int reg, int data)
470 sc = device_get_softc(dev);
472 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) |
473 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY);
475 for (i = 0; i < RL_PHY_TIMEOUT; i++) {
476 rval = CSR_READ_4(sc, RL_PHYAR);
477 if (!(rval & RL_PHYAR_BUSY))
482 if (i == RL_PHY_TIMEOUT) {
483 device_printf(sc->rl_dev, "PHY write failed\n");
488 * Controller requires a 20us delay to process next MDIO request.
496 re_miibus_readreg(device_t dev, int phy, int reg)
500 u_int16_t re8139_reg = 0;
502 sc = device_get_softc(dev);
504 if (sc->rl_type == RL_8169) {
505 rval = re_gmii_readreg(dev, phy, reg);
511 re8139_reg = RL_BMCR;
514 re8139_reg = RL_BMSR;
517 re8139_reg = RL_ANAR;
520 re8139_reg = RL_ANER;
523 re8139_reg = RL_LPAR;
529 * Allow the rlphy driver to read the media status
530 * register. If we have a link partner which does not
531 * support NWAY, this is the register which will tell
532 * us the results of parallel detection.
535 rval = CSR_READ_1(sc, RL_MEDIASTAT);
538 device_printf(sc->rl_dev, "bad phy register\n");
541 rval = CSR_READ_2(sc, re8139_reg);
542 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) {
543 /* 8139C+ has different bit layout. */
544 rval &= ~(BMCR_LOOP | BMCR_ISO);
550 re_miibus_writereg(device_t dev, int phy, int reg, int data)
553 u_int16_t re8139_reg = 0;
556 sc = device_get_softc(dev);
558 if (sc->rl_type == RL_8169) {
559 rval = re_gmii_writereg(dev, phy, reg, data);
565 re8139_reg = RL_BMCR;
566 if (sc->rl_type == RL_8139CPLUS) {
567 /* 8139C+ has different bit layout. */
568 data &= ~(BMCR_LOOP | BMCR_ISO);
572 re8139_reg = RL_BMSR;
575 re8139_reg = RL_ANAR;
578 re8139_reg = RL_ANER;
581 re8139_reg = RL_LPAR;
588 device_printf(sc->rl_dev, "bad phy register\n");
591 CSR_WRITE_2(sc, re8139_reg, data);
596 re_miibus_statchg(device_t dev)
600 struct mii_data *mii;
602 sc = device_get_softc(dev);
603 mii = device_get_softc(sc->rl_miibus);
605 if (mii == NULL || ifp == NULL ||
606 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
609 sc->rl_flags &= ~RL_FLAG_LINK;
610 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
611 (IFM_ACTIVE | IFM_AVALID)) {
612 switch (IFM_SUBTYPE(mii->mii_media_active)) {
615 sc->rl_flags |= RL_FLAG_LINK;
618 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0)
620 sc->rl_flags |= RL_FLAG_LINK;
627 * RealTek controllers does not provide any interface to
628 * Tx/Rx MACs for resolved speed, duplex and flow-control
634 * Set the RX configuration and 64-bit multicast hash filter.
637 re_set_rxmode(struct rl_softc *sc)
640 struct ifmultiaddr *ifma;
641 uint32_t hashes[2] = { 0, 0 };
648 rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD;
650 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
651 if (ifp->if_flags & IFF_PROMISC)
652 rxfilt |= RL_RXCFG_RX_ALLPHYS;
654 * Unlike other hardwares, we have to explicitly set
655 * RL_RXCFG_RX_MULTI to receive multicast frames in
658 rxfilt |= RL_RXCFG_RX_MULTI;
659 hashes[0] = hashes[1] = 0xffffffff;
664 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
665 if (ifma->ifma_addr->sa_family != AF_LINK)
667 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
668 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
670 hashes[0] |= (1 << h);
672 hashes[1] |= (1 << (h - 32));
674 if_maddr_runlock(ifp);
676 if (hashes[0] != 0 || hashes[1] != 0) {
678 * For some unfathomable reason, RealTek decided to
679 * reverse the order of the multicast hash registers
680 * in the PCI Express parts. This means we have to
681 * write the hash pattern in reverse order for those
684 if ((sc->rl_flags & RL_FLAG_PCIE) != 0) {
685 h = bswap32(hashes[0]);
686 hashes[0] = bswap32(hashes[1]);
689 rxfilt |= RL_RXCFG_RX_MULTI;
693 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
694 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
695 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
699 re_reset(struct rl_softc *sc)
705 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
707 for (i = 0; i < RL_TIMEOUT; i++) {
709 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
713 device_printf(sc->rl_dev, "reset never completed!\n");
715 if ((sc->rl_flags & RL_FLAG_MACRESET) != 0)
716 CSR_WRITE_1(sc, 0x82, 1);
717 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169S)
718 re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0);
724 * The following routine is designed to test for a defect on some
725 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
726 * lines connected to the bus, however for a 32-bit only card, they
727 * should be pulled high. The result of this defect is that the
728 * NIC will not work right if you plug it into a 64-bit slot: DMA
729 * operations will be done with 64-bit transfers, which will fail
730 * because the 64-bit data lines aren't connected.
732 * There's no way to work around this (short of talking a soldering
733 * iron to the board), however we can detect it. The method we use
734 * here is to put the NIC into digital loopback mode, set the receiver
735 * to promiscuous mode, and then try to send a frame. We then compare
736 * the frame data we sent to what was received. If the data matches,
737 * then the NIC is working correctly, otherwise we know the user has
738 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
739 * slot. In the latter case, there's no way the NIC can work correctly,
740 * so we print out a message on the console and abort the device attach.
744 re_diag(struct rl_softc *sc)
746 struct ifnet *ifp = sc->rl_ifp;
748 struct ether_header *eh;
749 struct rl_desc *cur_rx;
752 int total_len, i, error = 0, phyaddr;
753 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
754 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
756 /* Allocate a single mbuf */
757 MGETHDR(m0, M_DONTWAIT, MT_DATA);
764 * Initialize the NIC in test mode. This sets the chip up
765 * so that it can send and receive frames, but performs the
766 * following special functions:
767 * - Puts receiver in promiscuous mode
768 * - Enables digital loopback mode
769 * - Leaves interrupts turned off
772 ifp->if_flags |= IFF_PROMISC;
774 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
776 sc->rl_flags |= RL_FLAG_LINK;
777 if (sc->rl_type == RL_8169)
782 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET);
783 for (i = 0; i < RL_TIMEOUT; i++) {
784 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR);
785 if (!(status & BMCR_RESET))
789 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP);
790 CSR_WRITE_2(sc, RL_ISR, RL_INTRS);
794 /* Put some data in the mbuf */
796 eh = mtod(m0, struct ether_header *);
797 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN);
798 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN);
799 eh->ether_type = htons(ETHERTYPE_IP);
800 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
803 * Queue the packet, start transmission.
804 * Note: IF_HANDOFF() ultimately calls re_start() for us.
807 CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
809 /* XXX: re_diag must not be called when in ALTQ mode */
810 IF_HANDOFF(&ifp->if_snd, m0, ifp);
814 /* Wait for it to propagate through the chip */
817 for (i = 0; i < RL_TIMEOUT; i++) {
818 status = CSR_READ_2(sc, RL_ISR);
819 CSR_WRITE_2(sc, RL_ISR, status);
820 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) ==
821 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK))
826 if (i == RL_TIMEOUT) {
827 device_printf(sc->rl_dev,
828 "diagnostic failed, failed to receive packet in"
835 * The packet should have been dumped into the first
836 * entry in the RX DMA ring. Grab it from there.
839 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
840 sc->rl_ldata.rl_rx_list_map,
841 BUS_DMASYNC_POSTREAD);
842 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag,
843 sc->rl_ldata.rl_rx_desc[0].rx_dmamap,
844 BUS_DMASYNC_POSTREAD);
845 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag,
846 sc->rl_ldata.rl_rx_desc[0].rx_dmamap);
848 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m;
849 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL;
850 eh = mtod(m0, struct ether_header *);
852 cur_rx = &sc->rl_ldata.rl_rx_list[0];
853 total_len = RL_RXBYTES(cur_rx);
854 rxstat = le32toh(cur_rx->rl_cmdstat);
856 if (total_len != ETHER_MIN_LEN) {
857 device_printf(sc->rl_dev,
858 "diagnostic failed, received short packet\n");
863 /* Test that the received packet data matches what we sent. */
865 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) ||
866 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) ||
867 ntohs(eh->ether_type) != ETHERTYPE_IP) {
868 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n");
869 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n",
870 dst, ":", src, ":", ETHERTYPE_IP);
871 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n",
872 eh->ether_dhost, ":", eh->ether_shost, ":",
873 ntohs(eh->ether_type));
874 device_printf(sc->rl_dev, "You may have a defective 32-bit "
875 "NIC plugged into a 64-bit PCI slot.\n");
876 device_printf(sc->rl_dev, "Please re-install the NIC in a "
877 "32-bit slot for proper operation.\n");
878 device_printf(sc->rl_dev, "Read the re(4) man page for more "
884 /* Turn interface off, release resources */
887 sc->rl_flags &= ~RL_FLAG_LINK;
888 ifp->if_flags &= ~IFF_PROMISC;
901 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
902 * IDs against our list and return a device name if we find a match.
905 re_probe(device_t dev)
907 const struct rl_type *t;
908 uint16_t devid, vendor;
909 uint16_t revid, sdevid;
912 vendor = pci_get_vendor(dev);
913 devid = pci_get_device(dev);
914 revid = pci_get_revid(dev);
915 sdevid = pci_get_subdevice(dev);
917 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) {
918 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) {
920 * Only attach to rev. 3 of the Linksys EG1032 adapter.
921 * Rev. 2 is supported by sk(4).
927 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) {
929 /* 8139, let rl(4) take care of this device. */
935 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) {
936 if (vendor == t->rl_vid && devid == t->rl_did) {
937 device_set_desc(dev, t->rl_name);
938 return (BUS_PROBE_DEFAULT);
946 * Map a single buffer address.
950 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
957 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
959 *addr = segs->ds_addr;
963 re_allocmem(device_t dev, struct rl_softc *sc)
966 bus_size_t rx_list_size, tx_list_size;
970 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc);
971 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc);
974 * Allocate the parent bus DMA tag appropriate for PCI.
975 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD
976 * register should be set. However some RealTek chips are known
977 * to be buggy on DAC handling, therefore disable DAC by limiting
978 * DMA address space to 32bit. PCIe variants of RealTek chips
979 * may not have the limitation.
981 lowaddr = BUS_SPACE_MAXADDR;
982 if ((sc->rl_flags & RL_FLAG_PCIE) == 0)
983 lowaddr = BUS_SPACE_MAXADDR_32BIT;
984 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
985 lowaddr, BUS_SPACE_MAXADDR, NULL, NULL,
986 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
987 NULL, NULL, &sc->rl_parent_tag);
989 device_printf(dev, "could not allocate parent DMA tag\n");
994 * Allocate map for TX mbufs.
996 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0,
997 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
998 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0,
999 NULL, NULL, &sc->rl_ldata.rl_tx_mtag);
1001 device_printf(dev, "could not allocate TX DMA tag\n");
1006 * Allocate map for RX mbufs.
1009 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
1010 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t),
1011 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1012 MJUM9BYTES, 1, MJUM9BYTES, 0, NULL, NULL,
1013 &sc->rl_ldata.rl_jrx_mtag);
1016 "could not allocate jumbo RX DMA tag\n");
1020 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0,
1021 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1022 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag);
1024 device_printf(dev, "could not allocate RX DMA tag\n");
1029 * Allocate map for TX descriptor list.
1031 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
1032 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1033 NULL, tx_list_size, 1, tx_list_size, 0,
1034 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag);
1036 device_printf(dev, "could not allocate TX DMA ring tag\n");
1040 /* Allocate DMA'able memory for the TX ring */
1042 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag,
1043 (void **)&sc->rl_ldata.rl_tx_list,
1044 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
1045 &sc->rl_ldata.rl_tx_list_map);
1047 device_printf(dev, "could not allocate TX DMA ring\n");
1051 /* Load the map for the TX ring. */
1053 sc->rl_ldata.rl_tx_list_addr = 0;
1054 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag,
1055 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list,
1056 tx_list_size, re_dma_map_addr,
1057 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT);
1058 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) {
1059 device_printf(dev, "could not load TX DMA ring\n");
1063 /* Create DMA maps for TX buffers */
1065 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
1066 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0,
1067 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap);
1069 device_printf(dev, "could not create DMA map for TX\n");
1075 * Allocate map for RX descriptor list.
1077 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
1078 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1079 NULL, rx_list_size, 1, rx_list_size, 0,
1080 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag);
1082 device_printf(dev, "could not create RX DMA ring tag\n");
1086 /* Allocate DMA'able memory for the RX ring */
1088 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag,
1089 (void **)&sc->rl_ldata.rl_rx_list,
1090 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
1091 &sc->rl_ldata.rl_rx_list_map);
1093 device_printf(dev, "could not allocate RX DMA ring\n");
1097 /* Load the map for the RX ring. */
1099 sc->rl_ldata.rl_rx_list_addr = 0;
1100 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag,
1101 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list,
1102 rx_list_size, re_dma_map_addr,
1103 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT);
1104 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) {
1105 device_printf(dev, "could not load RX DMA ring\n");
1109 /* Create DMA maps for RX buffers */
1111 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
1112 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0,
1113 &sc->rl_ldata.rl_jrx_sparemap);
1116 "could not create spare DMA map for jumbo RX\n");
1119 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
1120 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0,
1121 &sc->rl_ldata.rl_jrx_desc[i].rx_dmamap);
1124 "could not create DMA map for jumbo RX\n");
1129 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0,
1130 &sc->rl_ldata.rl_rx_sparemap);
1132 device_printf(dev, "could not create spare DMA map for RX\n");
1135 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
1136 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0,
1137 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap);
1139 device_printf(dev, "could not create DMA map for RX\n");
1144 /* Create DMA map for statistics. */
1145 error = bus_dma_tag_create(sc->rl_parent_tag, RL_DUMP_ALIGN, 0,
1146 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1147 sizeof(struct rl_stats), 1, sizeof(struct rl_stats), 0, NULL, NULL,
1148 &sc->rl_ldata.rl_stag);
1150 device_printf(dev, "could not create statistics DMA tag\n");
1153 /* Allocate DMA'able memory for statistics. */
1154 error = bus_dmamem_alloc(sc->rl_ldata.rl_stag,
1155 (void **)&sc->rl_ldata.rl_stats,
1156 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
1157 &sc->rl_ldata.rl_smap);
1160 "could not allocate statistics DMA memory\n");
1163 /* Load the map for statistics. */
1164 sc->rl_ldata.rl_stats_addr = 0;
1165 error = bus_dmamap_load(sc->rl_ldata.rl_stag, sc->rl_ldata.rl_smap,
1166 sc->rl_ldata.rl_stats, sizeof(struct rl_stats), re_dma_map_addr,
1167 &sc->rl_ldata.rl_stats_addr, BUS_DMA_NOWAIT);
1168 if (error != 0 || sc->rl_ldata.rl_stats_addr == 0) {
1169 device_printf(dev, "could not load statistics DMA memory\n");
1177 * Attach the interface. Allocate softc structures, do ifmedia
1178 * setup and ethernet/BPF attach.
1181 re_attach(device_t dev)
1183 u_char eaddr[ETHER_ADDR_LEN];
1184 u_int16_t as[ETHER_ADDR_LEN / 2];
1185 struct rl_softc *sc;
1187 const struct rl_hwrev *hw_rev;
1190 u_int16_t devid, re_did = 0;
1191 int error = 0, i, phy, rid;
1192 int msic, msixc, reg;
1195 sc = device_get_softc(dev);
1198 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1200 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
1203 * Map control/status registers.
1205 pci_enable_busmaster(dev);
1207 devid = pci_get_device(dev);
1209 * Prefer memory space register mapping over IO space.
1210 * Because RTL8169SC does not seem to work when memory mapping
1211 * is used always activate io mapping.
1213 if (devid == RT_DEVICEID_8169SC)
1215 if (prefer_iomap == 0) {
1216 sc->rl_res_id = PCIR_BAR(1);
1217 sc->rl_res_type = SYS_RES_MEMORY;
1218 /* RTL8168/8101E seems to use different BARs. */
1219 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E)
1220 sc->rl_res_id = PCIR_BAR(2);
1222 sc->rl_res_id = PCIR_BAR(0);
1223 sc->rl_res_type = SYS_RES_IOPORT;
1225 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
1226 &sc->rl_res_id, RF_ACTIVE);
1227 if (sc->rl_res == NULL && prefer_iomap == 0) {
1228 sc->rl_res_id = PCIR_BAR(0);
1229 sc->rl_res_type = SYS_RES_IOPORT;
1230 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
1231 &sc->rl_res_id, RF_ACTIVE);
1233 if (sc->rl_res == NULL) {
1234 device_printf(dev, "couldn't map ports/memory\n");
1239 sc->rl_btag = rman_get_bustag(sc->rl_res);
1240 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
1242 msic = pci_msi_count(dev);
1243 msixc = pci_msix_count(dev);
1244 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) {
1245 sc->rl_flags |= RL_FLAG_PCIE;
1246 sc->rl_expcap = reg;
1249 device_printf(dev, "MSI count : %d\n", msic);
1250 device_printf(dev, "MSI-X count : %d\n", msixc);
1252 if (msix_disable > 0)
1254 if (msi_disable > 0)
1256 /* Prefer MSI-X to MSI. */
1260 sc->rl_res_pba = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1262 if (sc->rl_res_pba == NULL) {
1263 device_printf(sc->rl_dev,
1264 "could not allocate MSI-X PBA resource\n");
1266 if (sc->rl_res_pba != NULL &&
1267 pci_alloc_msix(dev, &msixc) == 0) {
1269 device_printf(dev, "Using %d MSI-X message\n",
1271 sc->rl_flags |= RL_FLAG_MSIX;
1273 pci_release_msi(dev);
1275 if ((sc->rl_flags & RL_FLAG_MSIX) == 0) {
1276 if (sc->rl_res_pba != NULL)
1277 bus_release_resource(dev, SYS_RES_MEMORY, rid,
1279 sc->rl_res_pba = NULL;
1283 /* Prefer MSI to INTx. */
1284 if (msixc == 0 && msic > 0) {
1286 if (pci_alloc_msi(dev, &msic) == 0) {
1287 if (msic == RL_MSI_MESSAGES) {
1288 device_printf(dev, "Using %d MSI message\n",
1290 sc->rl_flags |= RL_FLAG_MSI;
1291 /* Explicitly set MSI enable bit. */
1292 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
1293 cfg = CSR_READ_1(sc, RL_CFG2);
1295 CSR_WRITE_1(sc, RL_CFG2, cfg);
1296 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1298 pci_release_msi(dev);
1300 if ((sc->rl_flags & RL_FLAG_MSI) == 0)
1304 /* Allocate interrupt */
1305 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) {
1307 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1308 RF_SHAREABLE | RF_ACTIVE);
1309 if (sc->rl_irq[0] == NULL) {
1310 device_printf(dev, "couldn't allocate IRQ resources\n");
1315 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) {
1316 sc->rl_irq[i] = bus_alloc_resource_any(dev,
1317 SYS_RES_IRQ, &rid, RF_ACTIVE);
1318 if (sc->rl_irq[i] == NULL) {
1320 "couldn't llocate IRQ resources for "
1321 "message %d\n", rid);
1328 if ((sc->rl_flags & RL_FLAG_MSI) == 0) {
1329 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
1330 cfg = CSR_READ_1(sc, RL_CFG2);
1331 if ((cfg & RL_CFG2_MSI) != 0) {
1332 device_printf(dev, "turning off MSI enable bit.\n");
1333 cfg &= ~RL_CFG2_MSI;
1334 CSR_WRITE_1(sc, RL_CFG2, cfg);
1336 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1339 /* Disable ASPM L0S/L1. */
1340 if (sc->rl_expcap != 0) {
1341 cap = pci_read_config(dev, sc->rl_expcap +
1342 PCIR_EXPRESS_LINK_CAP, 2);
1343 if ((cap & PCIM_LINK_CAP_ASPM) != 0) {
1344 ctl = pci_read_config(dev, sc->rl_expcap +
1345 PCIR_EXPRESS_LINK_CTL, 2);
1346 if ((ctl & 0x0003) != 0) {
1348 pci_write_config(dev, sc->rl_expcap +
1349 PCIR_EXPRESS_LINK_CTL, ctl, 2);
1350 device_printf(dev, "ASPM disabled\n");
1353 device_printf(dev, "no ASPM capability\n");
1357 hwrev = CSR_READ_4(sc, RL_TXCFG);
1358 switch (hwrev & 0x70000000) {
1361 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000);
1362 hwrev &= (RL_TXCFG_HWREV | 0x80000000);
1365 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000);
1366 hwrev &= RL_TXCFG_HWREV;
1369 device_printf(dev, "MAC rev. 0x%08x\n", hwrev & 0x00700000);
1370 while (hw_rev->rl_desc != NULL) {
1371 if (hw_rev->rl_rev == hwrev) {
1372 sc->rl_type = hw_rev->rl_type;
1373 sc->rl_hwrev = hw_rev;
1378 if (hw_rev->rl_desc == NULL) {
1379 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev);
1384 switch (hw_rev->rl_rev) {
1385 case RL_HWREV_8139CPLUS:
1386 sc->rl_flags |= RL_FLAG_FASTETHER | RL_FLAG_AUTOPAD;
1388 case RL_HWREV_8100E:
1389 case RL_HWREV_8101E:
1390 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_FASTETHER;
1392 case RL_HWREV_8102E:
1393 case RL_HWREV_8102EL:
1394 case RL_HWREV_8102EL_SPIN1:
1395 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 |
1396 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP |
1399 case RL_HWREV_8103E:
1400 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 |
1401 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP |
1402 RL_FLAG_AUTOPAD | RL_FLAG_MACSLEEP;
1404 case RL_HWREV_8401E:
1405 case RL_HWREV_8105E:
1406 case RL_HWREV_8105E_SPIN1:
1407 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
1408 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
1409 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD;
1412 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
1413 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
1414 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD |
1415 RL_FLAG_CMDSTOP_WAIT_TXQ;
1417 case RL_HWREV_8168B_SPIN1:
1418 case RL_HWREV_8168B_SPIN2:
1419 sc->rl_flags |= RL_FLAG_WOLRXENB;
1421 case RL_HWREV_8168B_SPIN3:
1422 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT;
1424 case RL_HWREV_8168C_SPIN2:
1425 sc->rl_flags |= RL_FLAG_MACSLEEP;
1427 case RL_HWREV_8168C:
1428 if ((hwrev & 0x00700000) == 0x00200000)
1429 sc->rl_flags |= RL_FLAG_MACSLEEP;
1431 case RL_HWREV_8168CP:
1432 case RL_HWREV_8168D:
1433 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
1434 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP |
1435 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK;
1437 case RL_HWREV_8168DP:
1438 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
1439 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_AUTOPAD |
1440 RL_FLAG_JUMBOV2 | RL_FLAG_WAIT_TXPOLL | RL_FLAG_WOL_MANLINK;
1442 case RL_HWREV_8168E:
1443 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
1444 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
1445 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 |
1446 RL_FLAG_WOL_MANLINK;
1448 case RL_HWREV_8168E_VL:
1449 case RL_HWREV_8168F:
1451 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
1452 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP |
1453 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 |
1454 RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK;
1456 case RL_HWREV_8169_8110SB:
1457 case RL_HWREV_8169_8110SBL:
1458 case RL_HWREV_8169_8110SC:
1459 case RL_HWREV_8169_8110SCE:
1460 sc->rl_flags |= RL_FLAG_PHYWAKE;
1463 case RL_HWREV_8169S:
1464 case RL_HWREV_8110S:
1465 sc->rl_flags |= RL_FLAG_MACRESET;
1471 /* Reset the adapter. */
1477 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
1478 cfg = CSR_READ_1(sc, RL_CFG1);
1480 CSR_WRITE_1(sc, RL_CFG1, cfg);
1481 cfg = CSR_READ_1(sc, RL_CFG5);
1482 cfg &= RL_CFG5_PME_STS;
1483 CSR_WRITE_1(sc, RL_CFG5, cfg);
1484 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1486 if ((sc->rl_flags & RL_FLAG_PAR) != 0) {
1488 * XXX Should have a better way to extract station
1489 * address from EEPROM.
1491 for (i = 0; i < ETHER_ADDR_LEN; i++)
1492 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i);
1494 sc->rl_eewidth = RL_9356_ADDR_LEN;
1495 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1);
1496 if (re_did != 0x8129)
1497 sc->rl_eewidth = RL_9346_ADDR_LEN;
1500 * Get station address from the EEPROM.
1502 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3);
1503 for (i = 0; i < ETHER_ADDR_LEN / 2; i++)
1504 as[i] = le16toh(as[i]);
1505 bcopy(as, eaddr, sizeof(eaddr));
1508 if (sc->rl_type == RL_8169) {
1509 /* Set RX length mask and number of descriptors. */
1510 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN;
1511 sc->rl_txstart = RL_GTXSTART;
1512 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT;
1513 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT;
1515 /* Set RX length mask and number of descriptors. */
1516 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN;
1517 sc->rl_txstart = RL_TXSTART;
1518 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT;
1519 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT;
1522 error = re_allocmem(dev, sc);
1527 ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
1529 device_printf(dev, "can not if_alloc()\n");
1534 /* Take controller out of deep sleep mode. */
1535 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) {
1536 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)
1537 CSR_WRITE_1(sc, RL_GPIO,
1538 CSR_READ_1(sc, RL_GPIO) | 0x01);
1540 CSR_WRITE_1(sc, RL_GPIO,
1541 CSR_READ_1(sc, RL_GPIO) & ~0x01);
1544 /* Take PHY out of power down mode. */
1545 if ((sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) {
1546 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80);
1547 if (hw_rev->rl_rev == RL_HWREV_8401E)
1548 CSR_WRITE_1(sc, 0xD1, CSR_READ_1(sc, 0xD1) & ~0x08);
1550 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) {
1551 re_gmii_writereg(dev, 1, 0x1f, 0);
1552 re_gmii_writereg(dev, 1, 0x0e, 0);
1555 #define RE_PHYAD_INTERNAL 0
1558 phy = RE_PHYAD_INTERNAL;
1559 if (sc->rl_type == RL_8169)
1561 error = mii_attach(dev, &sc->rl_miibus, ifp, re_ifmedia_upd,
1562 re_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, MIIF_DOPAUSE);
1564 device_printf(dev, "attaching PHYs failed\n");
1569 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1570 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1571 ifp->if_ioctl = re_ioctl;
1572 ifp->if_start = re_start;
1574 * RTL8168/8111C generates wrong IP checksummed frame if the
1575 * packet has IP options so disable TX IP checksum offloading.
1577 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168C ||
1578 sc->rl_hwrev->rl_rev == RL_HWREV_8168C_SPIN2)
1579 ifp->if_hwassist = CSUM_TCP | CSUM_UDP;
1581 ifp->if_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP;
1582 ifp->if_hwassist |= CSUM_TSO;
1583 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4;
1584 ifp->if_capenable = ifp->if_capabilities;
1585 ifp->if_init = re_init;
1586 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN);
1587 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN;
1588 IFQ_SET_READY(&ifp->if_snd);
1590 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc);
1593 * Call MI attach routine.
1595 ether_ifattach(ifp, eaddr);
1597 /* VLAN capability setup */
1598 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
1599 if (ifp->if_capabilities & IFCAP_HWCSUM)
1600 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
1601 /* Enable WOL if PM is supported. */
1602 if (pci_find_cap(sc->rl_dev, PCIY_PMG, ®) == 0)
1603 ifp->if_capabilities |= IFCAP_WOL;
1604 ifp->if_capenable = ifp->if_capabilities;
1605 ifp->if_capenable &= ~(IFCAP_WOL_UCAST | IFCAP_WOL_MCAST);
1607 * Don't enable TSO by default. It is known to generate
1608 * corrupted TCP segments(bad TCP options) under certain
1611 ifp->if_hwassist &= ~CSUM_TSO;
1612 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO);
1613 #ifdef DEVICE_POLLING
1614 ifp->if_capabilities |= IFCAP_POLLING;
1617 * Tell the upper layer(s) we support long frames.
1618 * Must appear after the call to ether_ifattach() because
1619 * ether_ifattach() sets ifi_hdrlen to the default value.
1621 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1625 * Perform hardware diagnostic on the original RTL8169.
1626 * Some 32-bit cards were incorrectly wired and would
1627 * malfunction if plugged into a 64-bit slot.
1630 if (hwrev == RL_HWREV_8169) {
1631 error = re_diag(sc);
1634 "attach aborted due to hardware diag failure\n");
1635 ether_ifdetach(ifp);
1641 #ifdef RE_TX_MODERATION
1644 /* Hook interrupt last to avoid having to lock softc */
1645 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 &&
1647 error = bus_setup_intr(dev, sc->rl_irq[0],
1648 INTR_TYPE_NET | INTR_MPSAFE, NULL, re_intr_msi, sc,
1649 &sc->rl_intrhand[0]);
1651 error = bus_setup_intr(dev, sc->rl_irq[0],
1652 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc,
1653 &sc->rl_intrhand[0]);
1656 device_printf(dev, "couldn't set up irq\n");
1657 ether_ifdetach(ifp);
1669 * Shutdown hardware and free up resources. This can be called any
1670 * time after the mutex has been initialized. It is called in both
1671 * the error case in attach and the normal detach case so it needs
1672 * to be careful about only freeing resources that have actually been
1676 re_detach(device_t dev)
1678 struct rl_softc *sc;
1682 sc = device_get_softc(dev);
1684 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized"));
1686 /* These should only be active if attach succeeded */
1687 if (device_is_attached(dev)) {
1688 #ifdef DEVICE_POLLING
1689 if (ifp->if_capenable & IFCAP_POLLING)
1690 ether_poll_deregister(ifp);
1698 callout_drain(&sc->rl_stat_callout);
1699 taskqueue_drain(taskqueue_fast, &sc->rl_inttask);
1701 * Force off the IFF_UP flag here, in case someone
1702 * still had a BPF descriptor attached to this
1703 * interface. If they do, ether_ifdetach() will cause
1704 * the BPF code to try and clear the promisc mode
1705 * flag, which will bubble down to re_ioctl(),
1706 * which will try to call re_init() again. This will
1707 * turn the NIC back on and restart the MII ticker,
1708 * which will panic the system when the kernel tries
1709 * to invoke the re_tick() function that isn't there
1712 ifp->if_flags &= ~IFF_UP;
1713 ether_ifdetach(ifp);
1716 device_delete_child(dev, sc->rl_miibus);
1717 bus_generic_detach(dev);
1720 * The rest is resource deallocation, so we should already be
1724 if (sc->rl_intrhand[0] != NULL) {
1725 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]);
1726 sc->rl_intrhand[0] = NULL;
1730 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0)
1734 if (sc->rl_irq[0] != NULL) {
1735 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->rl_irq[0]);
1736 sc->rl_irq[0] = NULL;
1738 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0)
1739 pci_release_msi(dev);
1740 if (sc->rl_res_pba) {
1742 bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->rl_res_pba);
1745 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id,
1748 /* Unload and free the RX DMA ring memory and map */
1750 if (sc->rl_ldata.rl_rx_list_tag) {
1751 if (sc->rl_ldata.rl_rx_list_map)
1752 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag,
1753 sc->rl_ldata.rl_rx_list_map);
1754 if (sc->rl_ldata.rl_rx_list_map && sc->rl_ldata.rl_rx_list)
1755 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag,
1756 sc->rl_ldata.rl_rx_list,
1757 sc->rl_ldata.rl_rx_list_map);
1758 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag);
1761 /* Unload and free the TX DMA ring memory and map */
1763 if (sc->rl_ldata.rl_tx_list_tag) {
1764 if (sc->rl_ldata.rl_tx_list_map)
1765 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag,
1766 sc->rl_ldata.rl_tx_list_map);
1767 if (sc->rl_ldata.rl_tx_list_map && sc->rl_ldata.rl_tx_list)
1768 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag,
1769 sc->rl_ldata.rl_tx_list,
1770 sc->rl_ldata.rl_tx_list_map);
1771 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag);
1774 /* Destroy all the RX and TX buffer maps */
1776 if (sc->rl_ldata.rl_tx_mtag) {
1777 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
1778 if (sc->rl_ldata.rl_tx_desc[i].tx_dmamap)
1779 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag,
1780 sc->rl_ldata.rl_tx_desc[i].tx_dmamap);
1782 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag);
1784 if (sc->rl_ldata.rl_rx_mtag) {
1785 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
1786 if (sc->rl_ldata.rl_rx_desc[i].rx_dmamap)
1787 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag,
1788 sc->rl_ldata.rl_rx_desc[i].rx_dmamap);
1790 if (sc->rl_ldata.rl_rx_sparemap)
1791 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag,
1792 sc->rl_ldata.rl_rx_sparemap);
1793 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag);
1795 if (sc->rl_ldata.rl_jrx_mtag) {
1796 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
1797 if (sc->rl_ldata.rl_jrx_desc[i].rx_dmamap)
1798 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag,
1799 sc->rl_ldata.rl_jrx_desc[i].rx_dmamap);
1801 if (sc->rl_ldata.rl_jrx_sparemap)
1802 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag,
1803 sc->rl_ldata.rl_jrx_sparemap);
1804 bus_dma_tag_destroy(sc->rl_ldata.rl_jrx_mtag);
1806 /* Unload and free the stats buffer and map */
1808 if (sc->rl_ldata.rl_stag) {
1809 if (sc->rl_ldata.rl_smap)
1810 bus_dmamap_unload(sc->rl_ldata.rl_stag,
1811 sc->rl_ldata.rl_smap);
1812 if (sc->rl_ldata.rl_smap && sc->rl_ldata.rl_stats)
1813 bus_dmamem_free(sc->rl_ldata.rl_stag,
1814 sc->rl_ldata.rl_stats, sc->rl_ldata.rl_smap);
1815 bus_dma_tag_destroy(sc->rl_ldata.rl_stag);
1818 if (sc->rl_parent_tag)
1819 bus_dma_tag_destroy(sc->rl_parent_tag);
1821 mtx_destroy(&sc->rl_mtx);
1826 static __inline void
1827 re_discard_rxbuf(struct rl_softc *sc, int idx)
1829 struct rl_desc *desc;
1830 struct rl_rxdesc *rxd;
1833 if (sc->rl_ifp->if_mtu > RL_MTU &&
1834 (sc->rl_flags & RL_FLAG_JUMBOV2) != 0)
1835 rxd = &sc->rl_ldata.rl_jrx_desc[idx];
1837 rxd = &sc->rl_ldata.rl_rx_desc[idx];
1838 desc = &sc->rl_ldata.rl_rx_list[idx];
1839 desc->rl_vlanctl = 0;
1840 cmdstat = rxd->rx_size;
1841 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1)
1842 cmdstat |= RL_RDESC_CMD_EOR;
1843 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN);
1847 re_newbuf(struct rl_softc *sc, int idx)
1850 struct rl_rxdesc *rxd;
1851 bus_dma_segment_t segs[1];
1853 struct rl_desc *desc;
1857 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1861 m->m_len = m->m_pkthdr.len = MCLBYTES;
1864 * This is part of an evil trick to deal with non-x86 platforms.
1865 * The RealTek chip requires RX buffers to be aligned on 64-bit
1866 * boundaries, but that will hose non-x86 machines. To get around
1867 * this, we leave some empty space at the start of each buffer
1868 * and for non-x86 hosts, we copy the buffer back six bytes
1869 * to achieve word alignment. This is slightly more efficient
1870 * than allocating a new buffer, copying the contents, and
1871 * discarding the old buffer.
1873 m_adj(m, RE_ETHER_ALIGN);
1875 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag,
1876 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT);
1881 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs));
1883 rxd = &sc->rl_ldata.rl_rx_desc[idx];
1884 if (rxd->rx_m != NULL) {
1885 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap,
1886 BUS_DMASYNC_POSTREAD);
1887 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap);
1891 map = rxd->rx_dmamap;
1892 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap;
1893 rxd->rx_size = segs[0].ds_len;
1894 sc->rl_ldata.rl_rx_sparemap = map;
1895 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap,
1896 BUS_DMASYNC_PREREAD);
1898 desc = &sc->rl_ldata.rl_rx_list[idx];
1899 desc->rl_vlanctl = 0;
1900 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr));
1901 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr));
1902 cmdstat = segs[0].ds_len;
1903 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1)
1904 cmdstat |= RL_RDESC_CMD_EOR;
1905 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN);
1911 re_jumbo_newbuf(struct rl_softc *sc, int idx)
1914 struct rl_rxdesc *rxd;
1915 bus_dma_segment_t segs[1];
1917 struct rl_desc *desc;
1921 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
1924 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1926 m_adj(m, RE_ETHER_ALIGN);
1928 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_jrx_mtag,
1929 sc->rl_ldata.rl_jrx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT);
1934 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs));
1936 rxd = &sc->rl_ldata.rl_jrx_desc[idx];
1937 if (rxd->rx_m != NULL) {
1938 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap,
1939 BUS_DMASYNC_POSTREAD);
1940 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap);
1944 map = rxd->rx_dmamap;
1945 rxd->rx_dmamap = sc->rl_ldata.rl_jrx_sparemap;
1946 rxd->rx_size = segs[0].ds_len;
1947 sc->rl_ldata.rl_jrx_sparemap = map;
1948 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap,
1949 BUS_DMASYNC_PREREAD);
1951 desc = &sc->rl_ldata.rl_rx_list[idx];
1952 desc->rl_vlanctl = 0;
1953 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr));
1954 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr));
1955 cmdstat = segs[0].ds_len;
1956 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1)
1957 cmdstat |= RL_RDESC_CMD_EOR;
1958 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN);
1964 static __inline void
1965 re_fixup_rx(struct mbuf *m)
1968 uint16_t *src, *dst;
1970 src = mtod(m, uint16_t *);
1971 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src;
1973 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
1976 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN;
1981 re_tx_list_init(struct rl_softc *sc)
1983 struct rl_desc *desc;
1988 bzero(sc->rl_ldata.rl_tx_list,
1989 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc));
1990 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++)
1991 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL;
1993 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1];
1994 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR);
1996 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
1997 sc->rl_ldata.rl_tx_list_map,
1998 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2000 sc->rl_ldata.rl_tx_prodidx = 0;
2001 sc->rl_ldata.rl_tx_considx = 0;
2002 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt;
2008 re_rx_list_init(struct rl_softc *sc)
2012 bzero(sc->rl_ldata.rl_rx_list,
2013 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc));
2014 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
2015 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL;
2016 if ((error = re_newbuf(sc, i)) != 0)
2020 /* Flush the RX descriptors */
2022 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
2023 sc->rl_ldata.rl_rx_list_map,
2024 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
2026 sc->rl_ldata.rl_rx_prodidx = 0;
2027 sc->rl_head = sc->rl_tail = NULL;
2028 sc->rl_int_rx_act = 0;
2034 re_jrx_list_init(struct rl_softc *sc)
2038 bzero(sc->rl_ldata.rl_rx_list,
2039 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc));
2040 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
2041 sc->rl_ldata.rl_jrx_desc[i].rx_m = NULL;
2042 if ((error = re_jumbo_newbuf(sc, i)) != 0)
2046 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
2047 sc->rl_ldata.rl_rx_list_map,
2048 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2050 sc->rl_ldata.rl_rx_prodidx = 0;
2051 sc->rl_head = sc->rl_tail = NULL;
2052 sc->rl_int_rx_act = 0;
2058 * RX handler for C+ and 8169. For the gigE chips, we support
2059 * the reception of jumbo frames that have been fragmented
2060 * across multiple 2K mbuf cluster buffers.
2063 re_rxeof(struct rl_softc *sc, int *rx_npktsp)
2067 int i, rxerr, total_len;
2068 struct rl_desc *cur_rx;
2069 u_int32_t rxstat, rxvlan;
2070 int jumbo, maxpkt = 16, rx_npkts = 0;
2075 if (ifp->if_mtu > RL_MTU && (sc->rl_flags & RL_FLAG_JUMBOV2) != 0)
2080 /* Invalidate the descriptor memory */
2082 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
2083 sc->rl_ldata.rl_rx_list_map,
2084 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2086 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0;
2087 i = RL_RX_DESC_NXT(sc, i)) {
2088 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
2090 cur_rx = &sc->rl_ldata.rl_rx_list[i];
2091 rxstat = le32toh(cur_rx->rl_cmdstat);
2092 if ((rxstat & RL_RDESC_STAT_OWN) != 0)
2094 total_len = rxstat & sc->rl_rxlenmask;
2095 rxvlan = le32toh(cur_rx->rl_vlanctl);
2097 m = sc->rl_ldata.rl_jrx_desc[i].rx_m;
2099 m = sc->rl_ldata.rl_rx_desc[i].rx_m;
2101 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 &&
2102 (rxstat & (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) !=
2103 (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) {
2105 * RTL8168C or later controllers do not
2106 * support multi-fragment packet.
2108 re_discard_rxbuf(sc, i);
2110 } else if ((rxstat & RL_RDESC_STAT_EOF) == 0) {
2111 if (re_newbuf(sc, i) != 0) {
2113 * If this is part of a multi-fragment packet,
2114 * discard all the pieces.
2116 if (sc->rl_head != NULL) {
2117 m_freem(sc->rl_head);
2118 sc->rl_head = sc->rl_tail = NULL;
2120 re_discard_rxbuf(sc, i);
2123 m->m_len = RE_RX_DESC_BUFLEN;
2124 if (sc->rl_head == NULL)
2125 sc->rl_head = sc->rl_tail = m;
2127 m->m_flags &= ~M_PKTHDR;
2128 sc->rl_tail->m_next = m;
2135 * NOTE: for the 8139C+, the frame length field
2136 * is always 12 bits in size, but for the gigE chips,
2137 * it is 13 bits (since the max RX frame length is 16K).
2138 * Unfortunately, all 32 bits in the status word
2139 * were already used, so to make room for the extra
2140 * length bit, RealTek took out the 'frame alignment
2141 * error' bit and shifted the other status bits
2142 * over one slot. The OWN, EOR, FS and LS bits are
2143 * still in the same places. We have already extracted
2144 * the frame length and checked the OWN bit, so rather
2145 * than using an alternate bit mapping, we shift the
2146 * status bits one space to the right so we can evaluate
2147 * them using the 8169 status as though it was in the
2148 * same format as that of the 8139C+.
2150 if (sc->rl_type == RL_8169)
2154 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be
2155 * set, but if CRC is clear, it will still be a valid frame.
2157 if ((rxstat & RL_RDESC_STAT_RXERRSUM) != 0) {
2159 if ((sc->rl_flags & RL_FLAG_JUMBOV2) == 0 &&
2161 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)
2166 * If this is part of a multi-fragment packet,
2167 * discard all the pieces.
2169 if (sc->rl_head != NULL) {
2170 m_freem(sc->rl_head);
2171 sc->rl_head = sc->rl_tail = NULL;
2173 re_discard_rxbuf(sc, i);
2179 * If allocating a replacement mbuf fails,
2180 * reload the current one.
2183 rxerr = re_jumbo_newbuf(sc, i);
2185 rxerr = re_newbuf(sc, i);
2188 if (sc->rl_head != NULL) {
2189 m_freem(sc->rl_head);
2190 sc->rl_head = sc->rl_tail = NULL;
2192 re_discard_rxbuf(sc, i);
2196 if (sc->rl_head != NULL) {
2198 m->m_len = total_len;
2200 m->m_len = total_len % RE_RX_DESC_BUFLEN;
2202 m->m_len = RE_RX_DESC_BUFLEN;
2205 * Special case: if there's 4 bytes or less
2206 * in this buffer, the mbuf can be discarded:
2207 * the last 4 bytes is the CRC, which we don't
2208 * care about anyway.
2210 if (m->m_len <= ETHER_CRC_LEN) {
2211 sc->rl_tail->m_len -=
2212 (ETHER_CRC_LEN - m->m_len);
2215 m->m_len -= ETHER_CRC_LEN;
2216 m->m_flags &= ~M_PKTHDR;
2217 sc->rl_tail->m_next = m;
2220 sc->rl_head = sc->rl_tail = NULL;
2221 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
2223 m->m_pkthdr.len = m->m_len =
2224 (total_len - ETHER_CRC_LEN);
2230 m->m_pkthdr.rcvif = ifp;
2232 /* Do RX checksumming if enabled */
2234 if (ifp->if_capenable & IFCAP_RXCSUM) {
2235 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) {
2236 /* Check IP header checksum */
2237 if (rxstat & RL_RDESC_STAT_PROTOID)
2238 m->m_pkthdr.csum_flags |=
2240 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD))
2241 m->m_pkthdr.csum_flags |=
2244 /* Check TCP/UDP checksum */
2245 if ((RL_TCPPKT(rxstat) &&
2246 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) ||
2247 (RL_UDPPKT(rxstat) &&
2248 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) {
2249 m->m_pkthdr.csum_flags |=
2250 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
2251 m->m_pkthdr.csum_data = 0xffff;
2255 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP
2257 if ((rxstat & RL_RDESC_STAT_PROTOID) &&
2258 (rxvlan & RL_RDESC_IPV4))
2259 m->m_pkthdr.csum_flags |=
2261 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) &&
2262 (rxvlan & RL_RDESC_IPV4))
2263 m->m_pkthdr.csum_flags |=
2265 if (((rxstat & RL_RDESC_STAT_TCP) &&
2266 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) ||
2267 ((rxstat & RL_RDESC_STAT_UDP) &&
2268 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) {
2269 m->m_pkthdr.csum_flags |=
2270 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
2271 m->m_pkthdr.csum_data = 0xffff;
2276 if (rxvlan & RL_RDESC_VLANCTL_TAG) {
2277 m->m_pkthdr.ether_vtag =
2278 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA));
2279 m->m_flags |= M_VLANTAG;
2282 (*ifp->if_input)(ifp, m);
2287 /* Flush the RX DMA ring */
2289 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
2290 sc->rl_ldata.rl_rx_list_map,
2291 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
2293 sc->rl_ldata.rl_rx_prodidx = i;
2295 if (rx_npktsp != NULL)
2296 *rx_npktsp = rx_npkts;
2304 re_txeof(struct rl_softc *sc)
2307 struct rl_txdesc *txd;
2311 cons = sc->rl_ldata.rl_tx_considx;
2312 if (cons == sc->rl_ldata.rl_tx_prodidx)
2316 /* Invalidate the TX descriptor list */
2317 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
2318 sc->rl_ldata.rl_tx_list_map,
2319 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2321 for (; cons != sc->rl_ldata.rl_tx_prodidx;
2322 cons = RL_TX_DESC_NXT(sc, cons)) {
2323 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat);
2324 if (txstat & RL_TDESC_STAT_OWN)
2327 * We only stash mbufs in the last descriptor
2328 * in a fragment chain, which also happens to
2329 * be the only place where the TX status bits
2332 if (txstat & RL_TDESC_CMD_EOF) {
2333 txd = &sc->rl_ldata.rl_tx_desc[cons];
2334 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag,
2335 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2336 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag,
2338 KASSERT(txd->tx_m != NULL,
2339 ("%s: freeing NULL mbufs!", __func__));
2342 if (txstat & (RL_TDESC_STAT_EXCESSCOL|
2343 RL_TDESC_STAT_COLCNT))
2344 ifp->if_collisions++;
2345 if (txstat & RL_TDESC_STAT_TXERRSUM)
2350 sc->rl_ldata.rl_tx_free++;
2351 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2353 sc->rl_ldata.rl_tx_considx = cons;
2355 /* No changes made to the TX ring, so no flush needed */
2357 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) {
2358 #ifdef RE_TX_MODERATION
2360 * If not all descriptors have been reaped yet, reload
2361 * the timer so that we will eventually get another
2362 * interrupt that will cause us to re-enter this routine.
2363 * This is done in case the transmitter has gone idle.
2365 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2368 sc->rl_watchdog_timer = 0;
2374 struct rl_softc *sc;
2375 struct mii_data *mii;
2381 mii = device_get_softc(sc->rl_miibus);
2383 if ((sc->rl_flags & RL_FLAG_LINK) == 0)
2384 re_miibus_statchg(sc->rl_dev);
2386 * Reclaim transmitted frames here. Technically it is not
2387 * necessary to do here but it ensures periodic reclamation
2388 * regardless of Tx completion interrupt which seems to be
2389 * lost on PCIe based controllers under certain situations.
2393 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
2396 #ifdef DEVICE_POLLING
2398 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2400 struct rl_softc *sc = ifp->if_softc;
2404 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2405 rx_npkts = re_poll_locked(ifp, cmd, count);
2411 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
2413 struct rl_softc *sc = ifp->if_softc;
2418 sc->rxcycles = count;
2419 re_rxeof(sc, &rx_npkts);
2422 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2423 re_start_locked(ifp);
2425 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
2428 status = CSR_READ_2(sc, RL_ISR);
2429 if (status == 0xffff)
2432 CSR_WRITE_2(sc, RL_ISR, status);
2433 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) &&
2434 (sc->rl_flags & RL_FLAG_PCIE))
2435 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2438 * XXX check behaviour on receiver stalls.
2441 if (status & RL_ISR_SYSTEM_ERR) {
2442 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2448 #endif /* DEVICE_POLLING */
2453 struct rl_softc *sc;
2458 status = CSR_READ_2(sc, RL_ISR);
2459 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0)
2460 return (FILTER_STRAY);
2461 CSR_WRITE_2(sc, RL_IMR, 0);
2463 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask);
2465 return (FILTER_HANDLED);
2469 re_int_task(void *arg, int npending)
2471 struct rl_softc *sc;
2481 status = CSR_READ_2(sc, RL_ISR);
2482 CSR_WRITE_2(sc, RL_ISR, status);
2484 if (sc->suspended ||
2485 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2490 #ifdef DEVICE_POLLING
2491 if (ifp->if_capenable & IFCAP_POLLING) {
2497 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW))
2498 rval = re_rxeof(sc, NULL);
2501 * Some chips will ignore a second TX request issued
2502 * while an existing transmission is in progress. If
2503 * the transmitter goes idle but there are still
2504 * packets waiting to be sent, we need to restart the
2505 * channel here to flush them out. This only seems to
2506 * be required with the PCIe devices.
2508 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) &&
2509 (sc->rl_flags & RL_FLAG_PCIE))
2510 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2512 #ifdef RE_TX_MODERATION
2513 RL_ISR_TIMEOUT_EXPIRED|
2517 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL))
2520 if (status & RL_ISR_SYSTEM_ERR) {
2521 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2525 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2526 re_start_locked(ifp);
2530 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) {
2531 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask);
2535 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
2539 re_intr_msi(void *xsc)
2541 struct rl_softc *sc;
2543 uint16_t intrs, status;
2549 #ifdef DEVICE_POLLING
2550 if (ifp->if_capenable & IFCAP_POLLING) {
2555 /* Disable interrupts. */
2556 CSR_WRITE_2(sc, RL_IMR, 0);
2557 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2562 intrs = RL_INTRS_CPLUS;
2563 status = CSR_READ_2(sc, RL_ISR);
2564 CSR_WRITE_2(sc, RL_ISR, status);
2565 if (sc->rl_int_rx_act > 0) {
2566 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW |
2568 status &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW |
2572 if (status & (RL_ISR_TIMEOUT_EXPIRED | RL_ISR_RX_OK | RL_ISR_RX_ERR |
2573 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) {
2575 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2576 if (sc->rl_int_rx_mod != 0 &&
2577 (status & (RL_ISR_RX_OK | RL_ISR_RX_ERR |
2578 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) != 0) {
2579 /* Rearm one-shot timer. */
2580 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2581 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR |
2582 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN);
2583 sc->rl_int_rx_act = 1;
2585 intrs |= RL_ISR_RX_OK | RL_ISR_RX_ERR |
2586 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN;
2587 sc->rl_int_rx_act = 0;
2593 * Some chips will ignore a second TX request issued
2594 * while an existing transmission is in progress. If
2595 * the transmitter goes idle but there are still
2596 * packets waiting to be sent, we need to restart the
2597 * channel here to flush them out. This only seems to
2598 * be required with the PCIe devices.
2600 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) &&
2601 (sc->rl_flags & RL_FLAG_PCIE))
2602 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2603 if (status & (RL_ISR_TX_OK | RL_ISR_TX_ERR | RL_ISR_TX_DESC_UNAVAIL))
2606 if (status & RL_ISR_SYSTEM_ERR) {
2607 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2611 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2612 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2613 re_start_locked(ifp);
2614 CSR_WRITE_2(sc, RL_IMR, intrs);
2620 re_encap(struct rl_softc *sc, struct mbuf **m_head)
2622 struct rl_txdesc *txd, *txd_last;
2623 bus_dma_segment_t segs[RL_NTXSEGS];
2626 struct rl_desc *desc;
2628 int i, error, ei, si;
2630 uint32_t cmdstat, csum_flags, vlanctl;
2633 M_ASSERTPKTHDR((*m_head));
2636 * With some of the RealTek chips, using the checksum offload
2637 * support in conjunction with the autopadding feature results
2638 * in the transmission of corrupt frames. For example, if we
2639 * need to send a really small IP fragment that's less than 60
2640 * bytes in size, and IP header checksumming is enabled, the
2641 * resulting ethernet frame that appears on the wire will
2642 * have garbled payload. To work around this, if TX IP checksum
2643 * offload is enabled, we always manually pad short frames out
2644 * to the minimum ethernet frame size.
2646 if ((sc->rl_flags & RL_FLAG_AUTOPAD) == 0 &&
2647 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN &&
2648 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) {
2649 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len;
2650 if (M_WRITABLE(*m_head) == 0) {
2651 /* Get a writable copy. */
2652 m_new = m_dup(*m_head, M_DONTWAIT);
2654 if (m_new == NULL) {
2660 if ((*m_head)->m_next != NULL ||
2661 M_TRAILINGSPACE(*m_head) < padlen) {
2662 m_new = m_defrag(*m_head, M_DONTWAIT);
2663 if (m_new == NULL) {
2672 * Manually pad short frames, and zero the pad space
2673 * to avoid leaking data.
2675 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen);
2676 m_new->m_pkthdr.len += padlen;
2677 m_new->m_len = m_new->m_pkthdr.len;
2681 prod = sc->rl_ldata.rl_tx_prodidx;
2682 txd = &sc->rl_ldata.rl_tx_desc[prod];
2683 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap,
2684 *m_head, segs, &nsegs, BUS_DMA_NOWAIT);
2685 if (error == EFBIG) {
2686 m_new = m_collapse(*m_head, M_DONTWAIT, RL_NTXSEGS);
2687 if (m_new == NULL) {
2693 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag,
2694 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT);
2700 } else if (error != 0)
2708 /* Check for number of available descriptors. */
2709 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) {
2710 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap);
2714 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap,
2715 BUS_DMASYNC_PREWRITE);
2718 * Set up checksum offload. Note: checksum offload bits must
2719 * appear in all descriptors of a multi-descriptor transmit
2720 * attempt. This is according to testing done with an 8169
2721 * chip. This is a requirement.
2725 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
2726 if ((sc->rl_flags & RL_FLAG_DESCV2) != 0) {
2727 csum_flags |= RL_TDESC_CMD_LGSEND;
2728 vlanctl |= ((uint32_t)(*m_head)->m_pkthdr.tso_segsz <<
2729 RL_TDESC_CMD_MSSVALV2_SHIFT);
2731 csum_flags |= RL_TDESC_CMD_LGSEND |
2732 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz <<
2733 RL_TDESC_CMD_MSSVAL_SHIFT);
2737 * Unconditionally enable IP checksum if TCP or UDP
2738 * checksum is required. Otherwise, TCP/UDP checksum
2739 * does't make effects.
2741 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) {
2742 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) {
2743 csum_flags |= RL_TDESC_CMD_IPCSUM;
2744 if (((*m_head)->m_pkthdr.csum_flags &
2746 csum_flags |= RL_TDESC_CMD_TCPCSUM;
2747 if (((*m_head)->m_pkthdr.csum_flags &
2749 csum_flags |= RL_TDESC_CMD_UDPCSUM;
2751 vlanctl |= RL_TDESC_CMD_IPCSUMV2;
2752 if (((*m_head)->m_pkthdr.csum_flags &
2754 vlanctl |= RL_TDESC_CMD_TCPCSUMV2;
2755 if (((*m_head)->m_pkthdr.csum_flags &
2757 vlanctl |= RL_TDESC_CMD_UDPCSUMV2;
2763 * Set up hardware VLAN tagging. Note: vlan tag info must
2764 * appear in all descriptors of a multi-descriptor
2765 * transmission attempt.
2767 if ((*m_head)->m_flags & M_VLANTAG)
2768 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) |
2769 RL_TDESC_VLANCTL_TAG;
2772 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) {
2773 desc = &sc->rl_ldata.rl_tx_list[prod];
2774 desc->rl_vlanctl = htole32(vlanctl);
2775 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr));
2776 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr));
2777 cmdstat = segs[i].ds_len;
2779 cmdstat |= RL_TDESC_CMD_OWN;
2780 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1)
2781 cmdstat |= RL_TDESC_CMD_EOR;
2782 desc->rl_cmdstat = htole32(cmdstat | csum_flags);
2783 sc->rl_ldata.rl_tx_free--;
2785 /* Update producer index. */
2786 sc->rl_ldata.rl_tx_prodidx = prod;
2788 /* Set EOF on the last descriptor. */
2789 ei = RL_TX_DESC_PRV(sc, prod);
2790 desc = &sc->rl_ldata.rl_tx_list[ei];
2791 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF);
2793 desc = &sc->rl_ldata.rl_tx_list[si];
2794 /* Set SOF and transfer ownership of packet to the chip. */
2795 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF);
2798 * Insure that the map for this transmission
2799 * is placed at the array index of the last descriptor
2800 * in this chain. (Swap last and first dmamaps.)
2802 txd_last = &sc->rl_ldata.rl_tx_desc[ei];
2803 map = txd->tx_dmamap;
2804 txd->tx_dmamap = txd_last->tx_dmamap;
2805 txd_last->tx_dmamap = map;
2806 txd_last->tx_m = *m_head;
2812 re_start(struct ifnet *ifp)
2814 struct rl_softc *sc;
2818 re_start_locked(ifp);
2823 * Main transmit routine for C+ and gigE NICs.
2826 re_start_locked(struct ifnet *ifp)
2828 struct rl_softc *sc;
2829 struct mbuf *m_head;
2834 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2835 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0)
2838 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2839 sc->rl_ldata.rl_tx_free > 1;) {
2840 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2844 if (re_encap(sc, &m_head) != 0) {
2847 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2848 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2853 * If there's a BPF listener, bounce a copy of this frame
2856 ETHER_BPF_MTAP(ifp, m_head);
2862 #ifdef RE_TX_MODERATION
2863 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt)
2864 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2869 /* Flush the TX descriptors */
2871 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
2872 sc->rl_ldata.rl_tx_list_map,
2873 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
2875 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2877 #ifdef RE_TX_MODERATION
2879 * Use the countdown timer for interrupt moderation.
2880 * 'TX done' interrupts are disabled. Instead, we reset the
2881 * countdown timer, which will begin counting until it hits
2882 * the value in the TIMERINT register, and then trigger an
2883 * interrupt. Each time we write to the TIMERCNT register,
2884 * the timer count is reset to 0.
2886 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2890 * Set a timeout in case the chip goes out to lunch.
2892 sc->rl_watchdog_timer = 5;
2896 re_set_jumbo(struct rl_softc *sc, int jumbo)
2899 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168E_VL) {
2900 pci_set_max_read_req(sc->rl_dev, 4096);
2904 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
2906 CSR_WRITE_1(sc, RL_CFG3, CSR_READ_1(sc, RL_CFG3) |
2908 switch (sc->rl_hwrev->rl_rev) {
2909 case RL_HWREV_8168DP:
2911 case RL_HWREV_8168E:
2912 CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) |
2916 CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) |
2920 CSR_WRITE_1(sc, RL_CFG3, CSR_READ_1(sc, RL_CFG3) &
2921 ~RL_CFG3_JUMBO_EN0);
2922 switch (sc->rl_hwrev->rl_rev) {
2923 case RL_HWREV_8168DP:
2925 case RL_HWREV_8168E:
2926 CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) &
2930 CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) &
2931 ~RL_CFG4_JUMBO_EN1);
2934 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
2936 switch (sc->rl_hwrev->rl_rev) {
2937 case RL_HWREV_8168DP:
2938 pci_set_max_read_req(sc->rl_dev, 4096);
2942 pci_set_max_read_req(sc->rl_dev, 512);
2944 pci_set_max_read_req(sc->rl_dev, 4096);
2951 struct rl_softc *sc = xsc;
2959 re_init_locked(struct rl_softc *sc)
2961 struct ifnet *ifp = sc->rl_ifp;
2962 struct mii_data *mii;
2966 uint32_t align_dummy;
2967 u_char eaddr[ETHER_ADDR_LEN];
2972 mii = device_get_softc(sc->rl_miibus);
2974 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2978 * Cancel pending I/O and free all RX/TX buffers.
2982 /* Put controller into known state. */
2986 * For C+ mode, initialize the RX descriptors and mbufs.
2988 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
2989 if (ifp->if_mtu > RL_MTU) {
2990 if (re_jrx_list_init(sc) != 0) {
2991 device_printf(sc->rl_dev,
2992 "no memory for jumbo RX buffers\n");
2996 /* Disable checksum offloading for jumbo frames. */
2997 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_TSO4);
2998 ifp->if_hwassist &= ~(RE_CSUM_FEATURES | CSUM_TSO);
3000 if (re_rx_list_init(sc) != 0) {
3001 device_printf(sc->rl_dev,
3002 "no memory for RX buffers\n");
3007 re_set_jumbo(sc, ifp->if_mtu > RL_MTU);
3009 if (re_rx_list_init(sc) != 0) {
3010 device_printf(sc->rl_dev, "no memory for RX buffers\n");
3014 if ((sc->rl_flags & RL_FLAG_PCIE) != 0 &&
3015 pci_get_device(sc->rl_dev) != RT_DEVICEID_8101E) {
3016 if (ifp->if_mtu > RL_MTU)
3017 pci_set_max_read_req(sc->rl_dev, 512);
3019 pci_set_max_read_req(sc->rl_dev, 4096);
3022 re_tx_list_init(sc);
3025 * Enable C+ RX and TX mode, as well as VLAN stripping and
3026 * RX checksum offload. We must configure the C+ register
3027 * before all others.
3029 cfg = RL_CPLUSCMD_PCI_MRW;
3030 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
3031 cfg |= RL_CPLUSCMD_RXCSUM_ENB;
3032 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
3033 cfg |= RL_CPLUSCMD_VLANSTRIP;
3034 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) {
3035 cfg |= RL_CPLUSCMD_MACSTAT_DIS;
3039 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB;
3040 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg);
3041 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SC ||
3042 sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) {
3044 if ((CSR_READ_1(sc, RL_CFG2) & RL_CFG2_PCI66MHZ) != 0)
3046 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE)
3048 CSR_WRITE_4(sc, 0x7c, reg);
3049 /* Disable interrupt mitigation. */
3050 CSR_WRITE_2(sc, 0xe2, 0);
3053 * Disable TSO if interface MTU size is greater than MSS
3054 * allowed in controller.
3056 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) {
3057 ifp->if_capenable &= ~IFCAP_TSO4;
3058 ifp->if_hwassist &= ~CSUM_TSO;
3062 * Init our MAC address. Even though the chipset
3063 * documentation doesn't mention it, we need to enter "Config
3064 * register write enable" mode to modify the ID registers.
3066 /* Copy MAC address on stack to align. */
3067 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN);
3068 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
3069 CSR_WRITE_4(sc, RL_IDR0,
3070 htole32(*(u_int32_t *)(&eaddr.eaddr[0])));
3071 CSR_WRITE_4(sc, RL_IDR4,
3072 htole32(*(u_int32_t *)(&eaddr.eaddr[4])));
3073 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
3076 * Load the addresses of the RX and TX lists into the chip.
3079 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI,
3080 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr));
3081 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO,
3082 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr));
3084 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI,
3085 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr));
3086 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO,
3087 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr));
3090 * Enable transmit and receive.
3092 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
3095 * Set the initial TX configuration.
3097 if (sc->rl_testmode) {
3098 if (sc->rl_type == RL_8169)
3099 CSR_WRITE_4(sc, RL_TXCFG,
3100 RL_TXCFG_CONFIG|RL_LOOPTEST_ON);
3102 CSR_WRITE_4(sc, RL_TXCFG,
3103 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS);
3105 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
3107 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16);
3110 * Set the initial RX configuration.
3114 /* Configure interrupt moderation. */
3115 if (sc->rl_type == RL_8169) {
3116 /* Magic from vendor. */
3117 CSR_WRITE_2(sc, RL_INTRMOD, 0x5100);
3120 #ifdef DEVICE_POLLING
3122 * Disable interrupts if we are polling.
3124 if (ifp->if_capenable & IFCAP_POLLING)
3125 CSR_WRITE_2(sc, RL_IMR, 0);
3126 else /* otherwise ... */
3130 * Enable interrupts.
3132 if (sc->rl_testmode)
3133 CSR_WRITE_2(sc, RL_IMR, 0);
3135 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
3136 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS);
3138 /* Set initial TX threshold */
3139 sc->rl_txthresh = RL_TX_THRESH_INIT;
3141 /* Start RX/TX process. */
3142 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
3144 /* Enable receiver and transmitter. */
3145 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
3149 * Initialize the timer interrupt register so that
3150 * a timer interrupt will be generated once the timer
3151 * reaches a certain number of ticks. The timer is
3152 * reloaded on each transmit.
3154 #ifdef RE_TX_MODERATION
3156 * Use timer interrupt register to moderate TX interrupt
3157 * moderation, which dramatically improves TX frame rate.
3159 if (sc->rl_type == RL_8169)
3160 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800);
3162 CSR_WRITE_4(sc, RL_TIMERINT, 0x400);
3165 * Use timer interrupt register to moderate RX interrupt
3168 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 &&
3170 if (sc->rl_type == RL_8169)
3171 CSR_WRITE_4(sc, RL_TIMERINT_8169,
3172 RL_USECS(sc->rl_int_rx_mod));
3174 if (sc->rl_type == RL_8169)
3175 CSR_WRITE_4(sc, RL_TIMERINT_8169, RL_USECS(0));
3180 * For 8169 gigE NICs, set the max allowed RX packet
3181 * size so we can receive jumbo frames.
3183 if (sc->rl_type == RL_8169) {
3184 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
3186 * For controllers that use new jumbo frame scheme,
3187 * set maximum size of jumbo frame depedning on
3188 * controller revisions.
3190 if (ifp->if_mtu > RL_MTU)
3191 CSR_WRITE_2(sc, RL_MAXRXPKTLEN,
3192 sc->rl_hwrev->rl_max_mtu +
3193 ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN +
3196 CSR_WRITE_2(sc, RL_MAXRXPKTLEN,
3198 } else if ((sc->rl_flags & RL_FLAG_PCIE) != 0 &&
3199 sc->rl_hwrev->rl_max_mtu == RL_MTU) {
3200 /* RTL810x has no jumbo frame support. */
3201 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, RE_RX_DESC_BUFLEN);
3203 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383);
3206 if (sc->rl_testmode)
3209 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD);
3211 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3212 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3214 sc->rl_flags &= ~RL_FLAG_LINK;
3217 sc->rl_watchdog_timer = 0;
3218 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
3222 * Set media options.
3225 re_ifmedia_upd(struct ifnet *ifp)
3227 struct rl_softc *sc;
3228 struct mii_data *mii;
3232 mii = device_get_softc(sc->rl_miibus);
3234 error = mii_mediachg(mii);
3241 * Report current media status.
3244 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3246 struct rl_softc *sc;
3247 struct mii_data *mii;
3250 mii = device_get_softc(sc->rl_miibus);
3254 ifmr->ifm_active = mii->mii_media_active;
3255 ifmr->ifm_status = mii->mii_media_status;
3260 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3262 struct rl_softc *sc = ifp->if_softc;
3263 struct ifreq *ifr = (struct ifreq *) data;
3264 struct mii_data *mii;
3270 if (ifr->ifr_mtu < ETHERMIN ||
3271 ifr->ifr_mtu > sc->rl_hwrev->rl_max_mtu) {
3276 if (ifp->if_mtu != ifr->ifr_mtu) {
3277 ifp->if_mtu = ifr->ifr_mtu;
3278 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 &&
3279 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
3280 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3283 if (ifp->if_mtu > RL_TSO_MTU &&
3284 (ifp->if_capenable & IFCAP_TSO4) != 0) {
3285 ifp->if_capenable &= ~(IFCAP_TSO4 |
3287 ifp->if_hwassist &= ~CSUM_TSO;
3289 VLAN_CAPABILITIES(ifp);
3295 if ((ifp->if_flags & IFF_UP) != 0) {
3296 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
3297 if (((ifp->if_flags ^ sc->rl_if_flags)
3298 & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
3303 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
3306 sc->rl_if_flags = ifp->if_flags;
3312 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
3318 mii = device_get_softc(sc->rl_miibus);
3319 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
3325 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3327 #ifdef DEVICE_POLLING
3328 if (mask & IFCAP_POLLING) {
3329 if (ifr->ifr_reqcap & IFCAP_POLLING) {
3330 error = ether_poll_register(re_poll, ifp);
3334 /* Disable interrupts */
3335 CSR_WRITE_2(sc, RL_IMR, 0x0000);
3336 ifp->if_capenable |= IFCAP_POLLING;
3339 error = ether_poll_deregister(ifp);
3340 /* Enable interrupts. */
3342 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
3343 ifp->if_capenable &= ~IFCAP_POLLING;
3347 #endif /* DEVICE_POLLING */
3349 if ((mask & IFCAP_TXCSUM) != 0 &&
3350 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
3351 ifp->if_capenable ^= IFCAP_TXCSUM;
3352 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) {
3353 rev = sc->rl_hwrev->rl_rev;
3354 if (rev == RL_HWREV_8168C ||
3355 rev == RL_HWREV_8168C_SPIN2)
3356 ifp->if_hwassist |= CSUM_TCP | CSUM_UDP;
3358 ifp->if_hwassist |= RE_CSUM_FEATURES;
3360 ifp->if_hwassist &= ~RE_CSUM_FEATURES;
3363 if ((mask & IFCAP_RXCSUM) != 0 &&
3364 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) {
3365 ifp->if_capenable ^= IFCAP_RXCSUM;
3368 if ((mask & IFCAP_TSO4) != 0 &&
3369 (ifp->if_capabilities & IFCAP_TSO) != 0) {
3370 ifp->if_capenable ^= IFCAP_TSO4;
3371 if ((IFCAP_TSO4 & ifp->if_capenable) != 0)
3372 ifp->if_hwassist |= CSUM_TSO;
3374 ifp->if_hwassist &= ~CSUM_TSO;
3375 if (ifp->if_mtu > RL_TSO_MTU &&
3376 (ifp->if_capenable & IFCAP_TSO4) != 0) {
3377 ifp->if_capenable &= ~IFCAP_TSO4;
3378 ifp->if_hwassist &= ~CSUM_TSO;
3381 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
3382 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
3383 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
3384 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
3385 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
3386 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
3387 /* TSO over VLAN requires VLAN hardware tagging. */
3388 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
3389 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
3392 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 &&
3393 (mask & (IFCAP_HWCSUM | IFCAP_TSO4 |
3394 IFCAP_VLAN_HWTSO)) != 0)
3396 if ((mask & IFCAP_WOL) != 0 &&
3397 (ifp->if_capabilities & IFCAP_WOL) != 0) {
3398 if ((mask & IFCAP_WOL_UCAST) != 0)
3399 ifp->if_capenable ^= IFCAP_WOL_UCAST;
3400 if ((mask & IFCAP_WOL_MCAST) != 0)
3401 ifp->if_capenable ^= IFCAP_WOL_MCAST;
3402 if ((mask & IFCAP_WOL_MAGIC) != 0)
3403 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
3405 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) {
3406 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3410 VLAN_CAPABILITIES(ifp);
3414 error = ether_ioctl(ifp, command, data);
3422 re_watchdog(struct rl_softc *sc)
3428 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0)
3433 if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) {
3434 if_printf(ifp, "watchdog timeout (missed Tx interrupts) "
3436 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3437 re_start_locked(ifp);
3441 if_printf(ifp, "watchdog timeout\n");
3445 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3447 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3448 re_start_locked(ifp);
3452 * Stop the adapter and free any mbufs allocated to the
3456 re_stop(struct rl_softc *sc)
3460 struct rl_txdesc *txd;
3461 struct rl_rxdesc *rxd;
3467 sc->rl_watchdog_timer = 0;
3468 callout_stop(&sc->rl_stat_callout);
3469 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3472 * Disable accepting frames to put RX MAC into idle state.
3473 * Otherwise it's possible to get frames while stop command
3474 * execution is in progress and controller can DMA the frame
3475 * to already freed RX buffer during that period.
3477 CSR_WRITE_4(sc, RL_RXCFG, CSR_READ_4(sc, RL_RXCFG) &
3478 ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_MULTI |
3479 RL_RXCFG_RX_BROAD));
3481 if ((sc->rl_flags & RL_FLAG_WAIT_TXPOLL) != 0) {
3482 for (i = RL_TIMEOUT; i > 0; i--) {
3483 if ((CSR_READ_1(sc, sc->rl_txstart) &
3484 RL_TXSTART_START) == 0)
3489 device_printf(sc->rl_dev,
3490 "stopping TX poll timed out!\n");
3491 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
3492 } else if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) {
3493 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB |
3495 if ((sc->rl_flags & RL_FLAG_CMDSTOP_WAIT_TXQ) != 0) {
3496 for (i = RL_TIMEOUT; i > 0; i--) {
3497 if ((CSR_READ_4(sc, RL_TXCFG) &
3498 RL_TXCFG_QUEUE_EMPTY) != 0)
3503 device_printf(sc->rl_dev,
3504 "stopping TXQ timed out!\n");
3507 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
3509 CSR_WRITE_2(sc, RL_IMR, 0x0000);
3510 CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
3512 if (sc->rl_head != NULL) {
3513 m_freem(sc->rl_head);
3514 sc->rl_head = sc->rl_tail = NULL;
3517 /* Free the TX list buffers. */
3519 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
3520 txd = &sc->rl_ldata.rl_tx_desc[i];
3521 if (txd->tx_m != NULL) {
3522 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag,
3523 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
3524 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag,
3531 /* Free the RX list buffers. */
3533 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
3534 rxd = &sc->rl_ldata.rl_rx_desc[i];
3535 if (rxd->rx_m != NULL) {
3536 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag,
3537 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3538 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag,
3547 * Device suspend routine. Stop the interface and save some PCI
3548 * settings in case the BIOS doesn't restore them properly on
3552 re_suspend(device_t dev)
3554 struct rl_softc *sc;
3556 sc = device_get_softc(dev);
3568 * Device resume routine. Restore some PCI settings in case the BIOS
3569 * doesn't, re-enable busmastering, and restart the interface if
3573 re_resume(device_t dev)
3575 struct rl_softc *sc;
3578 sc = device_get_softc(dev);
3583 /* Take controller out of sleep mode. */
3584 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) {
3585 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)
3586 CSR_WRITE_1(sc, RL_GPIO,
3587 CSR_READ_1(sc, RL_GPIO) | 0x01);
3591 * Clear WOL matching such that normal Rx filtering
3592 * wouldn't interfere with WOL patterns.
3596 /* reinitialize interface if necessary */
3597 if (ifp->if_flags & IFF_UP)
3607 * Stop all chip I/O so that the kernel's probe routines don't
3608 * get confused by errant DMAs when rebooting.
3611 re_shutdown(device_t dev)
3613 struct rl_softc *sc;
3615 sc = device_get_softc(dev);
3620 * Mark interface as down since otherwise we will panic if
3621 * interrupt comes in later on, which can happen in some
3624 sc->rl_ifp->if_flags &= ~IFF_UP;
3632 re_set_linkspeed(struct rl_softc *sc)
3634 struct mii_softc *miisc;
3635 struct mii_data *mii;
3640 mii = device_get_softc(sc->rl_miibus);
3643 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
3644 (IFM_ACTIVE | IFM_AVALID)) {
3645 switch IFM_SUBTYPE(mii->mii_media_active) {
3656 miisc = LIST_FIRST(&mii->mii_phys);
3657 phyno = miisc->mii_phy;
3658 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3660 re_miibus_writereg(sc->rl_dev, phyno, MII_100T2CR, 0);
3661 re_miibus_writereg(sc->rl_dev, phyno,
3662 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
3663 re_miibus_writereg(sc->rl_dev, phyno,
3664 MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG);
3668 * Poll link state until re(4) get a 10/100Mbps link.
3670 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
3672 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID))
3673 == (IFM_ACTIVE | IFM_AVALID)) {
3674 switch (IFM_SUBTYPE(mii->mii_media_active)) {
3686 if (i == MII_ANEGTICKS_GIGE)
3687 device_printf(sc->rl_dev,
3688 "establishing a link failed, WOL may not work!");
3691 * No link, force MAC to have 100Mbps, full-duplex link.
3692 * MAC does not require reprogramming on resolved speed/duplex,
3693 * so this is just for completeness.
3695 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
3696 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
3700 re_setwol(struct rl_softc *sc)
3709 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
3713 /* Put controller into sleep mode. */
3714 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) {
3715 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)
3716 CSR_WRITE_1(sc, RL_GPIO,
3717 CSR_READ_1(sc, RL_GPIO) & ~0x01);
3719 if ((ifp->if_capenable & IFCAP_WOL) != 0) {
3721 if ((sc->rl_flags & RL_FLAG_WOL_MANLINK) != 0)
3722 re_set_linkspeed(sc);
3723 if ((sc->rl_flags & RL_FLAG_WOLRXENB) != 0)
3724 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB);
3726 /* Enable config register write. */
3727 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
3730 v = CSR_READ_1(sc, RL_CFG1);
3732 if ((ifp->if_capenable & IFCAP_WOL) != 0)
3734 CSR_WRITE_1(sc, RL_CFG1, v);
3736 v = CSR_READ_1(sc, RL_CFG3);
3737 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
3738 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
3739 v |= RL_CFG3_WOL_MAGIC;
3740 CSR_WRITE_1(sc, RL_CFG3, v);
3742 v = CSR_READ_1(sc, RL_CFG5);
3743 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST |
3744 RL_CFG5_WOL_LANWAKE);
3745 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0)
3746 v |= RL_CFG5_WOL_UCAST;
3747 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
3748 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST;
3749 if ((ifp->if_capenable & IFCAP_WOL) != 0)
3750 v |= RL_CFG5_WOL_LANWAKE;
3751 CSR_WRITE_1(sc, RL_CFG5, v);
3753 /* Config register write done. */
3754 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
3756 if ((ifp->if_capenable & IFCAP_WOL) != 0 &&
3757 (sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0)
3758 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80);
3760 * It seems that hardware resets its link speed to 100Mbps in
3761 * power down mode so switching to 100Mbps in driver is not
3765 /* Request PME if WOL is requested. */
3766 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2);
3767 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
3768 if ((ifp->if_capenable & IFCAP_WOL) != 0)
3769 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3770 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
3774 re_clrwol(struct rl_softc *sc)
3781 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
3784 /* Enable config register write. */
3785 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
3787 v = CSR_READ_1(sc, RL_CFG3);
3788 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
3789 CSR_WRITE_1(sc, RL_CFG3, v);
3791 /* Config register write done. */
3792 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
3794 v = CSR_READ_1(sc, RL_CFG5);
3795 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
3796 v &= ~RL_CFG5_WOL_LANWAKE;
3797 CSR_WRITE_1(sc, RL_CFG5, v);
3801 re_add_sysctls(struct rl_softc *sc)
3803 struct sysctl_ctx_list *ctx;
3804 struct sysctl_oid_list *children;
3807 ctx = device_get_sysctl_ctx(sc->rl_dev);
3808 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev));
3810 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "stats",
3811 CTLTYPE_INT | CTLFLAG_RW, sc, 0, re_sysctl_stats, "I",
3812 "Statistics Information");
3813 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0)
3816 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "int_rx_mod",
3817 CTLTYPE_INT | CTLFLAG_RW, &sc->rl_int_rx_mod, 0,
3818 sysctl_hw_re_int_mod, "I", "re RX interrupt moderation");
3819 /* Pull in device tunables. */
3820 sc->rl_int_rx_mod = RL_TIMER_DEFAULT;
3821 error = resource_int_value(device_get_name(sc->rl_dev),
3822 device_get_unit(sc->rl_dev), "int_rx_mod", &sc->rl_int_rx_mod);
3824 if (sc->rl_int_rx_mod < RL_TIMER_MIN ||
3825 sc->rl_int_rx_mod > RL_TIMER_MAX) {
3826 device_printf(sc->rl_dev, "int_rx_mod value out of "
3827 "range; using default: %d\n",
3829 sc->rl_int_rx_mod = RL_TIMER_DEFAULT;
3836 re_sysctl_stats(SYSCTL_HANDLER_ARGS)
3838 struct rl_softc *sc;
3839 struct rl_stats *stats;
3840 int error, i, result;
3843 error = sysctl_handle_int(oidp, &result, 0, req);
3844 if (error || req->newptr == NULL)
3848 sc = (struct rl_softc *)arg1;
3850 if ((sc->rl_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
3854 bus_dmamap_sync(sc->rl_ldata.rl_stag,
3855 sc->rl_ldata.rl_smap, BUS_DMASYNC_PREREAD);
3856 CSR_WRITE_4(sc, RL_DUMPSTATS_HI,
3857 RL_ADDR_HI(sc->rl_ldata.rl_stats_addr));
3858 CSR_WRITE_4(sc, RL_DUMPSTATS_LO,
3859 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr));
3860 CSR_WRITE_4(sc, RL_DUMPSTATS_LO,
3861 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr |
3862 RL_DUMPSTATS_START));
3863 for (i = RL_TIMEOUT; i > 0; i--) {
3864 if ((CSR_READ_4(sc, RL_DUMPSTATS_LO) &
3865 RL_DUMPSTATS_START) == 0)
3869 bus_dmamap_sync(sc->rl_ldata.rl_stag,
3870 sc->rl_ldata.rl_smap, BUS_DMASYNC_POSTREAD);
3873 device_printf(sc->rl_dev,
3874 "DUMP statistics request timedout\n");
3878 stats = sc->rl_ldata.rl_stats;
3879 printf("%s statistics:\n", device_get_nameunit(sc->rl_dev));
3880 printf("Tx frames : %ju\n",
3881 (uintmax_t)le64toh(stats->rl_tx_pkts));
3882 printf("Rx frames : %ju\n",
3883 (uintmax_t)le64toh(stats->rl_rx_pkts));
3884 printf("Tx errors : %ju\n",
3885 (uintmax_t)le64toh(stats->rl_tx_errs));
3886 printf("Rx errors : %u\n",
3887 le32toh(stats->rl_rx_errs));
3888 printf("Rx missed frames : %u\n",
3889 (uint32_t)le16toh(stats->rl_missed_pkts));
3890 printf("Rx frame alignment errs : %u\n",
3891 (uint32_t)le16toh(stats->rl_rx_framealign_errs));
3892 printf("Tx single collisions : %u\n",
3893 le32toh(stats->rl_tx_onecoll));
3894 printf("Tx multiple collisions : %u\n",
3895 le32toh(stats->rl_tx_multicolls));
3896 printf("Rx unicast frames : %ju\n",
3897 (uintmax_t)le64toh(stats->rl_rx_ucasts));
3898 printf("Rx broadcast frames : %ju\n",
3899 (uintmax_t)le64toh(stats->rl_rx_bcasts));
3900 printf("Rx multicast frames : %u\n",
3901 le32toh(stats->rl_rx_mcasts));
3902 printf("Tx aborts : %u\n",
3903 (uint32_t)le16toh(stats->rl_tx_aborts));
3904 printf("Tx underruns : %u\n",
3905 (uint32_t)le16toh(stats->rl_rx_underruns));
3912 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3918 value = *(int *)arg1;
3919 error = sysctl_handle_int(oidp, &value, 0, req);
3920 if (error || req->newptr == NULL)
3922 if (value < low || value > high)
3924 *(int *)arg1 = value;
3930 sysctl_hw_re_int_mod(SYSCTL_HANDLER_ARGS)
3933 return (sysctl_int_range(oidp, arg1, arg2, req, RL_TIMER_MIN,