2 * Copyright (c) 1997, 1998-2003
3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver
39 * Written by Bill Paul <wpaul@windriver.com>
40 * Senior Networking Software Engineer
45 * This driver is designed to support RealTek's next generation of
46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S,
48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E.
50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
51 * with the older 8139 family, however it also supports a special
52 * C+ mode of operation that provides several new performance enhancing
53 * features. These include:
55 * o Descriptor based DMA mechanism. Each descriptor represents
56 * a single packet fragment. Data buffers may be aligned on
61 * o TCP/IP checksum offload for both RX and TX
63 * o High and normal priority transmit DMA rings
65 * o VLAN tag insertion and extraction
67 * o TCP large send (segmentation offload)
69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
70 * programming API is fairly straightforward. The RX filtering, EEPROM
71 * access and PHY access is the same as it is on the older 8139 series
74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
75 * same programming API and feature set as the 8139C+ with the following
76 * differences and additions:
82 * o GMII and TBI ports/registers for interfacing with copper
85 * o RX and TX DMA rings can have up to 1024 descriptors
86 * (the 8139C+ allows a maximum of 64)
88 * o Slight differences in register layout from the 8139C+
90 * The TX start and timer interrupt registers are at different locations
91 * on the 8169 than they are on the 8139C+. Also, the status word in the
92 * RX descriptor has a slightly different bit layout. The 8169 does not
93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
97 * (the 'S' stands for 'single-chip'). These devices have the same
98 * programming API as the older 8169, but also have some vendor-specific
99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
102 * This driver takes advantage of the RX and TX checksum offload and
103 * VLAN tag insertion/extraction features. It also implements TX
104 * interrupt moderation using the timer interrupt registers, which
105 * significantly reduces TX interrupt load. There is also support
106 * for jumbo frames, however the 8169/8169S/8110S can not transmit
107 * jumbo frames larger than 7440, so the max MTU possible with this
108 * driver is 7422 bytes.
111 #ifdef HAVE_KERNEL_OPTION_HEADERS
112 #include "opt_device_polling.h"
115 #include <sys/param.h>
116 #include <sys/endian.h>
117 #include <sys/systm.h>
118 #include <sys/sockio.h>
119 #include <sys/mbuf.h>
120 #include <sys/malloc.h>
121 #include <sys/module.h>
122 #include <sys/kernel.h>
123 #include <sys/socket.h>
124 #include <sys/lock.h>
125 #include <sys/mutex.h>
126 #include <sys/sysctl.h>
127 #include <sys/taskqueue.h>
130 #include <net/if_arp.h>
131 #include <net/ethernet.h>
132 #include <net/if_dl.h>
133 #include <net/if_media.h>
134 #include <net/if_types.h>
135 #include <net/if_vlan_var.h>
139 #include <machine/bus.h>
140 #include <machine/resource.h>
142 #include <sys/rman.h>
144 #include <dev/mii/mii.h>
145 #include <dev/mii/miivar.h>
147 #include <dev/pci/pcireg.h>
148 #include <dev/pci/pcivar.h>
150 #include <pci/if_rlreg.h>
152 MODULE_DEPEND(re, pci, 1, 1, 1);
153 MODULE_DEPEND(re, ether, 1, 1, 1);
154 MODULE_DEPEND(re, miibus, 1, 1, 1);
156 /* "device miibus" required. See GENERIC if you get errors here. */
157 #include "miibus_if.h"
160 static int intr_filter = 0;
161 TUNABLE_INT("hw.re.intr_filter", &intr_filter);
162 static int msi_disable = 0;
163 TUNABLE_INT("hw.re.msi_disable", &msi_disable);
164 static int msix_disable = 0;
165 TUNABLE_INT("hw.re.msix_disable", &msix_disable);
166 static int prefer_iomap = 0;
167 TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap);
169 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
172 * Various supported device vendors/types and their names.
174 static const struct rl_type re_devs[] = {
175 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0,
176 "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
177 { DLINK_VENDORID, DLINK_DEVICEID_530T_REVC, 0,
178 "D-Link DGE-530(T) Gigabit Ethernet Adapter" },
179 { RT_VENDORID, RT_DEVICEID_8139, 0,
180 "RealTek 8139C+ 10/100BaseTX" },
181 { RT_VENDORID, RT_DEVICEID_8101E, 0,
182 "RealTek 810xE PCIe 10/100baseTX" },
183 { RT_VENDORID, RT_DEVICEID_8168, 0,
184 "RealTek 8168/8111 B/C/CP/D/DP/E/F PCIe Gigabit Ethernet" },
185 { RT_VENDORID, RT_DEVICEID_8169, 0,
186 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" },
187 { RT_VENDORID, RT_DEVICEID_8169SC, 0,
188 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
189 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0,
190 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" },
191 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0,
192 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" },
193 { USR_VENDORID, USR_DEVICEID_997902, 0,
194 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" }
197 static const struct rl_hwrev re_hwrevs[] = {
198 { RL_HWREV_8139, RL_8139, "", RL_MTU },
199 { RL_HWREV_8139A, RL_8139, "A", RL_MTU },
200 { RL_HWREV_8139AG, RL_8139, "A-G", RL_MTU },
201 { RL_HWREV_8139B, RL_8139, "B", RL_MTU },
202 { RL_HWREV_8130, RL_8139, "8130", RL_MTU },
203 { RL_HWREV_8139C, RL_8139, "C", RL_MTU },
204 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C", RL_MTU },
205 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+", RL_MTU },
206 { RL_HWREV_8168B_SPIN1, RL_8169, "8168", RL_JUMBO_MTU },
207 { RL_HWREV_8169, RL_8169, "8169", RL_JUMBO_MTU },
208 { RL_HWREV_8169S, RL_8169, "8169S", RL_JUMBO_MTU },
209 { RL_HWREV_8110S, RL_8169, "8110S", RL_JUMBO_MTU },
210 { RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB", RL_JUMBO_MTU },
211 { RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU },
212 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL", RL_JUMBO_MTU },
213 { RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU },
214 { RL_HWREV_8100, RL_8139, "8100", RL_MTU },
215 { RL_HWREV_8101, RL_8139, "8101", RL_MTU },
216 { RL_HWREV_8100E, RL_8169, "8100E", RL_MTU },
217 { RL_HWREV_8101E, RL_8169, "8101E", RL_MTU },
218 { RL_HWREV_8102E, RL_8169, "8102E", RL_MTU },
219 { RL_HWREV_8102EL, RL_8169, "8102EL", RL_MTU },
220 { RL_HWREV_8102EL_SPIN1, RL_8169, "8102EL", RL_MTU },
221 { RL_HWREV_8103E, RL_8169, "8103E", RL_MTU },
222 { RL_HWREV_8401E, RL_8169, "8401E", RL_MTU },
223 { RL_HWREV_8402, RL_8169, "8402", RL_MTU },
224 { RL_HWREV_8105E, RL_8169, "8105E", RL_MTU },
225 { RL_HWREV_8105E_SPIN1, RL_8169, "8105E", RL_MTU },
226 { RL_HWREV_8106E, RL_8169, "8106E", RL_MTU },
227 { RL_HWREV_8168B_SPIN2, RL_8169, "8168", RL_JUMBO_MTU },
228 { RL_HWREV_8168B_SPIN3, RL_8169, "8168", RL_JUMBO_MTU },
229 { RL_HWREV_8168C, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K },
230 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K },
231 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP", RL_JUMBO_MTU_6K },
232 { RL_HWREV_8168D, RL_8169, "8168D/8111D", RL_JUMBO_MTU_9K },
233 { RL_HWREV_8168DP, RL_8169, "8168DP/8111DP", RL_JUMBO_MTU_9K },
234 { RL_HWREV_8168E, RL_8169, "8168E/8111E", RL_JUMBO_MTU_9K},
235 { RL_HWREV_8168E_VL, RL_8169, "8168E/8111E-VL", RL_JUMBO_MTU_6K},
236 { RL_HWREV_8168F, RL_8169, "8168F/8111F", RL_JUMBO_MTU_9K},
237 { RL_HWREV_8411, RL_8169, "8411", RL_JUMBO_MTU_9K},
241 static int re_probe (device_t);
242 static int re_attach (device_t);
243 static int re_detach (device_t);
245 static int re_encap (struct rl_softc *, struct mbuf **);
247 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int);
248 static int re_allocmem (device_t, struct rl_softc *);
249 static __inline void re_discard_rxbuf
250 (struct rl_softc *, int);
251 static int re_newbuf (struct rl_softc *, int);
252 static int re_jumbo_newbuf (struct rl_softc *, int);
253 static int re_rx_list_init (struct rl_softc *);
254 static int re_jrx_list_init (struct rl_softc *);
255 static int re_tx_list_init (struct rl_softc *);
257 static __inline void re_fixup_rx
260 static int re_rxeof (struct rl_softc *, int *);
261 static void re_txeof (struct rl_softc *);
262 #ifdef DEVICE_POLLING
263 static int re_poll (struct ifnet *, enum poll_cmd, int);
264 static int re_poll_locked (struct ifnet *, enum poll_cmd, int);
266 static int re_intr (void *);
267 static void re_intr_msi (void *);
268 static void re_tick (void *);
269 static void re_int_task (void *, int);
270 static void re_start (struct ifnet *);
271 static void re_start_locked (struct ifnet *);
272 static int re_ioctl (struct ifnet *, u_long, caddr_t);
273 static void re_init (void *);
274 static void re_init_locked (struct rl_softc *);
275 static void re_stop (struct rl_softc *);
276 static void re_watchdog (struct rl_softc *);
277 static int re_suspend (device_t);
278 static int re_resume (device_t);
279 static int re_shutdown (device_t);
280 static int re_ifmedia_upd (struct ifnet *);
281 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *);
283 static void re_eeprom_putbyte (struct rl_softc *, int);
284 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *);
285 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int);
286 static int re_gmii_readreg (device_t, int, int);
287 static int re_gmii_writereg (device_t, int, int, int);
289 static int re_miibus_readreg (device_t, int, int);
290 static int re_miibus_writereg (device_t, int, int, int);
291 static void re_miibus_statchg (device_t);
293 static void re_set_jumbo (struct rl_softc *, int);
294 static void re_set_rxmode (struct rl_softc *);
295 static void re_reset (struct rl_softc *);
296 static void re_setwol (struct rl_softc *);
297 static void re_clrwol (struct rl_softc *);
298 static void re_set_linkspeed (struct rl_softc *);
300 #ifdef DEV_NETMAP /* see ixgbe.c for details */
301 #include <dev/netmap/if_re_netmap.h>
302 #endif /* !DEV_NETMAP */
305 static int re_diag (struct rl_softc *);
308 static void re_add_sysctls (struct rl_softc *);
309 static int re_sysctl_stats (SYSCTL_HANDLER_ARGS);
310 static int sysctl_int_range (SYSCTL_HANDLER_ARGS, int, int);
311 static int sysctl_hw_re_int_mod (SYSCTL_HANDLER_ARGS);
313 static device_method_t re_methods[] = {
314 /* Device interface */
315 DEVMETHOD(device_probe, re_probe),
316 DEVMETHOD(device_attach, re_attach),
317 DEVMETHOD(device_detach, re_detach),
318 DEVMETHOD(device_suspend, re_suspend),
319 DEVMETHOD(device_resume, re_resume),
320 DEVMETHOD(device_shutdown, re_shutdown),
323 DEVMETHOD(miibus_readreg, re_miibus_readreg),
324 DEVMETHOD(miibus_writereg, re_miibus_writereg),
325 DEVMETHOD(miibus_statchg, re_miibus_statchg),
330 static driver_t re_driver = {
333 sizeof(struct rl_softc)
336 static devclass_t re_devclass;
338 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0);
339 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0);
342 CSR_WRITE_1(sc, RL_EECMD, \
343 CSR_READ_1(sc, RL_EECMD) | x)
346 CSR_WRITE_1(sc, RL_EECMD, \
347 CSR_READ_1(sc, RL_EECMD) & ~x)
350 * Send a read command and address to the EEPROM, check for ACK.
353 re_eeprom_putbyte(struct rl_softc *sc, int addr)
357 d = addr | (RL_9346_READ << sc->rl_eewidth);
360 * Feed in each bit and strobe the clock.
363 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) {
365 EE_SET(RL_EE_DATAIN);
367 EE_CLR(RL_EE_DATAIN);
378 * Read a word of data stored in the EEPROM at address 'addr.'
381 re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest)
387 * Send address of word we want to read.
389 re_eeprom_putbyte(sc, addr);
392 * Start reading bits from EEPROM.
394 for (i = 0x8000; i; i >>= 1) {
397 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
407 * Read a sequence of words from the EEPROM.
410 re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt)
413 u_int16_t word = 0, *ptr;
415 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM);
419 for (i = 0; i < cnt; i++) {
420 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL);
421 re_eeprom_getword(sc, off + i, &word);
422 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL);
423 ptr = (u_int16_t *)(dest + (i * 2));
427 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM);
431 re_gmii_readreg(device_t dev, int phy, int reg)
437 sc = device_get_softc(dev);
439 /* Let the rgephy driver read the GMEDIASTAT register */
441 if (reg == RL_GMEDIASTAT) {
442 rval = CSR_READ_1(sc, RL_GMEDIASTAT);
446 CSR_WRITE_4(sc, RL_PHYAR, reg << 16);
448 for (i = 0; i < RL_PHY_TIMEOUT; i++) {
449 rval = CSR_READ_4(sc, RL_PHYAR);
450 if (rval & RL_PHYAR_BUSY)
455 if (i == RL_PHY_TIMEOUT) {
456 device_printf(sc->rl_dev, "PHY read failed\n");
461 * Controller requires a 20us delay to process next MDIO request.
465 return (rval & RL_PHYAR_PHYDATA);
469 re_gmii_writereg(device_t dev, int phy, int reg, int data)
475 sc = device_get_softc(dev);
477 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) |
478 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY);
480 for (i = 0; i < RL_PHY_TIMEOUT; i++) {
481 rval = CSR_READ_4(sc, RL_PHYAR);
482 if (!(rval & RL_PHYAR_BUSY))
487 if (i == RL_PHY_TIMEOUT) {
488 device_printf(sc->rl_dev, "PHY write failed\n");
493 * Controller requires a 20us delay to process next MDIO request.
501 re_miibus_readreg(device_t dev, int phy, int reg)
505 u_int16_t re8139_reg = 0;
507 sc = device_get_softc(dev);
509 if (sc->rl_type == RL_8169) {
510 rval = re_gmii_readreg(dev, phy, reg);
516 re8139_reg = RL_BMCR;
519 re8139_reg = RL_BMSR;
522 re8139_reg = RL_ANAR;
525 re8139_reg = RL_ANER;
528 re8139_reg = RL_LPAR;
534 * Allow the rlphy driver to read the media status
535 * register. If we have a link partner which does not
536 * support NWAY, this is the register which will tell
537 * us the results of parallel detection.
540 rval = CSR_READ_1(sc, RL_MEDIASTAT);
543 device_printf(sc->rl_dev, "bad phy register\n");
546 rval = CSR_READ_2(sc, re8139_reg);
547 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) {
548 /* 8139C+ has different bit layout. */
549 rval &= ~(BMCR_LOOP | BMCR_ISO);
555 re_miibus_writereg(device_t dev, int phy, int reg, int data)
558 u_int16_t re8139_reg = 0;
561 sc = device_get_softc(dev);
563 if (sc->rl_type == RL_8169) {
564 rval = re_gmii_writereg(dev, phy, reg, data);
570 re8139_reg = RL_BMCR;
571 if (sc->rl_type == RL_8139CPLUS) {
572 /* 8139C+ has different bit layout. */
573 data &= ~(BMCR_LOOP | BMCR_ISO);
577 re8139_reg = RL_BMSR;
580 re8139_reg = RL_ANAR;
583 re8139_reg = RL_ANER;
586 re8139_reg = RL_LPAR;
593 device_printf(sc->rl_dev, "bad phy register\n");
596 CSR_WRITE_2(sc, re8139_reg, data);
601 re_miibus_statchg(device_t dev)
605 struct mii_data *mii;
607 sc = device_get_softc(dev);
608 mii = device_get_softc(sc->rl_miibus);
610 if (mii == NULL || ifp == NULL ||
611 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
614 sc->rl_flags &= ~RL_FLAG_LINK;
615 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
616 (IFM_ACTIVE | IFM_AVALID)) {
617 switch (IFM_SUBTYPE(mii->mii_media_active)) {
620 sc->rl_flags |= RL_FLAG_LINK;
623 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0)
625 sc->rl_flags |= RL_FLAG_LINK;
632 * RealTek controllers does not provide any interface to
633 * Tx/Rx MACs for resolved speed, duplex and flow-control
639 * Set the RX configuration and 64-bit multicast hash filter.
642 re_set_rxmode(struct rl_softc *sc)
645 struct ifmultiaddr *ifma;
646 uint32_t hashes[2] = { 0, 0 };
653 rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD;
655 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
656 if (ifp->if_flags & IFF_PROMISC)
657 rxfilt |= RL_RXCFG_RX_ALLPHYS;
659 * Unlike other hardwares, we have to explicitly set
660 * RL_RXCFG_RX_MULTI to receive multicast frames in
663 rxfilt |= RL_RXCFG_RX_MULTI;
664 hashes[0] = hashes[1] = 0xffffffff;
669 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
670 if (ifma->ifma_addr->sa_family != AF_LINK)
672 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
673 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
675 hashes[0] |= (1 << h);
677 hashes[1] |= (1 << (h - 32));
679 if_maddr_runlock(ifp);
681 if (hashes[0] != 0 || hashes[1] != 0) {
683 * For some unfathomable reason, RealTek decided to
684 * reverse the order of the multicast hash registers
685 * in the PCI Express parts. This means we have to
686 * write the hash pattern in reverse order for those
689 if ((sc->rl_flags & RL_FLAG_PCIE) != 0) {
690 h = bswap32(hashes[0]);
691 hashes[0] = bswap32(hashes[1]);
694 rxfilt |= RL_RXCFG_RX_MULTI;
698 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
699 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
700 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
704 re_reset(struct rl_softc *sc)
710 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
712 for (i = 0; i < RL_TIMEOUT; i++) {
714 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
718 device_printf(sc->rl_dev, "reset never completed!\n");
720 if ((sc->rl_flags & RL_FLAG_MACRESET) != 0)
721 CSR_WRITE_1(sc, 0x82, 1);
722 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169S)
723 re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0);
729 * The following routine is designed to test for a defect on some
730 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
731 * lines connected to the bus, however for a 32-bit only card, they
732 * should be pulled high. The result of this defect is that the
733 * NIC will not work right if you plug it into a 64-bit slot: DMA
734 * operations will be done with 64-bit transfers, which will fail
735 * because the 64-bit data lines aren't connected.
737 * There's no way to work around this (short of talking a soldering
738 * iron to the board), however we can detect it. The method we use
739 * here is to put the NIC into digital loopback mode, set the receiver
740 * to promiscuous mode, and then try to send a frame. We then compare
741 * the frame data we sent to what was received. If the data matches,
742 * then the NIC is working correctly, otherwise we know the user has
743 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
744 * slot. In the latter case, there's no way the NIC can work correctly,
745 * so we print out a message on the console and abort the device attach.
749 re_diag(struct rl_softc *sc)
751 struct ifnet *ifp = sc->rl_ifp;
753 struct ether_header *eh;
754 struct rl_desc *cur_rx;
757 int total_len, i, error = 0, phyaddr;
758 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
759 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
761 /* Allocate a single mbuf */
762 MGETHDR(m0, M_NOWAIT, MT_DATA);
769 * Initialize the NIC in test mode. This sets the chip up
770 * so that it can send and receive frames, but performs the
771 * following special functions:
772 * - Puts receiver in promiscuous mode
773 * - Enables digital loopback mode
774 * - Leaves interrupts turned off
777 ifp->if_flags |= IFF_PROMISC;
779 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
781 sc->rl_flags |= RL_FLAG_LINK;
782 if (sc->rl_type == RL_8169)
787 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET);
788 for (i = 0; i < RL_TIMEOUT; i++) {
789 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR);
790 if (!(status & BMCR_RESET))
794 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP);
795 CSR_WRITE_2(sc, RL_ISR, RL_INTRS);
799 /* Put some data in the mbuf */
801 eh = mtod(m0, struct ether_header *);
802 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN);
803 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN);
804 eh->ether_type = htons(ETHERTYPE_IP);
805 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
808 * Queue the packet, start transmission.
809 * Note: IF_HANDOFF() ultimately calls re_start() for us.
812 CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
814 /* XXX: re_diag must not be called when in ALTQ mode */
815 IF_HANDOFF(&ifp->if_snd, m0, ifp);
819 /* Wait for it to propagate through the chip */
822 for (i = 0; i < RL_TIMEOUT; i++) {
823 status = CSR_READ_2(sc, RL_ISR);
824 CSR_WRITE_2(sc, RL_ISR, status);
825 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) ==
826 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK))
831 if (i == RL_TIMEOUT) {
832 device_printf(sc->rl_dev,
833 "diagnostic failed, failed to receive packet in"
840 * The packet should have been dumped into the first
841 * entry in the RX DMA ring. Grab it from there.
844 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
845 sc->rl_ldata.rl_rx_list_map,
846 BUS_DMASYNC_POSTREAD);
847 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag,
848 sc->rl_ldata.rl_rx_desc[0].rx_dmamap,
849 BUS_DMASYNC_POSTREAD);
850 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag,
851 sc->rl_ldata.rl_rx_desc[0].rx_dmamap);
853 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m;
854 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL;
855 eh = mtod(m0, struct ether_header *);
857 cur_rx = &sc->rl_ldata.rl_rx_list[0];
858 total_len = RL_RXBYTES(cur_rx);
859 rxstat = le32toh(cur_rx->rl_cmdstat);
861 if (total_len != ETHER_MIN_LEN) {
862 device_printf(sc->rl_dev,
863 "diagnostic failed, received short packet\n");
868 /* Test that the received packet data matches what we sent. */
870 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) ||
871 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) ||
872 ntohs(eh->ether_type) != ETHERTYPE_IP) {
873 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n");
874 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n",
875 dst, ":", src, ":", ETHERTYPE_IP);
876 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n",
877 eh->ether_dhost, ":", eh->ether_shost, ":",
878 ntohs(eh->ether_type));
879 device_printf(sc->rl_dev, "You may have a defective 32-bit "
880 "NIC plugged into a 64-bit PCI slot.\n");
881 device_printf(sc->rl_dev, "Please re-install the NIC in a "
882 "32-bit slot for proper operation.\n");
883 device_printf(sc->rl_dev, "Read the re(4) man page for more "
889 /* Turn interface off, release resources */
892 sc->rl_flags &= ~RL_FLAG_LINK;
893 ifp->if_flags &= ~IFF_PROMISC;
906 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
907 * IDs against our list and return a device name if we find a match.
910 re_probe(device_t dev)
912 const struct rl_type *t;
913 uint16_t devid, vendor;
914 uint16_t revid, sdevid;
917 vendor = pci_get_vendor(dev);
918 devid = pci_get_device(dev);
919 revid = pci_get_revid(dev);
920 sdevid = pci_get_subdevice(dev);
922 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) {
923 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) {
925 * Only attach to rev. 3 of the Linksys EG1032 adapter.
926 * Rev. 2 is supported by sk(4).
932 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) {
934 /* 8139, let rl(4) take care of this device. */
940 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) {
941 if (vendor == t->rl_vid && devid == t->rl_did) {
942 device_set_desc(dev, t->rl_name);
943 return (BUS_PROBE_DEFAULT);
951 * Map a single buffer address.
955 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
962 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
964 *addr = segs->ds_addr;
968 re_allocmem(device_t dev, struct rl_softc *sc)
971 bus_size_t rx_list_size, tx_list_size;
975 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc);
976 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc);
979 * Allocate the parent bus DMA tag appropriate for PCI.
980 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD
981 * register should be set. However some RealTek chips are known
982 * to be buggy on DAC handling, therefore disable DAC by limiting
983 * DMA address space to 32bit. PCIe variants of RealTek chips
984 * may not have the limitation.
986 lowaddr = BUS_SPACE_MAXADDR;
987 if ((sc->rl_flags & RL_FLAG_PCIE) == 0)
988 lowaddr = BUS_SPACE_MAXADDR_32BIT;
989 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
990 lowaddr, BUS_SPACE_MAXADDR, NULL, NULL,
991 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
992 NULL, NULL, &sc->rl_parent_tag);
994 device_printf(dev, "could not allocate parent DMA tag\n");
999 * Allocate map for TX mbufs.
1001 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0,
1002 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
1003 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0,
1004 NULL, NULL, &sc->rl_ldata.rl_tx_mtag);
1006 device_printf(dev, "could not allocate TX DMA tag\n");
1011 * Allocate map for RX mbufs.
1014 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
1015 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t),
1016 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1017 MJUM9BYTES, 1, MJUM9BYTES, 0, NULL, NULL,
1018 &sc->rl_ldata.rl_jrx_mtag);
1021 "could not allocate jumbo RX DMA tag\n");
1025 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0,
1026 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1027 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag);
1029 device_printf(dev, "could not allocate RX DMA tag\n");
1034 * Allocate map for TX descriptor list.
1036 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
1037 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1038 NULL, tx_list_size, 1, tx_list_size, 0,
1039 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag);
1041 device_printf(dev, "could not allocate TX DMA ring tag\n");
1045 /* Allocate DMA'able memory for the TX ring */
1047 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag,
1048 (void **)&sc->rl_ldata.rl_tx_list,
1049 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
1050 &sc->rl_ldata.rl_tx_list_map);
1052 device_printf(dev, "could not allocate TX DMA ring\n");
1056 /* Load the map for the TX ring. */
1058 sc->rl_ldata.rl_tx_list_addr = 0;
1059 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag,
1060 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list,
1061 tx_list_size, re_dma_map_addr,
1062 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT);
1063 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) {
1064 device_printf(dev, "could not load TX DMA ring\n");
1068 /* Create DMA maps for TX buffers */
1070 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
1071 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0,
1072 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap);
1074 device_printf(dev, "could not create DMA map for TX\n");
1080 * Allocate map for RX descriptor list.
1082 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
1083 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1084 NULL, rx_list_size, 1, rx_list_size, 0,
1085 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag);
1087 device_printf(dev, "could not create RX DMA ring tag\n");
1091 /* Allocate DMA'able memory for the RX ring */
1093 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag,
1094 (void **)&sc->rl_ldata.rl_rx_list,
1095 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
1096 &sc->rl_ldata.rl_rx_list_map);
1098 device_printf(dev, "could not allocate RX DMA ring\n");
1102 /* Load the map for the RX ring. */
1104 sc->rl_ldata.rl_rx_list_addr = 0;
1105 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag,
1106 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list,
1107 rx_list_size, re_dma_map_addr,
1108 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT);
1109 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) {
1110 device_printf(dev, "could not load RX DMA ring\n");
1114 /* Create DMA maps for RX buffers */
1116 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
1117 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0,
1118 &sc->rl_ldata.rl_jrx_sparemap);
1121 "could not create spare DMA map for jumbo RX\n");
1124 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
1125 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0,
1126 &sc->rl_ldata.rl_jrx_desc[i].rx_dmamap);
1129 "could not create DMA map for jumbo RX\n");
1134 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0,
1135 &sc->rl_ldata.rl_rx_sparemap);
1137 device_printf(dev, "could not create spare DMA map for RX\n");
1140 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
1141 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0,
1142 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap);
1144 device_printf(dev, "could not create DMA map for RX\n");
1149 /* Create DMA map for statistics. */
1150 error = bus_dma_tag_create(sc->rl_parent_tag, RL_DUMP_ALIGN, 0,
1151 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1152 sizeof(struct rl_stats), 1, sizeof(struct rl_stats), 0, NULL, NULL,
1153 &sc->rl_ldata.rl_stag);
1155 device_printf(dev, "could not create statistics DMA tag\n");
1158 /* Allocate DMA'able memory for statistics. */
1159 error = bus_dmamem_alloc(sc->rl_ldata.rl_stag,
1160 (void **)&sc->rl_ldata.rl_stats,
1161 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
1162 &sc->rl_ldata.rl_smap);
1165 "could not allocate statistics DMA memory\n");
1168 /* Load the map for statistics. */
1169 sc->rl_ldata.rl_stats_addr = 0;
1170 error = bus_dmamap_load(sc->rl_ldata.rl_stag, sc->rl_ldata.rl_smap,
1171 sc->rl_ldata.rl_stats, sizeof(struct rl_stats), re_dma_map_addr,
1172 &sc->rl_ldata.rl_stats_addr, BUS_DMA_NOWAIT);
1173 if (error != 0 || sc->rl_ldata.rl_stats_addr == 0) {
1174 device_printf(dev, "could not load statistics DMA memory\n");
1182 * Attach the interface. Allocate softc structures, do ifmedia
1183 * setup and ethernet/BPF attach.
1186 re_attach(device_t dev)
1188 u_char eaddr[ETHER_ADDR_LEN];
1189 u_int16_t as[ETHER_ADDR_LEN / 2];
1190 struct rl_softc *sc;
1192 const struct rl_hwrev *hw_rev;
1195 u_int16_t devid, re_did = 0;
1196 int error = 0, i, phy, rid;
1197 int msic, msixc, reg;
1200 sc = device_get_softc(dev);
1203 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1205 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
1208 * Map control/status registers.
1210 pci_enable_busmaster(dev);
1212 devid = pci_get_device(dev);
1214 * Prefer memory space register mapping over IO space.
1215 * Because RTL8169SC does not seem to work when memory mapping
1216 * is used always activate io mapping.
1218 if (devid == RT_DEVICEID_8169SC)
1220 if (prefer_iomap == 0) {
1221 sc->rl_res_id = PCIR_BAR(1);
1222 sc->rl_res_type = SYS_RES_MEMORY;
1223 /* RTL8168/8101E seems to use different BARs. */
1224 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E)
1225 sc->rl_res_id = PCIR_BAR(2);
1227 sc->rl_res_id = PCIR_BAR(0);
1228 sc->rl_res_type = SYS_RES_IOPORT;
1230 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
1231 &sc->rl_res_id, RF_ACTIVE);
1232 if (sc->rl_res == NULL && prefer_iomap == 0) {
1233 sc->rl_res_id = PCIR_BAR(0);
1234 sc->rl_res_type = SYS_RES_IOPORT;
1235 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
1236 &sc->rl_res_id, RF_ACTIVE);
1238 if (sc->rl_res == NULL) {
1239 device_printf(dev, "couldn't map ports/memory\n");
1244 sc->rl_btag = rman_get_bustag(sc->rl_res);
1245 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
1247 msic = pci_msi_count(dev);
1248 msixc = pci_msix_count(dev);
1249 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) {
1250 sc->rl_flags |= RL_FLAG_PCIE;
1251 sc->rl_expcap = reg;
1254 device_printf(dev, "MSI count : %d\n", msic);
1255 device_printf(dev, "MSI-X count : %d\n", msixc);
1257 if (msix_disable > 0)
1259 if (msi_disable > 0)
1261 /* Prefer MSI-X to MSI. */
1265 sc->rl_res_pba = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1267 if (sc->rl_res_pba == NULL) {
1268 device_printf(sc->rl_dev,
1269 "could not allocate MSI-X PBA resource\n");
1271 if (sc->rl_res_pba != NULL &&
1272 pci_alloc_msix(dev, &msixc) == 0) {
1274 device_printf(dev, "Using %d MSI-X message\n",
1276 sc->rl_flags |= RL_FLAG_MSIX;
1278 pci_release_msi(dev);
1280 if ((sc->rl_flags & RL_FLAG_MSIX) == 0) {
1281 if (sc->rl_res_pba != NULL)
1282 bus_release_resource(dev, SYS_RES_MEMORY, rid,
1284 sc->rl_res_pba = NULL;
1288 /* Prefer MSI to INTx. */
1289 if (msixc == 0 && msic > 0) {
1291 if (pci_alloc_msi(dev, &msic) == 0) {
1292 if (msic == RL_MSI_MESSAGES) {
1293 device_printf(dev, "Using %d MSI message\n",
1295 sc->rl_flags |= RL_FLAG_MSI;
1296 /* Explicitly set MSI enable bit. */
1297 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
1298 cfg = CSR_READ_1(sc, RL_CFG2);
1300 CSR_WRITE_1(sc, RL_CFG2, cfg);
1301 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1303 pci_release_msi(dev);
1305 if ((sc->rl_flags & RL_FLAG_MSI) == 0)
1309 /* Allocate interrupt */
1310 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) {
1312 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1313 RF_SHAREABLE | RF_ACTIVE);
1314 if (sc->rl_irq[0] == NULL) {
1315 device_printf(dev, "couldn't allocate IRQ resources\n");
1320 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) {
1321 sc->rl_irq[i] = bus_alloc_resource_any(dev,
1322 SYS_RES_IRQ, &rid, RF_ACTIVE);
1323 if (sc->rl_irq[i] == NULL) {
1325 "couldn't allocate IRQ resources for "
1326 "message %d\n", rid);
1333 if ((sc->rl_flags & RL_FLAG_MSI) == 0) {
1334 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
1335 cfg = CSR_READ_1(sc, RL_CFG2);
1336 if ((cfg & RL_CFG2_MSI) != 0) {
1337 device_printf(dev, "turning off MSI enable bit.\n");
1338 cfg &= ~RL_CFG2_MSI;
1339 CSR_WRITE_1(sc, RL_CFG2, cfg);
1341 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1344 /* Disable ASPM L0S/L1. */
1345 if (sc->rl_expcap != 0) {
1346 cap = pci_read_config(dev, sc->rl_expcap +
1348 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) {
1349 ctl = pci_read_config(dev, sc->rl_expcap +
1351 if ((ctl & PCIEM_LINK_CTL_ASPMC) != 0) {
1352 ctl &= ~PCIEM_LINK_CTL_ASPMC;
1353 pci_write_config(dev, sc->rl_expcap +
1354 PCIER_LINK_CTL, ctl, 2);
1355 device_printf(dev, "ASPM disabled\n");
1358 device_printf(dev, "no ASPM capability\n");
1362 hwrev = CSR_READ_4(sc, RL_TXCFG);
1363 switch (hwrev & 0x70000000) {
1366 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000);
1367 hwrev &= (RL_TXCFG_HWREV | 0x80000000);
1370 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000);
1371 sc->rl_macrev = hwrev & 0x00700000;
1372 hwrev &= RL_TXCFG_HWREV;
1375 device_printf(dev, "MAC rev. 0x%08x\n", sc->rl_macrev);
1376 while (hw_rev->rl_desc != NULL) {
1377 if (hw_rev->rl_rev == hwrev) {
1378 sc->rl_type = hw_rev->rl_type;
1379 sc->rl_hwrev = hw_rev;
1384 if (hw_rev->rl_desc == NULL) {
1385 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev);
1390 switch (hw_rev->rl_rev) {
1391 case RL_HWREV_8139CPLUS:
1392 sc->rl_flags |= RL_FLAG_FASTETHER | RL_FLAG_AUTOPAD;
1394 case RL_HWREV_8100E:
1395 case RL_HWREV_8101E:
1396 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_FASTETHER;
1398 case RL_HWREV_8102E:
1399 case RL_HWREV_8102EL:
1400 case RL_HWREV_8102EL_SPIN1:
1401 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 |
1402 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP |
1405 case RL_HWREV_8103E:
1406 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 |
1407 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP |
1408 RL_FLAG_AUTOPAD | RL_FLAG_MACSLEEP;
1410 case RL_HWREV_8401E:
1411 case RL_HWREV_8105E:
1412 case RL_HWREV_8105E_SPIN1:
1413 case RL_HWREV_8106E:
1414 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
1415 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
1416 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD;
1419 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
1420 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
1421 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD |
1422 RL_FLAG_CMDSTOP_WAIT_TXQ;
1424 case RL_HWREV_8168B_SPIN1:
1425 case RL_HWREV_8168B_SPIN2:
1426 sc->rl_flags |= RL_FLAG_WOLRXENB;
1428 case RL_HWREV_8168B_SPIN3:
1429 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT;
1431 case RL_HWREV_8168C_SPIN2:
1432 sc->rl_flags |= RL_FLAG_MACSLEEP;
1434 case RL_HWREV_8168C:
1435 if (sc->rl_macrev == 0x00200000)
1436 sc->rl_flags |= RL_FLAG_MACSLEEP;
1438 case RL_HWREV_8168CP:
1439 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
1440 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP |
1441 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK;
1443 case RL_HWREV_8168D:
1444 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
1445 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
1446 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 |
1447 RL_FLAG_WOL_MANLINK;
1449 case RL_HWREV_8168DP:
1450 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
1451 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_AUTOPAD |
1452 RL_FLAG_JUMBOV2 | RL_FLAG_WAIT_TXPOLL | RL_FLAG_WOL_MANLINK;
1454 case RL_HWREV_8168E:
1455 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
1456 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
1457 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 |
1458 RL_FLAG_WOL_MANLINK;
1460 case RL_HWREV_8168E_VL:
1461 case RL_HWREV_8168F:
1463 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
1464 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP |
1465 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 |
1466 RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK;
1468 case RL_HWREV_8169_8110SB:
1469 case RL_HWREV_8169_8110SBL:
1470 case RL_HWREV_8169_8110SC:
1471 case RL_HWREV_8169_8110SCE:
1472 sc->rl_flags |= RL_FLAG_PHYWAKE;
1475 case RL_HWREV_8169S:
1476 case RL_HWREV_8110S:
1477 sc->rl_flags |= RL_FLAG_MACRESET;
1483 if (sc->rl_hwrev->rl_rev == RL_HWREV_8139CPLUS) {
1484 sc->rl_cfg0 = RL_8139_CFG0;
1485 sc->rl_cfg1 = RL_8139_CFG1;
1487 sc->rl_cfg3 = RL_8139_CFG3;
1488 sc->rl_cfg4 = RL_8139_CFG4;
1489 sc->rl_cfg5 = RL_8139_CFG5;
1491 sc->rl_cfg0 = RL_CFG0;
1492 sc->rl_cfg1 = RL_CFG1;
1493 sc->rl_cfg2 = RL_CFG2;
1494 sc->rl_cfg3 = RL_CFG3;
1495 sc->rl_cfg4 = RL_CFG4;
1496 sc->rl_cfg5 = RL_CFG5;
1499 /* Reset the adapter. */
1505 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
1506 cfg = CSR_READ_1(sc, sc->rl_cfg1);
1508 CSR_WRITE_1(sc, sc->rl_cfg1, cfg);
1509 cfg = CSR_READ_1(sc, sc->rl_cfg5);
1510 cfg &= RL_CFG5_PME_STS;
1511 CSR_WRITE_1(sc, sc->rl_cfg5, cfg);
1512 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1514 if ((sc->rl_flags & RL_FLAG_PAR) != 0) {
1516 * XXX Should have a better way to extract station
1517 * address from EEPROM.
1519 for (i = 0; i < ETHER_ADDR_LEN; i++)
1520 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i);
1522 sc->rl_eewidth = RL_9356_ADDR_LEN;
1523 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1);
1524 if (re_did != 0x8129)
1525 sc->rl_eewidth = RL_9346_ADDR_LEN;
1528 * Get station address from the EEPROM.
1530 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3);
1531 for (i = 0; i < ETHER_ADDR_LEN / 2; i++)
1532 as[i] = le16toh(as[i]);
1533 bcopy(as, eaddr, ETHER_ADDR_LEN);
1536 if (sc->rl_type == RL_8169) {
1537 /* Set RX length mask and number of descriptors. */
1538 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN;
1539 sc->rl_txstart = RL_GTXSTART;
1540 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT;
1541 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT;
1543 /* Set RX length mask and number of descriptors. */
1544 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN;
1545 sc->rl_txstart = RL_TXSTART;
1546 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT;
1547 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT;
1550 error = re_allocmem(dev, sc);
1555 ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
1557 device_printf(dev, "can not if_alloc()\n");
1562 /* Take controller out of deep sleep mode. */
1563 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) {
1564 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)
1565 CSR_WRITE_1(sc, RL_GPIO,
1566 CSR_READ_1(sc, RL_GPIO) | 0x01);
1568 CSR_WRITE_1(sc, RL_GPIO,
1569 CSR_READ_1(sc, RL_GPIO) & ~0x01);
1572 /* Take PHY out of power down mode. */
1573 if ((sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) {
1574 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80);
1575 if (hw_rev->rl_rev == RL_HWREV_8401E)
1576 CSR_WRITE_1(sc, 0xD1, CSR_READ_1(sc, 0xD1) & ~0x08);
1578 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) {
1579 re_gmii_writereg(dev, 1, 0x1f, 0);
1580 re_gmii_writereg(dev, 1, 0x0e, 0);
1584 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1585 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1586 ifp->if_ioctl = re_ioctl;
1587 ifp->if_start = re_start;
1589 * RTL8168/8111C generates wrong IP checksummed frame if the
1590 * packet has IP options so disable TX IP checksum offloading.
1592 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168C ||
1593 sc->rl_hwrev->rl_rev == RL_HWREV_8168C_SPIN2 ||
1594 sc->rl_hwrev->rl_rev == RL_HWREV_8168CP)
1595 ifp->if_hwassist = CSUM_TCP | CSUM_UDP;
1597 ifp->if_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP;
1598 ifp->if_hwassist |= CSUM_TSO;
1599 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4;
1600 ifp->if_capenable = ifp->if_capabilities;
1601 ifp->if_init = re_init;
1602 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN);
1603 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN;
1604 IFQ_SET_READY(&ifp->if_snd);
1606 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc);
1608 #define RE_PHYAD_INTERNAL 0
1611 phy = RE_PHYAD_INTERNAL;
1612 if (sc->rl_type == RL_8169)
1614 error = mii_attach(dev, &sc->rl_miibus, ifp, re_ifmedia_upd,
1615 re_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, MIIF_DOPAUSE);
1617 device_printf(dev, "attaching PHYs failed\n");
1622 * Call MI attach routine.
1624 ether_ifattach(ifp, eaddr);
1626 /* VLAN capability setup */
1627 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
1628 if (ifp->if_capabilities & IFCAP_HWCSUM)
1629 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
1630 /* Enable WOL if PM is supported. */
1631 if (pci_find_cap(sc->rl_dev, PCIY_PMG, ®) == 0)
1632 ifp->if_capabilities |= IFCAP_WOL;
1633 ifp->if_capenable = ifp->if_capabilities;
1634 ifp->if_capenable &= ~(IFCAP_WOL_UCAST | IFCAP_WOL_MCAST);
1636 * Don't enable TSO by default. It is known to generate
1637 * corrupted TCP segments(bad TCP options) under certain
1640 ifp->if_hwassist &= ~CSUM_TSO;
1641 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO);
1642 #ifdef DEVICE_POLLING
1643 ifp->if_capabilities |= IFCAP_POLLING;
1646 * Tell the upper layer(s) we support long frames.
1647 * Must appear after the call to ether_ifattach() because
1648 * ether_ifattach() sets ifi_hdrlen to the default value.
1650 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1653 re_netmap_attach(sc);
1654 #endif /* DEV_NETMAP */
1657 * Perform hardware diagnostic on the original RTL8169.
1658 * Some 32-bit cards were incorrectly wired and would
1659 * malfunction if plugged into a 64-bit slot.
1662 if (hwrev == RL_HWREV_8169) {
1663 error = re_diag(sc);
1666 "attach aborted due to hardware diag failure\n");
1667 ether_ifdetach(ifp);
1673 #ifdef RE_TX_MODERATION
1676 /* Hook interrupt last to avoid having to lock softc */
1677 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 &&
1679 error = bus_setup_intr(dev, sc->rl_irq[0],
1680 INTR_TYPE_NET | INTR_MPSAFE, NULL, re_intr_msi, sc,
1681 &sc->rl_intrhand[0]);
1683 error = bus_setup_intr(dev, sc->rl_irq[0],
1684 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc,
1685 &sc->rl_intrhand[0]);
1688 device_printf(dev, "couldn't set up irq\n");
1689 ether_ifdetach(ifp);
1701 * Shutdown hardware and free up resources. This can be called any
1702 * time after the mutex has been initialized. It is called in both
1703 * the error case in attach and the normal detach case so it needs
1704 * to be careful about only freeing resources that have actually been
1708 re_detach(device_t dev)
1710 struct rl_softc *sc;
1714 sc = device_get_softc(dev);
1716 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized"));
1718 /* These should only be active if attach succeeded */
1719 if (device_is_attached(dev)) {
1720 #ifdef DEVICE_POLLING
1721 if (ifp->if_capenable & IFCAP_POLLING)
1722 ether_poll_deregister(ifp);
1730 callout_drain(&sc->rl_stat_callout);
1731 taskqueue_drain(taskqueue_fast, &sc->rl_inttask);
1733 * Force off the IFF_UP flag here, in case someone
1734 * still had a BPF descriptor attached to this
1735 * interface. If they do, ether_ifdetach() will cause
1736 * the BPF code to try and clear the promisc mode
1737 * flag, which will bubble down to re_ioctl(),
1738 * which will try to call re_init() again. This will
1739 * turn the NIC back on and restart the MII ticker,
1740 * which will panic the system when the kernel tries
1741 * to invoke the re_tick() function that isn't there
1744 ifp->if_flags &= ~IFF_UP;
1745 ether_ifdetach(ifp);
1748 device_delete_child(dev, sc->rl_miibus);
1749 bus_generic_detach(dev);
1752 * The rest is resource deallocation, so we should already be
1756 if (sc->rl_intrhand[0] != NULL) {
1757 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]);
1758 sc->rl_intrhand[0] = NULL;
1763 #endif /* DEV_NETMAP */
1766 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0)
1770 if (sc->rl_irq[0] != NULL) {
1771 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->rl_irq[0]);
1772 sc->rl_irq[0] = NULL;
1774 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0)
1775 pci_release_msi(dev);
1776 if (sc->rl_res_pba) {
1778 bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->rl_res_pba);
1781 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id,
1784 /* Unload and free the RX DMA ring memory and map */
1786 if (sc->rl_ldata.rl_rx_list_tag) {
1787 if (sc->rl_ldata.rl_rx_list_map)
1788 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag,
1789 sc->rl_ldata.rl_rx_list_map);
1790 if (sc->rl_ldata.rl_rx_list_map && sc->rl_ldata.rl_rx_list)
1791 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag,
1792 sc->rl_ldata.rl_rx_list,
1793 sc->rl_ldata.rl_rx_list_map);
1794 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag);
1797 /* Unload and free the TX DMA ring memory and map */
1799 if (sc->rl_ldata.rl_tx_list_tag) {
1800 if (sc->rl_ldata.rl_tx_list_map)
1801 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag,
1802 sc->rl_ldata.rl_tx_list_map);
1803 if (sc->rl_ldata.rl_tx_list_map && sc->rl_ldata.rl_tx_list)
1804 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag,
1805 sc->rl_ldata.rl_tx_list,
1806 sc->rl_ldata.rl_tx_list_map);
1807 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag);
1810 /* Destroy all the RX and TX buffer maps */
1812 if (sc->rl_ldata.rl_tx_mtag) {
1813 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
1814 if (sc->rl_ldata.rl_tx_desc[i].tx_dmamap)
1815 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag,
1816 sc->rl_ldata.rl_tx_desc[i].tx_dmamap);
1818 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag);
1820 if (sc->rl_ldata.rl_rx_mtag) {
1821 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
1822 if (sc->rl_ldata.rl_rx_desc[i].rx_dmamap)
1823 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag,
1824 sc->rl_ldata.rl_rx_desc[i].rx_dmamap);
1826 if (sc->rl_ldata.rl_rx_sparemap)
1827 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag,
1828 sc->rl_ldata.rl_rx_sparemap);
1829 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag);
1831 if (sc->rl_ldata.rl_jrx_mtag) {
1832 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
1833 if (sc->rl_ldata.rl_jrx_desc[i].rx_dmamap)
1834 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag,
1835 sc->rl_ldata.rl_jrx_desc[i].rx_dmamap);
1837 if (sc->rl_ldata.rl_jrx_sparemap)
1838 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag,
1839 sc->rl_ldata.rl_jrx_sparemap);
1840 bus_dma_tag_destroy(sc->rl_ldata.rl_jrx_mtag);
1842 /* Unload and free the stats buffer and map */
1844 if (sc->rl_ldata.rl_stag) {
1845 if (sc->rl_ldata.rl_smap)
1846 bus_dmamap_unload(sc->rl_ldata.rl_stag,
1847 sc->rl_ldata.rl_smap);
1848 if (sc->rl_ldata.rl_smap && sc->rl_ldata.rl_stats)
1849 bus_dmamem_free(sc->rl_ldata.rl_stag,
1850 sc->rl_ldata.rl_stats, sc->rl_ldata.rl_smap);
1851 bus_dma_tag_destroy(sc->rl_ldata.rl_stag);
1854 if (sc->rl_parent_tag)
1855 bus_dma_tag_destroy(sc->rl_parent_tag);
1857 mtx_destroy(&sc->rl_mtx);
1862 static __inline void
1863 re_discard_rxbuf(struct rl_softc *sc, int idx)
1865 struct rl_desc *desc;
1866 struct rl_rxdesc *rxd;
1869 if (sc->rl_ifp->if_mtu > RL_MTU &&
1870 (sc->rl_flags & RL_FLAG_JUMBOV2) != 0)
1871 rxd = &sc->rl_ldata.rl_jrx_desc[idx];
1873 rxd = &sc->rl_ldata.rl_rx_desc[idx];
1874 desc = &sc->rl_ldata.rl_rx_list[idx];
1875 desc->rl_vlanctl = 0;
1876 cmdstat = rxd->rx_size;
1877 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1)
1878 cmdstat |= RL_RDESC_CMD_EOR;
1879 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN);
1883 re_newbuf(struct rl_softc *sc, int idx)
1886 struct rl_rxdesc *rxd;
1887 bus_dma_segment_t segs[1];
1889 struct rl_desc *desc;
1893 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1897 m->m_len = m->m_pkthdr.len = MCLBYTES;
1900 * This is part of an evil trick to deal with non-x86 platforms.
1901 * The RealTek chip requires RX buffers to be aligned on 64-bit
1902 * boundaries, but that will hose non-x86 machines. To get around
1903 * this, we leave some empty space at the start of each buffer
1904 * and for non-x86 hosts, we copy the buffer back six bytes
1905 * to achieve word alignment. This is slightly more efficient
1906 * than allocating a new buffer, copying the contents, and
1907 * discarding the old buffer.
1909 m_adj(m, RE_ETHER_ALIGN);
1911 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag,
1912 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT);
1917 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs));
1919 rxd = &sc->rl_ldata.rl_rx_desc[idx];
1920 if (rxd->rx_m != NULL) {
1921 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap,
1922 BUS_DMASYNC_POSTREAD);
1923 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap);
1927 map = rxd->rx_dmamap;
1928 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap;
1929 rxd->rx_size = segs[0].ds_len;
1930 sc->rl_ldata.rl_rx_sparemap = map;
1931 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap,
1932 BUS_DMASYNC_PREREAD);
1934 desc = &sc->rl_ldata.rl_rx_list[idx];
1935 desc->rl_vlanctl = 0;
1936 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr));
1937 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr));
1938 cmdstat = segs[0].ds_len;
1939 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1)
1940 cmdstat |= RL_RDESC_CMD_EOR;
1941 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN);
1947 re_jumbo_newbuf(struct rl_softc *sc, int idx)
1950 struct rl_rxdesc *rxd;
1951 bus_dma_segment_t segs[1];
1953 struct rl_desc *desc;
1957 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
1960 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1962 m_adj(m, RE_ETHER_ALIGN);
1964 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_jrx_mtag,
1965 sc->rl_ldata.rl_jrx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT);
1970 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs));
1972 rxd = &sc->rl_ldata.rl_jrx_desc[idx];
1973 if (rxd->rx_m != NULL) {
1974 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap,
1975 BUS_DMASYNC_POSTREAD);
1976 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap);
1980 map = rxd->rx_dmamap;
1981 rxd->rx_dmamap = sc->rl_ldata.rl_jrx_sparemap;
1982 rxd->rx_size = segs[0].ds_len;
1983 sc->rl_ldata.rl_jrx_sparemap = map;
1984 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap,
1985 BUS_DMASYNC_PREREAD);
1987 desc = &sc->rl_ldata.rl_rx_list[idx];
1988 desc->rl_vlanctl = 0;
1989 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr));
1990 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr));
1991 cmdstat = segs[0].ds_len;
1992 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1)
1993 cmdstat |= RL_RDESC_CMD_EOR;
1994 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN);
2000 static __inline void
2001 re_fixup_rx(struct mbuf *m)
2004 uint16_t *src, *dst;
2006 src = mtod(m, uint16_t *);
2007 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src;
2009 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
2012 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN;
2017 re_tx_list_init(struct rl_softc *sc)
2019 struct rl_desc *desc;
2024 bzero(sc->rl_ldata.rl_tx_list,
2025 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc));
2026 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++)
2027 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL;
2029 re_netmap_tx_init(sc);
2030 #endif /* DEV_NETMAP */
2032 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1];
2033 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR);
2035 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
2036 sc->rl_ldata.rl_tx_list_map,
2037 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2039 sc->rl_ldata.rl_tx_prodidx = 0;
2040 sc->rl_ldata.rl_tx_considx = 0;
2041 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt;
2047 re_rx_list_init(struct rl_softc *sc)
2051 bzero(sc->rl_ldata.rl_rx_list,
2052 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc));
2053 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
2054 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL;
2055 if ((error = re_newbuf(sc, i)) != 0)
2059 re_netmap_rx_init(sc);
2060 #endif /* DEV_NETMAP */
2062 /* Flush the RX descriptors */
2064 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
2065 sc->rl_ldata.rl_rx_list_map,
2066 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
2068 sc->rl_ldata.rl_rx_prodidx = 0;
2069 sc->rl_head = sc->rl_tail = NULL;
2070 sc->rl_int_rx_act = 0;
2076 re_jrx_list_init(struct rl_softc *sc)
2080 bzero(sc->rl_ldata.rl_rx_list,
2081 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc));
2082 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
2083 sc->rl_ldata.rl_jrx_desc[i].rx_m = NULL;
2084 if ((error = re_jumbo_newbuf(sc, i)) != 0)
2088 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
2089 sc->rl_ldata.rl_rx_list_map,
2090 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2092 sc->rl_ldata.rl_rx_prodidx = 0;
2093 sc->rl_head = sc->rl_tail = NULL;
2094 sc->rl_int_rx_act = 0;
2100 * RX handler for C+ and 8169. For the gigE chips, we support
2101 * the reception of jumbo frames that have been fragmented
2102 * across multiple 2K mbuf cluster buffers.
2105 re_rxeof(struct rl_softc *sc, int *rx_npktsp)
2109 int i, rxerr, total_len;
2110 struct rl_desc *cur_rx;
2111 u_int32_t rxstat, rxvlan;
2112 int jumbo, maxpkt = 16, rx_npkts = 0;
2118 if (netmap_rx_irq(ifp, 0 | (NETMAP_LOCKED_ENTER|NETMAP_LOCKED_EXIT),
2121 #endif /* DEV_NETMAP */
2122 if (ifp->if_mtu > RL_MTU && (sc->rl_flags & RL_FLAG_JUMBOV2) != 0)
2127 /* Invalidate the descriptor memory */
2129 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
2130 sc->rl_ldata.rl_rx_list_map,
2131 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2133 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0;
2134 i = RL_RX_DESC_NXT(sc, i)) {
2135 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
2137 cur_rx = &sc->rl_ldata.rl_rx_list[i];
2138 rxstat = le32toh(cur_rx->rl_cmdstat);
2139 if ((rxstat & RL_RDESC_STAT_OWN) != 0)
2141 total_len = rxstat & sc->rl_rxlenmask;
2142 rxvlan = le32toh(cur_rx->rl_vlanctl);
2144 m = sc->rl_ldata.rl_jrx_desc[i].rx_m;
2146 m = sc->rl_ldata.rl_rx_desc[i].rx_m;
2148 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 &&
2149 (rxstat & (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) !=
2150 (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) {
2152 * RTL8168C or later controllers do not
2153 * support multi-fragment packet.
2155 re_discard_rxbuf(sc, i);
2157 } else if ((rxstat & RL_RDESC_STAT_EOF) == 0) {
2158 if (re_newbuf(sc, i) != 0) {
2160 * If this is part of a multi-fragment packet,
2161 * discard all the pieces.
2163 if (sc->rl_head != NULL) {
2164 m_freem(sc->rl_head);
2165 sc->rl_head = sc->rl_tail = NULL;
2167 re_discard_rxbuf(sc, i);
2170 m->m_len = RE_RX_DESC_BUFLEN;
2171 if (sc->rl_head == NULL)
2172 sc->rl_head = sc->rl_tail = m;
2174 m->m_flags &= ~M_PKTHDR;
2175 sc->rl_tail->m_next = m;
2182 * NOTE: for the 8139C+, the frame length field
2183 * is always 12 bits in size, but for the gigE chips,
2184 * it is 13 bits (since the max RX frame length is 16K).
2185 * Unfortunately, all 32 bits in the status word
2186 * were already used, so to make room for the extra
2187 * length bit, RealTek took out the 'frame alignment
2188 * error' bit and shifted the other status bits
2189 * over one slot. The OWN, EOR, FS and LS bits are
2190 * still in the same places. We have already extracted
2191 * the frame length and checked the OWN bit, so rather
2192 * than using an alternate bit mapping, we shift the
2193 * status bits one space to the right so we can evaluate
2194 * them using the 8169 status as though it was in the
2195 * same format as that of the 8139C+.
2197 if (sc->rl_type == RL_8169)
2201 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be
2202 * set, but if CRC is clear, it will still be a valid frame.
2204 if ((rxstat & RL_RDESC_STAT_RXERRSUM) != 0) {
2206 if ((sc->rl_flags & RL_FLAG_JUMBOV2) == 0 &&
2208 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)
2213 * If this is part of a multi-fragment packet,
2214 * discard all the pieces.
2216 if (sc->rl_head != NULL) {
2217 m_freem(sc->rl_head);
2218 sc->rl_head = sc->rl_tail = NULL;
2220 re_discard_rxbuf(sc, i);
2226 * If allocating a replacement mbuf fails,
2227 * reload the current one.
2230 rxerr = re_jumbo_newbuf(sc, i);
2232 rxerr = re_newbuf(sc, i);
2235 if (sc->rl_head != NULL) {
2236 m_freem(sc->rl_head);
2237 sc->rl_head = sc->rl_tail = NULL;
2239 re_discard_rxbuf(sc, i);
2243 if (sc->rl_head != NULL) {
2245 m->m_len = total_len;
2247 m->m_len = total_len % RE_RX_DESC_BUFLEN;
2249 m->m_len = RE_RX_DESC_BUFLEN;
2252 * Special case: if there's 4 bytes or less
2253 * in this buffer, the mbuf can be discarded:
2254 * the last 4 bytes is the CRC, which we don't
2255 * care about anyway.
2257 if (m->m_len <= ETHER_CRC_LEN) {
2258 sc->rl_tail->m_len -=
2259 (ETHER_CRC_LEN - m->m_len);
2262 m->m_len -= ETHER_CRC_LEN;
2263 m->m_flags &= ~M_PKTHDR;
2264 sc->rl_tail->m_next = m;
2267 sc->rl_head = sc->rl_tail = NULL;
2268 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
2270 m->m_pkthdr.len = m->m_len =
2271 (total_len - ETHER_CRC_LEN);
2277 m->m_pkthdr.rcvif = ifp;
2279 /* Do RX checksumming if enabled */
2281 if (ifp->if_capenable & IFCAP_RXCSUM) {
2282 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) {
2283 /* Check IP header checksum */
2284 if (rxstat & RL_RDESC_STAT_PROTOID)
2285 m->m_pkthdr.csum_flags |=
2287 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD))
2288 m->m_pkthdr.csum_flags |=
2291 /* Check TCP/UDP checksum */
2292 if ((RL_TCPPKT(rxstat) &&
2293 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) ||
2294 (RL_UDPPKT(rxstat) &&
2295 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) {
2296 m->m_pkthdr.csum_flags |=
2297 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
2298 m->m_pkthdr.csum_data = 0xffff;
2302 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP
2304 if ((rxstat & RL_RDESC_STAT_PROTOID) &&
2305 (rxvlan & RL_RDESC_IPV4))
2306 m->m_pkthdr.csum_flags |=
2308 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) &&
2309 (rxvlan & RL_RDESC_IPV4))
2310 m->m_pkthdr.csum_flags |=
2312 if (((rxstat & RL_RDESC_STAT_TCP) &&
2313 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) ||
2314 ((rxstat & RL_RDESC_STAT_UDP) &&
2315 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) {
2316 m->m_pkthdr.csum_flags |=
2317 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
2318 m->m_pkthdr.csum_data = 0xffff;
2323 if (rxvlan & RL_RDESC_VLANCTL_TAG) {
2324 m->m_pkthdr.ether_vtag =
2325 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA));
2326 m->m_flags |= M_VLANTAG;
2329 (*ifp->if_input)(ifp, m);
2334 /* Flush the RX DMA ring */
2336 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
2337 sc->rl_ldata.rl_rx_list_map,
2338 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
2340 sc->rl_ldata.rl_rx_prodidx = i;
2342 if (rx_npktsp != NULL)
2343 *rx_npktsp = rx_npkts;
2351 re_txeof(struct rl_softc *sc)
2354 struct rl_txdesc *txd;
2358 cons = sc->rl_ldata.rl_tx_considx;
2359 if (cons == sc->rl_ldata.rl_tx_prodidx)
2364 if (netmap_tx_irq(ifp, 0 | (NETMAP_LOCKED_ENTER|NETMAP_LOCKED_EXIT)))
2366 #endif /* DEV_NETMAP */
2367 /* Invalidate the TX descriptor list */
2368 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
2369 sc->rl_ldata.rl_tx_list_map,
2370 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2372 for (; cons != sc->rl_ldata.rl_tx_prodidx;
2373 cons = RL_TX_DESC_NXT(sc, cons)) {
2374 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat);
2375 if (txstat & RL_TDESC_STAT_OWN)
2378 * We only stash mbufs in the last descriptor
2379 * in a fragment chain, which also happens to
2380 * be the only place where the TX status bits
2383 if (txstat & RL_TDESC_CMD_EOF) {
2384 txd = &sc->rl_ldata.rl_tx_desc[cons];
2385 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag,
2386 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2387 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag,
2389 KASSERT(txd->tx_m != NULL,
2390 ("%s: freeing NULL mbufs!", __func__));
2393 if (txstat & (RL_TDESC_STAT_EXCESSCOL|
2394 RL_TDESC_STAT_COLCNT))
2395 ifp->if_collisions++;
2396 if (txstat & RL_TDESC_STAT_TXERRSUM)
2401 sc->rl_ldata.rl_tx_free++;
2402 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2404 sc->rl_ldata.rl_tx_considx = cons;
2406 /* No changes made to the TX ring, so no flush needed */
2408 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) {
2409 #ifdef RE_TX_MODERATION
2411 * If not all descriptors have been reaped yet, reload
2412 * the timer so that we will eventually get another
2413 * interrupt that will cause us to re-enter this routine.
2414 * This is done in case the transmitter has gone idle.
2416 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2419 sc->rl_watchdog_timer = 0;
2425 struct rl_softc *sc;
2426 struct mii_data *mii;
2432 mii = device_get_softc(sc->rl_miibus);
2434 if ((sc->rl_flags & RL_FLAG_LINK) == 0)
2435 re_miibus_statchg(sc->rl_dev);
2437 * Reclaim transmitted frames here. Technically it is not
2438 * necessary to do here but it ensures periodic reclamation
2439 * regardless of Tx completion interrupt which seems to be
2440 * lost on PCIe based controllers under certain situations.
2444 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
2447 #ifdef DEVICE_POLLING
2449 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2451 struct rl_softc *sc = ifp->if_softc;
2455 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2456 rx_npkts = re_poll_locked(ifp, cmd, count);
2462 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
2464 struct rl_softc *sc = ifp->if_softc;
2469 sc->rxcycles = count;
2470 re_rxeof(sc, &rx_npkts);
2473 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2474 re_start_locked(ifp);
2476 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
2479 status = CSR_READ_2(sc, RL_ISR);
2480 if (status == 0xffff)
2483 CSR_WRITE_2(sc, RL_ISR, status);
2484 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) &&
2485 (sc->rl_flags & RL_FLAG_PCIE))
2486 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2489 * XXX check behaviour on receiver stalls.
2492 if (status & RL_ISR_SYSTEM_ERR) {
2493 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2499 #endif /* DEVICE_POLLING */
2504 struct rl_softc *sc;
2509 status = CSR_READ_2(sc, RL_ISR);
2510 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0)
2511 return (FILTER_STRAY);
2512 CSR_WRITE_2(sc, RL_IMR, 0);
2514 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask);
2516 return (FILTER_HANDLED);
2520 re_int_task(void *arg, int npending)
2522 struct rl_softc *sc;
2532 status = CSR_READ_2(sc, RL_ISR);
2533 CSR_WRITE_2(sc, RL_ISR, status);
2535 if (sc->suspended ||
2536 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2541 #ifdef DEVICE_POLLING
2542 if (ifp->if_capenable & IFCAP_POLLING) {
2548 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW))
2549 rval = re_rxeof(sc, NULL);
2552 * Some chips will ignore a second TX request issued
2553 * while an existing transmission is in progress. If
2554 * the transmitter goes idle but there are still
2555 * packets waiting to be sent, we need to restart the
2556 * channel here to flush them out. This only seems to
2557 * be required with the PCIe devices.
2559 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) &&
2560 (sc->rl_flags & RL_FLAG_PCIE))
2561 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2563 #ifdef RE_TX_MODERATION
2564 RL_ISR_TIMEOUT_EXPIRED|
2568 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL))
2571 if (status & RL_ISR_SYSTEM_ERR) {
2572 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2576 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2577 re_start_locked(ifp);
2581 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) {
2582 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask);
2586 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
2590 re_intr_msi(void *xsc)
2592 struct rl_softc *sc;
2594 uint16_t intrs, status;
2600 #ifdef DEVICE_POLLING
2601 if (ifp->if_capenable & IFCAP_POLLING) {
2606 /* Disable interrupts. */
2607 CSR_WRITE_2(sc, RL_IMR, 0);
2608 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2613 intrs = RL_INTRS_CPLUS;
2614 status = CSR_READ_2(sc, RL_ISR);
2615 CSR_WRITE_2(sc, RL_ISR, status);
2616 if (sc->rl_int_rx_act > 0) {
2617 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW |
2619 status &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW |
2623 if (status & (RL_ISR_TIMEOUT_EXPIRED | RL_ISR_RX_OK | RL_ISR_RX_ERR |
2624 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) {
2626 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2627 if (sc->rl_int_rx_mod != 0 &&
2628 (status & (RL_ISR_RX_OK | RL_ISR_RX_ERR |
2629 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) != 0) {
2630 /* Rearm one-shot timer. */
2631 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2632 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR |
2633 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN);
2634 sc->rl_int_rx_act = 1;
2636 intrs |= RL_ISR_RX_OK | RL_ISR_RX_ERR |
2637 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN;
2638 sc->rl_int_rx_act = 0;
2644 * Some chips will ignore a second TX request issued
2645 * while an existing transmission is in progress. If
2646 * the transmitter goes idle but there are still
2647 * packets waiting to be sent, we need to restart the
2648 * channel here to flush them out. This only seems to
2649 * be required with the PCIe devices.
2651 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) &&
2652 (sc->rl_flags & RL_FLAG_PCIE))
2653 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2654 if (status & (RL_ISR_TX_OK | RL_ISR_TX_ERR | RL_ISR_TX_DESC_UNAVAIL))
2657 if (status & RL_ISR_SYSTEM_ERR) {
2658 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2662 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2663 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2664 re_start_locked(ifp);
2665 CSR_WRITE_2(sc, RL_IMR, intrs);
2671 re_encap(struct rl_softc *sc, struct mbuf **m_head)
2673 struct rl_txdesc *txd, *txd_last;
2674 bus_dma_segment_t segs[RL_NTXSEGS];
2677 struct rl_desc *desc;
2679 int i, error, ei, si;
2681 uint32_t cmdstat, csum_flags, vlanctl;
2684 M_ASSERTPKTHDR((*m_head));
2687 * With some of the RealTek chips, using the checksum offload
2688 * support in conjunction with the autopadding feature results
2689 * in the transmission of corrupt frames. For example, if we
2690 * need to send a really small IP fragment that's less than 60
2691 * bytes in size, and IP header checksumming is enabled, the
2692 * resulting ethernet frame that appears on the wire will
2693 * have garbled payload. To work around this, if TX IP checksum
2694 * offload is enabled, we always manually pad short frames out
2695 * to the minimum ethernet frame size.
2697 if ((sc->rl_flags & RL_FLAG_AUTOPAD) == 0 &&
2698 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN &&
2699 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) {
2700 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len;
2701 if (M_WRITABLE(*m_head) == 0) {
2702 /* Get a writable copy. */
2703 m_new = m_dup(*m_head, M_NOWAIT);
2705 if (m_new == NULL) {
2711 if ((*m_head)->m_next != NULL ||
2712 M_TRAILINGSPACE(*m_head) < padlen) {
2713 m_new = m_defrag(*m_head, M_NOWAIT);
2714 if (m_new == NULL) {
2723 * Manually pad short frames, and zero the pad space
2724 * to avoid leaking data.
2726 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen);
2727 m_new->m_pkthdr.len += padlen;
2728 m_new->m_len = m_new->m_pkthdr.len;
2732 prod = sc->rl_ldata.rl_tx_prodidx;
2733 txd = &sc->rl_ldata.rl_tx_desc[prod];
2734 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap,
2735 *m_head, segs, &nsegs, BUS_DMA_NOWAIT);
2736 if (error == EFBIG) {
2737 m_new = m_collapse(*m_head, M_NOWAIT, RL_NTXSEGS);
2738 if (m_new == NULL) {
2744 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag,
2745 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT);
2751 } else if (error != 0)
2759 /* Check for number of available descriptors. */
2760 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) {
2761 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap);
2765 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap,
2766 BUS_DMASYNC_PREWRITE);
2769 * Set up checksum offload. Note: checksum offload bits must
2770 * appear in all descriptors of a multi-descriptor transmit
2771 * attempt. This is according to testing done with an 8169
2772 * chip. This is a requirement.
2776 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
2777 if ((sc->rl_flags & RL_FLAG_DESCV2) != 0) {
2778 csum_flags |= RL_TDESC_CMD_LGSEND;
2779 vlanctl |= ((uint32_t)(*m_head)->m_pkthdr.tso_segsz <<
2780 RL_TDESC_CMD_MSSVALV2_SHIFT);
2782 csum_flags |= RL_TDESC_CMD_LGSEND |
2783 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz <<
2784 RL_TDESC_CMD_MSSVAL_SHIFT);
2788 * Unconditionally enable IP checksum if TCP or UDP
2789 * checksum is required. Otherwise, TCP/UDP checksum
2790 * doesn't make effects.
2792 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) {
2793 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) {
2794 csum_flags |= RL_TDESC_CMD_IPCSUM;
2795 if (((*m_head)->m_pkthdr.csum_flags &
2797 csum_flags |= RL_TDESC_CMD_TCPCSUM;
2798 if (((*m_head)->m_pkthdr.csum_flags &
2800 csum_flags |= RL_TDESC_CMD_UDPCSUM;
2802 vlanctl |= RL_TDESC_CMD_IPCSUMV2;
2803 if (((*m_head)->m_pkthdr.csum_flags &
2805 vlanctl |= RL_TDESC_CMD_TCPCSUMV2;
2806 if (((*m_head)->m_pkthdr.csum_flags &
2808 vlanctl |= RL_TDESC_CMD_UDPCSUMV2;
2814 * Set up hardware VLAN tagging. Note: vlan tag info must
2815 * appear in all descriptors of a multi-descriptor
2816 * transmission attempt.
2818 if ((*m_head)->m_flags & M_VLANTAG)
2819 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) |
2820 RL_TDESC_VLANCTL_TAG;
2823 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) {
2824 desc = &sc->rl_ldata.rl_tx_list[prod];
2825 desc->rl_vlanctl = htole32(vlanctl);
2826 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr));
2827 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr));
2828 cmdstat = segs[i].ds_len;
2830 cmdstat |= RL_TDESC_CMD_OWN;
2831 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1)
2832 cmdstat |= RL_TDESC_CMD_EOR;
2833 desc->rl_cmdstat = htole32(cmdstat | csum_flags);
2834 sc->rl_ldata.rl_tx_free--;
2836 /* Update producer index. */
2837 sc->rl_ldata.rl_tx_prodidx = prod;
2839 /* Set EOF on the last descriptor. */
2840 ei = RL_TX_DESC_PRV(sc, prod);
2841 desc = &sc->rl_ldata.rl_tx_list[ei];
2842 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF);
2844 desc = &sc->rl_ldata.rl_tx_list[si];
2845 /* Set SOF and transfer ownership of packet to the chip. */
2846 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF);
2849 * Insure that the map for this transmission
2850 * is placed at the array index of the last descriptor
2851 * in this chain. (Swap last and first dmamaps.)
2853 txd_last = &sc->rl_ldata.rl_tx_desc[ei];
2854 map = txd->tx_dmamap;
2855 txd->tx_dmamap = txd_last->tx_dmamap;
2856 txd_last->tx_dmamap = map;
2857 txd_last->tx_m = *m_head;
2863 re_start(struct ifnet *ifp)
2865 struct rl_softc *sc;
2869 re_start_locked(ifp);
2874 * Main transmit routine for C+ and gigE NICs.
2877 re_start_locked(struct ifnet *ifp)
2879 struct rl_softc *sc;
2880 struct mbuf *m_head;
2886 /* XXX is this necessary ? */
2887 if (ifp->if_capenable & IFCAP_NETMAP) {
2888 struct netmap_kring *kring = &NA(ifp)->tx_rings[0];
2889 if (sc->rl_ldata.rl_tx_prodidx != kring->nr_hwcur) {
2890 /* kick the tx unit */
2891 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2892 #ifdef RE_TX_MODERATION
2893 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2895 sc->rl_watchdog_timer = 5;
2899 #endif /* DEV_NETMAP */
2900 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2901 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0)
2904 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2905 sc->rl_ldata.rl_tx_free > 1;) {
2906 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2910 if (re_encap(sc, &m_head) != 0) {
2913 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2914 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2919 * If there's a BPF listener, bounce a copy of this frame
2922 ETHER_BPF_MTAP(ifp, m_head);
2928 #ifdef RE_TX_MODERATION
2929 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt)
2930 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2935 /* Flush the TX descriptors */
2937 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
2938 sc->rl_ldata.rl_tx_list_map,
2939 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
2941 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2943 #ifdef RE_TX_MODERATION
2945 * Use the countdown timer for interrupt moderation.
2946 * 'TX done' interrupts are disabled. Instead, we reset the
2947 * countdown timer, which will begin counting until it hits
2948 * the value in the TIMERINT register, and then trigger an
2949 * interrupt. Each time we write to the TIMERCNT register,
2950 * the timer count is reset to 0.
2952 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2956 * Set a timeout in case the chip goes out to lunch.
2958 sc->rl_watchdog_timer = 5;
2962 re_set_jumbo(struct rl_softc *sc, int jumbo)
2965 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168E_VL) {
2966 pci_set_max_read_req(sc->rl_dev, 4096);
2970 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
2972 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) |
2974 switch (sc->rl_hwrev->rl_rev) {
2975 case RL_HWREV_8168DP:
2977 case RL_HWREV_8168E:
2978 CSR_WRITE_1(sc, sc->rl_cfg4,
2979 CSR_READ_1(sc, sc->rl_cfg4) | 0x01);
2982 CSR_WRITE_1(sc, sc->rl_cfg4,
2983 CSR_READ_1(sc, sc->rl_cfg4) | RL_CFG4_JUMBO_EN1);
2986 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) &
2987 ~RL_CFG3_JUMBO_EN0);
2988 switch (sc->rl_hwrev->rl_rev) {
2989 case RL_HWREV_8168DP:
2991 case RL_HWREV_8168E:
2992 CSR_WRITE_1(sc, sc->rl_cfg4,
2993 CSR_READ_1(sc, sc->rl_cfg4) & ~0x01);
2996 CSR_WRITE_1(sc, sc->rl_cfg4,
2997 CSR_READ_1(sc, sc->rl_cfg4) & ~RL_CFG4_JUMBO_EN1);
3000 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
3002 switch (sc->rl_hwrev->rl_rev) {
3003 case RL_HWREV_8168DP:
3004 pci_set_max_read_req(sc->rl_dev, 4096);
3008 pci_set_max_read_req(sc->rl_dev, 512);
3010 pci_set_max_read_req(sc->rl_dev, 4096);
3017 struct rl_softc *sc = xsc;
3025 re_init_locked(struct rl_softc *sc)
3027 struct ifnet *ifp = sc->rl_ifp;
3028 struct mii_data *mii;
3032 uint32_t align_dummy;
3033 u_char eaddr[ETHER_ADDR_LEN];
3038 mii = device_get_softc(sc->rl_miibus);
3040 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
3044 * Cancel pending I/O and free all RX/TX buffers.
3048 /* Put controller into known state. */
3052 * For C+ mode, initialize the RX descriptors and mbufs.
3054 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
3055 if (ifp->if_mtu > RL_MTU) {
3056 if (re_jrx_list_init(sc) != 0) {
3057 device_printf(sc->rl_dev,
3058 "no memory for jumbo RX buffers\n");
3062 /* Disable checksum offloading for jumbo frames. */
3063 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_TSO4);
3064 ifp->if_hwassist &= ~(RE_CSUM_FEATURES | CSUM_TSO);
3066 if (re_rx_list_init(sc) != 0) {
3067 device_printf(sc->rl_dev,
3068 "no memory for RX buffers\n");
3073 re_set_jumbo(sc, ifp->if_mtu > RL_MTU);
3075 if (re_rx_list_init(sc) != 0) {
3076 device_printf(sc->rl_dev, "no memory for RX buffers\n");
3080 if ((sc->rl_flags & RL_FLAG_PCIE) != 0 &&
3081 pci_get_device(sc->rl_dev) != RT_DEVICEID_8101E) {
3082 if (ifp->if_mtu > RL_MTU)
3083 pci_set_max_read_req(sc->rl_dev, 512);
3085 pci_set_max_read_req(sc->rl_dev, 4096);
3088 re_tx_list_init(sc);
3091 * Enable C+ RX and TX mode, as well as VLAN stripping and
3092 * RX checksum offload. We must configure the C+ register
3093 * before all others.
3095 cfg = RL_CPLUSCMD_PCI_MRW;
3096 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
3097 cfg |= RL_CPLUSCMD_RXCSUM_ENB;
3098 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
3099 cfg |= RL_CPLUSCMD_VLANSTRIP;
3100 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) {
3101 cfg |= RL_CPLUSCMD_MACSTAT_DIS;
3105 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB;
3106 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg);
3107 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SC ||
3108 sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) {
3110 if ((CSR_READ_1(sc, sc->rl_cfg2) & RL_CFG2_PCI66MHZ) != 0)
3112 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE)
3114 CSR_WRITE_4(sc, 0x7c, reg);
3115 /* Disable interrupt mitigation. */
3116 CSR_WRITE_2(sc, 0xe2, 0);
3119 * Disable TSO if interface MTU size is greater than MSS
3120 * allowed in controller.
3122 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) {
3123 ifp->if_capenable &= ~IFCAP_TSO4;
3124 ifp->if_hwassist &= ~CSUM_TSO;
3128 * Init our MAC address. Even though the chipset
3129 * documentation doesn't mention it, we need to enter "Config
3130 * register write enable" mode to modify the ID registers.
3132 /* Copy MAC address on stack to align. */
3133 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN);
3134 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
3135 CSR_WRITE_4(sc, RL_IDR0,
3136 htole32(*(u_int32_t *)(&eaddr.eaddr[0])));
3137 CSR_WRITE_4(sc, RL_IDR4,
3138 htole32(*(u_int32_t *)(&eaddr.eaddr[4])));
3139 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
3142 * Load the addresses of the RX and TX lists into the chip.
3145 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI,
3146 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr));
3147 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO,
3148 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr));
3150 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI,
3151 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr));
3152 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO,
3153 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr));
3156 * Enable transmit and receive.
3158 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
3161 * Set the initial TX configuration.
3163 if (sc->rl_testmode) {
3164 if (sc->rl_type == RL_8169)
3165 CSR_WRITE_4(sc, RL_TXCFG,
3166 RL_TXCFG_CONFIG|RL_LOOPTEST_ON);
3168 CSR_WRITE_4(sc, RL_TXCFG,
3169 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS);
3171 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
3173 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16);
3176 * Set the initial RX configuration.
3180 /* Configure interrupt moderation. */
3181 if (sc->rl_type == RL_8169) {
3182 /* Magic from vendor. */
3183 CSR_WRITE_2(sc, RL_INTRMOD, 0x5100);
3186 #ifdef DEVICE_POLLING
3188 * Disable interrupts if we are polling.
3190 if (ifp->if_capenable & IFCAP_POLLING)
3191 CSR_WRITE_2(sc, RL_IMR, 0);
3192 else /* otherwise ... */
3196 * Enable interrupts.
3198 if (sc->rl_testmode)
3199 CSR_WRITE_2(sc, RL_IMR, 0);
3201 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
3202 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS);
3204 /* Set initial TX threshold */
3205 sc->rl_txthresh = RL_TX_THRESH_INIT;
3207 /* Start RX/TX process. */
3208 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
3210 /* Enable receiver and transmitter. */
3211 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
3215 * Initialize the timer interrupt register so that
3216 * a timer interrupt will be generated once the timer
3217 * reaches a certain number of ticks. The timer is
3218 * reloaded on each transmit.
3220 #ifdef RE_TX_MODERATION
3222 * Use timer interrupt register to moderate TX interrupt
3223 * moderation, which dramatically improves TX frame rate.
3225 if (sc->rl_type == RL_8169)
3226 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800);
3228 CSR_WRITE_4(sc, RL_TIMERINT, 0x400);
3231 * Use timer interrupt register to moderate RX interrupt
3234 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 &&
3236 if (sc->rl_type == RL_8169)
3237 CSR_WRITE_4(sc, RL_TIMERINT_8169,
3238 RL_USECS(sc->rl_int_rx_mod));
3240 if (sc->rl_type == RL_8169)
3241 CSR_WRITE_4(sc, RL_TIMERINT_8169, RL_USECS(0));
3246 * For 8169 gigE NICs, set the max allowed RX packet
3247 * size so we can receive jumbo frames.
3249 if (sc->rl_type == RL_8169) {
3250 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
3252 * For controllers that use new jumbo frame scheme,
3253 * set maximum size of jumbo frame depending on
3254 * controller revisions.
3256 if (ifp->if_mtu > RL_MTU)
3257 CSR_WRITE_2(sc, RL_MAXRXPKTLEN,
3258 sc->rl_hwrev->rl_max_mtu +
3259 ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN +
3262 CSR_WRITE_2(sc, RL_MAXRXPKTLEN,
3264 } else if ((sc->rl_flags & RL_FLAG_PCIE) != 0 &&
3265 sc->rl_hwrev->rl_max_mtu == RL_MTU) {
3266 /* RTL810x has no jumbo frame support. */
3267 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, RE_RX_DESC_BUFLEN);
3269 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383);
3272 if (sc->rl_testmode)
3275 CSR_WRITE_1(sc, sc->rl_cfg1, CSR_READ_1(sc, sc->rl_cfg1) |
3278 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3279 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3281 sc->rl_flags &= ~RL_FLAG_LINK;
3284 sc->rl_watchdog_timer = 0;
3285 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
3289 * Set media options.
3292 re_ifmedia_upd(struct ifnet *ifp)
3294 struct rl_softc *sc;
3295 struct mii_data *mii;
3299 mii = device_get_softc(sc->rl_miibus);
3301 error = mii_mediachg(mii);
3308 * Report current media status.
3311 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3313 struct rl_softc *sc;
3314 struct mii_data *mii;
3317 mii = device_get_softc(sc->rl_miibus);
3321 ifmr->ifm_active = mii->mii_media_active;
3322 ifmr->ifm_status = mii->mii_media_status;
3327 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3329 struct rl_softc *sc = ifp->if_softc;
3330 struct ifreq *ifr = (struct ifreq *) data;
3331 struct mii_data *mii;
3337 if (ifr->ifr_mtu < ETHERMIN ||
3338 ifr->ifr_mtu > sc->rl_hwrev->rl_max_mtu) {
3343 if (ifp->if_mtu != ifr->ifr_mtu) {
3344 ifp->if_mtu = ifr->ifr_mtu;
3345 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 &&
3346 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
3347 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3350 if (ifp->if_mtu > RL_TSO_MTU &&
3351 (ifp->if_capenable & IFCAP_TSO4) != 0) {
3352 ifp->if_capenable &= ~(IFCAP_TSO4 |
3354 ifp->if_hwassist &= ~CSUM_TSO;
3356 VLAN_CAPABILITIES(ifp);
3362 if ((ifp->if_flags & IFF_UP) != 0) {
3363 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
3364 if (((ifp->if_flags ^ sc->rl_if_flags)
3365 & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
3370 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
3373 sc->rl_if_flags = ifp->if_flags;
3379 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
3385 mii = device_get_softc(sc->rl_miibus);
3386 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
3392 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3394 #ifdef DEVICE_POLLING
3395 if (mask & IFCAP_POLLING) {
3396 if (ifr->ifr_reqcap & IFCAP_POLLING) {
3397 error = ether_poll_register(re_poll, ifp);
3401 /* Disable interrupts */
3402 CSR_WRITE_2(sc, RL_IMR, 0x0000);
3403 ifp->if_capenable |= IFCAP_POLLING;
3406 error = ether_poll_deregister(ifp);
3407 /* Enable interrupts. */
3409 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
3410 ifp->if_capenable &= ~IFCAP_POLLING;
3414 #endif /* DEVICE_POLLING */
3416 if ((mask & IFCAP_TXCSUM) != 0 &&
3417 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
3418 ifp->if_capenable ^= IFCAP_TXCSUM;
3419 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) {
3420 rev = sc->rl_hwrev->rl_rev;
3421 if (rev == RL_HWREV_8168C ||
3422 rev == RL_HWREV_8168C_SPIN2 ||
3423 rev == RL_HWREV_8168CP)
3424 ifp->if_hwassist |= CSUM_TCP | CSUM_UDP;
3426 ifp->if_hwassist |= RE_CSUM_FEATURES;
3428 ifp->if_hwassist &= ~RE_CSUM_FEATURES;
3431 if ((mask & IFCAP_RXCSUM) != 0 &&
3432 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) {
3433 ifp->if_capenable ^= IFCAP_RXCSUM;
3436 if ((mask & IFCAP_TSO4) != 0 &&
3437 (ifp->if_capabilities & IFCAP_TSO4) != 0) {
3438 ifp->if_capenable ^= IFCAP_TSO4;
3439 if ((IFCAP_TSO4 & ifp->if_capenable) != 0)
3440 ifp->if_hwassist |= CSUM_TSO;
3442 ifp->if_hwassist &= ~CSUM_TSO;
3443 if (ifp->if_mtu > RL_TSO_MTU &&
3444 (ifp->if_capenable & IFCAP_TSO4) != 0) {
3445 ifp->if_capenable &= ~IFCAP_TSO4;
3446 ifp->if_hwassist &= ~CSUM_TSO;
3449 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
3450 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
3451 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
3452 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
3453 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
3454 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
3455 /* TSO over VLAN requires VLAN hardware tagging. */
3456 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
3457 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
3460 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 &&
3461 (mask & (IFCAP_HWCSUM | IFCAP_TSO4 |
3462 IFCAP_VLAN_HWTSO)) != 0)
3464 if ((mask & IFCAP_WOL) != 0 &&
3465 (ifp->if_capabilities & IFCAP_WOL) != 0) {
3466 if ((mask & IFCAP_WOL_UCAST) != 0)
3467 ifp->if_capenable ^= IFCAP_WOL_UCAST;
3468 if ((mask & IFCAP_WOL_MCAST) != 0)
3469 ifp->if_capenable ^= IFCAP_WOL_MCAST;
3470 if ((mask & IFCAP_WOL_MAGIC) != 0)
3471 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
3473 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) {
3474 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3478 VLAN_CAPABILITIES(ifp);
3482 error = ether_ioctl(ifp, command, data);
3490 re_watchdog(struct rl_softc *sc)
3496 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0)
3501 if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) {
3502 if_printf(ifp, "watchdog timeout (missed Tx interrupts) "
3504 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3505 re_start_locked(ifp);
3509 if_printf(ifp, "watchdog timeout\n");
3513 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3515 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3516 re_start_locked(ifp);
3520 * Stop the adapter and free any mbufs allocated to the
3524 re_stop(struct rl_softc *sc)
3528 struct rl_txdesc *txd;
3529 struct rl_rxdesc *rxd;
3535 sc->rl_watchdog_timer = 0;
3536 callout_stop(&sc->rl_stat_callout);
3537 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3540 * Disable accepting frames to put RX MAC into idle state.
3541 * Otherwise it's possible to get frames while stop command
3542 * execution is in progress and controller can DMA the frame
3543 * to already freed RX buffer during that period.
3545 CSR_WRITE_4(sc, RL_RXCFG, CSR_READ_4(sc, RL_RXCFG) &
3546 ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_MULTI |
3547 RL_RXCFG_RX_BROAD));
3549 if ((sc->rl_flags & RL_FLAG_WAIT_TXPOLL) != 0) {
3550 for (i = RL_TIMEOUT; i > 0; i--) {
3551 if ((CSR_READ_1(sc, sc->rl_txstart) &
3552 RL_TXSTART_START) == 0)
3557 device_printf(sc->rl_dev,
3558 "stopping TX poll timed out!\n");
3559 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
3560 } else if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) {
3561 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB |
3563 if ((sc->rl_flags & RL_FLAG_CMDSTOP_WAIT_TXQ) != 0) {
3564 for (i = RL_TIMEOUT; i > 0; i--) {
3565 if ((CSR_READ_4(sc, RL_TXCFG) &
3566 RL_TXCFG_QUEUE_EMPTY) != 0)
3571 device_printf(sc->rl_dev,
3572 "stopping TXQ timed out!\n");
3575 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
3577 CSR_WRITE_2(sc, RL_IMR, 0x0000);
3578 CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
3580 if (sc->rl_head != NULL) {
3581 m_freem(sc->rl_head);
3582 sc->rl_head = sc->rl_tail = NULL;
3585 /* Free the TX list buffers. */
3586 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
3587 txd = &sc->rl_ldata.rl_tx_desc[i];
3588 if (txd->tx_m != NULL) {
3589 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag,
3590 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
3591 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag,
3598 /* Free the RX list buffers. */
3599 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
3600 rxd = &sc->rl_ldata.rl_rx_desc[i];
3601 if (rxd->rx_m != NULL) {
3602 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag,
3603 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3604 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag,
3611 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
3612 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
3613 rxd = &sc->rl_ldata.rl_jrx_desc[i];
3614 if (rxd->rx_m != NULL) {
3615 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag,
3616 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3617 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag,
3627 * Device suspend routine. Stop the interface and save some PCI
3628 * settings in case the BIOS doesn't restore them properly on
3632 re_suspend(device_t dev)
3634 struct rl_softc *sc;
3636 sc = device_get_softc(dev);
3648 * Device resume routine. Restore some PCI settings in case the BIOS
3649 * doesn't, re-enable busmastering, and restart the interface if
3653 re_resume(device_t dev)
3655 struct rl_softc *sc;
3658 sc = device_get_softc(dev);
3663 /* Take controller out of sleep mode. */
3664 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) {
3665 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)
3666 CSR_WRITE_1(sc, RL_GPIO,
3667 CSR_READ_1(sc, RL_GPIO) | 0x01);
3671 * Clear WOL matching such that normal Rx filtering
3672 * wouldn't interfere with WOL patterns.
3676 /* reinitialize interface if necessary */
3677 if (ifp->if_flags & IFF_UP)
3687 * Stop all chip I/O so that the kernel's probe routines don't
3688 * get confused by errant DMAs when rebooting.
3691 re_shutdown(device_t dev)
3693 struct rl_softc *sc;
3695 sc = device_get_softc(dev);
3700 * Mark interface as down since otherwise we will panic if
3701 * interrupt comes in later on, which can happen in some
3704 sc->rl_ifp->if_flags &= ~IFF_UP;
3712 re_set_linkspeed(struct rl_softc *sc)
3714 struct mii_softc *miisc;
3715 struct mii_data *mii;
3720 mii = device_get_softc(sc->rl_miibus);
3723 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
3724 (IFM_ACTIVE | IFM_AVALID)) {
3725 switch IFM_SUBTYPE(mii->mii_media_active) {
3736 miisc = LIST_FIRST(&mii->mii_phys);
3737 phyno = miisc->mii_phy;
3738 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3740 re_miibus_writereg(sc->rl_dev, phyno, MII_100T2CR, 0);
3741 re_miibus_writereg(sc->rl_dev, phyno,
3742 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
3743 re_miibus_writereg(sc->rl_dev, phyno,
3744 MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG);
3748 * Poll link state until re(4) get a 10/100Mbps link.
3750 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
3752 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID))
3753 == (IFM_ACTIVE | IFM_AVALID)) {
3754 switch (IFM_SUBTYPE(mii->mii_media_active)) {
3766 if (i == MII_ANEGTICKS_GIGE)
3767 device_printf(sc->rl_dev,
3768 "establishing a link failed, WOL may not work!");
3771 * No link, force MAC to have 100Mbps, full-duplex link.
3772 * MAC does not require reprogramming on resolved speed/duplex,
3773 * so this is just for completeness.
3775 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
3776 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
3780 re_setwol(struct rl_softc *sc)
3789 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
3793 /* Put controller into sleep mode. */
3794 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) {
3795 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)
3796 CSR_WRITE_1(sc, RL_GPIO,
3797 CSR_READ_1(sc, RL_GPIO) & ~0x01);
3799 if ((ifp->if_capenable & IFCAP_WOL) != 0) {
3801 if ((sc->rl_flags & RL_FLAG_WOL_MANLINK) != 0)
3802 re_set_linkspeed(sc);
3803 if ((sc->rl_flags & RL_FLAG_WOLRXENB) != 0)
3804 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB);
3806 /* Enable config register write. */
3807 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
3810 v = CSR_READ_1(sc, sc->rl_cfg1);
3812 if ((ifp->if_capenable & IFCAP_WOL) != 0)
3814 CSR_WRITE_1(sc, sc->rl_cfg1, v);
3816 v = CSR_READ_1(sc, sc->rl_cfg3);
3817 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
3818 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
3819 v |= RL_CFG3_WOL_MAGIC;
3820 CSR_WRITE_1(sc, sc->rl_cfg3, v);
3822 v = CSR_READ_1(sc, sc->rl_cfg5);
3823 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST |
3824 RL_CFG5_WOL_LANWAKE);
3825 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0)
3826 v |= RL_CFG5_WOL_UCAST;
3827 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
3828 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST;
3829 if ((ifp->if_capenable & IFCAP_WOL) != 0)
3830 v |= RL_CFG5_WOL_LANWAKE;
3831 CSR_WRITE_1(sc, sc->rl_cfg5, v);
3833 /* Config register write done. */
3834 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
3836 if ((ifp->if_capenable & IFCAP_WOL) == 0 &&
3837 (sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0)
3838 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80);
3840 * It seems that hardware resets its link speed to 100Mbps in
3841 * power down mode so switching to 100Mbps in driver is not
3845 /* Request PME if WOL is requested. */
3846 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2);
3847 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
3848 if ((ifp->if_capenable & IFCAP_WOL) != 0)
3849 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3850 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
3854 re_clrwol(struct rl_softc *sc)
3861 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
3864 /* Enable config register write. */
3865 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
3867 v = CSR_READ_1(sc, sc->rl_cfg3);
3868 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
3869 CSR_WRITE_1(sc, sc->rl_cfg3, v);
3871 /* Config register write done. */
3872 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
3874 v = CSR_READ_1(sc, sc->rl_cfg5);
3875 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
3876 v &= ~RL_CFG5_WOL_LANWAKE;
3877 CSR_WRITE_1(sc, sc->rl_cfg5, v);
3881 re_add_sysctls(struct rl_softc *sc)
3883 struct sysctl_ctx_list *ctx;
3884 struct sysctl_oid_list *children;
3887 ctx = device_get_sysctl_ctx(sc->rl_dev);
3888 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev));
3890 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "stats",
3891 CTLTYPE_INT | CTLFLAG_RW, sc, 0, re_sysctl_stats, "I",
3892 "Statistics Information");
3893 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0)
3896 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "int_rx_mod",
3897 CTLTYPE_INT | CTLFLAG_RW, &sc->rl_int_rx_mod, 0,
3898 sysctl_hw_re_int_mod, "I", "re RX interrupt moderation");
3899 /* Pull in device tunables. */
3900 sc->rl_int_rx_mod = RL_TIMER_DEFAULT;
3901 error = resource_int_value(device_get_name(sc->rl_dev),
3902 device_get_unit(sc->rl_dev), "int_rx_mod", &sc->rl_int_rx_mod);
3904 if (sc->rl_int_rx_mod < RL_TIMER_MIN ||
3905 sc->rl_int_rx_mod > RL_TIMER_MAX) {
3906 device_printf(sc->rl_dev, "int_rx_mod value out of "
3907 "range; using default: %d\n",
3909 sc->rl_int_rx_mod = RL_TIMER_DEFAULT;
3916 re_sysctl_stats(SYSCTL_HANDLER_ARGS)
3918 struct rl_softc *sc;
3919 struct rl_stats *stats;
3920 int error, i, result;
3923 error = sysctl_handle_int(oidp, &result, 0, req);
3924 if (error || req->newptr == NULL)
3928 sc = (struct rl_softc *)arg1;
3930 if ((sc->rl_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
3934 bus_dmamap_sync(sc->rl_ldata.rl_stag,
3935 sc->rl_ldata.rl_smap, BUS_DMASYNC_PREREAD);
3936 CSR_WRITE_4(sc, RL_DUMPSTATS_HI,
3937 RL_ADDR_HI(sc->rl_ldata.rl_stats_addr));
3938 CSR_WRITE_4(sc, RL_DUMPSTATS_LO,
3939 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr));
3940 CSR_WRITE_4(sc, RL_DUMPSTATS_LO,
3941 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr |
3942 RL_DUMPSTATS_START));
3943 for (i = RL_TIMEOUT; i > 0; i--) {
3944 if ((CSR_READ_4(sc, RL_DUMPSTATS_LO) &
3945 RL_DUMPSTATS_START) == 0)
3949 bus_dmamap_sync(sc->rl_ldata.rl_stag,
3950 sc->rl_ldata.rl_smap, BUS_DMASYNC_POSTREAD);
3953 device_printf(sc->rl_dev,
3954 "DUMP statistics request timed out\n");
3958 stats = sc->rl_ldata.rl_stats;
3959 printf("%s statistics:\n", device_get_nameunit(sc->rl_dev));
3960 printf("Tx frames : %ju\n",
3961 (uintmax_t)le64toh(stats->rl_tx_pkts));
3962 printf("Rx frames : %ju\n",
3963 (uintmax_t)le64toh(stats->rl_rx_pkts));
3964 printf("Tx errors : %ju\n",
3965 (uintmax_t)le64toh(stats->rl_tx_errs));
3966 printf("Rx errors : %u\n",
3967 le32toh(stats->rl_rx_errs));
3968 printf("Rx missed frames : %u\n",
3969 (uint32_t)le16toh(stats->rl_missed_pkts));
3970 printf("Rx frame alignment errs : %u\n",
3971 (uint32_t)le16toh(stats->rl_rx_framealign_errs));
3972 printf("Tx single collisions : %u\n",
3973 le32toh(stats->rl_tx_onecoll));
3974 printf("Tx multiple collisions : %u\n",
3975 le32toh(stats->rl_tx_multicolls));
3976 printf("Rx unicast frames : %ju\n",
3977 (uintmax_t)le64toh(stats->rl_rx_ucasts));
3978 printf("Rx broadcast frames : %ju\n",
3979 (uintmax_t)le64toh(stats->rl_rx_bcasts));
3980 printf("Rx multicast frames : %u\n",
3981 le32toh(stats->rl_rx_mcasts));
3982 printf("Tx aborts : %u\n",
3983 (uint32_t)le16toh(stats->rl_tx_aborts));
3984 printf("Tx underruns : %u\n",
3985 (uint32_t)le16toh(stats->rl_rx_underruns));
3992 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3998 value = *(int *)arg1;
3999 error = sysctl_handle_int(oidp, &value, 0, req);
4000 if (error || req->newptr == NULL)
4002 if (value < low || value > high)
4004 *(int *)arg1 = value;
4010 sysctl_hw_re_int_mod(SYSCTL_HANDLER_ARGS)
4013 return (sysctl_int_range(oidp, arg1, arg2, req, RL_TIMER_MIN,