2 * Copyright (c) 2011, Aleksandr Rybalko
4 * by Alexander Egorenkov <egorenar@gmail.com>
5 * and by Damien Bergamini <damien.bergamini@free.fr>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice unmodified, this list of conditions, and the following
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
38 #include <net/if_arp.h>
39 #include <net/ethernet.h>
40 #include <net/if_dl.h>
41 #include <net/if_media.h>
42 #include <net/if_types.h>
43 #include <net/if_vlan_var.h>
47 #include <machine/bus.h>
48 #include <machine/cache.h>
49 #include <machine/cpufunc.h>
50 #include <machine/resource.h>
51 #include <vm/vm_param.h>
54 #include <machine/pmap.h>
58 #include <dev/mii/mii.h>
59 #include <dev/mii/miivar.h>
61 #include <mips/rt305x/rt305x_sysctlvar.h>
62 #include <mips/rt305x/rt305xreg.h>
64 #ifdef IF_RT_PHY_SUPPORT
65 #include "miibus_if.h"
71 #define RT_MAX_AGG_SIZE 3840
73 #define RT_TX_DATA_SEG0_SIZE MJUMPAGESIZE
75 #define RT_MS(_v, _f) (((_v) & _f) >> _f##_S)
76 #define RT_SM(_v, _f) (((_v) << _f##_S) & _f)
78 #define RT_TX_WATCHDOG_TIMEOUT 5
81 * Static function prototypes
83 static int rt_probe(device_t dev);
84 static int rt_attach(device_t dev);
85 static int rt_detach(device_t dev);
86 static int rt_shutdown(device_t dev);
87 static int rt_suspend(device_t dev);
88 static int rt_resume(device_t dev);
89 static void rt_init_locked(void *priv);
90 static void rt_init(void *priv);
91 static void rt_stop_locked(void *priv);
92 static void rt_stop(void *priv);
93 static void rt_start(struct ifnet *ifp);
94 static int rt_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data);
95 static void rt_periodic(void *arg);
96 static void rt_tx_watchdog(void *arg);
97 static void rt_intr(void *arg);
98 static void rt_tx_coherent_intr(struct rt_softc *sc);
99 static void rt_rx_coherent_intr(struct rt_softc *sc);
100 static void rt_rx_delay_intr(struct rt_softc *sc);
101 static void rt_tx_delay_intr(struct rt_softc *sc);
102 static void rt_rx_intr(struct rt_softc *sc);
103 static void rt_tx_intr(struct rt_softc *sc, int qid);
104 static void rt_rx_done_task(void *context, int pending);
105 static void rt_tx_done_task(void *context, int pending);
106 static void rt_periodic_task(void *context, int pending);
107 static int rt_rx_eof(struct rt_softc *sc, int limit);
108 static void rt_tx_eof(struct rt_softc *sc,
109 struct rt_softc_tx_ring *ring);
110 static void rt_update_stats(struct rt_softc *sc);
111 static void rt_watchdog(struct rt_softc *sc);
112 static void rt_update_raw_counters(struct rt_softc *sc);
113 static void rt_intr_enable(struct rt_softc *sc, uint32_t intr_mask);
114 static void rt_intr_disable(struct rt_softc *sc, uint32_t intr_mask);
115 static int rt_txrx_enable(struct rt_softc *sc);
116 static int rt_alloc_rx_ring(struct rt_softc *sc,
117 struct rt_softc_rx_ring *ring);
118 static void rt_reset_rx_ring(struct rt_softc *sc,
119 struct rt_softc_rx_ring *ring);
120 static void rt_free_rx_ring(struct rt_softc *sc,
121 struct rt_softc_rx_ring *ring);
122 static int rt_alloc_tx_ring(struct rt_softc *sc,
123 struct rt_softc_tx_ring *ring, int qid);
124 static void rt_reset_tx_ring(struct rt_softc *sc,
125 struct rt_softc_tx_ring *ring);
126 static void rt_free_tx_ring(struct rt_softc *sc,
127 struct rt_softc_tx_ring *ring);
128 static void rt_dma_map_addr(void *arg, bus_dma_segment_t *segs,
129 int nseg, int error);
130 static void rt_sysctl_attach(struct rt_softc *sc);
131 #ifdef IF_RT_PHY_SUPPORT
132 void rt_miibus_statchg(device_t);
133 static int rt_miibus_readreg(device_t, int, int);
134 static int rt_miibus_writereg(device_t, int, int, int);
136 static int rt_ifmedia_upd(struct ifnet *);
137 static void rt_ifmedia_sts(struct ifnet *, struct ifmediareq *);
139 static SYSCTL_NODE(_hw, OID_AUTO, rt, CTLFLAG_RD, 0, "RT driver parameters");
141 static int rt_debug = 0;
142 SYSCTL_INT(_hw_rt, OID_AUTO, debug, CTLFLAG_RW, &rt_debug, 0,
144 TUNABLE_INT("hw.rt.debug", &rt_debug);
148 rt_probe(device_t dev)
150 device_set_desc(dev, "Ralink RT305XF onChip Ethernet MAC");
155 * macaddr_atoi - translate string MAC address to uint8_t array
158 macaddr_atoi(const char *str, uint8_t *mac)
161 unsigned int amac[ETHER_ADDR_LEN]; /* Aligned version */
163 count = sscanf(str, "%x%*c%x%*c%x%*c%x%*c%x%*c%x",
164 &amac[0], &amac[1], &amac[2],
165 &amac[3], &amac[4], &amac[5]);
166 if (count < ETHER_ADDR_LEN) {
167 memset(mac, 0, ETHER_ADDR_LEN);
171 /* Copy aligned to result */
172 for (i = 0; i < ETHER_ADDR_LEN; i ++)
173 mac[i] = (amac[i] & 0xff);
178 #ifdef USE_GENERATED_MAC_ADDRESS
180 kernenv_next(char *cp)
194 * generate_mac(uin8_t *mac)
195 * This is MAC address generator for cases when real device MAC address
196 * unknown or not yet accessible.
197 * Use 'b','s','d' signature and 3 octets from CRC32 on kenv.
198 * MAC = 'b', 's', 'd', CRC[3]^CRC[2], CRC[1], CRC[0]
200 * Output - MAC address, that do not change between reboots, if hints or
201 * bootloader info unchange.
204 generate_mac(uint8_t *mac)
208 uint32_t crc = 0xffffffff;
210 /* Generate CRC32 on kenv */
212 for (cp = kenvp[0]; cp != NULL; cp = kenvp[++i]) {
213 crc = calculate_crc32c(crc, cp, strlen(cp) + 1);
216 for (cp = kern_envp; cp != NULL; cp = kernenv_next(cp)) {
217 crc = calculate_crc32c(crc, cp, strlen(cp) + 1);
225 mac[3] = (crc >> 24) ^ ((crc >> 16) & 0xff);
226 mac[4] = (crc >> 8) & 0xff;
232 * ether_request_mac - try to find usable MAC address.
235 ether_request_mac(device_t dev, uint8_t *mac)
240 * "ethaddr" is passed via envp on RedBoot platforms
241 * "kmac" is passed via argv on RouterBOOT platforms
243 #if defined(__U_BOOT__) || defined(__REDBOOT__) || defined(__ROUTERBOOT__)
244 if ((var = getenv("ethaddr")) != NULL ||
245 (var = getenv("kmac")) != NULL ) {
247 if(!macaddr_atoi(var, mac)) {
248 printf("%s: use %s macaddr from KENV\n",
249 device_get_nameunit(dev), var);
259 * hint.[dev].[unit].macaddr
261 if (!resource_string_value(device_get_name(dev),
262 device_get_unit(dev), "macaddr", (const char **)&var)) {
264 if(!macaddr_atoi(var, mac)) {
265 printf("%s: use %s macaddr from hints\n",
266 device_get_nameunit(dev), var);
271 #ifdef USE_GENERATED_MAC_ADDRESS
274 device_printf(dev, "use generated %02x:%02x:%02x:%02x:%02x:%02x "
275 "macaddr\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
285 device_printf(dev, "use hardcoded 00:18:e7:d5:83:90 macaddr\n");
292 rt_attach(device_t dev)
298 sc = device_get_softc(dev);
301 mtx_init(&sc->lock, device_get_nameunit(dev), MTX_NETWORK_LOCK,
302 MTX_DEF | MTX_RECURSE);
305 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
307 if (sc->mem == NULL) {
308 device_printf(dev, "could not allocate memory resource\n");
313 sc->bst = rman_get_bustag(sc->mem);
314 sc->bsh = rman_get_bushandle(sc->mem);
317 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
319 if (sc->irq == NULL) {
321 "could not allocate interrupt resource\n");
327 sc->debug = rt_debug;
329 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
330 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
331 "debug", CTLFLAG_RW, &sc->debug, 0, "rt debug level");
334 device_printf(dev, "RT305XF Ethernet MAC (rev 0x%08x)\n",
338 RT_WRITE(sc, GE_PORT_BASE + FE_RST_GLO, PSE_RESET);
340 RT_WRITE(sc, GDMA1_BASE + GDMA_FWD_CFG,
342 GDM_ICS_EN | /* Enable IP Csum */
343 GDM_TCS_EN | /* Enable TCP Csum */
344 GDM_UCS_EN | /* Enable UDP Csum */
345 GDM_STRPCRC | /* Strip CRC from packet */
346 GDM_DST_PORT_CPU << GDM_UFRC_P_SHIFT | /* Forward UCast to CPU */
347 GDM_DST_PORT_CPU << GDM_BFRC_P_SHIFT | /* Forward BCast to CPU */
348 GDM_DST_PORT_CPU << GDM_MFRC_P_SHIFT | /* Forward MCast to CPU */
349 GDM_DST_PORT_CPU << GDM_OFRC_P_SHIFT /* Forward Other to CPU */
352 /* allocate Tx and Rx rings */
353 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) {
354 error = rt_alloc_tx_ring(sc, &sc->tx_ring[i], i);
356 device_printf(dev, "could not allocate Tx ring #%d\n",
362 sc->tx_ring_mgtqid = 5;
364 error = rt_alloc_rx_ring(sc, &sc->rx_ring);
366 device_printf(dev, "could not allocate Rx ring\n");
370 callout_init(&sc->periodic_ch, 0);
371 callout_init_mtx(&sc->tx_watchdog_ch, &sc->lock, 0);
373 ifp = sc->ifp = if_alloc(IFT_ETHER);
375 device_printf(dev, "could not if_alloc()\n");
381 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev));
382 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
383 ifp->if_init = rt_init;
384 ifp->if_ioctl = rt_ioctl;
385 ifp->if_start = rt_start;
386 ifp->if_mtu = ETHERMTU;
387 #define RT_TX_QLEN 256
389 IFQ_SET_MAXLEN(&ifp->if_snd, RT_TX_QLEN);
390 ifp->if_snd.ifq_drv_maxlen = RT_TX_QLEN;
391 IFQ_SET_READY(&ifp->if_snd);
393 #ifdef IF_RT_PHY_SUPPORT
394 error = mii_attach(dev, &sc->rt_miibus, ifp, rt_ifmedia_upd,
395 rt_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
397 device_printf(dev, "attaching PHYs failed\n");
402 ifmedia_init(&sc->rt_ifmedia, 0, rt_ifmedia_upd, rt_ifmedia_sts);
403 ifmedia_add(&sc->rt_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 0,
405 ifmedia_set(&sc->rt_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX);
407 #endif /* IF_RT_PHY_SUPPORT */
409 ether_request_mac(dev, sc->mac_addr);
410 ether_ifattach(ifp, sc->mac_addr);
413 * Tell the upper layer(s) we support long frames.
415 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
416 ifp->if_capabilities |= IFCAP_VLAN_MTU;
417 ifp->if_capenable |= IFCAP_VLAN_MTU;
418 ifp->if_capabilities |= IFCAP_RXCSUM|IFCAP_TXCSUM;
419 ifp->if_capenable |= IFCAP_RXCSUM|IFCAP_TXCSUM;
421 /* init task queue */
422 TASK_INIT(&sc->rx_done_task, 0, rt_rx_done_task, sc);
423 TASK_INIT(&sc->tx_done_task, 0, rt_tx_done_task, sc);
424 TASK_INIT(&sc->periodic_task, 0, rt_periodic_task, sc);
426 sc->rx_process_limit = 100;
428 sc->taskqueue = taskqueue_create("rt_taskq", M_NOWAIT,
429 taskqueue_thread_enqueue, &sc->taskqueue);
431 taskqueue_start_threads(&sc->taskqueue, 1, PI_NET, "%s taskq",
432 device_get_nameunit(sc->dev));
434 rt_sysctl_attach(sc);
436 /* set up interrupt */
437 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE,
438 NULL, rt_intr, sc, &sc->irqh);
440 printf("%s: could not set up interrupt\n",
441 device_get_nameunit(dev));
445 device_printf(dev, "debug var at %#08x\n", (u_int)&(sc->debug));
451 /* free Tx and Rx rings */
452 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++)
453 rt_free_tx_ring(sc, &sc->tx_ring[i]);
455 rt_free_rx_ring(sc, &sc->rx_ring);
457 mtx_destroy(&sc->lock);
460 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
464 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid,
474 rt_ifmedia_upd(struct ifnet *ifp)
477 #ifdef IF_RT_PHY_SUPPORT
478 struct mii_data *mii;
484 mii = device_get_softc(sc->rt_miibus);
485 if (mii->mii_instance) {
486 struct mii_softc *miisc;
487 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
488 miisc = LIST_NEXT(miisc, mii_list))
489 mii_phy_reset(miisc);
492 error = mii_mediachg(mii);
497 #else /* !IF_RT_PHY_SUPPORT */
500 struct ifmedia_entry *ife;
503 ifm = &sc->rt_ifmedia;
506 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
509 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
510 device_printf(sc->dev,
511 "AUTO is not supported for multiphy MAC");
519 #endif /* IF_RT_PHY_SUPPORT */
523 * Report current media status.
526 rt_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
528 #ifdef IF_RT_PHY_SUPPORT
530 struct mii_data *mii;
535 mii = device_get_softc(sc->rt_miibus);
537 ifmr->ifm_active = mii->mii_media_active;
538 ifmr->ifm_status = mii->mii_media_status;
539 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
540 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE;
542 #else /* !IF_RT_PHY_SUPPORT */
544 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE;
545 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
546 #endif /* IF_RT_PHY_SUPPORT */
550 rt_detach(device_t dev)
556 sc = device_get_softc(dev);
559 RT_DPRINTF(sc, RT_DEBUG_ANY, "detaching\n");
563 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
565 callout_stop(&sc->periodic_ch);
566 callout_stop(&sc->tx_watchdog_ch);
568 taskqueue_drain(sc->taskqueue, &sc->rx_done_task);
569 taskqueue_drain(sc->taskqueue, &sc->tx_done_task);
570 taskqueue_drain(sc->taskqueue, &sc->periodic_task);
572 /* free Tx and Rx rings */
573 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++)
574 rt_free_tx_ring(sc, &sc->tx_ring[i]);
576 rt_free_rx_ring(sc, &sc->rx_ring);
580 #ifdef IF_RT_PHY_SUPPORT
581 if (sc->rt_miibus != NULL)
582 device_delete_child(dev, sc->rt_miibus);
588 taskqueue_free(sc->taskqueue);
590 mtx_destroy(&sc->lock);
592 bus_generic_detach(dev);
593 bus_teardown_intr(dev, sc->irq, sc->irqh);
594 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, sc->irq);
595 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem);
601 rt_shutdown(device_t dev)
605 sc = device_get_softc(dev);
606 RT_DPRINTF(sc, RT_DEBUG_ANY, "shutting down\n");
613 rt_suspend(device_t dev)
617 sc = device_get_softc(dev);
618 RT_DPRINTF(sc, RT_DEBUG_ANY, "suspending\n");
625 rt_resume(device_t dev)
630 sc = device_get_softc(dev);
633 RT_DPRINTF(sc, RT_DEBUG_ANY, "resuming\n");
635 if (ifp->if_flags & IFF_UP)
642 * rt_init_locked - Run initialization process having locked mtx.
645 rt_init_locked(void *priv)
649 #ifdef IF_RT_PHY_SUPPORT
650 struct mii_data *mii;
657 #ifdef IF_RT_PHY_SUPPORT
658 mii = device_get_softc(sc->rt_miibus);
661 RT_DPRINTF(sc, RT_DEBUG_ANY, "initializing\n");
663 RT_SOFTC_ASSERT_LOCKED(sc);
666 RT_WRITE(sc, GE_PORT_BASE + FE_RST_GLO, PSE_RESET);
667 rt305x_sysctl_set(SYSCTL_RSTCTRL, SYSCTL_RSTCTRL_FRENG);
669 /* Fwd to CPU (uni|broad|multi)cast and Unknown */
670 RT_WRITE(sc, GDMA1_BASE + GDMA_FWD_CFG,
672 GDM_ICS_EN | /* Enable IP Csum */
673 GDM_TCS_EN | /* Enable TCP Csum */
674 GDM_UCS_EN | /* Enable UDP Csum */
675 GDM_STRPCRC | /* Strip CRC from packet */
676 GDM_DST_PORT_CPU << GDM_UFRC_P_SHIFT | /* Forward UCast to CPU */
677 GDM_DST_PORT_CPU << GDM_BFRC_P_SHIFT | /* Forward BCast to CPU */
678 GDM_DST_PORT_CPU << GDM_MFRC_P_SHIFT | /* Forward MCast to CPU */
679 GDM_DST_PORT_CPU << GDM_OFRC_P_SHIFT /* Forward Other to CPU */
682 /* disable DMA engine */
683 RT_WRITE(sc, PDMA_BASE + PDMA_GLO_CFG, 0);
684 RT_WRITE(sc, PDMA_BASE + PDMA_RST_IDX, 0xffffffff);
686 /* wait while DMA engine is busy */
687 for (ntries = 0; ntries < 100; ntries++) {
688 tmp = RT_READ(sc, PDMA_BASE + PDMA_GLO_CFG);
689 if (!(tmp & (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)))
695 device_printf(sc->dev, "timeout waiting for DMA engine\n");
699 /* reset Rx and Tx rings */
700 tmp = FE_RST_DRX_IDX0 |
706 RT_WRITE(sc, PDMA_BASE + PDMA_RST_IDX, tmp);
708 /* XXX switch set mac address */
709 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++)
710 rt_reset_tx_ring(sc, &sc->tx_ring[i]);
712 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) {
713 /* update TX_BASE_PTRx */
714 RT_WRITE(sc, PDMA_BASE + TX_BASE_PTR(i),
715 sc->tx_ring[i].desc_phys_addr);
716 RT_WRITE(sc, PDMA_BASE + TX_MAX_CNT(i),
717 RT_SOFTC_TX_RING_DESC_COUNT);
718 RT_WRITE(sc, PDMA_BASE + TX_CTX_IDX(i), 0);
722 rt_reset_rx_ring(sc, &sc->rx_ring);
724 /* update RX_BASE_PTR0 */
725 RT_WRITE(sc, PDMA_BASE + RX_BASE_PTR0,
726 sc->rx_ring.desc_phys_addr);
727 RT_WRITE(sc, PDMA_BASE + RX_MAX_CNT0,
728 RT_SOFTC_RX_RING_DATA_COUNT);
729 RT_WRITE(sc, PDMA_BASE + RX_CALC_IDX0,
730 RT_SOFTC_RX_RING_DATA_COUNT - 1);
732 /* write back DDONE, 16byte burst enable RX/TX DMA */
733 RT_WRITE(sc, PDMA_BASE + PDMA_GLO_CFG,
734 FE_TX_WB_DDONE | FE_DMA_BT_SIZE16 | FE_RX_DMA_EN | FE_TX_DMA_EN);
736 /* disable interrupts mitigation */
737 RT_WRITE(sc, PDMA_BASE + DELAY_INT_CFG, 0);
739 /* clear pending interrupts */
740 RT_WRITE(sc, GE_PORT_BASE + FE_INT_STATUS, 0xffffffff);
742 /* enable interrupts */
760 sc->intr_enable_mask = tmp;
762 RT_WRITE(sc, GE_PORT_BASE + FE_INT_ENABLE, tmp);
764 if (rt_txrx_enable(sc) != 0)
767 #ifdef IF_RT_PHY_SUPPORT
768 if (mii) mii_mediachg(mii);
769 #endif /* IF_RT_PHY_SUPPORT */
771 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
772 ifp->if_drv_flags |= IFF_DRV_RUNNING;
774 sc->periodic_round = 0;
776 callout_reset(&sc->periodic_ch, hz / 10, rt_periodic, sc);
785 * rt_init - lock and initialize device.
799 * rt_stop_locked - stop TX/RX w/ lock
802 rt_stop_locked(void *priv)
810 RT_DPRINTF(sc, RT_DEBUG_ANY, "stopping\n");
812 RT_SOFTC_ASSERT_LOCKED(sc);
814 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
815 callout_stop(&sc->periodic_ch);
816 callout_stop(&sc->tx_watchdog_ch);
818 taskqueue_block(sc->taskqueue);
821 * Sometime rt_stop_locked called from isr and we get panic
822 * When found, I fix it
825 taskqueue_drain(sc->taskqueue, &sc->rx_done_task);
826 taskqueue_drain(sc->taskqueue, &sc->tx_done_task);
827 taskqueue_drain(sc->taskqueue, &sc->periodic_task);
831 /* disable interrupts */
832 RT_WRITE(sc, GE_PORT_BASE + FE_INT_ENABLE, 0);
835 RT_WRITE(sc, GE_PORT_BASE + FE_RST_GLO, PSE_RESET);
837 RT_WRITE(sc, GDMA1_BASE + GDMA_FWD_CFG,
839 GDM_ICS_EN | /* Enable IP Csum */
840 GDM_TCS_EN | /* Enable TCP Csum */
841 GDM_UCS_EN | /* Enable UDP Csum */
842 GDM_STRPCRC | /* Strip CRC from packet */
843 GDM_DST_PORT_CPU << GDM_UFRC_P_SHIFT | /* Forward UCast to CPU */
844 GDM_DST_PORT_CPU << GDM_BFRC_P_SHIFT | /* Forward BCast to CPU */
845 GDM_DST_PORT_CPU << GDM_MFRC_P_SHIFT | /* Forward MCast to CPU */
846 GDM_DST_PORT_CPU << GDM_OFRC_P_SHIFT /* Forward Other to CPU */
862 * rt_tx_data - transmit packet.
865 rt_tx_data(struct rt_softc *sc, struct mbuf *m, int qid)
868 struct rt_softc_tx_ring *ring;
869 struct rt_softc_tx_data *data;
870 struct rt_txdesc *desc;
872 bus_dma_segment_t dma_seg[RT_SOFTC_MAX_SCATTER];
873 int error, ndmasegs, ndescs, i;
875 KASSERT(qid >= 0 && qid < RT_SOFTC_TX_RING_COUNT,
876 ("%s: Tx data: invalid qid=%d\n",
877 device_get_nameunit(sc->dev), qid));
879 RT_SOFTC_TX_RING_ASSERT_LOCKED(&sc->tx_ring[qid]);
882 ring = &sc->tx_ring[qid];
883 desc = &ring->desc[ring->desc_cur];
884 data = &ring->data[ring->data_cur];
886 error = bus_dmamap_load_mbuf_sg(ring->data_dma_tag, data->dma_map, m,
887 dma_seg, &ndmasegs, 0);
889 /* too many fragments, linearize */
891 RT_DPRINTF(sc, RT_DEBUG_TX,
892 "could not load mbuf DMA map, trying to linearize "
893 "mbuf: ndmasegs=%d, len=%d, error=%d\n",
894 ndmasegs, m->m_pkthdr.len, error);
896 m_d = m_collapse(m, M_NOWAIT, 16);
904 sc->tx_defrag_packets++;
906 error = bus_dmamap_load_mbuf_sg(ring->data_dma_tag,
907 data->dma_map, m, dma_seg, &ndmasegs, 0);
909 device_printf(sc->dev, "could not load mbuf DMA map: "
910 "ndmasegs=%d, len=%d, error=%d\n",
911 ndmasegs, m->m_pkthdr.len, error);
917 if (m->m_pkthdr.len == 0)
920 /* determine how many Tx descs are required */
921 ndescs = 1 + ndmasegs / 2;
922 if ((ring->desc_queued + ndescs) >
923 (RT_SOFTC_TX_RING_DESC_COUNT - 2)) {
924 RT_DPRINTF(sc, RT_DEBUG_TX,
925 "there are not enough Tx descs\n");
927 sc->no_tx_desc_avail++;
929 bus_dmamap_unload(ring->data_dma_tag, data->dma_map);
936 /* set up Tx descs */
937 for (i = 0; i < ndmasegs; i += 2) {
938 /* Set destenation */
939 desc->dst = (TXDSCR_DST_PORT_GDMA1);
940 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
941 desc->dst |= (TXDSCR_IP_CSUM_GEN|TXDSCR_UDP_CSUM_GEN|
942 TXDSCR_TCP_CSUM_GEN);
950 desc->sdp0 = htole32(dma_seg[i].ds_addr);
951 desc->sdl0 = htole16(dma_seg[i].ds_len |
952 ( ((i+1) == ndmasegs )?RT_TXDESC_SDL0_LASTSEG:0 ));
954 if ((i+1) < ndmasegs) {
955 desc->sdp1 = htole32(dma_seg[i+1].ds_addr);
956 desc->sdl1 = htole16(dma_seg[i+1].ds_len |
957 ( ((i+2) == ndmasegs )?RT_TXDESC_SDL1_LASTSEG:0 ));
963 if ((i+2) < ndmasegs) {
965 ring->desc_cur = (ring->desc_cur + 1) %
966 RT_SOFTC_TX_RING_DESC_COUNT;
968 desc = &ring->desc[ring->desc_cur];
971 RT_DPRINTF(sc, RT_DEBUG_TX, "sending data: len=%d, ndmasegs=%d, "
972 "DMA ds_len=%d/%d/%d/%d/%d\n",
973 m->m_pkthdr.len, ndmasegs,
974 (int) dma_seg[0].ds_len,
975 (int) dma_seg[1].ds_len,
976 (int) dma_seg[2].ds_len,
977 (int) dma_seg[3].ds_len,
978 (int) dma_seg[4].ds_len);
980 bus_dmamap_sync(ring->seg0_dma_tag, ring->seg0_dma_map,
981 BUS_DMASYNC_PREWRITE);
982 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
983 BUS_DMASYNC_PREWRITE);
984 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
985 BUS_DMASYNC_PREWRITE);
988 ring->desc_cur = (ring->desc_cur + 1) % RT_SOFTC_TX_RING_DESC_COUNT;
991 ring->data_cur = (ring->data_cur + 1) % RT_SOFTC_TX_RING_DATA_COUNT;
994 RT_WRITE(sc, PDMA_BASE + TX_CTX_IDX(qid), ring->desc_cur);
1000 * rt_start - start Transmit/Receive
1003 rt_start(struct ifnet *ifp)
1005 struct rt_softc *sc;
1007 int qid = 0 /* XXX must check QoS priority */;
1011 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1015 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
1019 m->m_pkthdr.rcvif = NULL;
1021 RT_SOFTC_TX_RING_LOCK(&sc->tx_ring[qid]);
1023 if (sc->tx_ring[qid].data_queued >=
1024 RT_SOFTC_TX_RING_DATA_COUNT) {
1025 RT_SOFTC_TX_RING_UNLOCK(&sc->tx_ring[qid]);
1027 RT_DPRINTF(sc, RT_DEBUG_TX,
1028 "if_start: Tx ring with qid=%d is full\n", qid);
1032 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1035 sc->tx_data_queue_full[qid]++;
1040 if (rt_tx_data(sc, m, qid) != 0) {
1041 RT_SOFTC_TX_RING_UNLOCK(&sc->tx_ring[qid]);
1048 RT_SOFTC_TX_RING_UNLOCK(&sc->tx_ring[qid]);
1049 sc->tx_timer = RT_TX_WATCHDOG_TIMEOUT;
1050 callout_reset(&sc->tx_watchdog_ch, hz, rt_tx_watchdog, sc);
1055 * rt_update_promisc - set/clear promiscuous mode. Unused yet, because
1056 * filtering done by attached Ethernet switch.
1059 rt_update_promisc(struct ifnet *ifp)
1061 struct rt_softc *sc;
1064 printf("%s: %s promiscuous mode\n",
1065 device_get_nameunit(sc->dev),
1066 (ifp->if_flags & IFF_PROMISC) ? "entering" : "leaving");
1070 * rt_ioctl - ioctl handler.
1073 rt_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1075 struct rt_softc *sc;
1077 #ifdef IF_RT_PHY_SUPPORT
1078 struct mii_data *mii;
1079 #endif /* IF_RT_PHY_SUPPORT */
1080 int error, startall;
1083 ifr = (struct ifreq *) data;
1091 if (ifp->if_flags & IFF_UP) {
1092 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1093 if ((ifp->if_flags ^ sc->if_flags) &
1095 rt_update_promisc(ifp);
1101 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1104 sc->if_flags = ifp->if_flags;
1105 RT_SOFTC_UNLOCK(sc);
1109 #ifdef IF_RT_PHY_SUPPORT
1110 mii = device_get_softc(sc->rt_miibus);
1111 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1113 error = ifmedia_ioctl(ifp, ifr, &sc->rt_ifmedia, cmd);
1114 #endif /* IF_RT_PHY_SUPPORT */
1117 error = ether_ioctl(ifp, cmd, data);
1124 * rt_periodic - Handler of PERIODIC interrupt
1127 rt_periodic(void *arg)
1129 struct rt_softc *sc;
1132 RT_DPRINTF(sc, RT_DEBUG_PERIODIC, "periodic\n");
1133 taskqueue_enqueue(sc->taskqueue, &sc->periodic_task);
1137 * rt_tx_watchdog - Handler of TX Watchdog
1140 rt_tx_watchdog(void *arg)
1142 struct rt_softc *sc;
1148 if (sc->tx_timer == 0)
1151 if (--sc->tx_timer == 0) {
1152 device_printf(sc->dev, "Tx watchdog timeout: resetting\n");
1155 * XXX: Commented out, because reset break input.
1161 sc->tx_watchdog_timeouts++;
1163 callout_reset(&sc->tx_watchdog_ch, hz, rt_tx_watchdog, sc);
1167 * rt_cnt_ppe_af - Handler of PPE Counter Table Almost Full interrupt
1170 rt_cnt_ppe_af(struct rt_softc *sc)
1173 RT_DPRINTF(sc, RT_DEBUG_INTR, "PPE Counter Table Almost Full\n");
1177 * rt_cnt_gdm_af - Handler of GDMA 1 & 2 Counter Table Almost Full interrupt
1180 rt_cnt_gdm_af(struct rt_softc *sc)
1183 RT_DPRINTF(sc, RT_DEBUG_INTR,
1184 "GDMA 1 & 2 Counter Table Almost Full\n");
1188 * rt_pse_p2_fc - Handler of PSE port2 (GDMA 2) flow control interrupt
1191 rt_pse_p2_fc(struct rt_softc *sc)
1194 RT_DPRINTF(sc, RT_DEBUG_INTR,
1195 "PSE port2 (GDMA 2) flow control asserted.\n");
1199 * rt_gdm_crc_drop - Handler of GDMA 1/2 discard a packet due to CRC error
1203 rt_gdm_crc_drop(struct rt_softc *sc)
1206 RT_DPRINTF(sc, RT_DEBUG_INTR,
1207 "GDMA 1 & 2 discard a packet due to CRC error\n");
1211 * rt_pse_buf_drop - Handler of buffer sharing limitation interrupt
1214 rt_pse_buf_drop(struct rt_softc *sc)
1217 RT_DPRINTF(sc, RT_DEBUG_INTR,
1218 "PSE discards a packet due to buffer sharing limitation\n");
1222 * rt_gdm_other_drop - Handler of discard on other reason interrupt
1225 rt_gdm_other_drop(struct rt_softc *sc)
1228 RT_DPRINTF(sc, RT_DEBUG_INTR,
1229 "GDMA 1 & 2 discard a packet due to other reason\n");
1233 * rt_pse_p1_fc - Handler of PSE port1 (GDMA 1) flow control interrupt
1236 rt_pse_p1_fc(struct rt_softc *sc)
1239 RT_DPRINTF(sc, RT_DEBUG_INTR,
1240 "PSE port1 (GDMA 1) flow control asserted.\n");
1244 * rt_pse_p0_fc - Handler of PSE port0 (CDMA) flow control interrupt
1247 rt_pse_p0_fc(struct rt_softc *sc)
1250 RT_DPRINTF(sc, RT_DEBUG_INTR,
1251 "PSE port0 (CDMA) flow control asserted.\n");
1255 * rt_pse_fq_empty - Handler of PSE free Q empty threshold reached interrupt
1258 rt_pse_fq_empty(struct rt_softc *sc)
1261 RT_DPRINTF(sc, RT_DEBUG_INTR,
1262 "PSE free Q empty threshold reached & forced drop "
1263 "condition occurred.\n");
1267 * rt_intr - main ISR
1272 struct rt_softc *sc;
1279 /* acknowledge interrupts */
1280 status = RT_READ(sc, GE_PORT_BASE + FE_INT_STATUS);
1281 RT_WRITE(sc, GE_PORT_BASE + FE_INT_STATUS, status);
1283 RT_DPRINTF(sc, RT_DEBUG_INTR, "interrupt: status=0x%08x\n", status);
1285 if (status == 0xffffffff || /* device likely went away */
1286 status == 0) /* not for us */
1291 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1294 if (status & CNT_PPE_AF)
1297 if (status & CNT_GDM_AF)
1300 if (status & PSE_P2_FC)
1303 if (status & GDM_CRC_DROP)
1304 rt_gdm_crc_drop(sc);
1306 if (status & PSE_BUF_DROP)
1307 rt_pse_buf_drop(sc);
1309 if (status & GDM_OTHER_DROP)
1310 rt_gdm_other_drop(sc);
1312 if (status & PSE_P1_FC)
1315 if (status & PSE_P0_FC)
1318 if (status & PSE_FQ_EMPTY)
1319 rt_pse_fq_empty(sc);
1321 if (status & INT_TX_COHERENT)
1322 rt_tx_coherent_intr(sc);
1324 if (status & INT_RX_COHERENT)
1325 rt_rx_coherent_intr(sc);
1327 if (status & RX_DLY_INT)
1328 rt_rx_delay_intr(sc);
1330 if (status & TX_DLY_INT)
1331 rt_tx_delay_intr(sc);
1333 if (status & INT_RX_DONE)
1336 if (status & INT_TXQ3_DONE)
1339 if (status & INT_TXQ2_DONE)
1342 if (status & INT_TXQ1_DONE)
1345 if (status & INT_TXQ0_DONE)
1350 rt_tx_coherent_intr(struct rt_softc *sc)
1355 RT_DPRINTF(sc, RT_DEBUG_INTR, "Tx coherent interrupt\n");
1357 sc->tx_coherent_interrupts++;
1359 /* restart DMA engine */
1360 tmp = RT_READ(sc, PDMA_BASE + PDMA_GLO_CFG);
1361 tmp &= ~(FE_TX_WB_DDONE | FE_TX_DMA_EN);
1362 RT_WRITE(sc, PDMA_BASE + PDMA_GLO_CFG, tmp);
1364 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++)
1365 rt_reset_tx_ring(sc, &sc->tx_ring[i]);
1367 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) {
1368 RT_WRITE(sc, PDMA_BASE + TX_BASE_PTR(i),
1369 sc->tx_ring[i].desc_phys_addr);
1370 RT_WRITE(sc, PDMA_BASE + TX_MAX_CNT(i),
1371 RT_SOFTC_TX_RING_DESC_COUNT);
1372 RT_WRITE(sc, PDMA_BASE + TX_CTX_IDX(i), 0);
1379 * rt_rx_coherent_intr
1382 rt_rx_coherent_intr(struct rt_softc *sc)
1386 RT_DPRINTF(sc, RT_DEBUG_INTR, "Rx coherent interrupt\n");
1388 sc->rx_coherent_interrupts++;
1390 /* restart DMA engine */
1391 tmp = RT_READ(sc, PDMA_BASE + PDMA_GLO_CFG);
1392 tmp &= ~(FE_RX_DMA_EN);
1393 RT_WRITE(sc, PDMA_BASE + PDMA_GLO_CFG, tmp);
1396 rt_reset_rx_ring(sc, &sc->rx_ring);
1397 RT_WRITE(sc, PDMA_BASE + RX_BASE_PTR0,
1398 sc->rx_ring.desc_phys_addr);
1399 RT_WRITE(sc, PDMA_BASE + RX_MAX_CNT0,
1400 RT_SOFTC_RX_RING_DATA_COUNT);
1401 RT_WRITE(sc, PDMA_BASE + RX_CALC_IDX0,
1402 RT_SOFTC_RX_RING_DATA_COUNT - 1);
1408 * rt_rx_intr - a packet received
1411 rt_rx_intr(struct rt_softc *sc)
1414 RT_DPRINTF(sc, RT_DEBUG_INTR, "Rx interrupt\n");
1415 sc->rx_interrupts++;
1418 if (!(sc->intr_disable_mask & INT_RX_DONE)) {
1419 rt_intr_disable(sc, INT_RX_DONE);
1420 taskqueue_enqueue(sc->taskqueue, &sc->rx_done_task);
1423 sc->intr_pending_mask |= INT_RX_DONE;
1424 RT_SOFTC_UNLOCK(sc);
1428 rt_rx_delay_intr(struct rt_softc *sc)
1431 RT_DPRINTF(sc, RT_DEBUG_INTR, "Rx delay interrupt\n");
1432 sc->rx_delay_interrupts++;
1436 rt_tx_delay_intr(struct rt_softc *sc)
1439 RT_DPRINTF(sc, RT_DEBUG_INTR, "Tx delay interrupt\n");
1440 sc->tx_delay_interrupts++;
1444 * rt_tx_intr - Transsmition of packet done
1447 rt_tx_intr(struct rt_softc *sc, int qid)
1450 KASSERT(qid >= 0 && qid < RT_SOFTC_TX_RING_COUNT,
1451 ("%s: Tx interrupt: invalid qid=%d\n",
1452 device_get_nameunit(sc->dev), qid));
1454 RT_DPRINTF(sc, RT_DEBUG_INTR, "Tx interrupt: qid=%d\n", qid);
1456 sc->tx_interrupts[qid]++;
1459 if (!(sc->intr_disable_mask & (INT_TXQ0_DONE << qid))) {
1460 rt_intr_disable(sc, (INT_TXQ0_DONE << qid));
1461 taskqueue_enqueue(sc->taskqueue, &sc->tx_done_task);
1464 sc->intr_pending_mask |= (INT_TXQ0_DONE << qid);
1465 RT_SOFTC_UNLOCK(sc);
1469 * rt_rx_done_task - run RX task
1472 rt_rx_done_task(void *context, int pending)
1474 struct rt_softc *sc;
1481 RT_DPRINTF(sc, RT_DEBUG_RX, "Rx done task\n");
1483 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1486 sc->intr_pending_mask &= ~INT_RX_DONE;
1488 again = rt_rx_eof(sc, sc->rx_process_limit);
1492 if ((sc->intr_pending_mask & INT_RX_DONE) || again) {
1493 RT_DPRINTF(sc, RT_DEBUG_RX,
1494 "Rx done task: scheduling again\n");
1495 taskqueue_enqueue(sc->taskqueue, &sc->rx_done_task);
1497 rt_intr_enable(sc, INT_RX_DONE);
1500 RT_SOFTC_UNLOCK(sc);
1504 * rt_tx_done_task - check for pending TX task in all queues
1507 rt_tx_done_task(void *context, int pending)
1509 struct rt_softc *sc;
1517 RT_DPRINTF(sc, RT_DEBUG_TX, "Tx done task\n");
1519 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1522 for (i = RT_SOFTC_TX_RING_COUNT - 1; i >= 0; i--) {
1523 if (sc->intr_pending_mask & (INT_TXQ0_DONE << i)) {
1524 sc->intr_pending_mask &= ~(INT_TXQ0_DONE << i);
1525 rt_tx_eof(sc, &sc->tx_ring[i]);
1531 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1541 rt_intr_enable(sc, ~sc->intr_pending_mask &
1542 (sc->intr_disable_mask & intr_mask));
1544 if (sc->intr_pending_mask & intr_mask) {
1545 RT_DPRINTF(sc, RT_DEBUG_TX,
1546 "Tx done task: scheduling again\n");
1547 taskqueue_enqueue(sc->taskqueue, &sc->tx_done_task);
1550 RT_SOFTC_UNLOCK(sc);
1552 if (!IFQ_IS_EMPTY(&ifp->if_snd))
1557 * rt_periodic_task - run periodic task
1560 rt_periodic_task(void *context, int pending)
1562 struct rt_softc *sc;
1568 RT_DPRINTF(sc, RT_DEBUG_PERIODIC, "periodic task: round=%lu\n",
1569 sc->periodic_round);
1571 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1575 sc->periodic_round++;
1576 rt_update_stats(sc);
1578 if ((sc->periodic_round % 10) == 0) {
1579 rt_update_raw_counters(sc);
1583 RT_SOFTC_UNLOCK(sc);
1584 callout_reset(&sc->periodic_ch, hz / 10, rt_periodic, sc);
1588 * rt_rx_eof - check for frames that done by DMA engine and pass it into
1589 * network subsystem.
1592 rt_rx_eof(struct rt_softc *sc, int limit)
1595 struct rt_softc_rx_ring *ring;
1596 struct rt_rxdesc *desc;
1597 struct rt_softc_rx_data *data;
1598 struct mbuf *m, *mnew;
1599 bus_dma_segment_t segs[1];
1600 bus_dmamap_t dma_map;
1601 uint32_t index, desc_flags;
1602 int error, nsegs, len, nframes;
1605 ring = &sc->rx_ring;
1609 while (limit != 0) {
1610 index = RT_READ(sc, PDMA_BASE + RX_DRX_IDX0);
1611 if (ring->cur == index)
1614 desc = &ring->desc[ring->cur];
1615 data = &ring->data[ring->cur];
1617 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
1618 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1621 if ( sc->debug & RT_DEBUG_RX ) {
1622 printf("\nRX Descriptor[%#08x] dump:\n", (u_int)desc);
1623 hexdump(desc, 16, 0, 0);
1624 printf("-----------------------------------\n");
1628 /* XXX Sometime device don`t set DDONE bit */
1630 if (!(desc->sdl0 & htole16(RT_RXDESC_SDL0_DDONE))) {
1631 RT_DPRINTF(sc, RT_DEBUG_RX, "DDONE=0, try next\n");
1636 len = le16toh(desc->sdl0) & 0x3fff;
1637 RT_DPRINTF(sc, RT_DEBUG_RX, "new frame len=%d\n", len);
1641 mnew = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR,
1644 sc->rx_mbuf_alloc_errors++;
1649 mnew->m_len = mnew->m_pkthdr.len = MJUMPAGESIZE;
1651 error = bus_dmamap_load_mbuf_sg(ring->data_dma_tag,
1652 ring->spare_dma_map, mnew, segs, &nsegs, BUS_DMA_NOWAIT);
1654 RT_DPRINTF(sc, RT_DEBUG_RX,
1655 "could not load Rx mbuf DMA map: "
1656 "error=%d, nsegs=%d\n",
1661 sc->rx_mbuf_dmamap_errors++;
1667 KASSERT(nsegs == 1, ("%s: too many DMA segments",
1668 device_get_nameunit(sc->dev)));
1670 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
1671 BUS_DMASYNC_POSTREAD);
1672 bus_dmamap_unload(ring->data_dma_tag, data->dma_map);
1674 dma_map = data->dma_map;
1675 data->dma_map = ring->spare_dma_map;
1676 ring->spare_dma_map = dma_map;
1678 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
1679 BUS_DMASYNC_PREREAD);
1682 desc_flags = desc->src;
1685 /* Add 2 for proper align of RX IP header */
1686 desc->sdp0 = htole32(segs[0].ds_addr+2);
1687 desc->sdl0 = htole32(segs[0].ds_len-2);
1692 RT_DPRINTF(sc, RT_DEBUG_RX,
1693 "Rx frame: rxdesc flags=0x%08x\n", desc_flags);
1695 m->m_pkthdr.rcvif = ifp;
1696 /* Add 2 to fix data align, after sdp0 = addr + 2 */
1698 m->m_pkthdr.len = m->m_len = len;
1700 /* check for crc errors */
1701 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) {
1702 /*check for valid checksum*/
1703 if (desc_flags & (RXDSXR_SRC_IP_CSUM_FAIL|
1704 RXDSXR_SRC_L4_CSUM_FAIL)) {
1705 RT_DPRINTF(sc, RT_DEBUG_RX,
1706 "rxdesc: crc error\n");
1710 if (!(ifp->if_flags & IFF_PROMISC)) {
1715 if ((desc_flags & RXDSXR_SRC_IP_CSUM_FAIL) != 0) {
1716 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1717 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1718 m->m_pkthdr.csum_data = 0xffff;
1720 m->m_flags &= ~M_HASFCS;
1723 (*ifp->if_input)(ifp, m);
1725 desc->sdl0 &= ~htole16(RT_RXDESC_SDL0_DDONE);
1727 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
1728 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1730 ring->cur = (ring->cur + 1) % RT_SOFTC_RX_RING_DATA_COUNT;
1736 RT_WRITE(sc, PDMA_BASE + RX_CALC_IDX0,
1737 RT_SOFTC_RX_RING_DATA_COUNT - 1);
1739 RT_WRITE(sc, PDMA_BASE + RX_CALC_IDX0,
1742 RT_DPRINTF(sc, RT_DEBUG_RX, "Rx eof: nframes=%d\n", nframes);
1744 sc->rx_packets += nframes;
1746 return (limit == 0);
1750 * rt_tx_eof - check for successful transmitted frames and mark their
1751 * descriptor as free.
1754 rt_tx_eof(struct rt_softc *sc, struct rt_softc_tx_ring *ring)
1757 struct rt_txdesc *desc;
1758 struct rt_softc_tx_data *data;
1760 int ndescs, nframes;
1768 index = RT_READ(sc, PDMA_BASE + TX_DTX_IDX(ring->qid));
1769 if (ring->desc_next == index)
1774 desc = &ring->desc[ring->desc_next];
1776 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
1777 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1779 if (desc->sdl0 & htole16(RT_TXDESC_SDL0_LASTSEG) ||
1780 desc->sdl1 & htole16(RT_TXDESC_SDL1_LASTSEG)) {
1783 data = &ring->data[ring->data_next];
1785 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
1786 BUS_DMASYNC_POSTWRITE);
1787 bus_dmamap_unload(ring->data_dma_tag, data->dma_map);
1795 RT_SOFTC_TX_RING_LOCK(ring);
1796 ring->data_queued--;
1797 ring->data_next = (ring->data_next + 1) %
1798 RT_SOFTC_TX_RING_DATA_COUNT;
1799 RT_SOFTC_TX_RING_UNLOCK(ring);
1802 desc->sdl0 &= ~htole16(RT_TXDESC_SDL0_DDONE);
1804 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
1805 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1807 RT_SOFTC_TX_RING_LOCK(ring);
1808 ring->desc_queued--;
1809 ring->desc_next = (ring->desc_next + 1) %
1810 RT_SOFTC_TX_RING_DESC_COUNT;
1811 RT_SOFTC_TX_RING_UNLOCK(ring);
1814 RT_DPRINTF(sc, RT_DEBUG_TX,
1815 "Tx eof: qid=%d, ndescs=%d, nframes=%d\n", ring->qid, ndescs,
1820 * rt_update_stats - query statistics counters and update related variables.
1823 rt_update_stats(struct rt_softc *sc)
1828 RT_DPRINTF(sc, RT_DEBUG_STATS, "update statistic: \n");
1829 /* XXX do update stats here */
1833 * rt_watchdog - reinit device on watchdog event.
1836 rt_watchdog(struct rt_softc *sc)
1843 tmp = RT_READ(sc, PSE_BASE + CDMA_OQ_STA);
1845 RT_DPRINTF(sc, RT_DEBUG_WATCHDOG, "watchdog: PSE_IQ_STA=0x%08x\n",
1848 /* XXX: do not reset */
1850 if (((tmp >> P0_IQ_PCNT_SHIFT) & 0xff) != 0) {
1851 sc->tx_queue_not_empty[0]++;
1853 for (ntries = 0; ntries < 10; ntries++) {
1854 tmp = RT_READ(sc, PSE_BASE + PSE_IQ_STA);
1855 if (((tmp >> P0_IQ_PCNT_SHIFT) & 0xff) == 0)
1862 if (((tmp >> P1_IQ_PCNT_SHIFT) & 0xff) != 0) {
1863 sc->tx_queue_not_empty[1]++;
1865 for (ntries = 0; ntries < 10; ntries++) {
1866 tmp = RT_READ(sc, PSE_BASE + PSE_IQ_STA);
1867 if (((tmp >> P1_IQ_PCNT_SHIFT) & 0xff) == 0)
1877 * rt_update_raw_counters - update counters.
1880 rt_update_raw_counters(struct rt_softc *sc)
1883 sc->tx_bytes += RT_READ(sc, CNTR_BASE + GDMA_TX_GBCNT0);
1884 sc->tx_packets += RT_READ(sc, CNTR_BASE + GDMA_TX_GPCNT0);
1885 sc->tx_skip += RT_READ(sc, CNTR_BASE + GDMA_TX_SKIPCNT0);
1886 sc->tx_collision+= RT_READ(sc, CNTR_BASE + GDMA_TX_COLCNT0);
1888 sc->rx_bytes += RT_READ(sc, CNTR_BASE + GDMA_RX_GBCNT0);
1889 sc->rx_packets += RT_READ(sc, CNTR_BASE + GDMA_RX_GPCNT0);
1890 sc->rx_crc_err += RT_READ(sc, CNTR_BASE + GDMA_RX_CSUM_ERCNT0);
1891 sc->rx_short_err+= RT_READ(sc, CNTR_BASE + GDMA_RX_SHORT_ERCNT0);
1892 sc->rx_long_err += RT_READ(sc, CNTR_BASE + GDMA_RX_LONG_ERCNT0);
1893 sc->rx_phy_err += RT_READ(sc, CNTR_BASE + GDMA_RX_FERCNT0);
1894 sc->rx_fifo_overflows+= RT_READ(sc, CNTR_BASE + GDMA_RX_OERCNT0);
1898 rt_intr_enable(struct rt_softc *sc, uint32_t intr_mask)
1902 sc->intr_disable_mask &= ~intr_mask;
1903 tmp = sc->intr_enable_mask & ~sc->intr_disable_mask;
1904 RT_WRITE(sc, GE_PORT_BASE + FE_INT_ENABLE, tmp);
1908 rt_intr_disable(struct rt_softc *sc, uint32_t intr_mask)
1912 sc->intr_disable_mask |= intr_mask;
1913 tmp = sc->intr_enable_mask & ~sc->intr_disable_mask;
1914 RT_WRITE(sc, GE_PORT_BASE + FE_INT_ENABLE, tmp);
1918 * rt_txrx_enable - enable TX/RX DMA
1921 rt_txrx_enable(struct rt_softc *sc)
1929 /* enable Tx/Rx DMA engine */
1930 for (ntries = 0; ntries < 200; ntries++) {
1931 tmp = RT_READ(sc, PDMA_BASE + PDMA_GLO_CFG);
1932 if (!(tmp & (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)))
1938 if (ntries == 200) {
1939 device_printf(sc->dev, "timeout waiting for DMA engine\n");
1945 tmp |= FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
1946 RT_WRITE(sc, PDMA_BASE + PDMA_GLO_CFG, tmp);
1948 /* XXX set Rx filter */
1953 * rt_alloc_rx_ring - allocate RX DMA ring buffer
1956 rt_alloc_rx_ring(struct rt_softc *sc, struct rt_softc_rx_ring *ring)
1958 struct rt_rxdesc *desc;
1959 struct rt_softc_rx_data *data;
1960 bus_dma_segment_t segs[1];
1961 int i, nsegs, error;
1963 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0,
1964 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1965 RT_SOFTC_RX_RING_DATA_COUNT * sizeof(struct rt_rxdesc), 1,
1966 RT_SOFTC_RX_RING_DATA_COUNT * sizeof(struct rt_rxdesc),
1967 0, NULL, NULL, &ring->desc_dma_tag);
1969 device_printf(sc->dev,
1970 "could not create Rx desc DMA tag\n");
1974 error = bus_dmamem_alloc(ring->desc_dma_tag, (void **) &ring->desc,
1975 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_dma_map);
1977 device_printf(sc->dev,
1978 "could not allocate Rx desc DMA memory\n");
1982 error = bus_dmamap_load(ring->desc_dma_tag, ring->desc_dma_map,
1984 RT_SOFTC_RX_RING_DATA_COUNT * sizeof(struct rt_rxdesc),
1985 rt_dma_map_addr, &ring->desc_phys_addr, 0);
1987 device_printf(sc->dev, "could not load Rx desc DMA map\n");
1991 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0,
1992 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1993 MJUMPAGESIZE, 1, MJUMPAGESIZE, 0, NULL, NULL,
1994 &ring->data_dma_tag);
1996 device_printf(sc->dev,
1997 "could not create Rx data DMA tag\n");
2001 for (i = 0; i < RT_SOFTC_RX_RING_DATA_COUNT; i++) {
2002 desc = &ring->desc[i];
2003 data = &ring->data[i];
2005 error = bus_dmamap_create(ring->data_dma_tag, 0,
2008 device_printf(sc->dev, "could not create Rx data DMA "
2013 data->m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR,
2015 if (data->m == NULL) {
2016 device_printf(sc->dev, "could not allocate Rx mbuf\n");
2021 data->m->m_len = data->m->m_pkthdr.len = MJUMPAGESIZE;
2023 error = bus_dmamap_load_mbuf_sg(ring->data_dma_tag,
2024 data->dma_map, data->m, segs, &nsegs, BUS_DMA_NOWAIT);
2026 device_printf(sc->dev,
2027 "could not load Rx mbuf DMA map\n");
2031 KASSERT(nsegs == 1, ("%s: too many DMA segments",
2032 device_get_nameunit(sc->dev)));
2034 /* Add 2 for proper align of RX IP header */
2035 desc->sdp0 = htole32(segs[0].ds_addr+2);
2036 desc->sdl0 = htole32(segs[0].ds_len-2);
2039 error = bus_dmamap_create(ring->data_dma_tag, 0,
2040 &ring->spare_dma_map);
2042 device_printf(sc->dev,
2043 "could not create Rx spare DMA map\n");
2047 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
2048 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2052 rt_free_rx_ring(sc, ring);
2057 * rt_reset_rx_ring - reset RX ring buffer
2060 rt_reset_rx_ring(struct rt_softc *sc, struct rt_softc_rx_ring *ring)
2062 struct rt_rxdesc *desc;
2065 for (i = 0; i < RT_SOFTC_RX_RING_DATA_COUNT; i++) {
2066 desc = &ring->desc[i];
2067 desc->sdl0 &= ~htole16(RT_RXDESC_SDL0_DDONE);
2070 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
2071 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2076 * rt_free_rx_ring - free memory used by RX ring buffer
2079 rt_free_rx_ring(struct rt_softc *sc, struct rt_softc_rx_ring *ring)
2081 struct rt_softc_rx_data *data;
2084 if (ring->desc != NULL) {
2085 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
2086 BUS_DMASYNC_POSTWRITE);
2087 bus_dmamap_unload(ring->desc_dma_tag, ring->desc_dma_map);
2088 bus_dmamem_free(ring->desc_dma_tag, ring->desc,
2089 ring->desc_dma_map);
2092 if (ring->desc_dma_tag != NULL)
2093 bus_dma_tag_destroy(ring->desc_dma_tag);
2095 for (i = 0; i < RT_SOFTC_RX_RING_DATA_COUNT; i++) {
2096 data = &ring->data[i];
2098 if (data->m != NULL) {
2099 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
2100 BUS_DMASYNC_POSTREAD);
2101 bus_dmamap_unload(ring->data_dma_tag, data->dma_map);
2105 if (data->dma_map != NULL)
2106 bus_dmamap_destroy(ring->data_dma_tag, data->dma_map);
2109 if (ring->spare_dma_map != NULL)
2110 bus_dmamap_destroy(ring->data_dma_tag, ring->spare_dma_map);
2112 if (ring->data_dma_tag != NULL)
2113 bus_dma_tag_destroy(ring->data_dma_tag);
2117 * rt_alloc_tx_ring - allocate TX ring buffer
2120 rt_alloc_tx_ring(struct rt_softc *sc, struct rt_softc_tx_ring *ring, int qid)
2122 struct rt_softc_tx_data *data;
2125 mtx_init(&ring->lock, device_get_nameunit(sc->dev), NULL, MTX_DEF);
2127 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0,
2128 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
2129 RT_SOFTC_TX_RING_DESC_COUNT * sizeof(struct rt_txdesc), 1,
2130 RT_SOFTC_TX_RING_DESC_COUNT * sizeof(struct rt_txdesc),
2131 0, NULL, NULL, &ring->desc_dma_tag);
2133 device_printf(sc->dev,
2134 "could not create Tx desc DMA tag\n");
2138 error = bus_dmamem_alloc(ring->desc_dma_tag, (void **) &ring->desc,
2139 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_dma_map);
2141 device_printf(sc->dev,
2142 "could not allocate Tx desc DMA memory\n");
2146 error = bus_dmamap_load(ring->desc_dma_tag, ring->desc_dma_map,
2147 ring->desc, (RT_SOFTC_TX_RING_DESC_COUNT *
2148 sizeof(struct rt_txdesc)), rt_dma_map_addr,
2149 &ring->desc_phys_addr, 0);
2151 device_printf(sc->dev, "could not load Tx desc DMA map\n");
2155 ring->desc_queued = 0;
2157 ring->desc_next = 0;
2159 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0,
2160 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
2161 RT_SOFTC_TX_RING_DATA_COUNT * RT_TX_DATA_SEG0_SIZE, 1,
2162 RT_SOFTC_TX_RING_DATA_COUNT * RT_TX_DATA_SEG0_SIZE,
2163 0, NULL, NULL, &ring->seg0_dma_tag);
2165 device_printf(sc->dev,
2166 "could not create Tx seg0 DMA tag\n");
2170 error = bus_dmamem_alloc(ring->seg0_dma_tag, (void **) &ring->seg0,
2171 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->seg0_dma_map);
2173 device_printf(sc->dev,
2174 "could not allocate Tx seg0 DMA memory\n");
2178 error = bus_dmamap_load(ring->seg0_dma_tag, ring->seg0_dma_map,
2180 RT_SOFTC_TX_RING_DATA_COUNT * RT_TX_DATA_SEG0_SIZE,
2181 rt_dma_map_addr, &ring->seg0_phys_addr, 0);
2183 device_printf(sc->dev, "could not load Tx seg0 DMA map\n");
2187 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0,
2188 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
2189 MJUMPAGESIZE, RT_SOFTC_MAX_SCATTER, MJUMPAGESIZE, 0, NULL, NULL,
2190 &ring->data_dma_tag);
2192 device_printf(sc->dev,
2193 "could not create Tx data DMA tag\n");
2197 for (i = 0; i < RT_SOFTC_TX_RING_DATA_COUNT; i++) {
2198 data = &ring->data[i];
2200 error = bus_dmamap_create(ring->data_dma_tag, 0,
2203 device_printf(sc->dev, "could not create Tx data DMA "
2209 ring->data_queued = 0;
2211 ring->data_next = 0;
2217 rt_free_tx_ring(sc, ring);
2222 * rt_reset_tx_ring - reset TX ring buffer to empty state
2225 rt_reset_tx_ring(struct rt_softc *sc, struct rt_softc_tx_ring *ring)
2227 struct rt_softc_tx_data *data;
2228 struct rt_txdesc *desc;
2231 for (i = 0; i < RT_SOFTC_TX_RING_DESC_COUNT; i++) {
2232 desc = &ring->desc[i];
2238 ring->desc_queued = 0;
2240 ring->desc_next = 0;
2242 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
2243 BUS_DMASYNC_PREWRITE);
2245 bus_dmamap_sync(ring->seg0_dma_tag, ring->seg0_dma_map,
2246 BUS_DMASYNC_PREWRITE);
2248 for (i = 0; i < RT_SOFTC_TX_RING_DATA_COUNT; i++) {
2249 data = &ring->data[i];
2251 if (data->m != NULL) {
2252 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
2253 BUS_DMASYNC_POSTWRITE);
2254 bus_dmamap_unload(ring->data_dma_tag, data->dma_map);
2260 ring->data_queued = 0;
2262 ring->data_next = 0;
2266 * rt_free_tx_ring - free RX ring buffer
2269 rt_free_tx_ring(struct rt_softc *sc, struct rt_softc_tx_ring *ring)
2271 struct rt_softc_tx_data *data;
2274 if (ring->desc != NULL) {
2275 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
2276 BUS_DMASYNC_POSTWRITE);
2277 bus_dmamap_unload(ring->desc_dma_tag, ring->desc_dma_map);
2278 bus_dmamem_free(ring->desc_dma_tag, ring->desc,
2279 ring->desc_dma_map);
2282 if (ring->desc_dma_tag != NULL)
2283 bus_dma_tag_destroy(ring->desc_dma_tag);
2285 if (ring->seg0 != NULL) {
2286 bus_dmamap_sync(ring->seg0_dma_tag, ring->seg0_dma_map,
2287 BUS_DMASYNC_POSTWRITE);
2288 bus_dmamap_unload(ring->seg0_dma_tag, ring->seg0_dma_map);
2289 bus_dmamem_free(ring->seg0_dma_tag, ring->seg0,
2290 ring->seg0_dma_map);
2293 if (ring->seg0_dma_tag != NULL)
2294 bus_dma_tag_destroy(ring->seg0_dma_tag);
2296 for (i = 0; i < RT_SOFTC_TX_RING_DATA_COUNT; i++) {
2297 data = &ring->data[i];
2299 if (data->m != NULL) {
2300 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
2301 BUS_DMASYNC_POSTWRITE);
2302 bus_dmamap_unload(ring->data_dma_tag, data->dma_map);
2306 if (data->dma_map != NULL)
2307 bus_dmamap_destroy(ring->data_dma_tag, data->dma_map);
2310 if (ring->data_dma_tag != NULL)
2311 bus_dma_tag_destroy(ring->data_dma_tag);
2313 mtx_destroy(&ring->lock);
2317 * rt_dma_map_addr - get address of busdma segment
2320 rt_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2325 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
2327 *(bus_addr_t *) arg = segs[0].ds_addr;
2331 * rt_sysctl_attach - attach sysctl nodes for NIC counters.
2334 rt_sysctl_attach(struct rt_softc *sc)
2336 struct sysctl_ctx_list *ctx;
2337 struct sysctl_oid *tree;
2338 struct sysctl_oid *stats;
2340 ctx = device_get_sysctl_ctx(sc->dev);
2341 tree = device_get_sysctl_tree(sc->dev);
2343 /* statistic counters */
2344 stats = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
2345 "stats", CTLFLAG_RD, 0, "statistic");
2347 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2348 "interrupts", CTLFLAG_RD, &sc->interrupts,
2351 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2352 "tx_coherent_interrupts", CTLFLAG_RD, &sc->tx_coherent_interrupts,
2353 "Tx coherent interrupts");
2355 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2356 "rx_coherent_interrupts", CTLFLAG_RD, &sc->rx_coherent_interrupts,
2357 "Rx coherent interrupts");
2359 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2360 "rx_interrupts", CTLFLAG_RD, &sc->rx_interrupts,
2363 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2364 "rx_delay_interrupts", CTLFLAG_RD, &sc->rx_delay_interrupts,
2365 "Rx delay interrupts");
2367 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2368 "TXQ3_interrupts", CTLFLAG_RD, &sc->tx_interrupts[3],
2369 "Tx AC3 interrupts");
2371 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2372 "TXQ2_interrupts", CTLFLAG_RD, &sc->tx_interrupts[2],
2373 "Tx AC2 interrupts");
2375 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2376 "TXQ1_interrupts", CTLFLAG_RD, &sc->tx_interrupts[1],
2377 "Tx AC1 interrupts");
2379 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2380 "TXQ0_interrupts", CTLFLAG_RD, &sc->tx_interrupts[0],
2381 "Tx AC0 interrupts");
2383 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2384 "tx_delay_interrupts", CTLFLAG_RD, &sc->tx_delay_interrupts,
2385 "Tx delay interrupts");
2387 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2388 "TXQ3_desc_queued", CTLFLAG_RD, &sc->tx_ring[3].desc_queued,
2389 0, "Tx AC3 descriptors queued");
2391 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2392 "TXQ3_data_queued", CTLFLAG_RD, &sc->tx_ring[3].data_queued,
2393 0, "Tx AC3 data queued");
2395 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2396 "TXQ2_desc_queued", CTLFLAG_RD, &sc->tx_ring[2].desc_queued,
2397 0, "Tx AC2 descriptors queued");
2399 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2400 "TXQ2_data_queued", CTLFLAG_RD, &sc->tx_ring[2].data_queued,
2401 0, "Tx AC2 data queued");
2403 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2404 "TXQ1_desc_queued", CTLFLAG_RD, &sc->tx_ring[1].desc_queued,
2405 0, "Tx AC1 descriptors queued");
2407 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2408 "TXQ1_data_queued", CTLFLAG_RD, &sc->tx_ring[1].data_queued,
2409 0, "Tx AC1 data queued");
2411 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2412 "TXQ0_desc_queued", CTLFLAG_RD, &sc->tx_ring[0].desc_queued,
2413 0, "Tx AC0 descriptors queued");
2415 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2416 "TXQ0_data_queued", CTLFLAG_RD, &sc->tx_ring[0].data_queued,
2417 0, "Tx AC0 data queued");
2419 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2420 "TXQ3_data_queue_full", CTLFLAG_RD, &sc->tx_data_queue_full[3],
2421 "Tx AC3 data queue full");
2423 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2424 "TXQ2_data_queue_full", CTLFLAG_RD, &sc->tx_data_queue_full[2],
2425 "Tx AC2 data queue full");
2427 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2428 "TXQ1_data_queue_full", CTLFLAG_RD, &sc->tx_data_queue_full[1],
2429 "Tx AC1 data queue full");
2431 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2432 "TXQ0_data_queue_full", CTLFLAG_RD, &sc->tx_data_queue_full[0],
2433 "Tx AC0 data queue full");
2435 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2436 "tx_watchdog_timeouts", CTLFLAG_RD, &sc->tx_watchdog_timeouts,
2437 "Tx watchdog timeouts");
2439 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2440 "tx_defrag_packets", CTLFLAG_RD, &sc->tx_defrag_packets,
2441 "Tx defragmented packets");
2443 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2444 "no_tx_desc_avail", CTLFLAG_RD, &sc->no_tx_desc_avail,
2445 "no Tx descriptors available");
2447 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2448 "rx_mbuf_alloc_errors", CTLFLAG_RD, &sc->rx_mbuf_alloc_errors,
2449 "Rx mbuf allocation errors");
2451 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2452 "rx_mbuf_dmamap_errors", CTLFLAG_RD, &sc->rx_mbuf_dmamap_errors,
2453 "Rx mbuf DMA mapping errors");
2455 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2456 "tx_queue_0_not_empty", CTLFLAG_RD, &sc->tx_queue_not_empty[0],
2457 "Tx queue 0 not empty");
2459 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2460 "tx_queue_1_not_empty", CTLFLAG_RD, &sc->tx_queue_not_empty[1],
2461 "Tx queue 1 not empty");
2463 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2464 "rx_packets", CTLFLAG_RD, &sc->rx_packets,
2467 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2468 "rx_crc_errors", CTLFLAG_RD, &sc->rx_crc_err,
2471 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2472 "rx_phy_errors", CTLFLAG_RD, &sc->rx_phy_err,
2475 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2476 "rx_dup_packets", CTLFLAG_RD, &sc->rx_dup_packets,
2477 "Rx duplicate packets");
2479 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2480 "rx_fifo_overflows", CTLFLAG_RD, &sc->rx_fifo_overflows,
2481 "Rx FIFO overflows");
2483 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2484 "rx_bytes", CTLFLAG_RD, &sc->rx_bytes,
2487 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2488 "rx_long_err", CTLFLAG_RD, &sc->rx_long_err,
2489 "Rx too long frame errors");
2491 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2492 "rx_short_err", CTLFLAG_RD, &sc->rx_short_err,
2493 "Rx too short frame errors");
2495 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2496 "tx_bytes", CTLFLAG_RD, &sc->tx_bytes,
2499 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2500 "tx_packets", CTLFLAG_RD, &sc->tx_packets,
2503 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2504 "tx_skip", CTLFLAG_RD, &sc->tx_skip,
2505 "Tx skip count for GDMA ports");
2507 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2508 "tx_collision", CTLFLAG_RD, &sc->tx_collision,
2509 "Tx collision count for GDMA ports");
2512 #ifdef IF_RT_PHY_SUPPORT
2514 rt_miibus_readreg(device_t dev, int phy, int reg)
2516 struct rt_softc *sc = device_get_softc(dev);
2519 * PSEUDO_PHYAD is a special value for indicate switch attached.
2520 * No one PHY use PSEUDO_PHYAD (0x1e) address.
2523 /* Fake PHY ID for bfeswitch attach */
2526 return (BMSR_EXTSTAT|BMSR_MEDIAMASK);
2528 return (0x40); /* As result of faking */
2529 case MII_PHYIDR2: /* PHY will detect as */
2530 return (0x6250); /* bfeswitch */
2534 /* Wait prev command done if any */
2535 while (RT_READ(sc, MDIO_ACCESS) & MDIO_CMD_ONGO);
2536 RT_WRITE(sc, MDIO_ACCESS,
2538 ((phy << MDIO_PHY_ADDR_SHIFT) & MDIO_PHY_ADDR_MASK) ||
2539 ((reg << MDIO_PHYREG_ADDR_SHIFT) & MDIO_PHYREG_ADDR_MASK));
2540 while (RT_READ(sc, MDIO_ACCESS) & MDIO_CMD_ONGO);
2542 return (RT_READ(sc, MDIO_ACCESS) & MDIO_PHY_DATA_MASK);
2546 rt_miibus_writereg(device_t dev, int phy, int reg, int val)
2548 struct rt_softc *sc = device_get_softc(dev);
2550 /* Wait prev command done if any */
2551 while (RT_READ(sc, MDIO_ACCESS) & MDIO_CMD_ONGO);
2552 RT_WRITE(sc, MDIO_ACCESS,
2553 MDIO_CMD_ONGO || MDIO_CMD_WR ||
2554 ((phy << MDIO_PHY_ADDR_SHIFT) & MDIO_PHY_ADDR_MASK) ||
2555 ((reg << MDIO_PHYREG_ADDR_SHIFT) & MDIO_PHYREG_ADDR_MASK) ||
2556 (val & MDIO_PHY_DATA_MASK));
2557 while (RT_READ(sc, MDIO_ACCESS) & MDIO_CMD_ONGO);
2563 rt_miibus_statchg(device_t dev)
2565 struct rt_softc *sc = device_get_softc(dev);
2566 struct mii_data *mii;
2568 mii = device_get_softc(sc->rt_miibus);
2570 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
2571 (IFM_ACTIVE | IFM_AVALID)) {
2572 switch (IFM_SUBTYPE(mii->mii_media_active)) {
2575 /* XXX check link here */
2583 #endif /* IF_RT_PHY_SUPPORT */
2585 static device_method_t rt_dev_methods[] =
2587 DEVMETHOD(device_probe, rt_probe),
2588 DEVMETHOD(device_attach, rt_attach),
2589 DEVMETHOD(device_detach, rt_detach),
2590 DEVMETHOD(device_shutdown, rt_shutdown),
2591 DEVMETHOD(device_suspend, rt_suspend),
2592 DEVMETHOD(device_resume, rt_resume),
2594 #ifdef IF_RT_PHY_SUPPORT
2596 DEVMETHOD(miibus_readreg, rt_miibus_readreg),
2597 DEVMETHOD(miibus_writereg, rt_miibus_writereg),
2598 DEVMETHOD(miibus_statchg, rt_miibus_statchg),
2604 static driver_t rt_driver =
2608 sizeof(struct rt_softc)
2611 static devclass_t rt_dev_class;
2613 DRIVER_MODULE(rt, nexus, rt_driver, rt_dev_class, 0, 0);
2614 MODULE_DEPEND(rt, ether, 1, 1, 1);
2615 MODULE_DEPEND(rt, miibus, 1, 1, 1);