2 * Copyright (c) 2012-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
36 #if EFSYS_OPT_MON_MCDI
40 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
42 #include "ef10_tlv_layout.h"
44 __checkReturn efx_rc_t
45 efx_mcdi_get_port_assignment(
47 __out uint32_t *portp)
50 uint8_t payload[MAX(MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN,
51 MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN)];
54 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
55 enp->en_family == EFX_FAMILY_MEDFORD);
57 (void) memset(payload, 0, sizeof (payload));
58 req.emr_cmd = MC_CMD_GET_PORT_ASSIGNMENT;
59 req.emr_in_buf = payload;
60 req.emr_in_length = MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN;
61 req.emr_out_buf = payload;
62 req.emr_out_length = MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN;
64 efx_mcdi_execute(enp, &req);
66 if (req.emr_rc != 0) {
71 if (req.emr_out_length_used < MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN) {
76 *portp = MCDI_OUT_DWORD(req, GET_PORT_ASSIGNMENT_OUT_PORT);
83 EFSYS_PROBE1(fail1, efx_rc_t, rc);
88 __checkReturn efx_rc_t
89 efx_mcdi_get_port_modes(
91 __out uint32_t *modesp,
92 __out_opt uint32_t *current_modep)
95 uint8_t payload[MAX(MC_CMD_GET_PORT_MODES_IN_LEN,
96 MC_CMD_GET_PORT_MODES_OUT_LEN)];
99 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
100 enp->en_family == EFX_FAMILY_MEDFORD);
102 (void) memset(payload, 0, sizeof (payload));
103 req.emr_cmd = MC_CMD_GET_PORT_MODES;
104 req.emr_in_buf = payload;
105 req.emr_in_length = MC_CMD_GET_PORT_MODES_IN_LEN;
106 req.emr_out_buf = payload;
107 req.emr_out_length = MC_CMD_GET_PORT_MODES_OUT_LEN;
109 efx_mcdi_execute(enp, &req);
111 if (req.emr_rc != 0) {
117 * Require only Modes and DefaultMode fields, unless the current mode
118 * was requested (CurrentMode field was added for Medford).
120 if (req.emr_out_length_used <
121 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST) {
125 if ((current_modep != NULL) && (req.emr_out_length_used <
126 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST + 4)) {
131 *modesp = MCDI_OUT_DWORD(req, GET_PORT_MODES_OUT_MODES);
133 if (current_modep != NULL) {
134 *current_modep = MCDI_OUT_DWORD(req,
135 GET_PORT_MODES_OUT_CURRENT_MODE);
145 EFSYS_PROBE1(fail1, efx_rc_t, rc);
150 __checkReturn efx_rc_t
151 ef10_nic_get_port_mode_bandwidth(
152 __in uint32_t port_mode,
153 __out uint32_t *bandwidth_mbpsp)
159 case TLV_PORT_MODE_10G:
162 case TLV_PORT_MODE_10G_10G:
163 bandwidth = 10000 * 2;
165 case TLV_PORT_MODE_10G_10G_10G_10G:
166 case TLV_PORT_MODE_10G_10G_10G_10G_Q:
167 case TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2:
168 case TLV_PORT_MODE_10G_10G_10G_10G_Q2:
169 bandwidth = 10000 * 4;
171 case TLV_PORT_MODE_40G:
174 case TLV_PORT_MODE_40G_40G:
175 bandwidth = 40000 * 2;
177 case TLV_PORT_MODE_40G_10G_10G:
178 case TLV_PORT_MODE_10G_10G_40G:
179 bandwidth = 40000 + (10000 * 2);
186 *bandwidth_mbpsp = bandwidth;
191 EFSYS_PROBE1(fail1, efx_rc_t, rc);
196 static __checkReturn efx_rc_t
197 efx_mcdi_vadaptor_alloc(
199 __in uint32_t port_id)
202 uint8_t payload[MAX(MC_CMD_VADAPTOR_ALLOC_IN_LEN,
203 MC_CMD_VADAPTOR_ALLOC_OUT_LEN)];
206 EFSYS_ASSERT3U(enp->en_vport_id, ==, EVB_PORT_ID_NULL);
208 (void) memset(payload, 0, sizeof (payload));
209 req.emr_cmd = MC_CMD_VADAPTOR_ALLOC;
210 req.emr_in_buf = payload;
211 req.emr_in_length = MC_CMD_VADAPTOR_ALLOC_IN_LEN;
212 req.emr_out_buf = payload;
213 req.emr_out_length = MC_CMD_VADAPTOR_ALLOC_OUT_LEN;
215 MCDI_IN_SET_DWORD(req, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
216 MCDI_IN_POPULATE_DWORD_1(req, VADAPTOR_ALLOC_IN_FLAGS,
217 VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED,
218 enp->en_nic_cfg.enc_allow_set_mac_with_installed_filters ? 1 : 0);
220 efx_mcdi_execute(enp, &req);
222 if (req.emr_rc != 0) {
230 EFSYS_PROBE1(fail1, efx_rc_t, rc);
235 static __checkReturn efx_rc_t
236 efx_mcdi_vadaptor_free(
238 __in uint32_t port_id)
241 uint8_t payload[MAX(MC_CMD_VADAPTOR_FREE_IN_LEN,
242 MC_CMD_VADAPTOR_FREE_OUT_LEN)];
245 (void) memset(payload, 0, sizeof (payload));
246 req.emr_cmd = MC_CMD_VADAPTOR_FREE;
247 req.emr_in_buf = payload;
248 req.emr_in_length = MC_CMD_VADAPTOR_FREE_IN_LEN;
249 req.emr_out_buf = payload;
250 req.emr_out_length = MC_CMD_VADAPTOR_FREE_OUT_LEN;
252 MCDI_IN_SET_DWORD(req, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
254 efx_mcdi_execute(enp, &req);
256 if (req.emr_rc != 0) {
264 EFSYS_PROBE1(fail1, efx_rc_t, rc);
269 __checkReturn efx_rc_t
270 efx_mcdi_get_mac_address_pf(
272 __out_ecount_opt(6) uint8_t mac_addrp[6])
275 uint8_t payload[MAX(MC_CMD_GET_MAC_ADDRESSES_IN_LEN,
276 MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)];
279 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
280 enp->en_family == EFX_FAMILY_MEDFORD);
282 (void) memset(payload, 0, sizeof (payload));
283 req.emr_cmd = MC_CMD_GET_MAC_ADDRESSES;
284 req.emr_in_buf = payload;
285 req.emr_in_length = MC_CMD_GET_MAC_ADDRESSES_IN_LEN;
286 req.emr_out_buf = payload;
287 req.emr_out_length = MC_CMD_GET_MAC_ADDRESSES_OUT_LEN;
289 efx_mcdi_execute(enp, &req);
291 if (req.emr_rc != 0) {
296 if (req.emr_out_length_used < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) {
301 if (MCDI_OUT_DWORD(req, GET_MAC_ADDRESSES_OUT_MAC_COUNT) < 1) {
306 if (mac_addrp != NULL) {
309 addrp = MCDI_OUT2(req, uint8_t,
310 GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE);
312 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
322 EFSYS_PROBE1(fail1, efx_rc_t, rc);
327 __checkReturn efx_rc_t
328 efx_mcdi_get_mac_address_vf(
330 __out_ecount_opt(6) uint8_t mac_addrp[6])
333 uint8_t payload[MAX(MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN,
334 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX)];
337 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
338 enp->en_family == EFX_FAMILY_MEDFORD);
340 (void) memset(payload, 0, sizeof (payload));
341 req.emr_cmd = MC_CMD_VPORT_GET_MAC_ADDRESSES;
342 req.emr_in_buf = payload;
343 req.emr_in_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN;
344 req.emr_out_buf = payload;
345 req.emr_out_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX;
347 MCDI_IN_SET_DWORD(req, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
348 EVB_PORT_ID_ASSIGNED);
350 efx_mcdi_execute(enp, &req);
352 if (req.emr_rc != 0) {
357 if (req.emr_out_length_used <
358 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN) {
363 if (MCDI_OUT_DWORD(req,
364 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT) < 1) {
369 if (mac_addrp != NULL) {
372 addrp = MCDI_OUT2(req, uint8_t,
373 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR);
375 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
385 EFSYS_PROBE1(fail1, efx_rc_t, rc);
390 __checkReturn efx_rc_t
393 __out uint32_t *sys_freqp,
394 __out uint32_t *dpcpu_freqp)
397 uint8_t payload[MAX(MC_CMD_GET_CLOCK_IN_LEN,
398 MC_CMD_GET_CLOCK_OUT_LEN)];
401 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
402 enp->en_family == EFX_FAMILY_MEDFORD);
404 (void) memset(payload, 0, sizeof (payload));
405 req.emr_cmd = MC_CMD_GET_CLOCK;
406 req.emr_in_buf = payload;
407 req.emr_in_length = MC_CMD_GET_CLOCK_IN_LEN;
408 req.emr_out_buf = payload;
409 req.emr_out_length = MC_CMD_GET_CLOCK_OUT_LEN;
411 efx_mcdi_execute(enp, &req);
413 if (req.emr_rc != 0) {
418 if (req.emr_out_length_used < MC_CMD_GET_CLOCK_OUT_LEN) {
423 *sys_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_SYS_FREQ);
424 if (*sys_freqp == 0) {
428 *dpcpu_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_DPCPU_FREQ);
429 if (*dpcpu_freqp == 0) {
443 EFSYS_PROBE1(fail1, efx_rc_t, rc);
448 __checkReturn efx_rc_t
449 efx_mcdi_get_vector_cfg(
451 __out_opt uint32_t *vec_basep,
452 __out_opt uint32_t *pf_nvecp,
453 __out_opt uint32_t *vf_nvecp)
456 uint8_t payload[MAX(MC_CMD_GET_VECTOR_CFG_IN_LEN,
457 MC_CMD_GET_VECTOR_CFG_OUT_LEN)];
460 (void) memset(payload, 0, sizeof (payload));
461 req.emr_cmd = MC_CMD_GET_VECTOR_CFG;
462 req.emr_in_buf = payload;
463 req.emr_in_length = MC_CMD_GET_VECTOR_CFG_IN_LEN;
464 req.emr_out_buf = payload;
465 req.emr_out_length = MC_CMD_GET_VECTOR_CFG_OUT_LEN;
467 efx_mcdi_execute(enp, &req);
469 if (req.emr_rc != 0) {
474 if (req.emr_out_length_used < MC_CMD_GET_VECTOR_CFG_OUT_LEN) {
479 if (vec_basep != NULL)
480 *vec_basep = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VEC_BASE);
481 if (pf_nvecp != NULL)
482 *pf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_PF);
483 if (vf_nvecp != NULL)
484 *vf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_VF);
491 EFSYS_PROBE1(fail1, efx_rc_t, rc);
496 static __checkReturn efx_rc_t
497 efx_mcdi_get_capabilities(
499 __out uint32_t *flagsp,
500 __out uint32_t *flags2p,
501 __out uint32_t *tso2ncp)
504 uint8_t payload[MAX(MC_CMD_GET_CAPABILITIES_IN_LEN,
505 MC_CMD_GET_CAPABILITIES_V2_OUT_LEN)];
508 (void) memset(payload, 0, sizeof (payload));
509 req.emr_cmd = MC_CMD_GET_CAPABILITIES;
510 req.emr_in_buf = payload;
511 req.emr_in_length = MC_CMD_GET_CAPABILITIES_IN_LEN;
512 req.emr_out_buf = payload;
513 req.emr_out_length = MC_CMD_GET_CAPABILITIES_V2_OUT_LEN;
515 efx_mcdi_execute(enp, &req);
517 if (req.emr_rc != 0) {
522 if (req.emr_out_length_used < MC_CMD_GET_CAPABILITIES_OUT_LEN) {
527 *flagsp = MCDI_OUT_DWORD(req, GET_CAPABILITIES_OUT_FLAGS1);
529 if (req.emr_out_length_used < MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) {
533 *flags2p = MCDI_OUT_DWORD(req, GET_CAPABILITIES_V2_OUT_FLAGS2);
534 *tso2ncp = MCDI_OUT_WORD(req,
535 GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS);
543 EFSYS_PROBE1(fail1, efx_rc_t, rc);
549 static __checkReturn efx_rc_t
552 __in uint32_t min_vi_count,
553 __in uint32_t max_vi_count,
554 __out uint32_t *vi_basep,
555 __out uint32_t *vi_countp,
556 __out uint32_t *vi_shiftp)
559 uint8_t payload[MAX(MC_CMD_ALLOC_VIS_IN_LEN,
560 MC_CMD_ALLOC_VIS_OUT_LEN)];
563 if (vi_countp == NULL) {
568 (void) memset(payload, 0, sizeof (payload));
569 req.emr_cmd = MC_CMD_ALLOC_VIS;
570 req.emr_in_buf = payload;
571 req.emr_in_length = MC_CMD_ALLOC_VIS_IN_LEN;
572 req.emr_out_buf = payload;
573 req.emr_out_length = MC_CMD_ALLOC_VIS_OUT_LEN;
575 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MIN_VI_COUNT, min_vi_count);
576 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MAX_VI_COUNT, max_vi_count);
578 efx_mcdi_execute(enp, &req);
580 if (req.emr_rc != 0) {
585 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_OUT_LEN) {
590 *vi_basep = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_BASE);
591 *vi_countp = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_COUNT);
593 /* Report VI_SHIFT if available (always zero for Huntington) */
594 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_EXT_OUT_LEN)
597 *vi_shiftp = MCDI_OUT_DWORD(req, ALLOC_VIS_EXT_OUT_VI_SHIFT);
606 EFSYS_PROBE1(fail1, efx_rc_t, rc);
612 static __checkReturn efx_rc_t
619 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_IN_LEN == 0);
620 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_OUT_LEN == 0);
622 req.emr_cmd = MC_CMD_FREE_VIS;
623 req.emr_in_buf = NULL;
624 req.emr_in_length = 0;
625 req.emr_out_buf = NULL;
626 req.emr_out_length = 0;
628 efx_mcdi_execute_quiet(enp, &req);
630 /* Ignore ELREADY (no allocated VIs, so nothing to free) */
631 if ((req.emr_rc != 0) && (req.emr_rc != EALREADY)) {
639 EFSYS_PROBE1(fail1, efx_rc_t, rc);
645 static __checkReturn efx_rc_t
646 efx_mcdi_alloc_piobuf(
648 __out efx_piobuf_handle_t *handlep)
651 uint8_t payload[MAX(MC_CMD_ALLOC_PIOBUF_IN_LEN,
652 MC_CMD_ALLOC_PIOBUF_OUT_LEN)];
655 if (handlep == NULL) {
660 (void) memset(payload, 0, sizeof (payload));
661 req.emr_cmd = MC_CMD_ALLOC_PIOBUF;
662 req.emr_in_buf = payload;
663 req.emr_in_length = MC_CMD_ALLOC_PIOBUF_IN_LEN;
664 req.emr_out_buf = payload;
665 req.emr_out_length = MC_CMD_ALLOC_PIOBUF_OUT_LEN;
667 efx_mcdi_execute_quiet(enp, &req);
669 if (req.emr_rc != 0) {
674 if (req.emr_out_length_used < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
679 *handlep = MCDI_OUT_DWORD(req, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
688 EFSYS_PROBE1(fail1, efx_rc_t, rc);
693 static __checkReturn efx_rc_t
694 efx_mcdi_free_piobuf(
696 __in efx_piobuf_handle_t handle)
699 uint8_t payload[MAX(MC_CMD_FREE_PIOBUF_IN_LEN,
700 MC_CMD_FREE_PIOBUF_OUT_LEN)];
703 (void) memset(payload, 0, sizeof (payload));
704 req.emr_cmd = MC_CMD_FREE_PIOBUF;
705 req.emr_in_buf = payload;
706 req.emr_in_length = MC_CMD_FREE_PIOBUF_IN_LEN;
707 req.emr_out_buf = payload;
708 req.emr_out_length = MC_CMD_FREE_PIOBUF_OUT_LEN;
710 MCDI_IN_SET_DWORD(req, FREE_PIOBUF_IN_PIOBUF_HANDLE, handle);
712 efx_mcdi_execute_quiet(enp, &req);
714 if (req.emr_rc != 0) {
722 EFSYS_PROBE1(fail1, efx_rc_t, rc);
727 static __checkReturn efx_rc_t
728 efx_mcdi_link_piobuf(
730 __in uint32_t vi_index,
731 __in efx_piobuf_handle_t handle)
734 uint8_t payload[MAX(MC_CMD_LINK_PIOBUF_IN_LEN,
735 MC_CMD_LINK_PIOBUF_OUT_LEN)];
738 (void) memset(payload, 0, sizeof (payload));
739 req.emr_cmd = MC_CMD_LINK_PIOBUF;
740 req.emr_in_buf = payload;
741 req.emr_in_length = MC_CMD_LINK_PIOBUF_IN_LEN;
742 req.emr_out_buf = payload;
743 req.emr_out_length = MC_CMD_LINK_PIOBUF_OUT_LEN;
745 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_PIOBUF_HANDLE, handle);
746 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
748 efx_mcdi_execute(enp, &req);
750 if (req.emr_rc != 0) {
758 EFSYS_PROBE1(fail1, efx_rc_t, rc);
763 static __checkReturn efx_rc_t
764 efx_mcdi_unlink_piobuf(
766 __in uint32_t vi_index)
769 uint8_t payload[MAX(MC_CMD_UNLINK_PIOBUF_IN_LEN,
770 MC_CMD_UNLINK_PIOBUF_OUT_LEN)];
773 (void) memset(payload, 0, sizeof (payload));
774 req.emr_cmd = MC_CMD_UNLINK_PIOBUF;
775 req.emr_in_buf = payload;
776 req.emr_in_length = MC_CMD_UNLINK_PIOBUF_IN_LEN;
777 req.emr_out_buf = payload;
778 req.emr_out_length = MC_CMD_UNLINK_PIOBUF_OUT_LEN;
780 MCDI_IN_SET_DWORD(req, UNLINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
782 efx_mcdi_execute_quiet(enp, &req);
784 if (req.emr_rc != 0) {
792 EFSYS_PROBE1(fail1, efx_rc_t, rc);
798 ef10_nic_alloc_piobufs(
800 __in uint32_t max_piobuf_count)
802 efx_piobuf_handle_t *handlep;
805 EFSYS_ASSERT3U(max_piobuf_count, <=,
806 EFX_ARRAY_SIZE(enp->en_arch.ef10.ena_piobuf_handle));
808 enp->en_arch.ef10.ena_piobuf_count = 0;
810 for (i = 0; i < max_piobuf_count; i++) {
811 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
813 if (efx_mcdi_alloc_piobuf(enp, handlep) != 0)
816 enp->en_arch.ef10.ena_pio_alloc_map[i] = 0;
817 enp->en_arch.ef10.ena_piobuf_count++;
823 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
824 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
826 efx_mcdi_free_piobuf(enp, *handlep);
827 *handlep = EFX_PIOBUF_HANDLE_INVALID;
829 enp->en_arch.ef10.ena_piobuf_count = 0;
834 ef10_nic_free_piobufs(
837 efx_piobuf_handle_t *handlep;
840 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
841 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
843 efx_mcdi_free_piobuf(enp, *handlep);
844 *handlep = EFX_PIOBUF_HANDLE_INVALID;
846 enp->en_arch.ef10.ena_piobuf_count = 0;
849 /* Sub-allocate a block from a piobuf */
850 __checkReturn efx_rc_t
852 __inout efx_nic_t *enp,
853 __out uint32_t *bufnump,
854 __out efx_piobuf_handle_t *handlep,
855 __out uint32_t *blknump,
856 __out uint32_t *offsetp,
859 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
860 efx_drv_cfg_t *edcp = &enp->en_drv_cfg;
861 uint32_t blk_per_buf;
865 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
866 enp->en_family == EFX_FAMILY_MEDFORD);
867 EFSYS_ASSERT(bufnump);
868 EFSYS_ASSERT(handlep);
869 EFSYS_ASSERT(blknump);
870 EFSYS_ASSERT(offsetp);
873 if ((edcp->edc_pio_alloc_size == 0) ||
874 (enp->en_arch.ef10.ena_piobuf_count == 0)) {
878 blk_per_buf = encp->enc_piobuf_size / edcp->edc_pio_alloc_size;
880 for (buf = 0; buf < enp->en_arch.ef10.ena_piobuf_count; buf++) {
881 uint32_t *map = &enp->en_arch.ef10.ena_pio_alloc_map[buf];
886 EFSYS_ASSERT3U(blk_per_buf, <=, (8 * sizeof (*map)));
887 for (blk = 0; blk < blk_per_buf; blk++) {
888 if ((*map & (1u << blk)) == 0) {
898 *handlep = enp->en_arch.ef10.ena_piobuf_handle[buf];
901 *sizep = edcp->edc_pio_alloc_size;
902 *offsetp = blk * (*sizep);
909 EFSYS_PROBE1(fail1, efx_rc_t, rc);
914 /* Free a piobuf sub-allocated block */
915 __checkReturn efx_rc_t
917 __inout efx_nic_t *enp,
918 __in uint32_t bufnum,
919 __in uint32_t blknum)
924 if ((bufnum >= enp->en_arch.ef10.ena_piobuf_count) ||
925 (blknum >= (8 * sizeof (*map)))) {
930 map = &enp->en_arch.ef10.ena_pio_alloc_map[bufnum];
931 if ((*map & (1u << blknum)) == 0) {
935 *map &= ~(1u << blknum);
942 EFSYS_PROBE1(fail1, efx_rc_t, rc);
947 __checkReturn efx_rc_t
949 __inout efx_nic_t *enp,
950 __in uint32_t vi_index,
951 __in efx_piobuf_handle_t handle)
953 return (efx_mcdi_link_piobuf(enp, vi_index, handle));
956 __checkReturn efx_rc_t
958 __inout efx_nic_t *enp,
959 __in uint32_t vi_index)
961 return (efx_mcdi_unlink_piobuf(enp, vi_index));
964 static __checkReturn efx_rc_t
965 ef10_mcdi_get_pf_count(
967 __out uint32_t *pf_countp)
970 uint8_t payload[MAX(MC_CMD_GET_PF_COUNT_IN_LEN,
971 MC_CMD_GET_PF_COUNT_OUT_LEN)];
974 (void) memset(payload, 0, sizeof (payload));
975 req.emr_cmd = MC_CMD_GET_PF_COUNT;
976 req.emr_in_buf = payload;
977 req.emr_in_length = MC_CMD_GET_PF_COUNT_IN_LEN;
978 req.emr_out_buf = payload;
979 req.emr_out_length = MC_CMD_GET_PF_COUNT_OUT_LEN;
981 efx_mcdi_execute(enp, &req);
983 if (req.emr_rc != 0) {
988 if (req.emr_out_length_used < MC_CMD_GET_PF_COUNT_OUT_LEN) {
993 *pf_countp = *MCDI_OUT(req, uint8_t,
994 MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST);
996 EFSYS_ASSERT(*pf_countp != 0);
1003 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1008 __checkReturn efx_rc_t
1009 ef10_get_datapath_caps(
1010 __in efx_nic_t *enp)
1012 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1018 if ((rc = efx_mcdi_get_capabilities(enp, &flags, &flags2,
1022 if ((rc = ef10_mcdi_get_pf_count(enp, &encp->enc_hw_pf_count)) != 0)
1025 #define CAP_FLAG(flags1, field) \
1026 ((flags1) & (1 << (MC_CMD_GET_CAPABILITIES_V2_OUT_ ## field ## _LBN)))
1028 #define CAP_FLAG2(flags2, field) \
1029 ((flags2) & (1 << (MC_CMD_GET_CAPABILITIES_V2_OUT_ ## field ## _LBN)))
1032 * Huntington RXDP firmware inserts a 0 or 14 byte prefix.
1033 * We only support the 14 byte prefix here.
1035 if (CAP_FLAG(flags, RX_PREFIX_LEN_14) == 0) {
1039 encp->enc_rx_prefix_size = 14;
1041 /* Check if the firmware supports TSO */
1042 encp->enc_fw_assisted_tso_enabled =
1043 CAP_FLAG(flags, TX_TSO) ? B_TRUE : B_FALSE;
1045 /* Check if the firmware supports FATSOv2 */
1046 encp->enc_fw_assisted_tso_v2_enabled =
1047 CAP_FLAG2(flags2, TX_TSO_V2) ? B_TRUE : B_FALSE;
1049 /* Get the number of TSO contexts (FATSOv2) */
1050 encp->enc_fw_assisted_tso_v2_n_contexts =
1051 CAP_FLAG2(flags2, TX_TSO_V2) ? tso2nc : 0;
1053 /* Check if the firmware has vadapter/vport/vswitch support */
1054 encp->enc_datapath_cap_evb =
1055 CAP_FLAG(flags, EVB) ? B_TRUE : B_FALSE;
1057 /* Check if the firmware supports VLAN insertion */
1058 encp->enc_hw_tx_insert_vlan_enabled =
1059 CAP_FLAG(flags, TX_VLAN_INSERTION) ? B_TRUE : B_FALSE;
1061 /* Check if the firmware supports RX event batching */
1062 encp->enc_rx_batching_enabled =
1063 CAP_FLAG(flags, RX_BATCHING) ? B_TRUE : B_FALSE;
1066 * Even if batching isn't reported as supported, we may still get
1069 encp->enc_rx_batch_max = 16;
1071 /* Check if the firmware supports disabling scatter on RXQs */
1072 encp->enc_rx_disable_scatter_supported =
1073 CAP_FLAG(flags, RX_DISABLE_SCATTER) ? B_TRUE : B_FALSE;
1075 /* Check if the firmware supports set mac with running filters */
1076 encp->enc_allow_set_mac_with_installed_filters =
1077 CAP_FLAG(flags, VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED) ?
1081 * Check if firmware supports the extended MC_CMD_SET_MAC, which allows
1082 * specifying which parameters to configure.
1084 encp->enc_enhanced_set_mac_supported =
1085 CAP_FLAG(flags, SET_MAC_ENHANCED) ? B_TRUE : B_FALSE;
1088 * Check if firmware supports version 2 of MC_CMD_INIT_EVQ, which allows
1089 * us to let the firmware choose the settings to use on an EVQ.
1091 encp->enc_init_evq_v2_supported =
1092 CAP_FLAG2(flags2, INIT_EVQ_V2) ? B_TRUE : B_FALSE;
1095 * Check if firmware provides packet memory and Rx datapath
1098 encp->enc_pm_and_rxdp_counters =
1099 CAP_FLAG(flags, PM_AND_RXDP_COUNTERS) ? B_TRUE : B_FALSE;
1102 * Check if the 40G MAC hardware is capable of reporting
1103 * statistics for Tx size bins.
1105 encp->enc_mac_stats_40g_tx_size_bins =
1106 CAP_FLAG2(flags2, MAC_STATS_40G_TX_SIZE_BINS) ? B_TRUE : B_FALSE;
1116 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1122 #define EF10_LEGACY_PF_PRIVILEGE_MASK \
1123 (MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN | \
1124 MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK | \
1125 MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD | \
1126 MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP | \
1127 MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS | \
1128 MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING | \
1129 MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST | \
1130 MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST | \
1131 MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST | \
1132 MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST | \
1133 MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS)
1135 #define EF10_LEGACY_VF_PRIVILEGE_MASK 0
1138 __checkReturn efx_rc_t
1139 ef10_get_privilege_mask(
1140 __in efx_nic_t *enp,
1141 __out uint32_t *maskp)
1143 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1147 if ((rc = efx_mcdi_privilege_mask(enp, encp->enc_pf, encp->enc_vf,
1152 /* Fallback for old firmware without privilege mask support */
1153 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
1154 /* Assume PF has admin privilege */
1155 mask = EF10_LEGACY_PF_PRIVILEGE_MASK;
1157 /* VF is always unprivileged by default */
1158 mask = EF10_LEGACY_VF_PRIVILEGE_MASK;
1167 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1174 * Table of mapping schemes from port number to the number of the external
1175 * connector on the board. The external numbering does not distinguish
1176 * off-board separated outputs such as from multi-headed cables.
1178 * The count of adjacent port numbers that map to each external port
1179 * and the offset in the numbering, is determined by the chip family and
1180 * current port mode.
1182 * For the Huntington family, the current port mode cannot be discovered,
1183 * so the mapping used is instead the last match in the table to the full
1184 * set of port modes to which the NIC can be configured. Therefore the
1185 * ordering of entries in the the mapping table is significant.
1188 efx_family_t family;
1189 uint32_t modes_mask;
1192 } __ef10_external_port_mappings[] = {
1193 /* Supported modes with 1 output per external port */
1195 EFX_FAMILY_HUNTINGTON,
1196 (1 << TLV_PORT_MODE_10G) |
1197 (1 << TLV_PORT_MODE_10G_10G) |
1198 (1 << TLV_PORT_MODE_10G_10G_10G_10G),
1204 (1 << TLV_PORT_MODE_10G) |
1205 (1 << TLV_PORT_MODE_10G_10G),
1209 /* Supported modes with 2 outputs per external port */
1211 EFX_FAMILY_HUNTINGTON,
1212 (1 << TLV_PORT_MODE_40G) |
1213 (1 << TLV_PORT_MODE_40G_40G) |
1214 (1 << TLV_PORT_MODE_40G_10G_10G) |
1215 (1 << TLV_PORT_MODE_10G_10G_40G),
1221 (1 << TLV_PORT_MODE_40G) |
1222 (1 << TLV_PORT_MODE_40G_40G) |
1223 (1 << TLV_PORT_MODE_40G_10G_10G) |
1224 (1 << TLV_PORT_MODE_10G_10G_40G) |
1225 (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2),
1229 /* Supported modes with 4 outputs per external port */
1232 (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q) |
1233 (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q1),
1239 (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q2),
1245 __checkReturn efx_rc_t
1246 ef10_external_port_mapping(
1247 __in efx_nic_t *enp,
1249 __out uint8_t *external_portp)
1253 uint32_t port_modes;
1256 int32_t count = 1; /* Default 1-1 mapping */
1257 int32_t offset = 1; /* Default starting external port number */
1259 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes, ¤t)) != 0) {
1261 * No current port mode information
1262 * - infer mapping from available modes
1264 if ((rc = efx_mcdi_get_port_modes(enp,
1265 &port_modes, NULL)) != 0) {
1267 * No port mode information available
1268 * - use default mapping
1273 /* Only need to scan the current mode */
1274 port_modes = 1 << current;
1278 * Infer the internal port -> external port mapping from
1279 * the possible port modes for this NIC.
1281 for (i = 0; i < EFX_ARRAY_SIZE(__ef10_external_port_mappings); ++i) {
1282 if (__ef10_external_port_mappings[i].family !=
1285 matches = (__ef10_external_port_mappings[i].modes_mask &
1288 count = __ef10_external_port_mappings[i].count;
1289 offset = __ef10_external_port_mappings[i].offset;
1290 port_modes &= ~matches;
1294 if (port_modes != 0) {
1295 /* Some advertised modes are not supported */
1302 * Scale as required by last matched mode and then convert to
1303 * correctly offset numbering
1305 *external_portp = (uint8_t)((port / count) + offset);
1309 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1315 __checkReturn efx_rc_t
1317 __in efx_nic_t *enp)
1319 const efx_nic_ops_t *enop = enp->en_enop;
1320 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1321 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1324 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1325 enp->en_family == EFX_FAMILY_MEDFORD);
1327 /* Read and clear any assertion state */
1328 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
1331 /* Exit the assertion handler */
1332 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
1336 if ((rc = efx_mcdi_drv_attach(enp, B_TRUE)) != 0)
1339 if ((rc = enop->eno_board_cfg(enp)) != 0)
1344 * Set default driver config limits (based on board config).
1346 * FIXME: For now allocate a fixed number of VIs which is likely to be
1347 * sufficient and small enough to allow multiple functions on the same
1350 edcp->edc_min_vi_count = edcp->edc_max_vi_count =
1351 MIN(128, MAX(encp->enc_rxq_limit, encp->enc_txq_limit));
1353 /* The client driver must configure and enable PIO buffer support */
1354 edcp->edc_max_piobuf_count = 0;
1355 edcp->edc_pio_alloc_size = 0;
1357 #if EFSYS_OPT_MAC_STATS
1358 /* Wipe the MAC statistics */
1359 if ((rc = efx_mcdi_mac_stats_clear(enp)) != 0)
1363 #if EFSYS_OPT_LOOPBACK
1364 if ((rc = efx_mcdi_get_loopback_modes(enp)) != 0)
1368 #if EFSYS_OPT_MON_STATS
1369 if ((rc = mcdi_mon_cfg_build(enp)) != 0) {
1370 /* Unprivileged functions do not have access to sensors */
1376 encp->enc_features = enp->en_features;
1380 #if EFSYS_OPT_MON_STATS
1384 #if EFSYS_OPT_LOOPBACK
1388 #if EFSYS_OPT_MAC_STATS
1399 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1404 __checkReturn efx_rc_t
1405 ef10_nic_set_drv_limits(
1406 __inout efx_nic_t *enp,
1407 __in efx_drv_limits_t *edlp)
1409 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1410 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1411 uint32_t min_evq_count, max_evq_count;
1412 uint32_t min_rxq_count, max_rxq_count;
1413 uint32_t min_txq_count, max_txq_count;
1421 /* Get minimum required and maximum usable VI limits */
1422 min_evq_count = MIN(edlp->edl_min_evq_count, encp->enc_evq_limit);
1423 min_rxq_count = MIN(edlp->edl_min_rxq_count, encp->enc_rxq_limit);
1424 min_txq_count = MIN(edlp->edl_min_txq_count, encp->enc_txq_limit);
1426 edcp->edc_min_vi_count =
1427 MAX(min_evq_count, MAX(min_rxq_count, min_txq_count));
1429 max_evq_count = MIN(edlp->edl_max_evq_count, encp->enc_evq_limit);
1430 max_rxq_count = MIN(edlp->edl_max_rxq_count, encp->enc_rxq_limit);
1431 max_txq_count = MIN(edlp->edl_max_txq_count, encp->enc_txq_limit);
1433 edcp->edc_max_vi_count =
1434 MAX(max_evq_count, MAX(max_rxq_count, max_txq_count));
1437 * Check limits for sub-allocated piobuf blocks.
1438 * PIO is optional, so don't fail if the limits are incorrect.
1440 if ((encp->enc_piobuf_size == 0) ||
1441 (encp->enc_piobuf_limit == 0) ||
1442 (edlp->edl_min_pio_alloc_size == 0) ||
1443 (edlp->edl_min_pio_alloc_size > encp->enc_piobuf_size)) {
1445 edcp->edc_max_piobuf_count = 0;
1446 edcp->edc_pio_alloc_size = 0;
1448 uint32_t blk_size, blk_count, blks_per_piobuf;
1451 MAX(edlp->edl_min_pio_alloc_size,
1452 encp->enc_piobuf_min_alloc_size);
1454 blks_per_piobuf = encp->enc_piobuf_size / blk_size;
1455 EFSYS_ASSERT3U(blks_per_piobuf, <=, 32);
1457 blk_count = (encp->enc_piobuf_limit * blks_per_piobuf);
1459 /* A zero max pio alloc count means unlimited */
1460 if ((edlp->edl_max_pio_alloc_count > 0) &&
1461 (edlp->edl_max_pio_alloc_count < blk_count)) {
1462 blk_count = edlp->edl_max_pio_alloc_count;
1465 edcp->edc_pio_alloc_size = blk_size;
1466 edcp->edc_max_piobuf_count =
1467 (blk_count + (blks_per_piobuf - 1)) / blks_per_piobuf;
1473 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1479 __checkReturn efx_rc_t
1481 __in efx_nic_t *enp)
1484 uint8_t payload[MAX(MC_CMD_ENTITY_RESET_IN_LEN,
1485 MC_CMD_ENTITY_RESET_OUT_LEN)];
1488 /* ef10_nic_reset() is called to recover from BADASSERT failures. */
1489 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
1491 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
1494 (void) memset(payload, 0, sizeof (payload));
1495 req.emr_cmd = MC_CMD_ENTITY_RESET;
1496 req.emr_in_buf = payload;
1497 req.emr_in_length = MC_CMD_ENTITY_RESET_IN_LEN;
1498 req.emr_out_buf = payload;
1499 req.emr_out_length = MC_CMD_ENTITY_RESET_OUT_LEN;
1501 MCDI_IN_POPULATE_DWORD_1(req, ENTITY_RESET_IN_FLAG,
1502 ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET, 1);
1504 efx_mcdi_execute(enp, &req);
1506 if (req.emr_rc != 0) {
1511 /* Clear RX/TX DMA queue errors */
1512 enp->en_reset_flags &= ~(EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR);
1521 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1526 __checkReturn efx_rc_t
1528 __in efx_nic_t *enp)
1530 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1531 uint32_t min_vi_count, max_vi_count;
1532 uint32_t vi_count, vi_base, vi_shift;
1538 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1539 enp->en_family == EFX_FAMILY_MEDFORD);
1541 /* Enable reporting of some events (e.g. link change) */
1542 if ((rc = efx_mcdi_log_ctrl(enp)) != 0)
1545 /* Allocate (optional) on-chip PIO buffers */
1546 ef10_nic_alloc_piobufs(enp, edcp->edc_max_piobuf_count);
1549 * For best performance, PIO writes should use a write-combined
1550 * (WC) memory mapping. Using a separate WC mapping for the PIO
1551 * aperture of each VI would be a burden to drivers (and not
1552 * possible if the host page size is >4Kbyte).
1554 * To avoid this we use a single uncached (UC) mapping for VI
1555 * register access, and a single WC mapping for extra VIs used
1558 * Each piobuf must be linked to a VI in the WC mapping, and to
1559 * each VI that is using a sub-allocated block from the piobuf.
1561 min_vi_count = edcp->edc_min_vi_count;
1563 edcp->edc_max_vi_count + enp->en_arch.ef10.ena_piobuf_count;
1565 /* Ensure that the previously attached driver's VIs are freed */
1566 if ((rc = efx_mcdi_free_vis(enp)) != 0)
1570 * Reserve VI resources (EVQ+RXQ+TXQ) for this PCIe function. If this
1571 * fails then retrying the request for fewer VI resources may succeed.
1574 if ((rc = efx_mcdi_alloc_vis(enp, min_vi_count, max_vi_count,
1575 &vi_base, &vi_count, &vi_shift)) != 0)
1578 EFSYS_PROBE2(vi_alloc, uint32_t, vi_base, uint32_t, vi_count);
1580 if (vi_count < min_vi_count) {
1585 enp->en_arch.ef10.ena_vi_base = vi_base;
1586 enp->en_arch.ef10.ena_vi_count = vi_count;
1587 enp->en_arch.ef10.ena_vi_shift = vi_shift;
1589 if (vi_count < min_vi_count + enp->en_arch.ef10.ena_piobuf_count) {
1590 /* Not enough extra VIs to map piobufs */
1591 ef10_nic_free_piobufs(enp);
1594 enp->en_arch.ef10.ena_pio_write_vi_base =
1595 vi_count - enp->en_arch.ef10.ena_piobuf_count;
1597 /* Save UC memory mapping details */
1598 enp->en_arch.ef10.ena_uc_mem_map_offset = 0;
1599 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
1600 enp->en_arch.ef10.ena_uc_mem_map_size =
1601 (ER_DZ_TX_PIOBUF_STEP *
1602 enp->en_arch.ef10.ena_pio_write_vi_base);
1604 enp->en_arch.ef10.ena_uc_mem_map_size =
1605 (ER_DZ_TX_PIOBUF_STEP *
1606 enp->en_arch.ef10.ena_vi_count);
1609 /* Save WC memory mapping details */
1610 enp->en_arch.ef10.ena_wc_mem_map_offset =
1611 enp->en_arch.ef10.ena_uc_mem_map_offset +
1612 enp->en_arch.ef10.ena_uc_mem_map_size;
1614 enp->en_arch.ef10.ena_wc_mem_map_size =
1615 (ER_DZ_TX_PIOBUF_STEP *
1616 enp->en_arch.ef10.ena_piobuf_count);
1618 /* Link piobufs to extra VIs in WC mapping */
1619 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
1620 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
1621 rc = efx_mcdi_link_piobuf(enp,
1622 enp->en_arch.ef10.ena_pio_write_vi_base + i,
1623 enp->en_arch.ef10.ena_piobuf_handle[i]);
1630 * Allocate a vAdaptor attached to our upstream vPort/pPort.
1632 * On a VF, this may fail with MC_CMD_ERR_NO_EVB_PORT (ENOENT) if the PF
1633 * driver has yet to bring up the EVB port. See bug 56147. In this case,
1634 * retry the request several times after waiting a while. The wait time
1635 * between retries starts small (10ms) and exponentially increases.
1636 * Total wait time is a little over two seconds. Retry logic in the
1637 * client driver may mean this whole loop is repeated if it continues to
1642 while ((rc = efx_mcdi_vadaptor_alloc(enp, EVB_PORT_ID_ASSIGNED)) != 0) {
1643 if (EFX_PCI_FUNCTION_IS_PF(&enp->en_nic_cfg) ||
1646 * Do not retry alloc for PF, or for other errors on
1652 /* VF startup before PF is ready. Retry allocation. */
1654 /* Too many attempts */
1658 EFSYS_PROBE1(mcdi_no_evb_port_retry, int, retry);
1659 EFSYS_SLEEP(delay_us);
1661 if (delay_us < 500000)
1665 enp->en_vport_id = EVB_PORT_ID_ASSIGNED;
1666 enp->en_nic_cfg.enc_mcdi_max_payload_length = MCDI_CTL_SDU_LEN_MAX_V2;
1681 ef10_nic_free_piobufs(enp);
1684 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1689 __checkReturn efx_rc_t
1690 ef10_nic_get_vi_pool(
1691 __in efx_nic_t *enp,
1692 __out uint32_t *vi_countp)
1694 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1695 enp->en_family == EFX_FAMILY_MEDFORD);
1698 * Report VIs that the client driver can use.
1699 * Do not include VIs used for PIO buffer writes.
1701 *vi_countp = enp->en_arch.ef10.ena_pio_write_vi_base;
1706 __checkReturn efx_rc_t
1707 ef10_nic_get_bar_region(
1708 __in efx_nic_t *enp,
1709 __in efx_nic_region_t region,
1710 __out uint32_t *offsetp,
1711 __out size_t *sizep)
1715 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1716 enp->en_family == EFX_FAMILY_MEDFORD);
1719 * TODO: Specify host memory mapping alignment and granularity
1720 * in efx_drv_limits_t so that they can be taken into account
1721 * when allocating extra VIs for PIO writes.
1725 /* UC mapped memory BAR region for VI registers */
1726 *offsetp = enp->en_arch.ef10.ena_uc_mem_map_offset;
1727 *sizep = enp->en_arch.ef10.ena_uc_mem_map_size;
1730 case EFX_REGION_PIO_WRITE_VI:
1731 /* WC mapped memory BAR region for piobuf writes */
1732 *offsetp = enp->en_arch.ef10.ena_wc_mem_map_offset;
1733 *sizep = enp->en_arch.ef10.ena_wc_mem_map_size;
1744 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1751 __in efx_nic_t *enp)
1756 (void) efx_mcdi_vadaptor_free(enp, enp->en_vport_id);
1757 enp->en_vport_id = 0;
1759 /* Unlink piobufs from extra VIs in WC mapping */
1760 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
1761 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
1762 rc = efx_mcdi_unlink_piobuf(enp,
1763 enp->en_arch.ef10.ena_pio_write_vi_base + i);
1769 ef10_nic_free_piobufs(enp);
1771 (void) efx_mcdi_free_vis(enp);
1772 enp->en_arch.ef10.ena_vi_count = 0;
1777 __in efx_nic_t *enp)
1779 #if EFSYS_OPT_MON_STATS
1780 mcdi_mon_cfg_free(enp);
1781 #endif /* EFSYS_OPT_MON_STATS */
1782 (void) efx_mcdi_drv_attach(enp, B_FALSE);
1787 __checkReturn efx_rc_t
1788 ef10_nic_register_test(
1789 __in efx_nic_t *enp)
1794 _NOTE(ARGUNUSED(enp))
1795 _NOTE(CONSTANTCONDITION)
1805 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1810 #endif /* EFSYS_OPT_DIAG */
1813 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */