2 * Copyright (c) 2012-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
38 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
41 #define EFX_TX_QSTAT_INCR(_etp, _stat) \
43 (_etp)->et_stat[_stat]++; \
44 _NOTE(CONSTANTCONDITION) \
47 #define EFX_TX_QSTAT_INCR(_etp, _stat)
50 static __checkReturn efx_rc_t
54 __in uint32_t target_evq,
56 __in uint32_t instance,
58 __in efsys_mem_t *esmp)
61 uint8_t payload[MAX(MC_CMD_INIT_TXQ_IN_LEN(EFX_TXQ_MAX_BUFS),
62 MC_CMD_INIT_TXQ_OUT_LEN)];
63 efx_qword_t *dma_addr;
69 EFSYS_ASSERT(EFX_TXQ_MAX_BUFS >=
70 EFX_TXQ_NBUFS(enp->en_nic_cfg.enc_txq_max_ndescs));
72 npages = EFX_TXQ_NBUFS(size);
73 if (npages > MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM) {
78 (void) memset(payload, 0, sizeof (payload));
79 req.emr_cmd = MC_CMD_INIT_TXQ;
80 req.emr_in_buf = payload;
81 req.emr_in_length = MC_CMD_INIT_TXQ_IN_LEN(npages);
82 req.emr_out_buf = payload;
83 req.emr_out_length = MC_CMD_INIT_TXQ_OUT_LEN;
85 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_SIZE, size);
86 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_TARGET_EVQ, target_evq);
87 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_LABEL, label);
88 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_INSTANCE, instance);
90 MCDI_IN_POPULATE_DWORD_9(req, INIT_TXQ_IN_FLAGS,
91 INIT_TXQ_IN_FLAG_BUFF_MODE, 0,
92 INIT_TXQ_IN_FLAG_IP_CSUM_DIS,
93 (flags & EFX_TXQ_CKSUM_IPV4) ? 0 : 1,
94 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS,
95 (flags & EFX_TXQ_CKSUM_TCPUDP) ? 0 : 1,
96 INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN,
97 (flags & EFX_TXQ_CKSUM_INNER_IPV4) ? 1 : 0,
98 INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN,
99 (flags & EFX_TXQ_CKSUM_INNER_TCPUDP) ? 1 : 0,
100 INIT_TXQ_EXT_IN_FLAG_TSOV2_EN, (flags & EFX_TXQ_FATSOV2) ? 1 : 0,
101 INIT_TXQ_IN_FLAG_TCP_UDP_ONLY, 0,
102 INIT_TXQ_IN_CRC_MODE, 0,
103 INIT_TXQ_IN_FLAG_TIMESTAMP, 0);
105 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_OWNER_ID, 0);
106 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
108 dma_addr = MCDI_IN2(req, efx_qword_t, INIT_TXQ_IN_DMA_ADDR);
109 addr = EFSYS_MEM_ADDR(esmp);
111 for (i = 0; i < npages; i++) {
112 EFX_POPULATE_QWORD_2(*dma_addr,
113 EFX_DWORD_1, (uint32_t)(addr >> 32),
114 EFX_DWORD_0, (uint32_t)(addr & 0xffffffff));
117 addr += EFX_BUF_SIZE;
120 efx_mcdi_execute(enp, &req);
122 if (req.emr_rc != 0) {
132 EFSYS_PROBE1(fail1, efx_rc_t, rc);
137 static __checkReturn efx_rc_t
140 __in uint32_t instance)
143 uint8_t payload[MAX(MC_CMD_FINI_TXQ_IN_LEN,
144 MC_CMD_FINI_TXQ_OUT_LEN)];
147 (void) memset(payload, 0, sizeof (payload));
148 req.emr_cmd = MC_CMD_FINI_TXQ;
149 req.emr_in_buf = payload;
150 req.emr_in_length = MC_CMD_FINI_TXQ_IN_LEN;
151 req.emr_out_buf = payload;
152 req.emr_out_length = MC_CMD_FINI_TXQ_OUT_LEN;
154 MCDI_IN_SET_DWORD(req, FINI_TXQ_IN_INSTANCE, instance);
156 efx_mcdi_execute_quiet(enp, &req);
158 if (req.emr_rc != 0) {
167 * EALREADY is not an error, but indicates that the MC has rebooted and
168 * that the TXQ has already been destroyed.
171 EFSYS_PROBE1(fail1, efx_rc_t, rc);
176 __checkReturn efx_rc_t
180 _NOTE(ARGUNUSED(enp))
188 _NOTE(ARGUNUSED(enp))
191 __checkReturn efx_rc_t
194 __in unsigned int index,
195 __in unsigned int label,
196 __in efsys_mem_t *esmp,
202 __out unsigned int *addedp)
204 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
211 inner_csum = EFX_TXQ_CKSUM_INNER_IPV4 | EFX_TXQ_CKSUM_INNER_TCPUDP;
212 if (((flags & inner_csum) != 0) &&
213 (encp->enc_tunnel_encapsulations_supported == 0)) {
218 if ((rc = efx_mcdi_init_txq(enp, n, eep->ee_index, label, index, flags,
223 * A previous user of this TX queue may have written a descriptor to the
224 * TX push collector, but not pushed the doorbell (e.g. after a crash).
225 * The next doorbell write would then push the stale descriptor.
227 * Ensure the (per network port) TX push collector is cleared by writing
228 * a no-op TX option descriptor. See bug29981 for details.
231 ef10_tx_qdesc_checksum_create(etp, flags, &desc);
233 EFSYS_MEM_WRITEQ(etp->et_esmp, 0, &desc.ed_eq);
234 ef10_tx_qpush(etp, *addedp, 0);
241 EFSYS_PROBE1(fail1, efx_rc_t, rc);
251 _NOTE(ARGUNUSED(etp))
255 __checkReturn efx_rc_t
259 efx_nic_t *enp = etp->et_enp;
260 efx_piobuf_handle_t handle;
263 if (etp->et_pio_size != 0) {
268 /* Sub-allocate a PIO block from a piobuf */
269 if ((rc = ef10_nic_pio_alloc(enp,
274 &etp->et_pio_size)) != 0) {
277 EFSYS_ASSERT3U(etp->et_pio_size, !=, 0);
279 /* Link the piobuf to this TXQ */
280 if ((rc = ef10_nic_pio_link(enp, etp->et_index, handle)) != 0) {
285 * et_pio_offset is the offset of the sub-allocated block within the
286 * hardware PIO buffer. It is used as the buffer address in the PIO
289 * et_pio_write_offset is the offset of the sub-allocated block from the
290 * start of the write-combined memory mapping, and is used for writing
291 * data into the PIO buffer.
293 etp->et_pio_write_offset =
294 (etp->et_pio_bufnum * ER_DZ_TX_PIOBUF_STEP) +
295 ER_DZ_TX_PIOBUF_OFST + etp->et_pio_offset;
301 (void) ef10_nic_pio_free(enp, etp->et_pio_bufnum, etp->et_pio_blknum);
302 etp->et_pio_size = 0;
306 EFSYS_PROBE1(fail1, efx_rc_t, rc);
312 ef10_tx_qpio_disable(
315 efx_nic_t *enp = etp->et_enp;
317 if (etp->et_pio_size != 0) {
318 /* Unlink the piobuf from this TXQ */
319 if (ef10_nic_pio_unlink(enp, etp->et_index) != 0)
322 /* Free the sub-allocated PIO block */
323 (void) ef10_nic_pio_free(enp, etp->et_pio_bufnum,
325 etp->et_pio_size = 0;
326 etp->et_pio_write_offset = 0;
330 __checkReturn efx_rc_t
333 __in_ecount(length) uint8_t *buffer,
337 efx_nic_t *enp = etp->et_enp;
338 efsys_bar_t *esbp = enp->en_esbp;
339 uint32_t write_offset;
340 uint32_t write_offset_limit;
344 EFSYS_ASSERT(length % sizeof (efx_qword_t) == 0);
346 if (etp->et_pio_size == 0) {
350 if (offset + length > etp->et_pio_size) {
356 * Writes to PIO buffers must be 64 bit aligned, and multiples of
359 write_offset = etp->et_pio_write_offset + offset;
360 write_offset_limit = write_offset + length;
361 eqp = (efx_qword_t *)buffer;
362 while (write_offset < write_offset_limit) {
363 EFSYS_BAR_WC_WRITEQ(esbp, write_offset, eqp);
365 write_offset += sizeof (efx_qword_t);
373 EFSYS_PROBE1(fail1, efx_rc_t, rc);
378 __checkReturn efx_rc_t
381 __in size_t pkt_length,
382 __in unsigned int completed,
383 __inout unsigned int *addedp)
385 efx_qword_t pio_desc;
388 unsigned int added = *addedp;
392 if (added - completed + 1 > EFX_TXQ_LIMIT(etp->et_mask + 1)) {
397 if (etp->et_pio_size == 0) {
402 id = added++ & etp->et_mask;
403 offset = id * sizeof (efx_qword_t);
405 EFSYS_PROBE4(tx_pio_post, unsigned int, etp->et_index,
406 unsigned int, id, uint32_t, etp->et_pio_offset,
409 EFX_POPULATE_QWORD_5(pio_desc,
410 ESF_DZ_TX_DESC_IS_OPT, 1,
411 ESF_DZ_TX_OPTION_TYPE, 1,
412 ESF_DZ_TX_PIO_CONT, 0,
413 ESF_DZ_TX_PIO_BYTE_CNT, pkt_length,
414 ESF_DZ_TX_PIO_BUF_ADDR, etp->et_pio_offset);
416 EFSYS_MEM_WRITEQ(etp->et_esmp, offset, &pio_desc);
418 EFX_TX_QSTAT_INCR(etp, TX_POST_PIO);
426 EFSYS_PROBE1(fail1, efx_rc_t, rc);
431 __checkReturn efx_rc_t
434 __in_ecount(n) efx_buffer_t *eb,
436 __in unsigned int completed,
437 __inout unsigned int *addedp)
439 unsigned int added = *addedp;
443 if (added - completed + n > EFX_TXQ_LIMIT(etp->et_mask + 1)) {
448 for (i = 0; i < n; i++) {
449 efx_buffer_t *ebp = &eb[i];
450 efsys_dma_addr_t addr = ebp->eb_addr;
451 size_t size = ebp->eb_size;
452 boolean_t eop = ebp->eb_eop;
457 /* No limitations on boundary crossing */
459 etp->et_enp->en_nic_cfg.enc_tx_dma_desc_size_max);
461 id = added++ & etp->et_mask;
462 offset = id * sizeof (efx_qword_t);
464 EFSYS_PROBE5(tx_post, unsigned int, etp->et_index,
465 unsigned int, id, efsys_dma_addr_t, addr,
466 size_t, size, boolean_t, eop);
468 EFX_POPULATE_QWORD_5(qword,
469 ESF_DZ_TX_KER_TYPE, 0,
470 ESF_DZ_TX_KER_CONT, (eop) ? 0 : 1,
471 ESF_DZ_TX_KER_BYTE_CNT, (uint32_t)(size),
472 ESF_DZ_TX_KER_BUF_ADDR_DW0, (uint32_t)(addr & 0xffffffff),
473 ESF_DZ_TX_KER_BUF_ADDR_DW1, (uint32_t)(addr >> 32));
475 EFSYS_MEM_WRITEQ(etp->et_esmp, offset, &qword);
478 EFX_TX_QSTAT_INCR(etp, TX_POST);
484 EFSYS_PROBE1(fail1, efx_rc_t, rc);
490 * This improves performance by, when possible, pushing a TX descriptor at the
491 * same time as the doorbell. The descriptor must be added to the TXQ, so that
492 * can be used if the hardware decides not to use the pushed descriptor.
497 __in unsigned int added,
498 __in unsigned int pushed)
500 efx_nic_t *enp = etp->et_enp;
507 wptr = added & etp->et_mask;
508 id = pushed & etp->et_mask;
509 offset = id * sizeof (efx_qword_t);
511 EFSYS_MEM_READQ(etp->et_esmp, offset, &desc);
514 * SF Bug 65776: TSO option descriptors cannot be pushed if pacer bypass
515 * is enabled on the event queue this transmit queue is attached to.
517 * To ensure the code is safe, it is easiest to simply test the type of
518 * the descriptor to push, and only push it is if it not a TSO option
521 if ((EFX_QWORD_FIELD(desc, ESF_DZ_TX_DESC_IS_OPT) != 1) ||
522 (EFX_QWORD_FIELD(desc, ESF_DZ_TX_OPTION_TYPE) !=
523 ESE_DZ_TX_OPTION_DESC_TSO)) {
524 /* Push the descriptor and update the wptr. */
525 EFX_POPULATE_OWORD_3(oword, ERF_DZ_TX_DESC_WPTR, wptr,
526 ERF_DZ_TX_DESC_HWORD, EFX_QWORD_FIELD(desc, EFX_DWORD_1),
527 ERF_DZ_TX_DESC_LWORD, EFX_QWORD_FIELD(desc, EFX_DWORD_0));
529 /* Ensure ordering of memory (descriptors) and PIO (doorbell) */
530 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(etp->et_esmp, etp->et_mask + 1,
532 EFSYS_PIO_WRITE_BARRIER();
533 EFX_BAR_TBL_DOORBELL_WRITEO(enp, ER_DZ_TX_DESC_UPD_REG,
534 etp->et_index, &oword);
539 * Only update the wptr. This is signalled to the hardware by
540 * only writing one DWORD of the doorbell register.
542 EFX_POPULATE_OWORD_1(oword, ERF_DZ_TX_DESC_WPTR, wptr);
543 dword = oword.eo_dword[2];
545 /* Ensure ordering of memory (descriptors) and PIO (doorbell) */
546 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(etp->et_esmp, etp->et_mask + 1,
548 EFSYS_PIO_WRITE_BARRIER();
549 EFX_BAR_TBL_WRITED2(enp, ER_DZ_TX_DESC_UPD_REG,
550 etp->et_index, &dword, B_FALSE);
554 __checkReturn efx_rc_t
557 __in_ecount(n) efx_desc_t *ed,
559 __in unsigned int completed,
560 __inout unsigned int *addedp)
562 unsigned int added = *addedp;
566 if (added - completed + n > EFX_TXQ_LIMIT(etp->et_mask + 1)) {
571 for (i = 0; i < n; i++) {
572 efx_desc_t *edp = &ed[i];
576 id = added++ & etp->et_mask;
577 offset = id * sizeof (efx_desc_t);
579 EFSYS_MEM_WRITEQ(etp->et_esmp, offset, &edp->ed_eq);
582 EFSYS_PROBE3(tx_desc_post, unsigned int, etp->et_index,
583 unsigned int, added, unsigned int, n);
585 EFX_TX_QSTAT_INCR(etp, TX_POST);
591 EFSYS_PROBE1(fail1, efx_rc_t, rc);
597 ef10_tx_qdesc_dma_create(
599 __in efsys_dma_addr_t addr,
602 __out efx_desc_t *edp)
604 _NOTE(ARGUNUSED(etp))
606 /* No limitations on boundary crossing */
607 EFSYS_ASSERT(size <= etp->et_enp->en_nic_cfg.enc_tx_dma_desc_size_max);
609 EFSYS_PROBE4(tx_desc_dma_create, unsigned int, etp->et_index,
610 efsys_dma_addr_t, addr,
611 size_t, size, boolean_t, eop);
613 EFX_POPULATE_QWORD_5(edp->ed_eq,
614 ESF_DZ_TX_KER_TYPE, 0,
615 ESF_DZ_TX_KER_CONT, (eop) ? 0 : 1,
616 ESF_DZ_TX_KER_BYTE_CNT, (uint32_t)(size),
617 ESF_DZ_TX_KER_BUF_ADDR_DW0, (uint32_t)(addr & 0xffffffff),
618 ESF_DZ_TX_KER_BUF_ADDR_DW1, (uint32_t)(addr >> 32));
622 ef10_tx_qdesc_tso_create(
624 __in uint16_t ipv4_id,
625 __in uint32_t tcp_seq,
626 __in uint8_t tcp_flags,
627 __out efx_desc_t *edp)
629 _NOTE(ARGUNUSED(etp))
631 EFSYS_PROBE4(tx_desc_tso_create, unsigned int, etp->et_index,
632 uint16_t, ipv4_id, uint32_t, tcp_seq,
635 EFX_POPULATE_QWORD_5(edp->ed_eq,
636 ESF_DZ_TX_DESC_IS_OPT, 1,
637 ESF_DZ_TX_OPTION_TYPE,
638 ESE_DZ_TX_OPTION_DESC_TSO,
639 ESF_DZ_TX_TSO_TCP_FLAGS, tcp_flags,
640 ESF_DZ_TX_TSO_IP_ID, ipv4_id,
641 ESF_DZ_TX_TSO_TCP_SEQNO, tcp_seq);
645 ef10_tx_qdesc_tso2_create(
647 __in uint16_t ipv4_id,
648 __in uint32_t tcp_seq,
649 __in uint16_t tcp_mss,
650 __out_ecount(count) efx_desc_t *edp,
653 _NOTE(ARGUNUSED(etp, count))
655 EFSYS_PROBE4(tx_desc_tso2_create, unsigned int, etp->et_index,
656 uint16_t, ipv4_id, uint32_t, tcp_seq,
659 EFSYS_ASSERT(count >= EFX_TX_FATSOV2_OPT_NDESCS);
661 EFX_POPULATE_QWORD_5(edp[0].ed_eq,
662 ESF_DZ_TX_DESC_IS_OPT, 1,
663 ESF_DZ_TX_OPTION_TYPE,
664 ESE_DZ_TX_OPTION_DESC_TSO,
665 ESF_DZ_TX_TSO_OPTION_TYPE,
666 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A,
667 ESF_DZ_TX_TSO_IP_ID, ipv4_id,
668 ESF_DZ_TX_TSO_TCP_SEQNO, tcp_seq);
669 EFX_POPULATE_QWORD_4(edp[1].ed_eq,
670 ESF_DZ_TX_DESC_IS_OPT, 1,
671 ESF_DZ_TX_OPTION_TYPE,
672 ESE_DZ_TX_OPTION_DESC_TSO,
673 ESF_DZ_TX_TSO_OPTION_TYPE,
674 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B,
675 ESF_DZ_TX_TSO_TCP_MSS, tcp_mss);
679 ef10_tx_qdesc_vlantci_create(
682 __out efx_desc_t *edp)
684 _NOTE(ARGUNUSED(etp))
686 EFSYS_PROBE2(tx_desc_vlantci_create, unsigned int, etp->et_index,
689 EFX_POPULATE_QWORD_4(edp->ed_eq,
690 ESF_DZ_TX_DESC_IS_OPT, 1,
691 ESF_DZ_TX_OPTION_TYPE,
692 ESE_DZ_TX_OPTION_DESC_VLAN,
693 ESF_DZ_TX_VLAN_OP, tci ? 1 : 0,
694 ESF_DZ_TX_VLAN_TAG1, tci);
698 ef10_tx_qdesc_checksum_create(
701 __out efx_desc_t *edp)
703 _NOTE(ARGUNUSED(etp));
705 EFSYS_PROBE2(tx_desc_checksum_create, unsigned int, etp->et_index,
708 EFX_POPULATE_QWORD_6(edp->ed_eq,
709 ESF_DZ_TX_DESC_IS_OPT, 1,
710 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
711 ESF_DZ_TX_OPTION_UDP_TCP_CSUM,
712 (flags & EFX_TXQ_CKSUM_TCPUDP) ? 1 : 0,
713 ESF_DZ_TX_OPTION_IP_CSUM,
714 (flags & EFX_TXQ_CKSUM_IPV4) ? 1 : 0,
715 ESF_DZ_TX_OPTION_INNER_UDP_TCP_CSUM,
716 (flags & EFX_TXQ_CKSUM_INNER_TCPUDP) ? 1 : 0,
717 ESF_DZ_TX_OPTION_INNER_IP_CSUM,
718 (flags & EFX_TXQ_CKSUM_INNER_IPV4) ? 1 : 0);
722 __checkReturn efx_rc_t
725 __in unsigned int ns)
730 _NOTE(ARGUNUSED(etp, ns))
731 _NOTE(CONSTANTCONDITION)
742 * EALREADY is not an error, but indicates that the MC has rebooted and
743 * that the TXQ has already been destroyed. Callers need to know that
744 * the TXQ flush has completed to avoid waiting until timeout for a
745 * flush done event that will not be delivered.
748 EFSYS_PROBE1(fail1, efx_rc_t, rc);
753 __checkReturn efx_rc_t
757 efx_nic_t *enp = etp->et_enp;
760 if ((rc = efx_mcdi_fini_txq(enp, etp->et_index)) != 0)
766 EFSYS_PROBE1(fail1, efx_rc_t, rc);
776 _NOTE(ARGUNUSED(etp))
782 ef10_tx_qstats_update(
784 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat)
788 for (id = 0; id < TX_NQSTATS; id++) {
789 efsys_stat_t *essp = &stat[id];
791 EFSYS_STAT_INCR(essp, etp->et_stat[id]);
792 etp->et_stat[id] = 0;
796 #endif /* EFSYS_OPT_QSTATS */
798 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */