2 * Copyright (c) 2006-2015 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
37 #include "efx_check.h"
38 #include "efx_phy_ids.h"
44 #define EFX_STATIC_ASSERT(_cond) \
45 ((void)sizeof(char[(_cond) ? 1 : -1]))
47 #define EFX_ARRAY_SIZE(_array) \
48 (sizeof(_array) / sizeof((_array)[0]))
50 #define EFX_FIELD_OFFSET(_type, _field) \
51 ((size_t) &(((_type *)0)->_field))
55 typedef __success(return == 0) int efx_rc_t;
60 typedef enum efx_family_e {
64 EFX_FAMILY_HUNTINGTON,
69 extern __checkReturn efx_rc_t
73 __out efx_family_t *efp);
76 #define EFX_PCI_VENID_SFC 0x1924
78 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
80 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
81 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
82 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
84 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
85 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
86 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
88 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
89 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
91 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
92 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
93 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
102 EFX_ERR_BUFID_DC_OOB,
115 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
116 extern __checkReturn uint32_t
118 __in uint32_t crc_init,
119 __in_ecount(length) uint8_t const *input,
123 /* Type prototypes */
125 typedef struct efx_rxq_s efx_rxq_t;
129 typedef struct efx_nic_s efx_nic_t;
131 #define EFX_NIC_FUNC_PRIMARY 0x00000001
132 #define EFX_NIC_FUNC_LINKCTRL 0x00000002
133 #define EFX_NIC_FUNC_TRUSTED 0x00000004
136 extern __checkReturn efx_rc_t
138 __in efx_family_t family,
139 __in efsys_identifier_t *esip,
140 __in efsys_bar_t *esbp,
141 __in efsys_lock_t *eslp,
142 __deref_out efx_nic_t **enpp);
144 extern __checkReturn efx_rc_t
146 __in efx_nic_t *enp);
148 extern __checkReturn efx_rc_t
150 __in efx_nic_t *enp);
152 extern __checkReturn efx_rc_t
154 __in efx_nic_t *enp);
158 extern __checkReturn efx_rc_t
159 efx_nic_register_test(
160 __in efx_nic_t *enp);
162 #endif /* EFSYS_OPT_DIAG */
166 __in efx_nic_t *enp);
170 __in efx_nic_t *enp);
174 __in efx_nic_t *enp);
178 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
179 /* Huntington and Medford require MCDIv2 commands */
180 #define WITH_MCDI_V2 1
183 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
185 typedef enum efx_mcdi_exception_e {
186 EFX_MCDI_EXCEPTION_MC_REBOOT,
187 EFX_MCDI_EXCEPTION_MC_BADASSERT,
188 } efx_mcdi_exception_t;
190 #if EFSYS_OPT_MCDI_LOGGING
191 typedef enum efx_log_msg_e
194 EFX_LOG_MCDI_REQUEST,
195 EFX_LOG_MCDI_RESPONSE,
197 #endif /* EFSYS_OPT_MCDI_LOGGING */
199 typedef struct efx_mcdi_transport_s {
201 efsys_mem_t *emt_dma_mem;
202 void (*emt_execute)(void *, efx_mcdi_req_t *);
203 void (*emt_ev_cpl)(void *);
204 void (*emt_exception)(void *, efx_mcdi_exception_t);
205 #if EFSYS_OPT_MCDI_LOGGING
206 void (*emt_logger)(void *, efx_log_msg_t,
207 void *, size_t, void *, size_t);
208 #endif /* EFSYS_OPT_MCDI_LOGGING */
209 #if EFSYS_OPT_MCDI_PROXY_AUTH
210 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
211 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
212 } efx_mcdi_transport_t;
214 extern __checkReturn efx_rc_t
217 __in const efx_mcdi_transport_t *mtp);
219 extern __checkReturn efx_rc_t
221 __in efx_nic_t *enp);
225 __in efx_nic_t *enp);
228 efx_mcdi_request_start(
230 __in efx_mcdi_req_t *emrp,
231 __in boolean_t ev_cpl);
233 extern __checkReturn boolean_t
234 efx_mcdi_request_poll(
235 __in efx_nic_t *enp);
237 extern __checkReturn boolean_t
238 efx_mcdi_request_abort(
239 __in efx_nic_t *enp);
243 __in efx_nic_t *enp);
245 #endif /* EFSYS_OPT_MCDI */
249 #define EFX_NINTR_FALCON 64
250 #define EFX_NINTR_SIENA 1024
252 typedef enum efx_intr_type_e {
253 EFX_INTR_INVALID = 0,
259 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
261 extern __checkReturn efx_rc_t
264 __in efx_intr_type_t type,
265 __in efsys_mem_t *esmp);
269 __in efx_nic_t *enp);
273 __in efx_nic_t *enp);
276 efx_intr_disable_unlocked(
277 __in efx_nic_t *enp);
279 #define EFX_INTR_NEVQS 32
281 extern __checkReturn efx_rc_t
284 __in unsigned int level);
287 efx_intr_status_line(
289 __out boolean_t *fatalp,
290 __out uint32_t *maskp);
293 efx_intr_status_message(
295 __in unsigned int message,
296 __out boolean_t *fatalp);
300 __in efx_nic_t *enp);
304 __in efx_nic_t *enp);
308 #if EFSYS_OPT_MAC_STATS
310 /* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */
311 typedef enum efx_mac_stat_e {
314 EFX_MAC_RX_UNICST_PKTS,
315 EFX_MAC_RX_MULTICST_PKTS,
316 EFX_MAC_RX_BRDCST_PKTS,
317 EFX_MAC_RX_PAUSE_PKTS,
318 EFX_MAC_RX_LE_64_PKTS,
319 EFX_MAC_RX_65_TO_127_PKTS,
320 EFX_MAC_RX_128_TO_255_PKTS,
321 EFX_MAC_RX_256_TO_511_PKTS,
322 EFX_MAC_RX_512_TO_1023_PKTS,
323 EFX_MAC_RX_1024_TO_15XX_PKTS,
324 EFX_MAC_RX_GE_15XX_PKTS,
326 EFX_MAC_RX_FCS_ERRORS,
327 EFX_MAC_RX_DROP_EVENTS,
328 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
329 EFX_MAC_RX_SYMBOL_ERRORS,
330 EFX_MAC_RX_ALIGN_ERRORS,
331 EFX_MAC_RX_INTERNAL_ERRORS,
332 EFX_MAC_RX_JABBER_PKTS,
333 EFX_MAC_RX_LANE0_CHAR_ERR,
334 EFX_MAC_RX_LANE1_CHAR_ERR,
335 EFX_MAC_RX_LANE2_CHAR_ERR,
336 EFX_MAC_RX_LANE3_CHAR_ERR,
337 EFX_MAC_RX_LANE0_DISP_ERR,
338 EFX_MAC_RX_LANE1_DISP_ERR,
339 EFX_MAC_RX_LANE2_DISP_ERR,
340 EFX_MAC_RX_LANE3_DISP_ERR,
341 EFX_MAC_RX_MATCH_FAULT,
342 EFX_MAC_RX_NODESC_DROP_CNT,
345 EFX_MAC_TX_UNICST_PKTS,
346 EFX_MAC_TX_MULTICST_PKTS,
347 EFX_MAC_TX_BRDCST_PKTS,
348 EFX_MAC_TX_PAUSE_PKTS,
349 EFX_MAC_TX_LE_64_PKTS,
350 EFX_MAC_TX_65_TO_127_PKTS,
351 EFX_MAC_TX_128_TO_255_PKTS,
352 EFX_MAC_TX_256_TO_511_PKTS,
353 EFX_MAC_TX_512_TO_1023_PKTS,
354 EFX_MAC_TX_1024_TO_15XX_PKTS,
355 EFX_MAC_TX_GE_15XX_PKTS,
357 EFX_MAC_TX_SGL_COL_PKTS,
358 EFX_MAC_TX_MULT_COL_PKTS,
359 EFX_MAC_TX_EX_COL_PKTS,
360 EFX_MAC_TX_LATE_COL_PKTS,
362 EFX_MAC_TX_EX_DEF_PKTS,
363 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
364 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
365 EFX_MAC_PM_TRUNC_VFIFO_FULL,
366 EFX_MAC_PM_DISCARD_VFIFO_FULL,
367 EFX_MAC_PM_TRUNC_QBB,
368 EFX_MAC_PM_DISCARD_QBB,
369 EFX_MAC_PM_DISCARD_MAPPING,
370 EFX_MAC_RXDP_Q_DISABLED_PKTS,
371 EFX_MAC_RXDP_DI_DROPPED_PKTS,
372 EFX_MAC_RXDP_STREAMING_PKTS,
373 EFX_MAC_RXDP_HLB_FETCH,
374 EFX_MAC_RXDP_HLB_WAIT,
375 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
376 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
377 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
378 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
379 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
380 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
381 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
382 EFX_MAC_VADAPTER_RX_BAD_BYTES,
383 EFX_MAC_VADAPTER_RX_OVERFLOW,
384 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
385 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
386 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
387 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
388 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
389 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
390 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
391 EFX_MAC_VADAPTER_TX_BAD_BYTES,
392 EFX_MAC_VADAPTER_TX_OVERFLOW,
396 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
398 #endif /* EFSYS_OPT_MAC_STATS */
400 typedef enum efx_link_mode_e {
401 EFX_LINK_UNKNOWN = 0,
414 #define EFX_MAC_ADDR_LEN 6
416 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t*)_address)[0] & 0x01)
418 #define EFX_MAC_MULTICAST_LIST_MAX 256
420 #define EFX_MAC_SDU_MAX 9202
422 #define EFX_MAC_PDU(_sdu) \
427 + /* bug16011 */ 16), \
430 #define EFX_MAC_PDU_MIN 60
431 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
433 extern __checkReturn efx_rc_t
438 extern __checkReturn efx_rc_t
443 extern __checkReturn efx_rc_t
446 __in boolean_t all_unicst,
447 __in boolean_t mulcst,
448 __in boolean_t all_mulcst,
449 __in boolean_t brdcst);
451 extern __checkReturn efx_rc_t
452 efx_mac_multicast_list_set(
454 __in_ecount(6*count) uint8_t const *addrs,
457 extern __checkReturn efx_rc_t
458 efx_mac_filter_default_rxq_set(
461 __in boolean_t using_rss);
464 efx_mac_filter_default_rxq_clear(
465 __in efx_nic_t *enp);
467 extern __checkReturn efx_rc_t
470 __in boolean_t enabled);
472 extern __checkReturn efx_rc_t
475 __out boolean_t *mac_upp);
477 #define EFX_FCNTL_RESPOND 0x00000001
478 #define EFX_FCNTL_GENERATE 0x00000002
480 extern __checkReturn efx_rc_t
483 __in unsigned int fcntl,
484 __in boolean_t autoneg);
489 __out unsigned int *fcntl_wantedp,
490 __out unsigned int *fcntl_linkp);
493 #if EFSYS_OPT_MAC_STATS
497 extern __checkReturn const char *
500 __in unsigned int id);
502 #endif /* EFSYS_OPT_NAMES */
504 #define EFX_MAC_STATS_SIZE 0x400
507 * Upload mac statistics supported by the hardware into the given buffer.
509 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes,
512 * The hardware will only DMA statistics that it understands (of course).
513 * Drivers should not make any assumptions about which statistics are
514 * supported, especially when the statistics are generated by firmware.
516 * Thus, drivers should zero this buffer before use, so that not-understood
517 * statistics read back as zero.
519 extern __checkReturn efx_rc_t
520 efx_mac_stats_upload(
522 __in efsys_mem_t *esmp);
524 extern __checkReturn efx_rc_t
525 efx_mac_stats_periodic(
527 __in efsys_mem_t *esmp,
528 __in uint16_t period_ms,
529 __in boolean_t events);
531 extern __checkReturn efx_rc_t
532 efx_mac_stats_update(
534 __in efsys_mem_t *esmp,
535 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
536 __inout_opt uint32_t *generationp);
538 #endif /* EFSYS_OPT_MAC_STATS */
542 typedef enum efx_mon_type_e {
557 __in efx_nic_t *enp);
559 #endif /* EFSYS_OPT_NAMES */
561 extern __checkReturn efx_rc_t
563 __in efx_nic_t *enp);
565 #if EFSYS_OPT_MON_STATS
567 #define EFX_MON_STATS_PAGE_SIZE 0x100
568 #define EFX_MON_MASK_ELEMENT_SIZE 32
570 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock c09b13f732431f23 */
571 typedef enum efx_mon_stat_e {
578 EFX_MON_STAT_EXT_TEMP,
579 EFX_MON_STAT_INT_TEMP,
582 EFX_MON_STAT_INT_COOLING,
583 EFX_MON_STAT_EXT_COOLING,
591 EFX_MON_STAT_AOE_TEMP,
592 EFX_MON_STAT_PSU_AOE_TEMP,
593 EFX_MON_STAT_PSU_TEMP,
599 EFX_MON_STAT_VAOE_IN,
601 EFX_MON_STAT_IAOE_IN,
602 EFX_MON_STAT_NIC_POWER,
606 EFX_MON_STAT_0_9V_ADC,
607 EFX_MON_STAT_INT_TEMP2,
608 EFX_MON_STAT_VREG_TEMP,
609 EFX_MON_STAT_VREG_0_9V_TEMP,
610 EFX_MON_STAT_VREG_1_2V_TEMP,
611 EFX_MON_STAT_INT_VPTAT,
612 EFX_MON_STAT_INT_ADC_TEMP,
613 EFX_MON_STAT_EXT_VPTAT,
614 EFX_MON_STAT_EXT_ADC_TEMP,
615 EFX_MON_STAT_AMBIENT_TEMP,
616 EFX_MON_STAT_AIRFLOW,
617 EFX_MON_STAT_VDD08D_VSS08D_CSR,
618 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
619 EFX_MON_STAT_HOTPOINT_TEMP,
620 EFX_MON_STAT_PHY_POWER_SWITCH_PORT0,
621 EFX_MON_STAT_PHY_POWER_SWITCH_PORT1,
622 EFX_MON_STAT_MUM_VCC,
625 EFX_MON_STAT_0V9_A_TEMP,
628 EFX_MON_STAT_0V9_B_TEMP,
629 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
630 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,
631 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
632 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,
633 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
634 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
635 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,
636 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,
637 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
638 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
639 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,
640 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,
641 EFX_MON_STAT_SODIMM_VOUT,
642 EFX_MON_STAT_SODIMM_0_TEMP,
643 EFX_MON_STAT_SODIMM_1_TEMP,
644 EFX_MON_STAT_PHY0_VCC,
645 EFX_MON_STAT_PHY1_VCC,
646 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
650 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
652 typedef enum efx_mon_stat_state_e {
653 EFX_MON_STAT_STATE_OK = 0,
654 EFX_MON_STAT_STATE_WARNING = 1,
655 EFX_MON_STAT_STATE_FATAL = 2,
656 EFX_MON_STAT_STATE_BROKEN = 3,
657 EFX_MON_STAT_STATE_NO_READING = 4,
658 } efx_mon_stat_state_t;
660 typedef struct efx_mon_stat_value_s {
663 } efx_mon_stat_value_t;
670 __in efx_mon_stat_t id);
672 #endif /* EFSYS_OPT_NAMES */
674 extern __checkReturn efx_rc_t
675 efx_mon_stats_update(
677 __in efsys_mem_t *esmp,
678 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
680 #endif /* EFSYS_OPT_MON_STATS */
684 __in efx_nic_t *enp);
688 #define PMA_PMD_MMD 1
693 #define CL22EXT_MMD 29
695 #define MAXMMD ((1 << 5) - 1)
697 extern __checkReturn efx_rc_t
699 __in efx_nic_t *enp);
701 #if EFSYS_OPT_PHY_LED_CONTROL
703 typedef enum efx_phy_led_mode_e {
704 EFX_PHY_LED_DEFAULT = 0,
709 } efx_phy_led_mode_t;
711 extern __checkReturn efx_rc_t
714 __in efx_phy_led_mode_t mode);
716 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
718 extern __checkReturn efx_rc_t
720 __in efx_nic_t *enp);
722 #if EFSYS_OPT_LOOPBACK
724 typedef enum efx_loopback_type_e {
725 EFX_LOOPBACK_OFF = 0,
726 EFX_LOOPBACK_DATA = 1,
727 EFX_LOOPBACK_GMAC = 2,
728 EFX_LOOPBACK_XGMII = 3,
729 EFX_LOOPBACK_XGXS = 4,
730 EFX_LOOPBACK_XAUI = 5,
731 EFX_LOOPBACK_GMII = 6,
732 EFX_LOOPBACK_SGMII = 7,
733 EFX_LOOPBACK_XGBR = 8,
734 EFX_LOOPBACK_XFI = 9,
735 EFX_LOOPBACK_XAUI_FAR = 10,
736 EFX_LOOPBACK_GMII_FAR = 11,
737 EFX_LOOPBACK_SGMII_FAR = 12,
738 EFX_LOOPBACK_XFI_FAR = 13,
739 EFX_LOOPBACK_GPHY = 14,
740 EFX_LOOPBACK_PHY_XS = 15,
741 EFX_LOOPBACK_PCS = 16,
742 EFX_LOOPBACK_PMA_PMD = 17,
743 EFX_LOOPBACK_XPORT = 18,
744 EFX_LOOPBACK_XGMII_WS = 19,
745 EFX_LOOPBACK_XAUI_WS = 20,
746 EFX_LOOPBACK_XAUI_WS_FAR = 21,
747 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
748 EFX_LOOPBACK_GMII_WS = 23,
749 EFX_LOOPBACK_XFI_WS = 24,
750 EFX_LOOPBACK_XFI_WS_FAR = 25,
751 EFX_LOOPBACK_PHYXS_WS = 26,
752 EFX_LOOPBACK_PMA_INT = 27,
753 EFX_LOOPBACK_SD_NEAR = 28,
754 EFX_LOOPBACK_SD_FAR = 29,
755 EFX_LOOPBACK_PMA_INT_WS = 30,
756 EFX_LOOPBACK_SD_FEP2_WS = 31,
757 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
758 EFX_LOOPBACK_SD_FEP_WS = 33,
759 EFX_LOOPBACK_SD_FES_WS = 34,
761 } efx_loopback_type_t;
763 typedef enum efx_loopback_kind_e {
764 EFX_LOOPBACK_KIND_OFF = 0,
765 EFX_LOOPBACK_KIND_ALL,
766 EFX_LOOPBACK_KIND_MAC,
767 EFX_LOOPBACK_KIND_PHY,
769 } efx_loopback_kind_t;
773 __in efx_loopback_kind_t loopback_kind,
774 __out efx_qword_t *maskp);
776 extern __checkReturn efx_rc_t
777 efx_port_loopback_set(
779 __in efx_link_mode_t link_mode,
780 __in efx_loopback_type_t type);
784 extern __checkReturn const char *
785 efx_loopback_type_name(
787 __in efx_loopback_type_t type);
789 #endif /* EFSYS_OPT_NAMES */
791 #endif /* EFSYS_OPT_LOOPBACK */
793 extern __checkReturn efx_rc_t
796 __out_opt efx_link_mode_t *link_modep);
800 __in efx_nic_t *enp);
802 typedef enum efx_phy_cap_type_e {
803 EFX_PHY_CAP_INVALID = 0,
810 EFX_PHY_CAP_10000FDX,
814 EFX_PHY_CAP_40000FDX,
816 } efx_phy_cap_type_t;
819 #define EFX_PHY_CAP_CURRENT 0x00000000
820 #define EFX_PHY_CAP_DEFAULT 0x00000001
821 #define EFX_PHY_CAP_PERM 0x00000002
827 __out uint32_t *maskp);
829 extern __checkReturn efx_rc_t
837 __out uint32_t *maskp);
839 extern __checkReturn efx_rc_t
842 __out uint32_t *ouip);
844 typedef enum efx_phy_media_type_e {
845 EFX_PHY_MEDIA_INVALID = 0,
850 EFX_PHY_MEDIA_SFP_PLUS,
851 EFX_PHY_MEDIA_BASE_T,
852 EFX_PHY_MEDIA_QSFP_PLUS,
854 } efx_phy_media_type_t;
856 /* Get the type of medium currently used. If the board has ports for
857 * modules, a module is present, and we recognise the media type of
858 * the module, then this will be the media type of the module.
859 * Otherwise it will be the media type of the port.
862 efx_phy_media_type_get(
864 __out efx_phy_media_type_t *typep);
867 efx_phy_module_get_info(
869 __in uint8_t dev_addr,
872 __out_bcount(len) uint8_t *data);
874 #if EFSYS_OPT_PHY_STATS
876 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
877 typedef enum efx_phy_stat_e {
879 EFX_PHY_STAT_PMA_PMD_LINK_UP,
880 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
881 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
882 EFX_PHY_STAT_PMA_PMD_REV_A,
883 EFX_PHY_STAT_PMA_PMD_REV_B,
884 EFX_PHY_STAT_PMA_PMD_REV_C,
885 EFX_PHY_STAT_PMA_PMD_REV_D,
886 EFX_PHY_STAT_PCS_LINK_UP,
887 EFX_PHY_STAT_PCS_RX_FAULT,
888 EFX_PHY_STAT_PCS_TX_FAULT,
889 EFX_PHY_STAT_PCS_BER,
890 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
891 EFX_PHY_STAT_PHY_XS_LINK_UP,
892 EFX_PHY_STAT_PHY_XS_RX_FAULT,
893 EFX_PHY_STAT_PHY_XS_TX_FAULT,
894 EFX_PHY_STAT_PHY_XS_ALIGN,
895 EFX_PHY_STAT_PHY_XS_SYNC_A,
896 EFX_PHY_STAT_PHY_XS_SYNC_B,
897 EFX_PHY_STAT_PHY_XS_SYNC_C,
898 EFX_PHY_STAT_PHY_XS_SYNC_D,
899 EFX_PHY_STAT_AN_LINK_UP,
900 EFX_PHY_STAT_AN_MASTER,
901 EFX_PHY_STAT_AN_LOCAL_RX_OK,
902 EFX_PHY_STAT_AN_REMOTE_RX_OK,
903 EFX_PHY_STAT_CL22EXT_LINK_UP,
908 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
909 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
910 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
911 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
912 EFX_PHY_STAT_AN_COMPLETE,
913 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
914 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
915 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
916 EFX_PHY_STAT_PCS_FW_VERSION_0,
917 EFX_PHY_STAT_PCS_FW_VERSION_1,
918 EFX_PHY_STAT_PCS_FW_VERSION_2,
919 EFX_PHY_STAT_PCS_FW_VERSION_3,
920 EFX_PHY_STAT_PCS_FW_BUILD_YY,
921 EFX_PHY_STAT_PCS_FW_BUILD_MM,
922 EFX_PHY_STAT_PCS_FW_BUILD_DD,
923 EFX_PHY_STAT_PCS_OP_MODE,
927 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
934 __in efx_phy_stat_t stat);
936 #endif /* EFSYS_OPT_NAMES */
938 #define EFX_PHY_STATS_SIZE 0x100
940 extern __checkReturn efx_rc_t
941 efx_phy_stats_update(
943 __in efsys_mem_t *esmp,
944 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
946 #endif /* EFSYS_OPT_PHY_STATS */
948 #if EFSYS_OPT_PHY_PROPS
955 __in unsigned int id);
957 #endif /* EFSYS_OPT_NAMES */
959 #define EFX_PHY_PROP_DEFAULT 0x00000001
961 extern __checkReturn efx_rc_t
964 __in unsigned int id,
966 __out uint32_t *valp);
968 extern __checkReturn efx_rc_t
971 __in unsigned int id,
974 #endif /* EFSYS_OPT_PHY_PROPS */
978 typedef enum efx_bist_type_e {
979 EFX_BIST_TYPE_UNKNOWN,
980 EFX_BIST_TYPE_PHY_NORMAL,
981 EFX_BIST_TYPE_PHY_CABLE_SHORT,
982 EFX_BIST_TYPE_PHY_CABLE_LONG,
983 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
984 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus*/
985 EFX_BIST_TYPE_REG, /* Test the register memories */
986 EFX_BIST_TYPE_NTYPES,
989 typedef enum efx_bist_result_e {
990 EFX_BIST_RESULT_UNKNOWN,
991 EFX_BIST_RESULT_RUNNING,
992 EFX_BIST_RESULT_PASSED,
993 EFX_BIST_RESULT_FAILED,
996 typedef enum efx_phy_cable_status_e {
997 EFX_PHY_CABLE_STATUS_OK,
998 EFX_PHY_CABLE_STATUS_INVALID,
999 EFX_PHY_CABLE_STATUS_OPEN,
1000 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1001 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1002 EFX_PHY_CABLE_STATUS_BUSY,
1003 } efx_phy_cable_status_t;
1005 typedef enum efx_bist_value_e {
1006 EFX_BIST_PHY_CABLE_LENGTH_A,
1007 EFX_BIST_PHY_CABLE_LENGTH_B,
1008 EFX_BIST_PHY_CABLE_LENGTH_C,
1009 EFX_BIST_PHY_CABLE_LENGTH_D,
1010 EFX_BIST_PHY_CABLE_STATUS_A,
1011 EFX_BIST_PHY_CABLE_STATUS_B,
1012 EFX_BIST_PHY_CABLE_STATUS_C,
1013 EFX_BIST_PHY_CABLE_STATUS_D,
1014 EFX_BIST_FAULT_CODE,
1015 /* Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1020 EFX_BIST_MEM_EXPECT,
1021 EFX_BIST_MEM_ACTUAL,
1023 EFX_BIST_MEM_ECC_PARITY,
1024 EFX_BIST_MEM_ECC_FATAL,
1028 extern __checkReturn efx_rc_t
1029 efx_bist_enable_offline(
1030 __in efx_nic_t *enp);
1032 extern __checkReturn efx_rc_t
1034 __in efx_nic_t *enp,
1035 __in efx_bist_type_t type);
1037 extern __checkReturn efx_rc_t
1039 __in efx_nic_t *enp,
1040 __in efx_bist_type_t type,
1041 __out efx_bist_result_t *resultp,
1042 __out_opt uint32_t *value_maskp,
1043 __out_ecount_opt(count) unsigned long *valuesp,
1048 __in efx_nic_t *enp,
1049 __in efx_bist_type_t type);
1051 #endif /* EFSYS_OPT_BIST */
1053 #define EFX_FEATURE_IPV6 0x00000001
1054 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1055 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1056 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1057 #define EFX_FEATURE_WOL 0x00000010
1058 #define EFX_FEATURE_MCDI 0x00000020
1059 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1060 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1061 #define EFX_FEATURE_TURBO 0x00000100
1062 #define EFX_FEATURE_MCDI_DMA 0x00000200
1063 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1064 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1065 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1066 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1068 typedef struct efx_nic_cfg_s {
1069 uint32_t enc_board_type;
1070 uint32_t enc_phy_type;
1072 char enc_phy_name[21];
1074 char enc_phy_revision[21];
1075 efx_mon_type_t enc_mon_type;
1076 #if EFSYS_OPT_MON_STATS
1077 uint32_t enc_mon_stat_dma_buf_size;
1078 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1080 unsigned int enc_features;
1081 uint8_t enc_mac_addr[6];
1082 uint8_t enc_port; /* PHY port number */
1083 uint32_t enc_func_flags;
1084 uint32_t enc_intr_vec_base;
1085 uint32_t enc_intr_limit;
1086 uint32_t enc_evq_limit;
1087 uint32_t enc_txq_limit;
1088 uint32_t enc_rxq_limit;
1089 uint32_t enc_buftbl_limit;
1090 uint32_t enc_piobuf_limit;
1091 uint32_t enc_piobuf_size;
1092 uint32_t enc_piobuf_min_alloc_size;
1093 uint32_t enc_evq_timer_quantum_ns;
1094 uint32_t enc_evq_timer_max_us;
1095 uint32_t enc_clk_mult;
1096 uint32_t enc_rx_prefix_size;
1097 uint32_t enc_rx_buf_align_start;
1098 uint32_t enc_rx_buf_align_end;
1099 #if EFSYS_OPT_LOOPBACK
1100 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1101 #endif /* EFSYS_OPT_LOOPBACK */
1102 #if EFSYS_OPT_PHY_FLAGS
1103 uint32_t enc_phy_flags_mask;
1104 #endif /* EFSYS_OPT_PHY_FLAGS */
1105 #if EFSYS_OPT_PHY_LED_CONTROL
1106 uint32_t enc_led_mask;
1107 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1108 #if EFSYS_OPT_PHY_STATS
1109 uint64_t enc_phy_stat_mask;
1110 #endif /* EFSYS_OPT_PHY_STATS */
1111 #if EFSYS_OPT_PHY_PROPS
1112 unsigned int enc_phy_nprops;
1113 #endif /* EFSYS_OPT_PHY_PROPS */
1115 uint8_t enc_mcdi_mdio_channel;
1116 #if EFSYS_OPT_PHY_STATS
1117 uint32_t enc_mcdi_phy_stat_mask;
1118 #endif /* EFSYS_OPT_PHY_STATS */
1119 #endif /* EFSYS_OPT_SIENA */
1120 #if (EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
1121 #if EFSYS_OPT_MON_STATS
1122 uint32_t *enc_mcdi_sensor_maskp;
1123 uint32_t enc_mcdi_sensor_mask_size;
1124 #endif /* EFSYS_OPT_MON_STATS */
1125 #endif /* (EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
1127 uint32_t enc_bist_mask;
1128 #endif /* EFSYS_OPT_BIST */
1129 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
1132 uint32_t enc_privilege_mask;
1133 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
1134 boolean_t enc_bug26807_workaround;
1135 boolean_t enc_bug35388_workaround;
1136 boolean_t enc_bug41750_workaround;
1137 boolean_t enc_rx_batching_enabled;
1138 /* Maximum number of descriptors completed in an rx event. */
1139 uint32_t enc_rx_batch_max;
1140 /* Number of rx descriptors the hardware requires for a push. */
1141 uint32_t enc_rx_push_align;
1143 * Maximum number of bytes into the packet the TCP header can start for
1144 * the hardware to apply TSO packet edits.
1146 uint32_t enc_tx_tso_tcp_header_offset_limit;
1147 boolean_t enc_fw_assisted_tso_enabled;
1148 boolean_t enc_fw_assisted_tso_v2_enabled;
1149 boolean_t enc_hw_tx_insert_vlan_enabled;
1150 /* Datapath firmware vadapter/vport/vswitch support */
1151 boolean_t enc_datapath_cap_evb;
1152 boolean_t enc_rx_disable_scatter_supported;
1153 boolean_t enc_allow_set_mac_with_installed_filters;
1154 boolean_t enc_enhanced_set_mac_supported;
1155 /* External port identifier */
1156 uint8_t enc_external_port;
1157 uint32_t enc_mcdi_max_payload_length;
1158 /* VPD may be per-PF or global */
1159 boolean_t enc_vpd_is_global;
1162 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1163 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1165 #define EFX_PCI_FUNCTION(_encp) \
1166 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1168 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1170 extern const efx_nic_cfg_t *
1172 __in efx_nic_t *enp);
1174 /* Driver resource limits (minimum required/maximum usable). */
1175 typedef struct efx_drv_limits_s
1177 uint32_t edl_min_evq_count;
1178 uint32_t edl_max_evq_count;
1180 uint32_t edl_min_rxq_count;
1181 uint32_t edl_max_rxq_count;
1183 uint32_t edl_min_txq_count;
1184 uint32_t edl_max_txq_count;
1186 /* PIO blocks (sub-allocated from piobuf) */
1187 uint32_t edl_min_pio_alloc_size;
1188 uint32_t edl_max_pio_alloc_count;
1191 extern __checkReturn efx_rc_t
1192 efx_nic_set_drv_limits(
1193 __inout efx_nic_t *enp,
1194 __in efx_drv_limits_t *edlp);
1196 typedef enum efx_nic_region_e {
1197 EFX_REGION_VI, /* Memory BAR UC mapping */
1198 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1201 extern __checkReturn efx_rc_t
1202 efx_nic_get_bar_region(
1203 __in efx_nic_t *enp,
1204 __in efx_nic_region_t region,
1205 __out uint32_t *offsetp,
1206 __out size_t *sizep);
1208 extern __checkReturn efx_rc_t
1209 efx_nic_get_vi_pool(
1210 __in efx_nic_t *enp,
1211 __out uint32_t *evq_countp,
1212 __out uint32_t *rxq_countp,
1213 __out uint32_t *txq_countp);
1218 typedef enum efx_vpd_tag_e {
1225 typedef uint16_t efx_vpd_keyword_t;
1227 typedef struct efx_vpd_value_s {
1228 efx_vpd_tag_t evv_tag;
1229 efx_vpd_keyword_t evv_keyword;
1231 uint8_t evv_value[0x100];
1235 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1237 extern __checkReturn efx_rc_t
1239 __in efx_nic_t *enp);
1241 extern __checkReturn efx_rc_t
1243 __in efx_nic_t *enp,
1244 __out size_t *sizep);
1246 extern __checkReturn efx_rc_t
1248 __in efx_nic_t *enp,
1249 __out_bcount(size) caddr_t data,
1252 extern __checkReturn efx_rc_t
1254 __in efx_nic_t *enp,
1255 __in_bcount(size) caddr_t data,
1258 extern __checkReturn efx_rc_t
1260 __in efx_nic_t *enp,
1261 __in_bcount(size) caddr_t data,
1264 extern __checkReturn efx_rc_t
1266 __in efx_nic_t *enp,
1267 __in_bcount(size) caddr_t data,
1269 __inout efx_vpd_value_t *evvp);
1271 extern __checkReturn efx_rc_t
1273 __in efx_nic_t *enp,
1274 __inout_bcount(size) caddr_t data,
1276 __in efx_vpd_value_t *evvp);
1278 extern __checkReturn efx_rc_t
1280 __in efx_nic_t *enp,
1281 __inout_bcount(size) caddr_t data,
1283 __out efx_vpd_value_t *evvp,
1284 __inout unsigned int *contp);
1286 extern __checkReturn efx_rc_t
1288 __in efx_nic_t *enp,
1289 __in_bcount(size) caddr_t data,
1294 __in efx_nic_t *enp);
1296 #endif /* EFSYS_OPT_VPD */
1302 typedef enum efx_nvram_type_e {
1303 EFX_NVRAM_INVALID = 0,
1305 EFX_NVRAM_BOOTROM_CFG,
1306 EFX_NVRAM_MC_FIRMWARE,
1307 EFX_NVRAM_MC_GOLDEN,
1313 EFX_NVRAM_FPGA_BACKUP,
1314 EFX_NVRAM_DYNAMIC_CFG,
1319 extern __checkReturn efx_rc_t
1321 __in efx_nic_t *enp);
1325 extern __checkReturn efx_rc_t
1327 __in efx_nic_t *enp);
1329 #endif /* EFSYS_OPT_DIAG */
1331 extern __checkReturn efx_rc_t
1333 __in efx_nic_t *enp,
1334 __in efx_nvram_type_t type,
1335 __out size_t *sizep);
1337 extern __checkReturn efx_rc_t
1339 __in efx_nic_t *enp,
1340 __in efx_nvram_type_t type,
1341 __out_opt size_t *pref_chunkp);
1344 efx_nvram_rw_finish(
1345 __in efx_nic_t *enp,
1346 __in efx_nvram_type_t type);
1348 extern __checkReturn efx_rc_t
1349 efx_nvram_get_version(
1350 __in efx_nic_t *enp,
1351 __in efx_nvram_type_t type,
1352 __out uint32_t *subtypep,
1353 __out_ecount(4) uint16_t version[4]);
1355 extern __checkReturn efx_rc_t
1356 efx_nvram_read_chunk(
1357 __in efx_nic_t *enp,
1358 __in efx_nvram_type_t type,
1359 __in unsigned int offset,
1360 __out_bcount(size) caddr_t data,
1363 extern __checkReturn efx_rc_t
1364 efx_nvram_set_version(
1365 __in efx_nic_t *enp,
1366 __in efx_nvram_type_t type,
1367 __in_ecount(4) uint16_t version[4]);
1369 extern __checkReturn efx_rc_t
1371 __in efx_nic_t *enp,
1372 __in efx_nvram_type_t type,
1373 __in_bcount(partn_size) caddr_t partn_data,
1374 __in size_t partn_size);
1376 extern __checkReturn efx_rc_t
1378 __in efx_nic_t *enp,
1379 __in efx_nvram_type_t type);
1381 extern __checkReturn efx_rc_t
1382 efx_nvram_write_chunk(
1383 __in efx_nic_t *enp,
1384 __in efx_nvram_type_t type,
1385 __in unsigned int offset,
1386 __in_bcount(size) caddr_t data,
1391 __in efx_nic_t *enp);
1393 #endif /* EFSYS_OPT_NVRAM */
1395 #if EFSYS_OPT_BOOTCFG
1399 __in efx_nic_t *enp,
1400 __out_bcount(size) caddr_t data,
1405 __in efx_nic_t *enp,
1406 __in_bcount(size) caddr_t data,
1409 #endif /* EFSYS_OPT_BOOTCFG */
1413 typedef enum efx_wol_type_e {
1414 EFX_WOL_TYPE_INVALID,
1416 EFX_WOL_TYPE_BITMAP,
1421 typedef enum efx_lightsout_offload_type_e {
1422 EFX_LIGHTSOUT_OFFLOAD_TYPE_INVALID,
1423 EFX_LIGHTSOUT_OFFLOAD_TYPE_ARP,
1424 EFX_LIGHTSOUT_OFFLOAD_TYPE_NS,
1425 } efx_lightsout_offload_type_t;
1427 #define EFX_WOL_BITMAP_MASK_SIZE (48)
1428 #define EFX_WOL_BITMAP_VALUE_SIZE (128)
1430 typedef union efx_wol_param_u {
1432 uint8_t mac_addr[6];
1435 uint8_t mask[EFX_WOL_BITMAP_MASK_SIZE]; /* 1 bit per byte */
1436 uint8_t value[EFX_WOL_BITMAP_VALUE_SIZE]; /* value to match */
1441 typedef union efx_lightsout_offload_param_u {
1443 uint8_t mac_addr[6];
1447 uint8_t mac_addr[6];
1448 uint32_t solicited_node[4];
1451 } efx_lightsout_offload_param_t;
1453 extern __checkReturn efx_rc_t
1455 __in efx_nic_t *enp);
1457 extern __checkReturn efx_rc_t
1458 efx_wol_filter_clear(
1459 __in efx_nic_t *enp);
1461 extern __checkReturn efx_rc_t
1463 __in efx_nic_t *enp,
1464 __in efx_wol_type_t type,
1465 __in efx_wol_param_t *paramp,
1466 __out uint32_t *filter_idp);
1468 extern __checkReturn efx_rc_t
1469 efx_wol_filter_remove(
1470 __in efx_nic_t *enp,
1471 __in uint32_t filter_id);
1473 extern __checkReturn efx_rc_t
1474 efx_lightsout_offload_add(
1475 __in efx_nic_t *enp,
1476 __in efx_lightsout_offload_type_t type,
1477 __in efx_lightsout_offload_param_t *paramp,
1478 __out uint32_t *filter_idp);
1480 extern __checkReturn efx_rc_t
1481 efx_lightsout_offload_remove(
1482 __in efx_nic_t *enp,
1483 __in efx_lightsout_offload_type_t type,
1484 __in uint32_t filter_id);
1488 __in efx_nic_t *enp);
1490 #endif /* EFSYS_OPT_WOL */
1494 typedef enum efx_pattern_type_t {
1495 EFX_PATTERN_BYTE_INCREMENT = 0,
1496 EFX_PATTERN_ALL_THE_SAME,
1497 EFX_PATTERN_BIT_ALTERNATE,
1498 EFX_PATTERN_BYTE_ALTERNATE,
1499 EFX_PATTERN_BYTE_CHANGING,
1500 EFX_PATTERN_BIT_SWEEP,
1502 } efx_pattern_type_t;
1505 (*efx_sram_pattern_fn_t)(
1507 __in boolean_t negate,
1508 __out efx_qword_t *eqp);
1510 extern __checkReturn efx_rc_t
1512 __in efx_nic_t *enp,
1513 __in efx_pattern_type_t type);
1515 #endif /* EFSYS_OPT_DIAG */
1517 extern __checkReturn efx_rc_t
1518 efx_sram_buf_tbl_set(
1519 __in efx_nic_t *enp,
1521 __in efsys_mem_t *esmp,
1525 efx_sram_buf_tbl_clear(
1526 __in efx_nic_t *enp,
1530 #define EFX_BUF_TBL_SIZE 0x20000
1532 #define EFX_BUF_SIZE 4096
1536 typedef struct efx_evq_s efx_evq_t;
1538 #if EFSYS_OPT_QSTATS
1540 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1541 typedef enum efx_ev_qstat_e {
1547 EV_RX_PAUSE_FRM_ERR,
1548 EV_RX_BUF_OWNER_ID_ERR,
1549 EV_RX_IPV4_HDR_CHKSUM_ERR,
1550 EV_RX_TCP_UDP_CHKSUM_ERR,
1554 EV_RX_MCAST_HASH_MATCH,
1571 EV_DRIVER_SRM_UPD_DONE,
1572 EV_DRIVER_TX_DESCQ_FLS_DONE,
1573 EV_DRIVER_RX_DESCQ_FLS_DONE,
1574 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1575 EV_DRIVER_RX_DSC_ERROR,
1576 EV_DRIVER_TX_DSC_ERROR,
1582 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1584 #endif /* EFSYS_OPT_QSTATS */
1586 extern __checkReturn efx_rc_t
1588 __in efx_nic_t *enp);
1592 __in efx_nic_t *enp);
1594 #define EFX_EVQ_MAXNEVS 32768
1595 #define EFX_EVQ_MINNEVS 512
1597 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
1598 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1600 extern __checkReturn efx_rc_t
1602 __in efx_nic_t *enp,
1603 __in unsigned int index,
1604 __in efsys_mem_t *esmp,
1607 __deref_out efx_evq_t **eepp);
1611 __in efx_evq_t *eep,
1612 __in uint16_t data);
1614 typedef __checkReturn boolean_t
1615 (*efx_initialized_ev_t)(
1616 __in_opt void *arg);
1618 #define EFX_PKT_UNICAST 0x0004
1619 #define EFX_PKT_START 0x0008
1621 #define EFX_PKT_VLAN_TAGGED 0x0010
1622 #define EFX_CKSUM_TCPUDP 0x0020
1623 #define EFX_CKSUM_IPV4 0x0040
1624 #define EFX_PKT_CONT 0x0080
1626 #define EFX_CHECK_VLAN 0x0100
1627 #define EFX_PKT_TCP 0x0200
1628 #define EFX_PKT_UDP 0x0400
1629 #define EFX_PKT_IPV4 0x0800
1631 #define EFX_PKT_IPV6 0x1000
1632 #define EFX_PKT_PREFIX_LEN 0x2000
1633 #define EFX_ADDR_MISMATCH 0x4000
1634 #define EFX_DISCARD 0x8000
1636 #define EFX_EV_RX_NLABELS 32
1637 #define EFX_EV_TX_NLABELS 32
1639 typedef __checkReturn boolean_t
1642 __in uint32_t label,
1645 __in uint16_t flags);
1647 typedef __checkReturn boolean_t
1650 __in uint32_t label,
1653 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
1654 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
1655 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
1656 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
1657 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
1658 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
1659 #define EFX_EXCEPTION_RX_ERROR 0x00000007
1660 #define EFX_EXCEPTION_TX_ERROR 0x00000008
1661 #define EFX_EXCEPTION_EV_ERROR 0x00000009
1663 typedef __checkReturn boolean_t
1664 (*efx_exception_ev_t)(
1666 __in uint32_t label,
1667 __in uint32_t data);
1669 typedef __checkReturn boolean_t
1670 (*efx_rxq_flush_done_ev_t)(
1672 __in uint32_t rxq_index);
1674 typedef __checkReturn boolean_t
1675 (*efx_rxq_flush_failed_ev_t)(
1677 __in uint32_t rxq_index);
1679 typedef __checkReturn boolean_t
1680 (*efx_txq_flush_done_ev_t)(
1682 __in uint32_t txq_index);
1684 typedef __checkReturn boolean_t
1685 (*efx_software_ev_t)(
1687 __in uint16_t magic);
1689 typedef __checkReturn boolean_t
1692 __in uint32_t code);
1694 #define EFX_SRAM_CLEAR 0
1695 #define EFX_SRAM_UPDATE 1
1696 #define EFX_SRAM_ILLEGAL_CLEAR 2
1698 typedef __checkReturn boolean_t
1699 (*efx_wake_up_ev_t)(
1701 __in uint32_t label);
1703 typedef __checkReturn boolean_t
1706 __in uint32_t label);
1708 typedef __checkReturn boolean_t
1709 (*efx_link_change_ev_t)(
1711 __in efx_link_mode_t link_mode);
1713 #if EFSYS_OPT_MON_STATS
1715 typedef __checkReturn boolean_t
1716 (*efx_monitor_ev_t)(
1718 __in efx_mon_stat_t id,
1719 __in efx_mon_stat_value_t value);
1721 #endif /* EFSYS_OPT_MON_STATS */
1723 #if EFSYS_OPT_MAC_STATS
1725 typedef __checkReturn boolean_t
1726 (*efx_mac_stats_ev_t)(
1728 __in uint32_t generation
1731 #endif /* EFSYS_OPT_MAC_STATS */
1733 typedef struct efx_ev_callbacks_s {
1734 efx_initialized_ev_t eec_initialized;
1737 efx_exception_ev_t eec_exception;
1738 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
1739 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
1740 efx_txq_flush_done_ev_t eec_txq_flush_done;
1741 efx_software_ev_t eec_software;
1742 efx_sram_ev_t eec_sram;
1743 efx_wake_up_ev_t eec_wake_up;
1744 efx_timer_ev_t eec_timer;
1745 efx_link_change_ev_t eec_link_change;
1746 #if EFSYS_OPT_MON_STATS
1747 efx_monitor_ev_t eec_monitor;
1748 #endif /* EFSYS_OPT_MON_STATS */
1749 #if EFSYS_OPT_MAC_STATS
1750 efx_mac_stats_ev_t eec_mac_stats;
1751 #endif /* EFSYS_OPT_MAC_STATS */
1752 } efx_ev_callbacks_t;
1754 extern __checkReturn boolean_t
1756 __in efx_evq_t *eep,
1757 __in unsigned int count);
1759 #if EFSYS_OPT_EV_PREFETCH
1763 __in efx_evq_t *eep,
1764 __in unsigned int count);
1766 #endif /* EFSYS_OPT_EV_PREFETCH */
1770 __in efx_evq_t *eep,
1771 __inout unsigned int *countp,
1772 __in const efx_ev_callbacks_t *eecp,
1773 __in_opt void *arg);
1775 extern __checkReturn efx_rc_t
1777 __in efx_evq_t *eep,
1778 __in unsigned int us);
1780 extern __checkReturn efx_rc_t
1782 __in efx_evq_t *eep,
1783 __in unsigned int count);
1785 #if EFSYS_OPT_QSTATS
1791 __in efx_nic_t *enp,
1792 __in unsigned int id);
1794 #endif /* EFSYS_OPT_NAMES */
1797 efx_ev_qstats_update(
1798 __in efx_evq_t *eep,
1799 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
1801 #endif /* EFSYS_OPT_QSTATS */
1805 __in efx_evq_t *eep);
1809 extern __checkReturn efx_rc_t
1811 __inout efx_nic_t *enp);
1815 __in efx_nic_t *enp);
1817 #if EFSYS_OPT_RX_SCATTER
1818 __checkReturn efx_rc_t
1819 efx_rx_scatter_enable(
1820 __in efx_nic_t *enp,
1821 __in unsigned int buf_size);
1822 #endif /* EFSYS_OPT_RX_SCATTER */
1824 #if EFSYS_OPT_RX_SCALE
1826 typedef enum efx_rx_hash_alg_e {
1827 EFX_RX_HASHALG_LFSR = 0,
1828 EFX_RX_HASHALG_TOEPLITZ
1829 } efx_rx_hash_alg_t;
1831 typedef enum efx_rx_hash_type_e {
1832 EFX_RX_HASH_IPV4 = 0,
1833 EFX_RX_HASH_TCPIPV4,
1835 EFX_RX_HASH_TCPIPV6,
1836 } efx_rx_hash_type_t;
1838 typedef enum efx_rx_hash_support_e {
1839 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
1840 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
1841 } efx_rx_hash_support_t;
1843 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
1844 #define EFX_MAXRSS 64 /* RX indirection entry range */
1845 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
1847 typedef enum efx_rx_scale_support_e {
1848 EFX_RX_SCALE_UNAVAILABLE = 0, /* Not supported */
1849 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
1850 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
1851 } efx_rx_scale_support_t;
1853 extern __checkReturn efx_rc_t
1854 efx_rx_hash_support_get(
1855 __in efx_nic_t *enp,
1856 __out efx_rx_hash_support_t *supportp);
1859 extern __checkReturn efx_rc_t
1860 efx_rx_scale_support_get(
1861 __in efx_nic_t *enp,
1862 __out efx_rx_scale_support_t *supportp);
1864 extern __checkReturn efx_rc_t
1865 efx_rx_scale_mode_set(
1866 __in efx_nic_t *enp,
1867 __in efx_rx_hash_alg_t alg,
1868 __in efx_rx_hash_type_t type,
1869 __in boolean_t insert);
1871 extern __checkReturn efx_rc_t
1872 efx_rx_scale_tbl_set(
1873 __in efx_nic_t *enp,
1874 __in_ecount(n) unsigned int *table,
1877 extern __checkReturn efx_rc_t
1878 efx_rx_scale_key_set(
1879 __in efx_nic_t *enp,
1880 __in_ecount(n) uint8_t *key,
1883 extern __checkReturn uint32_t
1884 efx_psuedo_hdr_hash_get(
1885 __in efx_nic_t *enp,
1886 __in efx_rx_hash_alg_t func,
1887 __in uint8_t *buffer);
1889 #endif /* EFSYS_OPT_RX_SCALE */
1891 extern __checkReturn efx_rc_t
1892 efx_psuedo_hdr_pkt_length_get(
1893 __in efx_nic_t *enp,
1894 __in uint8_t *buffer,
1895 __out uint16_t *pkt_lengthp);
1897 #define EFX_RXQ_MAXNDESCS 4096
1898 #define EFX_RXQ_MINNDESCS 512
1900 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
1901 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1902 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
1903 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
1905 typedef enum efx_rxq_type_e {
1906 EFX_RXQ_TYPE_DEFAULT,
1907 EFX_RXQ_TYPE_SCATTER,
1911 extern __checkReturn efx_rc_t
1913 __in efx_nic_t *enp,
1914 __in unsigned int index,
1915 __in unsigned int label,
1916 __in efx_rxq_type_t type,
1917 __in efsys_mem_t *esmp,
1920 __in efx_evq_t *eep,
1921 __deref_out efx_rxq_t **erpp);
1923 typedef struct efx_buffer_s {
1924 efsys_dma_addr_t eb_addr;
1929 typedef struct efx_desc_s {
1935 __in efx_rxq_t *erp,
1936 __in_ecount(n) efsys_dma_addr_t *addrp,
1938 __in unsigned int n,
1939 __in unsigned int completed,
1940 __in unsigned int added);
1944 __in efx_rxq_t *erp,
1945 __in unsigned int added,
1946 __inout unsigned int *pushedp);
1948 extern __checkReturn efx_rc_t
1950 __in efx_rxq_t *erp);
1954 __in efx_rxq_t *erp);
1958 __in efx_rxq_t *erp);
1962 typedef struct efx_txq_s efx_txq_t;
1964 #if EFSYS_OPT_QSTATS
1966 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
1967 typedef enum efx_tx_qstat_e {
1973 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
1975 #endif /* EFSYS_OPT_QSTATS */
1977 extern __checkReturn efx_rc_t
1979 __in efx_nic_t *enp);
1983 __in efx_nic_t *enp);
1985 #define EFX_BUG35388_WORKAROUND(_encp) \
1986 (((_encp) == NULL) ? 1 : ((_encp)->enc_bug35388_workaround != 0))
1988 #define EFX_TXQ_MAXNDESCS(_encp) \
1989 ((EFX_BUG35388_WORKAROUND(_encp)) ? 2048 : 4096)
1991 #define EFX_TXQ_MINNDESCS 512
1993 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
1994 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1995 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
1996 #define EFX_TXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
1998 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2000 #define EFX_TXQ_CKSUM_IPV4 0x0001
2001 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
2002 #define EFX_TXQ_FATSOV2 0x0004
2004 extern __checkReturn efx_rc_t
2006 __in efx_nic_t *enp,
2007 __in unsigned int index,
2008 __in unsigned int label,
2009 __in efsys_mem_t *esmp,
2012 __in uint16_t flags,
2013 __in efx_evq_t *eep,
2014 __deref_out efx_txq_t **etpp,
2015 __out unsigned int *addedp);
2017 extern __checkReturn efx_rc_t
2019 __in efx_txq_t *etp,
2020 __in_ecount(n) efx_buffer_t *eb,
2021 __in unsigned int n,
2022 __in unsigned int completed,
2023 __inout unsigned int *addedp);
2025 extern __checkReturn efx_rc_t
2027 __in efx_txq_t *etp,
2028 __in unsigned int ns);
2032 __in efx_txq_t *etp,
2033 __in unsigned int added,
2034 __in unsigned int pushed);
2036 extern __checkReturn efx_rc_t
2038 __in efx_txq_t *etp);
2042 __in efx_txq_t *etp);
2044 extern __checkReturn efx_rc_t
2046 __in efx_txq_t *etp);
2049 efx_tx_qpio_disable(
2050 __in efx_txq_t *etp);
2052 extern __checkReturn efx_rc_t
2054 __in efx_txq_t *etp,
2055 __in_ecount(buf_length) uint8_t *buffer,
2056 __in size_t buf_length,
2057 __in size_t pio_buf_offset);
2059 extern __checkReturn efx_rc_t
2061 __in efx_txq_t *etp,
2062 __in size_t pkt_length,
2063 __in unsigned int completed,
2064 __inout unsigned int *addedp);
2066 extern __checkReturn efx_rc_t
2068 __in efx_txq_t *etp,
2069 __in_ecount(n) efx_desc_t *ed,
2070 __in unsigned int n,
2071 __in unsigned int completed,
2072 __inout unsigned int *addedp);
2075 efx_tx_qdesc_dma_create(
2076 __in efx_txq_t *etp,
2077 __in efsys_dma_addr_t addr,
2080 __out efx_desc_t *edp);
2083 efx_tx_qdesc_tso_create(
2084 __in efx_txq_t *etp,
2085 __in uint16_t ipv4_id,
2086 __in uint32_t tcp_seq,
2087 __in uint8_t tcp_flags,
2088 __out efx_desc_t *edp);
2090 /* Number of FATSOv2 option descriptors */
2091 #define EFX_TX_FATSOV2_OPT_NDESCS 2
2093 /* Maximum number of DMA segments per TSO packet (not superframe) */
2094 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
2097 efx_tx_qdesc_tso2_create(
2098 __in efx_txq_t *etp,
2099 __in uint16_t ipv4_id,
2100 __in uint32_t tcp_seq,
2101 __in uint16_t tcp_mss,
2102 __out_ecount(count) efx_desc_t *edp,
2106 efx_tx_qdesc_vlantci_create(
2107 __in efx_txq_t *etp,
2109 __out efx_desc_t *edp);
2111 #if EFSYS_OPT_QSTATS
2117 __in efx_nic_t *etp,
2118 __in unsigned int id);
2120 #endif /* EFSYS_OPT_NAMES */
2123 efx_tx_qstats_update(
2124 __in efx_txq_t *etp,
2125 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
2127 #endif /* EFSYS_OPT_QSTATS */
2131 __in efx_txq_t *etp);
2136 #if EFSYS_OPT_FILTER
2138 #define EFX_ETHER_TYPE_IPV4 0x0800
2139 #define EFX_ETHER_TYPE_IPV6 0x86DD
2141 #define EFX_IPPROTO_TCP 6
2142 #define EFX_IPPROTO_UDP 17
2144 typedef enum efx_filter_flag_e {
2145 EFX_FILTER_FLAG_RX_RSS = 0x01, /* use RSS to spread across
2146 * multiple queues */
2147 EFX_FILTER_FLAG_RX_SCATTER = 0x02, /* enable RX scatter */
2148 EFX_FILTER_FLAG_RX_OVER_AUTO = 0x04, /* Override an automatic filter
2149 * (priority EFX_FILTER_PRI_AUTO).
2150 * May only be set by the filter
2151 * implementation for each type.
2152 * A removal request will
2153 * restore the automatic filter
2155 EFX_FILTER_FLAG_RX = 0x08, /* Filter is for RX */
2156 EFX_FILTER_FLAG_TX = 0x10, /* Filter is for TX */
2157 } efx_filter_flag_t;
2159 typedef enum efx_filter_match_flags_e {
2160 EFX_FILTER_MATCH_REM_HOST = 0x0001, /* Match by remote IP host
2162 EFX_FILTER_MATCH_LOC_HOST = 0x0002, /* Match by local IP host
2164 EFX_FILTER_MATCH_REM_MAC = 0x0004, /* Match by remote MAC address */
2165 EFX_FILTER_MATCH_REM_PORT = 0x0008, /* Match by remote TCP/UDP port */
2166 EFX_FILTER_MATCH_LOC_MAC = 0x0010, /* Match by remote TCP/UDP port */
2167 EFX_FILTER_MATCH_LOC_PORT = 0x0020, /* Match by local TCP/UDP port */
2168 EFX_FILTER_MATCH_ETHER_TYPE = 0x0040, /* Match by Ether-type */
2169 EFX_FILTER_MATCH_INNER_VID = 0x0080, /* Match by inner VLAN ID */
2170 EFX_FILTER_MATCH_OUTER_VID = 0x0100, /* Match by outer VLAN ID */
2171 EFX_FILTER_MATCH_IP_PROTO = 0x0200, /* Match by IP transport
2173 EFX_FILTER_MATCH_LOC_MAC_IG = 0x0400, /* Match by local MAC address
2174 * I/G bit. Used for RX default
2175 * unicast and multicast/
2176 * broadcast filters. */
2177 } efx_filter_match_flags_t;
2179 typedef enum efx_filter_priority_s {
2180 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
2181 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
2182 * address list or hardware
2183 * requirements. This may only be used
2184 * by the filter implementation for
2186 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
2187 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
2188 * client (e.g. SR-IOV, HyperV VMQ etc.)
2190 } efx_filter_priority_t;
2193 * FIXME: All these fields are assumed to be in little-endian byte order.
2194 * It may be better for some to be big-endian. See bug42804.
2197 typedef struct efx_filter_spec_s {
2198 uint32_t efs_match_flags:12;
2199 uint32_t efs_priority:2;
2200 uint32_t efs_flags:6;
2201 uint32_t efs_dmaq_id:12;
2202 uint32_t efs_rss_context;
2203 uint16_t efs_outer_vid;
2204 uint16_t efs_inner_vid;
2205 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
2206 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
2207 uint16_t efs_ether_type;
2208 uint8_t efs_ip_proto;
2209 uint16_t efs_loc_port;
2210 uint16_t efs_rem_port;
2211 efx_oword_t efs_rem_host;
2212 efx_oword_t efs_loc_host;
2213 } efx_filter_spec_t;
2216 /* Default values for use in filter specifications */
2217 #define EFX_FILTER_SPEC_RSS_CONTEXT_DEFAULT 0xffffffff
2218 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
2219 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
2221 extern __checkReturn efx_rc_t
2223 __in efx_nic_t *enp);
2227 __in efx_nic_t *enp);
2229 extern __checkReturn efx_rc_t
2231 __in efx_nic_t *enp,
2232 __inout efx_filter_spec_t *spec);
2234 extern __checkReturn efx_rc_t
2236 __in efx_nic_t *enp,
2237 __inout efx_filter_spec_t *spec);
2239 extern __checkReturn efx_rc_t
2241 __in efx_nic_t *enp);
2243 extern __checkReturn efx_rc_t
2244 efx_filter_supported_filters(
2245 __in efx_nic_t *enp,
2246 __out uint32_t *list,
2247 __out size_t *length);
2250 efx_filter_spec_init_rx(
2251 __out efx_filter_spec_t *spec,
2252 __in efx_filter_priority_t priority,
2253 __in efx_filter_flag_t flags,
2254 __in efx_rxq_t *erp);
2257 efx_filter_spec_init_tx(
2258 __out efx_filter_spec_t *spec,
2259 __in efx_txq_t *etp);
2261 extern __checkReturn efx_rc_t
2262 efx_filter_spec_set_ipv4_local(
2263 __inout efx_filter_spec_t *spec,
2266 __in uint16_t port);
2268 extern __checkReturn efx_rc_t
2269 efx_filter_spec_set_ipv4_full(
2270 __inout efx_filter_spec_t *spec,
2272 __in uint32_t lhost,
2273 __in uint16_t lport,
2274 __in uint32_t rhost,
2275 __in uint16_t rport);
2277 extern __checkReturn efx_rc_t
2278 efx_filter_spec_set_eth_local(
2279 __inout efx_filter_spec_t *spec,
2281 __in const uint8_t *addr);
2283 extern __checkReturn efx_rc_t
2284 efx_filter_spec_set_uc_def(
2285 __inout efx_filter_spec_t *spec);
2287 extern __checkReturn efx_rc_t
2288 efx_filter_spec_set_mc_def(
2289 __inout efx_filter_spec_t *spec);
2291 #endif /* EFSYS_OPT_FILTER */
2295 extern __checkReturn uint32_t
2297 __in_ecount(count) uint32_t const *input,
2299 __in uint32_t init);
2301 extern __checkReturn uint32_t
2303 __in_ecount(length) uint8_t const *input,
2305 __in uint32_t init);
2307 #if EFSYS_OPT_LICENSING
2311 typedef struct efx_key_stats_s {
2313 uint32_t eks_invalid;
2314 uint32_t eks_blacklisted;
2315 uint32_t eks_unverifiable;
2316 uint32_t eks_wrong_node;
2317 uint32_t eks_licensed_apps_lo;
2318 uint32_t eks_licensed_apps_hi;
2319 uint32_t eks_licensed_features_lo;
2320 uint32_t eks_licensed_features_hi;
2323 extern __checkReturn efx_rc_t
2325 __in efx_nic_t *enp);
2329 __in efx_nic_t *enp);
2331 extern __checkReturn efx_rc_t
2332 efx_lic_update_licenses(
2333 __in efx_nic_t *enp);
2335 extern __checkReturn efx_rc_t
2336 efx_lic_get_key_stats(
2337 __in efx_nic_t *enp,
2338 __out efx_key_stats_t *ksp);
2340 extern __checkReturn efx_rc_t
2342 __in efx_nic_t *enp,
2343 __in uint64_t app_id,
2344 __out boolean_t *licensedp);
2346 extern __checkReturn efx_rc_t
2348 __in efx_nic_t *enp,
2349 __in size_t buffer_size,
2350 __out uint32_t *typep,
2351 __out size_t *lengthp,
2352 __out_opt uint8_t *bufferp);
2355 #endif /* EFSYS_OPT_LICENSING */
2363 #endif /* _SYS_EFX_H */