2 * Copyright (c) 2006-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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37 #include "efx_check.h"
38 #include "efx_phy_ids.h"
44 #define EFX_STATIC_ASSERT(_cond) \
45 ((void)sizeof(char[(_cond) ? 1 : -1]))
47 #define EFX_ARRAY_SIZE(_array) \
48 (sizeof(_array) / sizeof((_array)[0]))
50 #define EFX_FIELD_OFFSET(_type, _field) \
51 ((size_t) &(((_type *)0)->_field))
55 typedef __success(return == 0) int efx_rc_t;
60 typedef enum efx_family_e {
62 EFX_FAMILY_FALCON, /* Obsolete and not supported */
64 EFX_FAMILY_HUNTINGTON,
69 extern __checkReturn efx_rc_t
73 __out efx_family_t *efp);
76 #define EFX_PCI_VENID_SFC 0x1924
78 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
80 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
81 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
82 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
84 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
85 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
86 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
88 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
89 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
91 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
92 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
93 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
102 EFX_ERR_BUFID_DC_OOB,
115 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
116 extern __checkReturn uint32_t
118 __in uint32_t crc_init,
119 __in_ecount(length) uint8_t const *input,
123 /* Type prototypes */
125 typedef struct efx_rxq_s efx_rxq_t;
129 typedef struct efx_nic_s efx_nic_t;
131 extern __checkReturn efx_rc_t
133 __in efx_family_t family,
134 __in efsys_identifier_t *esip,
135 __in efsys_bar_t *esbp,
136 __in efsys_lock_t *eslp,
137 __deref_out efx_nic_t **enpp);
139 extern __checkReturn efx_rc_t
141 __in efx_nic_t *enp);
143 extern __checkReturn efx_rc_t
145 __in efx_nic_t *enp);
147 extern __checkReturn efx_rc_t
149 __in efx_nic_t *enp);
153 extern __checkReturn efx_rc_t
154 efx_nic_register_test(
155 __in efx_nic_t *enp);
157 #endif /* EFSYS_OPT_DIAG */
161 __in efx_nic_t *enp);
165 __in efx_nic_t *enp);
169 __in efx_nic_t *enp);
171 #define EFX_PCIE_LINK_SPEED_GEN1 1
172 #define EFX_PCIE_LINK_SPEED_GEN2 2
173 #define EFX_PCIE_LINK_SPEED_GEN3 3
175 typedef enum efx_pcie_link_performance_e {
176 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
177 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
178 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
179 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
180 } efx_pcie_link_performance_t;
182 extern __checkReturn efx_rc_t
183 efx_nic_calculate_pcie_link_bandwidth(
184 __in uint32_t pcie_link_width,
185 __in uint32_t pcie_link_gen,
186 __out uint32_t *bandwidth_mbpsp);
188 extern __checkReturn efx_rc_t
189 efx_nic_check_pcie_link_speed(
191 __in uint32_t pcie_link_width,
192 __in uint32_t pcie_link_gen,
193 __out efx_pcie_link_performance_t *resultp);
197 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
198 /* Huntington and Medford require MCDIv2 commands */
199 #define WITH_MCDI_V2 1
202 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
204 typedef enum efx_mcdi_exception_e {
205 EFX_MCDI_EXCEPTION_MC_REBOOT,
206 EFX_MCDI_EXCEPTION_MC_BADASSERT,
207 } efx_mcdi_exception_t;
209 #if EFSYS_OPT_MCDI_LOGGING
210 typedef enum efx_log_msg_e {
212 EFX_LOG_MCDI_REQUEST,
213 EFX_LOG_MCDI_RESPONSE,
215 #endif /* EFSYS_OPT_MCDI_LOGGING */
217 typedef struct efx_mcdi_transport_s {
219 efsys_mem_t *emt_dma_mem;
220 void (*emt_execute)(void *, efx_mcdi_req_t *);
221 void (*emt_ev_cpl)(void *);
222 void (*emt_exception)(void *, efx_mcdi_exception_t);
223 #if EFSYS_OPT_MCDI_LOGGING
224 void (*emt_logger)(void *, efx_log_msg_t,
225 void *, size_t, void *, size_t);
226 #endif /* EFSYS_OPT_MCDI_LOGGING */
227 #if EFSYS_OPT_MCDI_PROXY_AUTH
228 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
229 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
230 } efx_mcdi_transport_t;
232 extern __checkReturn efx_rc_t
235 __in const efx_mcdi_transport_t *mtp);
237 extern __checkReturn efx_rc_t
239 __in efx_nic_t *enp);
243 __in efx_nic_t *enp);
246 efx_mcdi_request_start(
248 __in efx_mcdi_req_t *emrp,
249 __in boolean_t ev_cpl);
251 extern __checkReturn boolean_t
252 efx_mcdi_request_poll(
253 __in efx_nic_t *enp);
255 extern __checkReturn boolean_t
256 efx_mcdi_request_abort(
257 __in efx_nic_t *enp);
261 __in efx_nic_t *enp);
263 #endif /* EFSYS_OPT_MCDI */
267 #define EFX_NINTR_SIENA 1024
269 typedef enum efx_intr_type_e {
270 EFX_INTR_INVALID = 0,
276 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
278 extern __checkReturn efx_rc_t
281 __in efx_intr_type_t type,
282 __in efsys_mem_t *esmp);
286 __in efx_nic_t *enp);
290 __in efx_nic_t *enp);
293 efx_intr_disable_unlocked(
294 __in efx_nic_t *enp);
296 #define EFX_INTR_NEVQS 32
298 extern __checkReturn efx_rc_t
301 __in unsigned int level);
304 efx_intr_status_line(
306 __out boolean_t *fatalp,
307 __out uint32_t *maskp);
310 efx_intr_status_message(
312 __in unsigned int message,
313 __out boolean_t *fatalp);
317 __in efx_nic_t *enp);
321 __in efx_nic_t *enp);
325 #if EFSYS_OPT_MAC_STATS
327 /* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */
328 typedef enum efx_mac_stat_e {
331 EFX_MAC_RX_UNICST_PKTS,
332 EFX_MAC_RX_MULTICST_PKTS,
333 EFX_MAC_RX_BRDCST_PKTS,
334 EFX_MAC_RX_PAUSE_PKTS,
335 EFX_MAC_RX_LE_64_PKTS,
336 EFX_MAC_RX_65_TO_127_PKTS,
337 EFX_MAC_RX_128_TO_255_PKTS,
338 EFX_MAC_RX_256_TO_511_PKTS,
339 EFX_MAC_RX_512_TO_1023_PKTS,
340 EFX_MAC_RX_1024_TO_15XX_PKTS,
341 EFX_MAC_RX_GE_15XX_PKTS,
343 EFX_MAC_RX_FCS_ERRORS,
344 EFX_MAC_RX_DROP_EVENTS,
345 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
346 EFX_MAC_RX_SYMBOL_ERRORS,
347 EFX_MAC_RX_ALIGN_ERRORS,
348 EFX_MAC_RX_INTERNAL_ERRORS,
349 EFX_MAC_RX_JABBER_PKTS,
350 EFX_MAC_RX_LANE0_CHAR_ERR,
351 EFX_MAC_RX_LANE1_CHAR_ERR,
352 EFX_MAC_RX_LANE2_CHAR_ERR,
353 EFX_MAC_RX_LANE3_CHAR_ERR,
354 EFX_MAC_RX_LANE0_DISP_ERR,
355 EFX_MAC_RX_LANE1_DISP_ERR,
356 EFX_MAC_RX_LANE2_DISP_ERR,
357 EFX_MAC_RX_LANE3_DISP_ERR,
358 EFX_MAC_RX_MATCH_FAULT,
359 EFX_MAC_RX_NODESC_DROP_CNT,
362 EFX_MAC_TX_UNICST_PKTS,
363 EFX_MAC_TX_MULTICST_PKTS,
364 EFX_MAC_TX_BRDCST_PKTS,
365 EFX_MAC_TX_PAUSE_PKTS,
366 EFX_MAC_TX_LE_64_PKTS,
367 EFX_MAC_TX_65_TO_127_PKTS,
368 EFX_MAC_TX_128_TO_255_PKTS,
369 EFX_MAC_TX_256_TO_511_PKTS,
370 EFX_MAC_TX_512_TO_1023_PKTS,
371 EFX_MAC_TX_1024_TO_15XX_PKTS,
372 EFX_MAC_TX_GE_15XX_PKTS,
374 EFX_MAC_TX_SGL_COL_PKTS,
375 EFX_MAC_TX_MULT_COL_PKTS,
376 EFX_MAC_TX_EX_COL_PKTS,
377 EFX_MAC_TX_LATE_COL_PKTS,
379 EFX_MAC_TX_EX_DEF_PKTS,
380 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
381 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
382 EFX_MAC_PM_TRUNC_VFIFO_FULL,
383 EFX_MAC_PM_DISCARD_VFIFO_FULL,
384 EFX_MAC_PM_TRUNC_QBB,
385 EFX_MAC_PM_DISCARD_QBB,
386 EFX_MAC_PM_DISCARD_MAPPING,
387 EFX_MAC_RXDP_Q_DISABLED_PKTS,
388 EFX_MAC_RXDP_DI_DROPPED_PKTS,
389 EFX_MAC_RXDP_STREAMING_PKTS,
390 EFX_MAC_RXDP_HLB_FETCH,
391 EFX_MAC_RXDP_HLB_WAIT,
392 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
393 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
394 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
395 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
396 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
397 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
398 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
399 EFX_MAC_VADAPTER_RX_BAD_BYTES,
400 EFX_MAC_VADAPTER_RX_OVERFLOW,
401 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
402 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
403 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
404 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
405 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
406 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
407 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
408 EFX_MAC_VADAPTER_TX_BAD_BYTES,
409 EFX_MAC_VADAPTER_TX_OVERFLOW,
413 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
415 #endif /* EFSYS_OPT_MAC_STATS */
417 typedef enum efx_link_mode_e {
418 EFX_LINK_UNKNOWN = 0,
431 #define EFX_MAC_ADDR_LEN 6
433 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
435 #define EFX_MAC_MULTICAST_LIST_MAX 256
437 #define EFX_MAC_SDU_MAX 9202
439 #define EFX_MAC_PDU_ADJUSTMENT \
443 + /* bug16011 */ 16) \
445 #define EFX_MAC_PDU(_sdu) \
446 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
449 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
450 * the SDU rounded up slightly.
452 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
454 #define EFX_MAC_PDU_MIN 60
455 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
457 extern __checkReturn efx_rc_t
462 extern __checkReturn efx_rc_t
467 extern __checkReturn efx_rc_t
472 extern __checkReturn efx_rc_t
475 __in boolean_t all_unicst,
476 __in boolean_t mulcst,
477 __in boolean_t all_mulcst,
478 __in boolean_t brdcst);
480 extern __checkReturn efx_rc_t
481 efx_mac_multicast_list_set(
483 __in_ecount(6*count) uint8_t const *addrs,
486 extern __checkReturn efx_rc_t
487 efx_mac_filter_default_rxq_set(
490 __in boolean_t using_rss);
493 efx_mac_filter_default_rxq_clear(
494 __in efx_nic_t *enp);
496 extern __checkReturn efx_rc_t
499 __in boolean_t enabled);
501 extern __checkReturn efx_rc_t
504 __out boolean_t *mac_upp);
506 #define EFX_FCNTL_RESPOND 0x00000001
507 #define EFX_FCNTL_GENERATE 0x00000002
509 extern __checkReturn efx_rc_t
512 __in unsigned int fcntl,
513 __in boolean_t autoneg);
518 __out unsigned int *fcntl_wantedp,
519 __out unsigned int *fcntl_linkp);
522 #if EFSYS_OPT_MAC_STATS
526 extern __checkReturn const char *
529 __in unsigned int id);
531 #endif /* EFSYS_OPT_NAMES */
533 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
535 #define EFX_MAC_STATS_MASK_NPAGES \
536 (P2ROUNDUP(EFX_MAC_NSTATS, EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
537 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
540 * Get mask of MAC statistics supported by the hardware.
542 * If mask_size is insufficient to return the mask, EINVAL error is
543 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
544 * (which is sizeof (uint32_t)) is sufficient.
546 extern __checkReturn efx_rc_t
547 efx_mac_stats_get_mask(
549 __out_bcount(mask_size) uint32_t *maskp,
550 __in size_t mask_size);
552 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
553 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
554 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
556 #define EFX_MAC_STATS_SIZE 0x400
559 * Upload mac statistics supported by the hardware into the given buffer.
561 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes,
564 * The hardware will only DMA statistics that it understands (of course).
565 * Drivers should not make any assumptions about which statistics are
566 * supported, especially when the statistics are generated by firmware.
568 * Thus, drivers should zero this buffer before use, so that not-understood
569 * statistics read back as zero.
571 extern __checkReturn efx_rc_t
572 efx_mac_stats_upload(
574 __in efsys_mem_t *esmp);
576 extern __checkReturn efx_rc_t
577 efx_mac_stats_periodic(
579 __in efsys_mem_t *esmp,
580 __in uint16_t period_ms,
581 __in boolean_t events);
583 extern __checkReturn efx_rc_t
584 efx_mac_stats_update(
586 __in efsys_mem_t *esmp,
587 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
588 __inout_opt uint32_t *generationp);
590 #endif /* EFSYS_OPT_MAC_STATS */
594 typedef enum efx_mon_type_e {
606 __in efx_nic_t *enp);
608 #endif /* EFSYS_OPT_NAMES */
610 extern __checkReturn efx_rc_t
612 __in efx_nic_t *enp);
614 #if EFSYS_OPT_MON_STATS
616 #define EFX_MON_STATS_PAGE_SIZE 0x100
617 #define EFX_MON_MASK_ELEMENT_SIZE 32
619 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 5d4ee5185e419abe */
620 typedef enum efx_mon_stat_e {
627 EFX_MON_STAT_EXT_TEMP,
628 EFX_MON_STAT_INT_TEMP,
631 EFX_MON_STAT_INT_COOLING,
632 EFX_MON_STAT_EXT_COOLING,
640 EFX_MON_STAT_AOE_TEMP,
641 EFX_MON_STAT_PSU_AOE_TEMP,
642 EFX_MON_STAT_PSU_TEMP,
648 EFX_MON_STAT_VAOE_IN,
650 EFX_MON_STAT_IAOE_IN,
651 EFX_MON_STAT_NIC_POWER,
655 EFX_MON_STAT_0_9V_ADC,
656 EFX_MON_STAT_INT_TEMP2,
657 EFX_MON_STAT_VREG_TEMP,
658 EFX_MON_STAT_VREG_0_9V_TEMP,
659 EFX_MON_STAT_VREG_1_2V_TEMP,
660 EFX_MON_STAT_INT_VPTAT,
661 EFX_MON_STAT_INT_ADC_TEMP,
662 EFX_MON_STAT_EXT_VPTAT,
663 EFX_MON_STAT_EXT_ADC_TEMP,
664 EFX_MON_STAT_AMBIENT_TEMP,
665 EFX_MON_STAT_AIRFLOW,
666 EFX_MON_STAT_VDD08D_VSS08D_CSR,
667 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
668 EFX_MON_STAT_HOTPOINT_TEMP,
669 EFX_MON_STAT_PHY_POWER_SWITCH_PORT0,
670 EFX_MON_STAT_PHY_POWER_SWITCH_PORT1,
671 EFX_MON_STAT_MUM_VCC,
674 EFX_MON_STAT_0V9_A_TEMP,
677 EFX_MON_STAT_0V9_B_TEMP,
678 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
679 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,
680 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
681 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,
682 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
683 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
684 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,
685 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,
686 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
687 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
688 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,
689 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,
690 EFX_MON_STAT_SODIMM_VOUT,
691 EFX_MON_STAT_SODIMM_0_TEMP,
692 EFX_MON_STAT_SODIMM_1_TEMP,
693 EFX_MON_STAT_PHY0_VCC,
694 EFX_MON_STAT_PHY1_VCC,
695 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
696 EFX_MON_STAT_BOARD_FRONT_TEMP,
697 EFX_MON_STAT_BOARD_BACK_TEMP,
701 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
703 typedef enum efx_mon_stat_state_e {
704 EFX_MON_STAT_STATE_OK = 0,
705 EFX_MON_STAT_STATE_WARNING = 1,
706 EFX_MON_STAT_STATE_FATAL = 2,
707 EFX_MON_STAT_STATE_BROKEN = 3,
708 EFX_MON_STAT_STATE_NO_READING = 4,
709 } efx_mon_stat_state_t;
711 typedef struct efx_mon_stat_value_s {
714 } efx_mon_stat_value_t;
721 __in efx_mon_stat_t id);
723 #endif /* EFSYS_OPT_NAMES */
725 extern __checkReturn efx_rc_t
726 efx_mon_stats_update(
728 __in efsys_mem_t *esmp,
729 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
731 #endif /* EFSYS_OPT_MON_STATS */
735 __in efx_nic_t *enp);
739 extern __checkReturn efx_rc_t
741 __in efx_nic_t *enp);
743 #if EFSYS_OPT_PHY_LED_CONTROL
745 typedef enum efx_phy_led_mode_e {
746 EFX_PHY_LED_DEFAULT = 0,
751 } efx_phy_led_mode_t;
753 extern __checkReturn efx_rc_t
756 __in efx_phy_led_mode_t mode);
758 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
760 extern __checkReturn efx_rc_t
762 __in efx_nic_t *enp);
764 #if EFSYS_OPT_LOOPBACK
766 typedef enum efx_loopback_type_e {
767 EFX_LOOPBACK_OFF = 0,
768 EFX_LOOPBACK_DATA = 1,
769 EFX_LOOPBACK_GMAC = 2,
770 EFX_LOOPBACK_XGMII = 3,
771 EFX_LOOPBACK_XGXS = 4,
772 EFX_LOOPBACK_XAUI = 5,
773 EFX_LOOPBACK_GMII = 6,
774 EFX_LOOPBACK_SGMII = 7,
775 EFX_LOOPBACK_XGBR = 8,
776 EFX_LOOPBACK_XFI = 9,
777 EFX_LOOPBACK_XAUI_FAR = 10,
778 EFX_LOOPBACK_GMII_FAR = 11,
779 EFX_LOOPBACK_SGMII_FAR = 12,
780 EFX_LOOPBACK_XFI_FAR = 13,
781 EFX_LOOPBACK_GPHY = 14,
782 EFX_LOOPBACK_PHY_XS = 15,
783 EFX_LOOPBACK_PCS = 16,
784 EFX_LOOPBACK_PMA_PMD = 17,
785 EFX_LOOPBACK_XPORT = 18,
786 EFX_LOOPBACK_XGMII_WS = 19,
787 EFX_LOOPBACK_XAUI_WS = 20,
788 EFX_LOOPBACK_XAUI_WS_FAR = 21,
789 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
790 EFX_LOOPBACK_GMII_WS = 23,
791 EFX_LOOPBACK_XFI_WS = 24,
792 EFX_LOOPBACK_XFI_WS_FAR = 25,
793 EFX_LOOPBACK_PHYXS_WS = 26,
794 EFX_LOOPBACK_PMA_INT = 27,
795 EFX_LOOPBACK_SD_NEAR = 28,
796 EFX_LOOPBACK_SD_FAR = 29,
797 EFX_LOOPBACK_PMA_INT_WS = 30,
798 EFX_LOOPBACK_SD_FEP2_WS = 31,
799 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
800 EFX_LOOPBACK_SD_FEP_WS = 33,
801 EFX_LOOPBACK_SD_FES_WS = 34,
803 } efx_loopback_type_t;
805 typedef enum efx_loopback_kind_e {
806 EFX_LOOPBACK_KIND_OFF = 0,
807 EFX_LOOPBACK_KIND_ALL,
808 EFX_LOOPBACK_KIND_MAC,
809 EFX_LOOPBACK_KIND_PHY,
811 } efx_loopback_kind_t;
815 __in efx_loopback_kind_t loopback_kind,
816 __out efx_qword_t *maskp);
818 extern __checkReturn efx_rc_t
819 efx_port_loopback_set(
821 __in efx_link_mode_t link_mode,
822 __in efx_loopback_type_t type);
826 extern __checkReturn const char *
827 efx_loopback_type_name(
829 __in efx_loopback_type_t type);
831 #endif /* EFSYS_OPT_NAMES */
833 #endif /* EFSYS_OPT_LOOPBACK */
835 extern __checkReturn efx_rc_t
838 __out_opt efx_link_mode_t *link_modep);
842 __in efx_nic_t *enp);
844 typedef enum efx_phy_cap_type_e {
845 EFX_PHY_CAP_INVALID = 0,
852 EFX_PHY_CAP_10000FDX,
856 EFX_PHY_CAP_40000FDX,
858 } efx_phy_cap_type_t;
861 #define EFX_PHY_CAP_CURRENT 0x00000000
862 #define EFX_PHY_CAP_DEFAULT 0x00000001
863 #define EFX_PHY_CAP_PERM 0x00000002
869 __out uint32_t *maskp);
871 extern __checkReturn efx_rc_t
879 __out uint32_t *maskp);
881 extern __checkReturn efx_rc_t
884 __out uint32_t *ouip);
886 typedef enum efx_phy_media_type_e {
887 EFX_PHY_MEDIA_INVALID = 0,
892 EFX_PHY_MEDIA_SFP_PLUS,
893 EFX_PHY_MEDIA_BASE_T,
894 EFX_PHY_MEDIA_QSFP_PLUS,
896 } efx_phy_media_type_t;
898 /* Get the type of medium currently used. If the board has ports for
899 * modules, a module is present, and we recognise the media type of
900 * the module, then this will be the media type of the module.
901 * Otherwise it will be the media type of the port.
904 efx_phy_media_type_get(
906 __out efx_phy_media_type_t *typep);
909 efx_phy_module_get_info(
911 __in uint8_t dev_addr,
914 __out_bcount(len) uint8_t *data);
916 #if EFSYS_OPT_PHY_STATS
918 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
919 typedef enum efx_phy_stat_e {
921 EFX_PHY_STAT_PMA_PMD_LINK_UP,
922 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
923 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
924 EFX_PHY_STAT_PMA_PMD_REV_A,
925 EFX_PHY_STAT_PMA_PMD_REV_B,
926 EFX_PHY_STAT_PMA_PMD_REV_C,
927 EFX_PHY_STAT_PMA_PMD_REV_D,
928 EFX_PHY_STAT_PCS_LINK_UP,
929 EFX_PHY_STAT_PCS_RX_FAULT,
930 EFX_PHY_STAT_PCS_TX_FAULT,
931 EFX_PHY_STAT_PCS_BER,
932 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
933 EFX_PHY_STAT_PHY_XS_LINK_UP,
934 EFX_PHY_STAT_PHY_XS_RX_FAULT,
935 EFX_PHY_STAT_PHY_XS_TX_FAULT,
936 EFX_PHY_STAT_PHY_XS_ALIGN,
937 EFX_PHY_STAT_PHY_XS_SYNC_A,
938 EFX_PHY_STAT_PHY_XS_SYNC_B,
939 EFX_PHY_STAT_PHY_XS_SYNC_C,
940 EFX_PHY_STAT_PHY_XS_SYNC_D,
941 EFX_PHY_STAT_AN_LINK_UP,
942 EFX_PHY_STAT_AN_MASTER,
943 EFX_PHY_STAT_AN_LOCAL_RX_OK,
944 EFX_PHY_STAT_AN_REMOTE_RX_OK,
945 EFX_PHY_STAT_CL22EXT_LINK_UP,
950 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
951 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
952 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
953 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
954 EFX_PHY_STAT_AN_COMPLETE,
955 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
956 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
957 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
958 EFX_PHY_STAT_PCS_FW_VERSION_0,
959 EFX_PHY_STAT_PCS_FW_VERSION_1,
960 EFX_PHY_STAT_PCS_FW_VERSION_2,
961 EFX_PHY_STAT_PCS_FW_VERSION_3,
962 EFX_PHY_STAT_PCS_FW_BUILD_YY,
963 EFX_PHY_STAT_PCS_FW_BUILD_MM,
964 EFX_PHY_STAT_PCS_FW_BUILD_DD,
965 EFX_PHY_STAT_PCS_OP_MODE,
969 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
976 __in efx_phy_stat_t stat);
978 #endif /* EFSYS_OPT_NAMES */
980 #define EFX_PHY_STATS_SIZE 0x100
982 extern __checkReturn efx_rc_t
983 efx_phy_stats_update(
985 __in efsys_mem_t *esmp,
986 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
988 #endif /* EFSYS_OPT_PHY_STATS */
993 typedef enum efx_bist_type_e {
994 EFX_BIST_TYPE_UNKNOWN,
995 EFX_BIST_TYPE_PHY_NORMAL,
996 EFX_BIST_TYPE_PHY_CABLE_SHORT,
997 EFX_BIST_TYPE_PHY_CABLE_LONG,
998 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
999 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus*/
1000 EFX_BIST_TYPE_REG, /* Test the register memories */
1001 EFX_BIST_TYPE_NTYPES,
1004 typedef enum efx_bist_result_e {
1005 EFX_BIST_RESULT_UNKNOWN,
1006 EFX_BIST_RESULT_RUNNING,
1007 EFX_BIST_RESULT_PASSED,
1008 EFX_BIST_RESULT_FAILED,
1009 } efx_bist_result_t;
1011 typedef enum efx_phy_cable_status_e {
1012 EFX_PHY_CABLE_STATUS_OK,
1013 EFX_PHY_CABLE_STATUS_INVALID,
1014 EFX_PHY_CABLE_STATUS_OPEN,
1015 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1016 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1017 EFX_PHY_CABLE_STATUS_BUSY,
1018 } efx_phy_cable_status_t;
1020 typedef enum efx_bist_value_e {
1021 EFX_BIST_PHY_CABLE_LENGTH_A,
1022 EFX_BIST_PHY_CABLE_LENGTH_B,
1023 EFX_BIST_PHY_CABLE_LENGTH_C,
1024 EFX_BIST_PHY_CABLE_LENGTH_D,
1025 EFX_BIST_PHY_CABLE_STATUS_A,
1026 EFX_BIST_PHY_CABLE_STATUS_B,
1027 EFX_BIST_PHY_CABLE_STATUS_C,
1028 EFX_BIST_PHY_CABLE_STATUS_D,
1029 EFX_BIST_FAULT_CODE,
1030 /* Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1035 EFX_BIST_MEM_EXPECT,
1036 EFX_BIST_MEM_ACTUAL,
1038 EFX_BIST_MEM_ECC_PARITY,
1039 EFX_BIST_MEM_ECC_FATAL,
1043 extern __checkReturn efx_rc_t
1044 efx_bist_enable_offline(
1045 __in efx_nic_t *enp);
1047 extern __checkReturn efx_rc_t
1049 __in efx_nic_t *enp,
1050 __in efx_bist_type_t type);
1052 extern __checkReturn efx_rc_t
1054 __in efx_nic_t *enp,
1055 __in efx_bist_type_t type,
1056 __out efx_bist_result_t *resultp,
1057 __out_opt uint32_t *value_maskp,
1058 __out_ecount_opt(count) unsigned long *valuesp,
1063 __in efx_nic_t *enp,
1064 __in efx_bist_type_t type);
1066 #endif /* EFSYS_OPT_BIST */
1068 #define EFX_FEATURE_IPV6 0x00000001
1069 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1070 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1071 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1072 #define EFX_FEATURE_WOL 0x00000010
1073 #define EFX_FEATURE_MCDI 0x00000020
1074 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1075 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1076 #define EFX_FEATURE_TURBO 0x00000100
1077 #define EFX_FEATURE_MCDI_DMA 0x00000200
1078 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1079 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1080 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1081 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1083 typedef struct efx_nic_cfg_s {
1084 uint32_t enc_board_type;
1085 uint32_t enc_phy_type;
1087 char enc_phy_name[21];
1089 char enc_phy_revision[21];
1090 efx_mon_type_t enc_mon_type;
1091 #if EFSYS_OPT_MON_STATS
1092 uint32_t enc_mon_stat_dma_buf_size;
1093 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1095 unsigned int enc_features;
1096 uint8_t enc_mac_addr[6];
1097 uint8_t enc_port; /* PHY port number */
1098 uint32_t enc_intr_vec_base;
1099 uint32_t enc_intr_limit;
1100 uint32_t enc_evq_limit;
1101 uint32_t enc_txq_limit;
1102 uint32_t enc_rxq_limit;
1103 uint32_t enc_buftbl_limit;
1104 uint32_t enc_piobuf_limit;
1105 uint32_t enc_piobuf_size;
1106 uint32_t enc_piobuf_min_alloc_size;
1107 uint32_t enc_evq_timer_quantum_ns;
1108 uint32_t enc_evq_timer_max_us;
1109 uint32_t enc_clk_mult;
1110 uint32_t enc_rx_prefix_size;
1111 uint32_t enc_rx_buf_align_start;
1112 uint32_t enc_rx_buf_align_end;
1113 #if EFSYS_OPT_LOOPBACK
1114 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1115 #endif /* EFSYS_OPT_LOOPBACK */
1116 #if EFSYS_OPT_PHY_FLAGS
1117 uint32_t enc_phy_flags_mask;
1118 #endif /* EFSYS_OPT_PHY_FLAGS */
1119 #if EFSYS_OPT_PHY_LED_CONTROL
1120 uint32_t enc_led_mask;
1121 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1122 #if EFSYS_OPT_PHY_STATS
1123 uint64_t enc_phy_stat_mask;
1124 #endif /* EFSYS_OPT_PHY_STATS */
1126 uint8_t enc_mcdi_mdio_channel;
1127 #if EFSYS_OPT_PHY_STATS
1128 uint32_t enc_mcdi_phy_stat_mask;
1129 #endif /* EFSYS_OPT_PHY_STATS */
1130 #if EFSYS_OPT_MON_STATS
1131 uint32_t *enc_mcdi_sensor_maskp;
1132 uint32_t enc_mcdi_sensor_mask_size;
1133 #endif /* EFSYS_OPT_MON_STATS */
1134 #endif /* EFSYS_OPT_MCDI */
1136 uint32_t enc_bist_mask;
1137 #endif /* EFSYS_OPT_BIST */
1138 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
1141 uint32_t enc_privilege_mask;
1142 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
1143 boolean_t enc_bug26807_workaround;
1144 boolean_t enc_bug35388_workaround;
1145 boolean_t enc_bug41750_workaround;
1146 boolean_t enc_bug61265_workaround;
1147 boolean_t enc_rx_batching_enabled;
1148 /* Maximum number of descriptors completed in an rx event. */
1149 uint32_t enc_rx_batch_max;
1150 /* Number of rx descriptors the hardware requires for a push. */
1151 uint32_t enc_rx_push_align;
1153 * Maximum number of bytes into the packet the TCP header can start for
1154 * the hardware to apply TSO packet edits.
1156 uint32_t enc_tx_tso_tcp_header_offset_limit;
1157 boolean_t enc_fw_assisted_tso_enabled;
1158 boolean_t enc_fw_assisted_tso_v2_enabled;
1159 /* Number of TSO contexts on the NIC (FATSOv2) */
1160 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1161 boolean_t enc_hw_tx_insert_vlan_enabled;
1162 /* Number of PFs on the NIC */
1163 uint32_t enc_hw_pf_count;
1164 /* Datapath firmware vadapter/vport/vswitch support */
1165 boolean_t enc_datapath_cap_evb;
1166 boolean_t enc_rx_disable_scatter_supported;
1167 boolean_t enc_allow_set_mac_with_installed_filters;
1168 boolean_t enc_enhanced_set_mac_supported;
1169 boolean_t enc_init_evq_v2_supported;
1170 boolean_t enc_pm_and_rxdp_counters;
1171 boolean_t enc_mac_stats_40g_tx_size_bins;
1172 /* External port identifier */
1173 uint8_t enc_external_port;
1174 uint32_t enc_mcdi_max_payload_length;
1175 /* VPD may be per-PF or global */
1176 boolean_t enc_vpd_is_global;
1177 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1178 uint32_t enc_required_pcie_bandwidth_mbps;
1179 uint32_t enc_max_pcie_link_gen;
1182 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1183 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1185 #define EFX_PCI_FUNCTION(_encp) \
1186 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1188 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1190 extern const efx_nic_cfg_t *
1192 __in efx_nic_t *enp);
1194 /* Driver resource limits (minimum required/maximum usable). */
1195 typedef struct efx_drv_limits_s {
1196 uint32_t edl_min_evq_count;
1197 uint32_t edl_max_evq_count;
1199 uint32_t edl_min_rxq_count;
1200 uint32_t edl_max_rxq_count;
1202 uint32_t edl_min_txq_count;
1203 uint32_t edl_max_txq_count;
1205 /* PIO blocks (sub-allocated from piobuf) */
1206 uint32_t edl_min_pio_alloc_size;
1207 uint32_t edl_max_pio_alloc_count;
1210 extern __checkReturn efx_rc_t
1211 efx_nic_set_drv_limits(
1212 __inout efx_nic_t *enp,
1213 __in efx_drv_limits_t *edlp);
1215 typedef enum efx_nic_region_e {
1216 EFX_REGION_VI, /* Memory BAR UC mapping */
1217 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1220 extern __checkReturn efx_rc_t
1221 efx_nic_get_bar_region(
1222 __in efx_nic_t *enp,
1223 __in efx_nic_region_t region,
1224 __out uint32_t *offsetp,
1225 __out size_t *sizep);
1227 extern __checkReturn efx_rc_t
1228 efx_nic_get_vi_pool(
1229 __in efx_nic_t *enp,
1230 __out uint32_t *evq_countp,
1231 __out uint32_t *rxq_countp,
1232 __out uint32_t *txq_countp);
1237 typedef enum efx_vpd_tag_e {
1244 typedef uint16_t efx_vpd_keyword_t;
1246 typedef struct efx_vpd_value_s {
1247 efx_vpd_tag_t evv_tag;
1248 efx_vpd_keyword_t evv_keyword;
1250 uint8_t evv_value[0x100];
1254 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1256 extern __checkReturn efx_rc_t
1258 __in efx_nic_t *enp);
1260 extern __checkReturn efx_rc_t
1262 __in efx_nic_t *enp,
1263 __out size_t *sizep);
1265 extern __checkReturn efx_rc_t
1267 __in efx_nic_t *enp,
1268 __out_bcount(size) caddr_t data,
1271 extern __checkReturn efx_rc_t
1273 __in efx_nic_t *enp,
1274 __in_bcount(size) caddr_t data,
1277 extern __checkReturn efx_rc_t
1279 __in efx_nic_t *enp,
1280 __in_bcount(size) caddr_t data,
1283 extern __checkReturn efx_rc_t
1285 __in efx_nic_t *enp,
1286 __in_bcount(size) caddr_t data,
1288 __inout efx_vpd_value_t *evvp);
1290 extern __checkReturn efx_rc_t
1292 __in efx_nic_t *enp,
1293 __inout_bcount(size) caddr_t data,
1295 __in efx_vpd_value_t *evvp);
1297 extern __checkReturn efx_rc_t
1299 __in efx_nic_t *enp,
1300 __inout_bcount(size) caddr_t data,
1302 __out efx_vpd_value_t *evvp,
1303 __inout unsigned int *contp);
1305 extern __checkReturn efx_rc_t
1307 __in efx_nic_t *enp,
1308 __in_bcount(size) caddr_t data,
1313 __in efx_nic_t *enp);
1315 #endif /* EFSYS_OPT_VPD */
1321 typedef enum efx_nvram_type_e {
1322 EFX_NVRAM_INVALID = 0,
1324 EFX_NVRAM_BOOTROM_CFG,
1325 EFX_NVRAM_MC_FIRMWARE,
1326 EFX_NVRAM_MC_GOLDEN,
1332 EFX_NVRAM_FPGA_BACKUP,
1333 EFX_NVRAM_DYNAMIC_CFG,
1339 extern __checkReturn efx_rc_t
1341 __in efx_nic_t *enp);
1345 extern __checkReturn efx_rc_t
1347 __in efx_nic_t *enp);
1349 #endif /* EFSYS_OPT_DIAG */
1351 extern __checkReturn efx_rc_t
1353 __in efx_nic_t *enp,
1354 __in efx_nvram_type_t type,
1355 __out size_t *sizep);
1357 extern __checkReturn efx_rc_t
1359 __in efx_nic_t *enp,
1360 __in efx_nvram_type_t type,
1361 __out_opt size_t *pref_chunkp);
1364 efx_nvram_rw_finish(
1365 __in efx_nic_t *enp,
1366 __in efx_nvram_type_t type);
1368 extern __checkReturn efx_rc_t
1369 efx_nvram_get_version(
1370 __in efx_nic_t *enp,
1371 __in efx_nvram_type_t type,
1372 __out uint32_t *subtypep,
1373 __out_ecount(4) uint16_t version[4]);
1375 extern __checkReturn efx_rc_t
1376 efx_nvram_read_chunk(
1377 __in efx_nic_t *enp,
1378 __in efx_nvram_type_t type,
1379 __in unsigned int offset,
1380 __out_bcount(size) caddr_t data,
1383 extern __checkReturn efx_rc_t
1384 efx_nvram_set_version(
1385 __in efx_nic_t *enp,
1386 __in efx_nvram_type_t type,
1387 __in_ecount(4) uint16_t version[4]);
1389 extern __checkReturn efx_rc_t
1391 __in efx_nic_t *enp,
1392 __in efx_nvram_type_t type,
1393 __in_bcount(partn_size) caddr_t partn_data,
1394 __in size_t partn_size);
1396 extern __checkReturn efx_rc_t
1398 __in efx_nic_t *enp,
1399 __in efx_nvram_type_t type);
1401 extern __checkReturn efx_rc_t
1402 efx_nvram_write_chunk(
1403 __in efx_nic_t *enp,
1404 __in efx_nvram_type_t type,
1405 __in unsigned int offset,
1406 __in_bcount(size) caddr_t data,
1411 __in efx_nic_t *enp);
1413 #endif /* EFSYS_OPT_NVRAM */
1415 #if EFSYS_OPT_BOOTCFG
1419 __in efx_nic_t *enp,
1420 __out_bcount(size) caddr_t data,
1425 __in efx_nic_t *enp,
1426 __in_bcount(size) caddr_t data,
1429 #endif /* EFSYS_OPT_BOOTCFG */
1433 typedef enum efx_wol_type_e {
1434 EFX_WOL_TYPE_INVALID,
1436 EFX_WOL_TYPE_BITMAP,
1441 typedef enum efx_lightsout_offload_type_e {
1442 EFX_LIGHTSOUT_OFFLOAD_TYPE_INVALID,
1443 EFX_LIGHTSOUT_OFFLOAD_TYPE_ARP,
1444 EFX_LIGHTSOUT_OFFLOAD_TYPE_NS,
1445 } efx_lightsout_offload_type_t;
1447 #define EFX_WOL_BITMAP_MASK_SIZE (48)
1448 #define EFX_WOL_BITMAP_VALUE_SIZE (128)
1450 typedef union efx_wol_param_u {
1452 uint8_t mac_addr[6];
1455 uint8_t mask[EFX_WOL_BITMAP_MASK_SIZE]; /* 1 bit per byte */
1456 uint8_t value[EFX_WOL_BITMAP_VALUE_SIZE]; /* value to match */
1461 typedef union efx_lightsout_offload_param_u {
1463 uint8_t mac_addr[6];
1467 uint8_t mac_addr[6];
1468 uint32_t solicited_node[4];
1471 } efx_lightsout_offload_param_t;
1473 extern __checkReturn efx_rc_t
1475 __in efx_nic_t *enp);
1477 extern __checkReturn efx_rc_t
1478 efx_wol_filter_clear(
1479 __in efx_nic_t *enp);
1481 extern __checkReturn efx_rc_t
1483 __in efx_nic_t *enp,
1484 __in efx_wol_type_t type,
1485 __in efx_wol_param_t *paramp,
1486 __out uint32_t *filter_idp);
1488 extern __checkReturn efx_rc_t
1489 efx_wol_filter_remove(
1490 __in efx_nic_t *enp,
1491 __in uint32_t filter_id);
1493 extern __checkReturn efx_rc_t
1494 efx_lightsout_offload_add(
1495 __in efx_nic_t *enp,
1496 __in efx_lightsout_offload_type_t type,
1497 __in efx_lightsout_offload_param_t *paramp,
1498 __out uint32_t *filter_idp);
1500 extern __checkReturn efx_rc_t
1501 efx_lightsout_offload_remove(
1502 __in efx_nic_t *enp,
1503 __in efx_lightsout_offload_type_t type,
1504 __in uint32_t filter_id);
1508 __in efx_nic_t *enp);
1510 #endif /* EFSYS_OPT_WOL */
1514 typedef enum efx_pattern_type_t {
1515 EFX_PATTERN_BYTE_INCREMENT = 0,
1516 EFX_PATTERN_ALL_THE_SAME,
1517 EFX_PATTERN_BIT_ALTERNATE,
1518 EFX_PATTERN_BYTE_ALTERNATE,
1519 EFX_PATTERN_BYTE_CHANGING,
1520 EFX_PATTERN_BIT_SWEEP,
1522 } efx_pattern_type_t;
1525 (*efx_sram_pattern_fn_t)(
1527 __in boolean_t negate,
1528 __out efx_qword_t *eqp);
1530 extern __checkReturn efx_rc_t
1532 __in efx_nic_t *enp,
1533 __in efx_pattern_type_t type);
1535 #endif /* EFSYS_OPT_DIAG */
1537 extern __checkReturn efx_rc_t
1538 efx_sram_buf_tbl_set(
1539 __in efx_nic_t *enp,
1541 __in efsys_mem_t *esmp,
1545 efx_sram_buf_tbl_clear(
1546 __in efx_nic_t *enp,
1550 #define EFX_BUF_TBL_SIZE 0x20000
1552 #define EFX_BUF_SIZE 4096
1556 typedef struct efx_evq_s efx_evq_t;
1558 #if EFSYS_OPT_QSTATS
1560 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1561 typedef enum efx_ev_qstat_e {
1567 EV_RX_PAUSE_FRM_ERR,
1568 EV_RX_BUF_OWNER_ID_ERR,
1569 EV_RX_IPV4_HDR_CHKSUM_ERR,
1570 EV_RX_TCP_UDP_CHKSUM_ERR,
1574 EV_RX_MCAST_HASH_MATCH,
1591 EV_DRIVER_SRM_UPD_DONE,
1592 EV_DRIVER_TX_DESCQ_FLS_DONE,
1593 EV_DRIVER_RX_DESCQ_FLS_DONE,
1594 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1595 EV_DRIVER_RX_DSC_ERROR,
1596 EV_DRIVER_TX_DSC_ERROR,
1602 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1604 #endif /* EFSYS_OPT_QSTATS */
1606 extern __checkReturn efx_rc_t
1608 __in efx_nic_t *enp);
1612 __in efx_nic_t *enp);
1614 #define EFX_EVQ_MAXNEVS 32768
1615 #define EFX_EVQ_MINNEVS 512
1617 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
1618 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1620 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
1621 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
1622 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
1623 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
1625 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
1626 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
1627 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
1629 extern __checkReturn efx_rc_t
1631 __in efx_nic_t *enp,
1632 __in unsigned int index,
1633 __in efsys_mem_t *esmp,
1637 __in uint32_t flags,
1638 __deref_out efx_evq_t **eepp);
1642 __in efx_evq_t *eep,
1643 __in uint16_t data);
1645 typedef __checkReturn boolean_t
1646 (*efx_initialized_ev_t)(
1647 __in_opt void *arg);
1649 #define EFX_PKT_UNICAST 0x0004
1650 #define EFX_PKT_START 0x0008
1652 #define EFX_PKT_VLAN_TAGGED 0x0010
1653 #define EFX_CKSUM_TCPUDP 0x0020
1654 #define EFX_CKSUM_IPV4 0x0040
1655 #define EFX_PKT_CONT 0x0080
1657 #define EFX_CHECK_VLAN 0x0100
1658 #define EFX_PKT_TCP 0x0200
1659 #define EFX_PKT_UDP 0x0400
1660 #define EFX_PKT_IPV4 0x0800
1662 #define EFX_PKT_IPV6 0x1000
1663 #define EFX_PKT_PREFIX_LEN 0x2000
1664 #define EFX_ADDR_MISMATCH 0x4000
1665 #define EFX_DISCARD 0x8000
1667 #define EFX_EV_RX_NLABELS 32
1668 #define EFX_EV_TX_NLABELS 32
1670 typedef __checkReturn boolean_t
1673 __in uint32_t label,
1676 __in uint16_t flags);
1678 typedef __checkReturn boolean_t
1681 __in uint32_t label,
1684 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
1685 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
1686 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
1687 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
1688 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
1689 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
1690 #define EFX_EXCEPTION_RX_ERROR 0x00000007
1691 #define EFX_EXCEPTION_TX_ERROR 0x00000008
1692 #define EFX_EXCEPTION_EV_ERROR 0x00000009
1694 typedef __checkReturn boolean_t
1695 (*efx_exception_ev_t)(
1697 __in uint32_t label,
1698 __in uint32_t data);
1700 typedef __checkReturn boolean_t
1701 (*efx_rxq_flush_done_ev_t)(
1703 __in uint32_t rxq_index);
1705 typedef __checkReturn boolean_t
1706 (*efx_rxq_flush_failed_ev_t)(
1708 __in uint32_t rxq_index);
1710 typedef __checkReturn boolean_t
1711 (*efx_txq_flush_done_ev_t)(
1713 __in uint32_t txq_index);
1715 typedef __checkReturn boolean_t
1716 (*efx_software_ev_t)(
1718 __in uint16_t magic);
1720 typedef __checkReturn boolean_t
1723 __in uint32_t code);
1725 #define EFX_SRAM_CLEAR 0
1726 #define EFX_SRAM_UPDATE 1
1727 #define EFX_SRAM_ILLEGAL_CLEAR 2
1729 typedef __checkReturn boolean_t
1730 (*efx_wake_up_ev_t)(
1732 __in uint32_t label);
1734 typedef __checkReturn boolean_t
1737 __in uint32_t label);
1739 typedef __checkReturn boolean_t
1740 (*efx_link_change_ev_t)(
1742 __in efx_link_mode_t link_mode);
1744 #if EFSYS_OPT_MON_STATS
1746 typedef __checkReturn boolean_t
1747 (*efx_monitor_ev_t)(
1749 __in efx_mon_stat_t id,
1750 __in efx_mon_stat_value_t value);
1752 #endif /* EFSYS_OPT_MON_STATS */
1754 #if EFSYS_OPT_MAC_STATS
1756 typedef __checkReturn boolean_t
1757 (*efx_mac_stats_ev_t)(
1759 __in uint32_t generation
1762 #endif /* EFSYS_OPT_MAC_STATS */
1764 typedef struct efx_ev_callbacks_s {
1765 efx_initialized_ev_t eec_initialized;
1768 efx_exception_ev_t eec_exception;
1769 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
1770 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
1771 efx_txq_flush_done_ev_t eec_txq_flush_done;
1772 efx_software_ev_t eec_software;
1773 efx_sram_ev_t eec_sram;
1774 efx_wake_up_ev_t eec_wake_up;
1775 efx_timer_ev_t eec_timer;
1776 efx_link_change_ev_t eec_link_change;
1777 #if EFSYS_OPT_MON_STATS
1778 efx_monitor_ev_t eec_monitor;
1779 #endif /* EFSYS_OPT_MON_STATS */
1780 #if EFSYS_OPT_MAC_STATS
1781 efx_mac_stats_ev_t eec_mac_stats;
1782 #endif /* EFSYS_OPT_MAC_STATS */
1783 } efx_ev_callbacks_t;
1785 extern __checkReturn boolean_t
1787 __in efx_evq_t *eep,
1788 __in unsigned int count);
1790 #if EFSYS_OPT_EV_PREFETCH
1794 __in efx_evq_t *eep,
1795 __in unsigned int count);
1797 #endif /* EFSYS_OPT_EV_PREFETCH */
1801 __in efx_evq_t *eep,
1802 __inout unsigned int *countp,
1803 __in const efx_ev_callbacks_t *eecp,
1804 __in_opt void *arg);
1806 extern __checkReturn efx_rc_t
1807 efx_ev_usecs_to_ticks(
1808 __in efx_nic_t *enp,
1809 __in unsigned int usecs,
1810 __out unsigned int *ticksp);
1812 extern __checkReturn efx_rc_t
1814 __in efx_evq_t *eep,
1815 __in unsigned int us);
1817 extern __checkReturn efx_rc_t
1819 __in efx_evq_t *eep,
1820 __in unsigned int count);
1822 #if EFSYS_OPT_QSTATS
1828 __in efx_nic_t *enp,
1829 __in unsigned int id);
1831 #endif /* EFSYS_OPT_NAMES */
1834 efx_ev_qstats_update(
1835 __in efx_evq_t *eep,
1836 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
1838 #endif /* EFSYS_OPT_QSTATS */
1842 __in efx_evq_t *eep);
1846 extern __checkReturn efx_rc_t
1848 __inout efx_nic_t *enp);
1852 __in efx_nic_t *enp);
1854 #if EFSYS_OPT_RX_SCATTER
1855 __checkReturn efx_rc_t
1856 efx_rx_scatter_enable(
1857 __in efx_nic_t *enp,
1858 __in unsigned int buf_size);
1859 #endif /* EFSYS_OPT_RX_SCATTER */
1861 #if EFSYS_OPT_RX_SCALE
1863 typedef enum efx_rx_hash_alg_e {
1864 EFX_RX_HASHALG_LFSR = 0,
1865 EFX_RX_HASHALG_TOEPLITZ
1866 } efx_rx_hash_alg_t;
1868 #define EFX_RX_HASH_IPV4 (1U << 0)
1869 #define EFX_RX_HASH_TCPIPV4 (1U << 1)
1870 #define EFX_RX_HASH_IPV6 (1U << 2)
1871 #define EFX_RX_HASH_TCPIPV6 (1U << 3)
1873 typedef unsigned int efx_rx_hash_type_t;
1875 typedef enum efx_rx_hash_support_e {
1876 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
1877 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
1878 } efx_rx_hash_support_t;
1880 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
1881 #define EFX_MAXRSS 64 /* RX indirection entry range */
1882 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
1884 typedef enum efx_rx_scale_support_e {
1885 EFX_RX_SCALE_UNAVAILABLE = 0, /* Not supported */
1886 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
1887 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
1888 } efx_rx_scale_support_t;
1890 extern __checkReturn efx_rc_t
1891 efx_rx_hash_support_get(
1892 __in efx_nic_t *enp,
1893 __out efx_rx_hash_support_t *supportp);
1896 extern __checkReturn efx_rc_t
1897 efx_rx_scale_support_get(
1898 __in efx_nic_t *enp,
1899 __out efx_rx_scale_support_t *supportp);
1901 extern __checkReturn efx_rc_t
1902 efx_rx_scale_mode_set(
1903 __in efx_nic_t *enp,
1904 __in efx_rx_hash_alg_t alg,
1905 __in efx_rx_hash_type_t type,
1906 __in boolean_t insert);
1908 extern __checkReturn efx_rc_t
1909 efx_rx_scale_tbl_set(
1910 __in efx_nic_t *enp,
1911 __in_ecount(n) unsigned int *table,
1914 extern __checkReturn efx_rc_t
1915 efx_rx_scale_key_set(
1916 __in efx_nic_t *enp,
1917 __in_ecount(n) uint8_t *key,
1920 extern __checkReturn uint32_t
1921 efx_pseudo_hdr_hash_get(
1922 __in efx_rxq_t *erp,
1923 __in efx_rx_hash_alg_t func,
1924 __in uint8_t *buffer);
1926 #endif /* EFSYS_OPT_RX_SCALE */
1928 extern __checkReturn efx_rc_t
1929 efx_pseudo_hdr_pkt_length_get(
1930 __in efx_rxq_t *erp,
1931 __in uint8_t *buffer,
1932 __out uint16_t *pkt_lengthp);
1934 #define EFX_RXQ_MAXNDESCS 4096
1935 #define EFX_RXQ_MINNDESCS 512
1937 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
1938 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1939 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
1940 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
1942 typedef enum efx_rxq_type_e {
1943 EFX_RXQ_TYPE_DEFAULT,
1944 EFX_RXQ_TYPE_SCATTER,
1948 extern __checkReturn efx_rc_t
1950 __in efx_nic_t *enp,
1951 __in unsigned int index,
1952 __in unsigned int label,
1953 __in efx_rxq_type_t type,
1954 __in efsys_mem_t *esmp,
1957 __in efx_evq_t *eep,
1958 __deref_out efx_rxq_t **erpp);
1960 typedef struct efx_buffer_s {
1961 efsys_dma_addr_t eb_addr;
1966 typedef struct efx_desc_s {
1972 __in efx_rxq_t *erp,
1973 __in_ecount(n) efsys_dma_addr_t *addrp,
1975 __in unsigned int n,
1976 __in unsigned int completed,
1977 __in unsigned int added);
1981 __in efx_rxq_t *erp,
1982 __in unsigned int added,
1983 __inout unsigned int *pushedp);
1985 extern __checkReturn efx_rc_t
1987 __in efx_rxq_t *erp);
1991 __in efx_rxq_t *erp);
1995 __in efx_rxq_t *erp);
1999 typedef struct efx_txq_s efx_txq_t;
2001 #if EFSYS_OPT_QSTATS
2003 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
2004 typedef enum efx_tx_qstat_e {
2010 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
2012 #endif /* EFSYS_OPT_QSTATS */
2014 extern __checkReturn efx_rc_t
2016 __in efx_nic_t *enp);
2020 __in efx_nic_t *enp);
2022 #define EFX_BUG35388_WORKAROUND(_encp) \
2023 (((_encp) == NULL) ? 1 : ((_encp)->enc_bug35388_workaround != 0))
2025 #define EFX_TXQ_MAXNDESCS(_encp) \
2026 ((EFX_BUG35388_WORKAROUND(_encp)) ? 2048 : 4096)
2028 #define EFX_TXQ_MINNDESCS 512
2030 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2031 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2032 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2033 #define EFX_TXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
2035 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2037 #define EFX_TXQ_CKSUM_IPV4 0x0001
2038 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
2039 #define EFX_TXQ_FATSOV2 0x0004
2041 extern __checkReturn efx_rc_t
2043 __in efx_nic_t *enp,
2044 __in unsigned int index,
2045 __in unsigned int label,
2046 __in efsys_mem_t *esmp,
2049 __in uint16_t flags,
2050 __in efx_evq_t *eep,
2051 __deref_out efx_txq_t **etpp,
2052 __out unsigned int *addedp);
2054 extern __checkReturn efx_rc_t
2056 __in efx_txq_t *etp,
2057 __in_ecount(n) efx_buffer_t *eb,
2058 __in unsigned int n,
2059 __in unsigned int completed,
2060 __inout unsigned int *addedp);
2062 extern __checkReturn efx_rc_t
2064 __in efx_txq_t *etp,
2065 __in unsigned int ns);
2069 __in efx_txq_t *etp,
2070 __in unsigned int added,
2071 __in unsigned int pushed);
2073 extern __checkReturn efx_rc_t
2075 __in efx_txq_t *etp);
2079 __in efx_txq_t *etp);
2081 extern __checkReturn efx_rc_t
2083 __in efx_txq_t *etp);
2086 efx_tx_qpio_disable(
2087 __in efx_txq_t *etp);
2089 extern __checkReturn efx_rc_t
2091 __in efx_txq_t *etp,
2092 __in_ecount(buf_length) uint8_t *buffer,
2093 __in size_t buf_length,
2094 __in size_t pio_buf_offset);
2096 extern __checkReturn efx_rc_t
2098 __in efx_txq_t *etp,
2099 __in size_t pkt_length,
2100 __in unsigned int completed,
2101 __inout unsigned int *addedp);
2103 extern __checkReturn efx_rc_t
2105 __in efx_txq_t *etp,
2106 __in_ecount(n) efx_desc_t *ed,
2107 __in unsigned int n,
2108 __in unsigned int completed,
2109 __inout unsigned int *addedp);
2112 efx_tx_qdesc_dma_create(
2113 __in efx_txq_t *etp,
2114 __in efsys_dma_addr_t addr,
2117 __out efx_desc_t *edp);
2120 efx_tx_qdesc_tso_create(
2121 __in efx_txq_t *etp,
2122 __in uint16_t ipv4_id,
2123 __in uint32_t tcp_seq,
2124 __in uint8_t tcp_flags,
2125 __out efx_desc_t *edp);
2127 /* Number of FATSOv2 option descriptors */
2128 #define EFX_TX_FATSOV2_OPT_NDESCS 2
2130 /* Maximum number of DMA segments per TSO packet (not superframe) */
2131 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
2134 efx_tx_qdesc_tso2_create(
2135 __in efx_txq_t *etp,
2136 __in uint16_t ipv4_id,
2137 __in uint32_t tcp_seq,
2138 __in uint16_t tcp_mss,
2139 __out_ecount(count) efx_desc_t *edp,
2143 efx_tx_qdesc_vlantci_create(
2144 __in efx_txq_t *etp,
2146 __out efx_desc_t *edp);
2148 #if EFSYS_OPT_QSTATS
2154 __in efx_nic_t *etp,
2155 __in unsigned int id);
2157 #endif /* EFSYS_OPT_NAMES */
2160 efx_tx_qstats_update(
2161 __in efx_txq_t *etp,
2162 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
2164 #endif /* EFSYS_OPT_QSTATS */
2168 __in efx_txq_t *etp);
2173 #if EFSYS_OPT_FILTER
2175 #define EFX_ETHER_TYPE_IPV4 0x0800
2176 #define EFX_ETHER_TYPE_IPV6 0x86DD
2178 #define EFX_IPPROTO_TCP 6
2179 #define EFX_IPPROTO_UDP 17
2181 /* Use RSS to spread across multiple queues */
2182 #define EFX_FILTER_FLAG_RX_RSS 0x01
2183 /* Enable RX scatter */
2184 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
2186 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
2187 * May only be set by the filter implementation for each type.
2188 * A removal request will restore the automatic filter in its place.
2190 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
2191 /* Filter is for RX */
2192 #define EFX_FILTER_FLAG_RX 0x08
2193 /* Filter is for TX */
2194 #define EFX_FILTER_FLAG_TX 0x10
2196 typedef unsigned int efx_filter_flags_t;
2198 typedef enum efx_filter_match_flags_e {
2199 EFX_FILTER_MATCH_REM_HOST = 0x0001, /* Match by remote IP host
2201 EFX_FILTER_MATCH_LOC_HOST = 0x0002, /* Match by local IP host
2203 EFX_FILTER_MATCH_REM_MAC = 0x0004, /* Match by remote MAC address */
2204 EFX_FILTER_MATCH_REM_PORT = 0x0008, /* Match by remote TCP/UDP port */
2205 EFX_FILTER_MATCH_LOC_MAC = 0x0010, /* Match by remote TCP/UDP port */
2206 EFX_FILTER_MATCH_LOC_PORT = 0x0020, /* Match by local TCP/UDP port */
2207 EFX_FILTER_MATCH_ETHER_TYPE = 0x0040, /* Match by Ether-type */
2208 EFX_FILTER_MATCH_INNER_VID = 0x0080, /* Match by inner VLAN ID */
2209 EFX_FILTER_MATCH_OUTER_VID = 0x0100, /* Match by outer VLAN ID */
2210 EFX_FILTER_MATCH_IP_PROTO = 0x0200, /* Match by IP transport
2212 /* Match otherwise-unmatched multicast and broadcast packets */
2213 EFX_FILTER_MATCH_UNKNOWN_MCAST_DST = 0x40000000,
2214 /* Match otherwise-unmatched unicast packets */
2215 EFX_FILTER_MATCH_UNKNOWN_UCAST_DST = 0x80000000,
2216 } efx_filter_match_flags_t;
2218 typedef enum efx_filter_priority_s {
2219 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
2220 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
2221 * address list or hardware
2222 * requirements. This may only be used
2223 * by the filter implementation for
2225 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
2226 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
2227 * client (e.g. SR-IOV, HyperV VMQ etc.)
2229 } efx_filter_priority_t;
2232 * FIXME: All these fields are assumed to be in little-endian byte order.
2233 * It may be better for some to be big-endian. See bug42804.
2236 typedef struct efx_filter_spec_s {
2237 uint32_t efs_match_flags;
2238 uint32_t efs_priority:2;
2239 uint32_t efs_flags:6;
2240 uint32_t efs_dmaq_id:12;
2241 uint32_t efs_rss_context;
2242 uint16_t efs_outer_vid;
2243 uint16_t efs_inner_vid;
2244 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
2245 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
2246 uint16_t efs_ether_type;
2247 uint8_t efs_ip_proto;
2248 uint16_t efs_loc_port;
2249 uint16_t efs_rem_port;
2250 efx_oword_t efs_rem_host;
2251 efx_oword_t efs_loc_host;
2252 } efx_filter_spec_t;
2255 /* Default values for use in filter specifications */
2256 #define EFX_FILTER_SPEC_RSS_CONTEXT_DEFAULT 0xffffffff
2257 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
2258 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
2260 extern __checkReturn efx_rc_t
2262 __in efx_nic_t *enp);
2266 __in efx_nic_t *enp);
2268 extern __checkReturn efx_rc_t
2270 __in efx_nic_t *enp,
2271 __inout efx_filter_spec_t *spec);
2273 extern __checkReturn efx_rc_t
2275 __in efx_nic_t *enp,
2276 __inout efx_filter_spec_t *spec);
2278 extern __checkReturn efx_rc_t
2280 __in efx_nic_t *enp);
2282 extern __checkReturn efx_rc_t
2283 efx_filter_supported_filters(
2284 __in efx_nic_t *enp,
2285 __out_ecount(buffer_length) uint32_t *buffer,
2286 __in size_t buffer_length,
2287 __out size_t *list_lengthp);
2290 efx_filter_spec_init_rx(
2291 __out efx_filter_spec_t *spec,
2292 __in efx_filter_priority_t priority,
2293 __in efx_filter_flags_t flags,
2294 __in efx_rxq_t *erp);
2297 efx_filter_spec_init_tx(
2298 __out efx_filter_spec_t *spec,
2299 __in efx_txq_t *etp);
2301 extern __checkReturn efx_rc_t
2302 efx_filter_spec_set_ipv4_local(
2303 __inout efx_filter_spec_t *spec,
2306 __in uint16_t port);
2308 extern __checkReturn efx_rc_t
2309 efx_filter_spec_set_ipv4_full(
2310 __inout efx_filter_spec_t *spec,
2312 __in uint32_t lhost,
2313 __in uint16_t lport,
2314 __in uint32_t rhost,
2315 __in uint16_t rport);
2317 extern __checkReturn efx_rc_t
2318 efx_filter_spec_set_eth_local(
2319 __inout efx_filter_spec_t *spec,
2321 __in const uint8_t *addr);
2323 extern __checkReturn efx_rc_t
2324 efx_filter_spec_set_uc_def(
2325 __inout efx_filter_spec_t *spec);
2327 extern __checkReturn efx_rc_t
2328 efx_filter_spec_set_mc_def(
2329 __inout efx_filter_spec_t *spec);
2331 #endif /* EFSYS_OPT_FILTER */
2335 extern __checkReturn uint32_t
2337 __in_ecount(count) uint32_t const *input,
2339 __in uint32_t init);
2341 extern __checkReturn uint32_t
2343 __in_ecount(length) uint8_t const *input,
2345 __in uint32_t init);
2347 #if EFSYS_OPT_LICENSING
2351 typedef struct efx_key_stats_s {
2353 uint32_t eks_invalid;
2354 uint32_t eks_blacklisted;
2355 uint32_t eks_unverifiable;
2356 uint32_t eks_wrong_node;
2357 uint32_t eks_licensed_apps_lo;
2358 uint32_t eks_licensed_apps_hi;
2359 uint32_t eks_licensed_features_lo;
2360 uint32_t eks_licensed_features_hi;
2363 extern __checkReturn efx_rc_t
2365 __in efx_nic_t *enp);
2369 __in efx_nic_t *enp);
2371 extern __checkReturn boolean_t
2372 efx_lic_check_support(
2373 __in efx_nic_t *enp);
2375 extern __checkReturn efx_rc_t
2376 efx_lic_update_licenses(
2377 __in efx_nic_t *enp);
2379 extern __checkReturn efx_rc_t
2380 efx_lic_get_key_stats(
2381 __in efx_nic_t *enp,
2382 __out efx_key_stats_t *ksp);
2384 extern __checkReturn efx_rc_t
2386 __in efx_nic_t *enp,
2387 __in uint64_t app_id,
2388 __out boolean_t *licensedp);
2390 extern __checkReturn efx_rc_t
2392 __in efx_nic_t *enp,
2393 __in size_t buffer_size,
2394 __out uint32_t *typep,
2395 __out size_t *lengthp,
2396 __out_opt uint8_t *bufferp);
2399 extern __checkReturn efx_rc_t
2401 __in efx_nic_t *enp,
2402 __in_bcount(buffer_size)
2404 __in size_t buffer_size,
2405 __out uint32_t *startp
2408 extern __checkReturn efx_rc_t
2410 __in efx_nic_t *enp,
2411 __in_bcount(buffer_size)
2413 __in size_t buffer_size,
2414 __in uint32_t offset,
2415 __out uint32_t *endp
2418 extern __checkReturn __success(return != B_FALSE) boolean_t
2420 __in efx_nic_t *enp,
2421 __in_bcount(buffer_size)
2423 __in size_t buffer_size,
2424 __in uint32_t offset,
2425 __out uint32_t *startp,
2426 __out uint32_t *lengthp
2429 extern __checkReturn __success(return != B_FALSE) boolean_t
2430 efx_lic_validate_key(
2431 __in efx_nic_t *enp,
2432 __in_bcount(length) caddr_t keyp,
2433 __in uint32_t length
2436 extern __checkReturn efx_rc_t
2438 __in efx_nic_t *enp,
2439 __in_bcount(buffer_size)
2441 __in size_t buffer_size,
2442 __in uint32_t offset,
2443 __in uint32_t length,
2444 __out_bcount_part(key_max_size, *lengthp)
2446 __in size_t key_max_size,
2447 __out uint32_t *lengthp
2450 extern __checkReturn efx_rc_t
2452 __in efx_nic_t *enp,
2453 __in_bcount(buffer_size)
2455 __in size_t buffer_size,
2456 __in uint32_t offset,
2457 __in_bcount(length) caddr_t keyp,
2458 __in uint32_t length,
2459 __out uint32_t *lengthp
2462 __checkReturn efx_rc_t
2464 __in efx_nic_t *enp,
2465 __in_bcount(buffer_size)
2467 __in size_t buffer_size,
2468 __in uint32_t offset,
2469 __in uint32_t length,
2471 __out uint32_t *deltap
2474 extern __checkReturn efx_rc_t
2475 efx_lic_create_partition(
2476 __in efx_nic_t *enp,
2477 __in_bcount(buffer_size)
2479 __in size_t buffer_size
2482 extern __checkReturn efx_rc_t
2483 efx_lic_finish_partition(
2484 __in efx_nic_t *enp,
2485 __in_bcount(buffer_size)
2487 __in size_t buffer_size
2490 #endif /* EFSYS_OPT_LICENSING */
2498 #endif /* _SYS_EFX_H */