2 * Copyright (c) 2006-2015 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
37 #include "efx_phy_ids.h"
43 #define EFX_STATIC_ASSERT(_cond) \
44 ((void)sizeof(char[(_cond) ? 1 : -1]))
46 #define EFX_ARRAY_SIZE(_array) \
47 (sizeof(_array) / sizeof((_array)[0]))
49 #define EFX_FIELD_OFFSET(_type, _field) \
50 ((size_t) &(((_type *)0)->_field))
54 typedef __success(return == 0) int efx_rc_t;
59 typedef enum efx_family_e {
63 EFX_FAMILY_HUNTINGTON,
67 extern __checkReturn efx_rc_t
71 __out efx_family_t *efp);
73 extern __checkReturn efx_rc_t
75 __in efsys_bar_t *esbp,
76 __out efx_family_t *efp);
78 #define EFX_PCI_VENID_SFC 0x1924
80 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
82 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
83 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
84 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
86 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
87 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
88 #define EFX_PCI_DEVID_HUNTINGTON 0x0913 /* SFL9122 PF */
89 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
91 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
92 #define EFX_PCI_DEVID_HUNTINGTON_VF 0x1913 /* SFL9122 VF */
93 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
103 EFX_ERR_BUFID_DC_OOB,
116 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
117 extern __checkReturn uint32_t
119 __in uint32_t crc_init,
120 __in_ecount(length) uint8_t const *input,
124 /* Type prototypes */
126 typedef struct efx_rxq_s efx_rxq_t;
130 typedef struct efx_nic_s efx_nic_t;
132 #define EFX_NIC_FUNC_PRIMARY 0x00000001
133 #define EFX_NIC_FUNC_LINKCTRL 0x00000002
134 #define EFX_NIC_FUNC_TRUSTED 0x00000004
137 extern __checkReturn efx_rc_t
139 __in efx_family_t family,
140 __in efsys_identifier_t *esip,
141 __in efsys_bar_t *esbp,
142 __in efsys_lock_t *eslp,
143 __deref_out efx_nic_t **enpp);
145 extern __checkReturn efx_rc_t
147 __in efx_nic_t *enp);
149 #if EFSYS_OPT_PCIE_TUNE
151 extern __checkReturn efx_rc_t
154 unsigned int nlanes);
156 extern __checkReturn efx_rc_t
157 efx_nic_pcie_extended_sync(
158 __in efx_nic_t *enp);
160 #endif /* EFSYS_OPT_PCIE_TUNE */
162 extern __checkReturn efx_rc_t
164 __in efx_nic_t *enp);
166 extern __checkReturn efx_rc_t
168 __in efx_nic_t *enp);
172 extern __checkReturn efx_rc_t
173 efx_nic_register_test(
174 __in efx_nic_t *enp);
176 #endif /* EFSYS_OPT_DIAG */
180 __in efx_nic_t *enp);
184 __in efx_nic_t *enp);
188 __in efx_nic_t *enp);
192 #if EFSYS_OPT_HUNTINGTON
193 /* Huntington requires MCDIv2 commands */
194 #define WITH_MCDI_V2 1
197 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
199 typedef enum efx_mcdi_exception_e {
200 EFX_MCDI_EXCEPTION_MC_REBOOT,
201 EFX_MCDI_EXCEPTION_MC_BADASSERT,
202 } efx_mcdi_exception_t;
204 typedef struct efx_mcdi_transport_s {
206 efsys_mem_t *emt_dma_mem;
207 void (*emt_execute)(void *, efx_mcdi_req_t *);
208 void (*emt_ev_cpl)(void *);
209 void (*emt_exception)(void *, efx_mcdi_exception_t);
210 } efx_mcdi_transport_t;
212 extern __checkReturn efx_rc_t
215 __in const efx_mcdi_transport_t *mtp);
217 extern __checkReturn efx_rc_t
219 __in efx_nic_t *enp);
223 __in efx_nic_t *enp);
226 efx_mcdi_request_start(
228 __in efx_mcdi_req_t *emrp,
229 __in boolean_t ev_cpl);
231 extern __checkReturn boolean_t
232 efx_mcdi_request_poll(
233 __in efx_nic_t *enp);
235 extern __checkReturn boolean_t
236 efx_mcdi_request_abort(
237 __in efx_nic_t *enp);
241 __in efx_nic_t *enp);
243 #endif /* EFSYS_OPT_MCDI */
247 #define EFX_NINTR_FALCON 64
248 #define EFX_NINTR_SIENA 1024
250 typedef enum efx_intr_type_e {
251 EFX_INTR_INVALID = 0,
257 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
259 extern __checkReturn efx_rc_t
262 __in efx_intr_type_t type,
263 __in efsys_mem_t *esmp);
267 __in efx_nic_t *enp);
271 __in efx_nic_t *enp);
274 efx_intr_disable_unlocked(
275 __in efx_nic_t *enp);
277 #define EFX_INTR_NEVQS 32
279 extern __checkReturn efx_rc_t
282 __in unsigned int level);
285 efx_intr_status_line(
287 __out boolean_t *fatalp,
288 __out uint32_t *maskp);
291 efx_intr_status_message(
293 __in unsigned int message,
294 __out boolean_t *fatalp);
298 __in efx_nic_t *enp);
302 __in efx_nic_t *enp);
306 #if EFSYS_OPT_MAC_STATS
308 /* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */
309 typedef enum efx_mac_stat_e {
312 EFX_MAC_RX_UNICST_PKTS,
313 EFX_MAC_RX_MULTICST_PKTS,
314 EFX_MAC_RX_BRDCST_PKTS,
315 EFX_MAC_RX_PAUSE_PKTS,
316 EFX_MAC_RX_LE_64_PKTS,
317 EFX_MAC_RX_65_TO_127_PKTS,
318 EFX_MAC_RX_128_TO_255_PKTS,
319 EFX_MAC_RX_256_TO_511_PKTS,
320 EFX_MAC_RX_512_TO_1023_PKTS,
321 EFX_MAC_RX_1024_TO_15XX_PKTS,
322 EFX_MAC_RX_GE_15XX_PKTS,
324 EFX_MAC_RX_FCS_ERRORS,
325 EFX_MAC_RX_DROP_EVENTS,
326 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
327 EFX_MAC_RX_SYMBOL_ERRORS,
328 EFX_MAC_RX_ALIGN_ERRORS,
329 EFX_MAC_RX_INTERNAL_ERRORS,
330 EFX_MAC_RX_JABBER_PKTS,
331 EFX_MAC_RX_LANE0_CHAR_ERR,
332 EFX_MAC_RX_LANE1_CHAR_ERR,
333 EFX_MAC_RX_LANE2_CHAR_ERR,
334 EFX_MAC_RX_LANE3_CHAR_ERR,
335 EFX_MAC_RX_LANE0_DISP_ERR,
336 EFX_MAC_RX_LANE1_DISP_ERR,
337 EFX_MAC_RX_LANE2_DISP_ERR,
338 EFX_MAC_RX_LANE3_DISP_ERR,
339 EFX_MAC_RX_MATCH_FAULT,
340 EFX_MAC_RX_NODESC_DROP_CNT,
343 EFX_MAC_TX_UNICST_PKTS,
344 EFX_MAC_TX_MULTICST_PKTS,
345 EFX_MAC_TX_BRDCST_PKTS,
346 EFX_MAC_TX_PAUSE_PKTS,
347 EFX_MAC_TX_LE_64_PKTS,
348 EFX_MAC_TX_65_TO_127_PKTS,
349 EFX_MAC_TX_128_TO_255_PKTS,
350 EFX_MAC_TX_256_TO_511_PKTS,
351 EFX_MAC_TX_512_TO_1023_PKTS,
352 EFX_MAC_TX_1024_TO_15XX_PKTS,
353 EFX_MAC_TX_GE_15XX_PKTS,
355 EFX_MAC_TX_SGL_COL_PKTS,
356 EFX_MAC_TX_MULT_COL_PKTS,
357 EFX_MAC_TX_EX_COL_PKTS,
358 EFX_MAC_TX_LATE_COL_PKTS,
360 EFX_MAC_TX_EX_DEF_PKTS,
361 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
362 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
363 EFX_MAC_PM_TRUNC_VFIFO_FULL,
364 EFX_MAC_PM_DISCARD_VFIFO_FULL,
365 EFX_MAC_PM_TRUNC_QBB,
366 EFX_MAC_PM_DISCARD_QBB,
367 EFX_MAC_PM_DISCARD_MAPPING,
368 EFX_MAC_RXDP_Q_DISABLED_PKTS,
369 EFX_MAC_RXDP_DI_DROPPED_PKTS,
370 EFX_MAC_RXDP_STREAMING_PKTS,
371 EFX_MAC_RXDP_HLB_FETCH,
372 EFX_MAC_RXDP_HLB_WAIT,
373 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
374 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
375 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
376 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
377 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
378 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
379 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
380 EFX_MAC_VADAPTER_RX_BAD_BYTES,
381 EFX_MAC_VADAPTER_RX_OVERFLOW,
382 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
383 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
384 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
385 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
386 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
387 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
388 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
389 EFX_MAC_VADAPTER_TX_BAD_BYTES,
390 EFX_MAC_VADAPTER_TX_OVERFLOW,
394 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
396 #endif /* EFSYS_OPT_MAC_STATS */
398 typedef enum efx_link_mode_e {
399 EFX_LINK_UNKNOWN = 0,
412 #define EFX_MAC_ADDR_LEN 6
414 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t*)_address)[0] & 0x01)
416 #define EFX_MAC_MULTICAST_LIST_MAX 256
418 #define EFX_MAC_SDU_MAX 9202
420 #define EFX_MAC_PDU(_sdu) \
425 + /* bug16011 */ 16), \
428 #define EFX_MAC_PDU_MIN 60
429 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
431 extern __checkReturn efx_rc_t
436 extern __checkReturn efx_rc_t
441 extern __checkReturn efx_rc_t
444 __in boolean_t all_unicst,
445 __in boolean_t mulcst,
446 __in boolean_t all_mulcst,
447 __in boolean_t brdcst);
449 extern __checkReturn efx_rc_t
450 efx_mac_multicast_list_set(
452 __in_ecount(6*count) uint8_t const *addrs,
455 extern __checkReturn efx_rc_t
456 efx_mac_filter_default_rxq_set(
459 __in boolean_t using_rss);
462 efx_mac_filter_default_rxq_clear(
463 __in efx_nic_t *enp);
465 extern __checkReturn efx_rc_t
468 __in boolean_t enabled);
470 extern __checkReturn efx_rc_t
473 __out boolean_t *mac_upp);
475 #define EFX_FCNTL_RESPOND 0x00000001
476 #define EFX_FCNTL_GENERATE 0x00000002
478 extern __checkReturn efx_rc_t
481 __in unsigned int fcntl,
482 __in boolean_t autoneg);
487 __out unsigned int *fcntl_wantedp,
488 __out unsigned int *fcntl_linkp);
490 #define EFX_MAC_HASH_BITS (1 << 8)
492 extern __checkReturn efx_rc_t
494 __in efx_nic_t *enp);
498 __in efx_nic_t *enp);
500 extern __checkReturn efx_rc_t
503 __in boolean_t unicst,
504 __in boolean_t brdcst);
506 extern __checkReturn efx_rc_t
509 __in_ecount(EFX_MAC_HASH_BITS) unsigned int const *bucket);
511 #if EFSYS_OPT_MCAST_FILTER_LIST
512 extern __checkReturn efx_rc_t
513 efx_pktfilter_mcast_list_set(
515 __in uint8_t const *addrs,
517 #endif /* EFSYS_OPT_MCAST_FILTER_LIST */
519 extern __checkReturn efx_rc_t
520 efx_pktfilter_mcast_all(
521 __in efx_nic_t *enp);
523 #if EFSYS_OPT_MAC_STATS
527 extern __checkReturn const char *
530 __in unsigned int id);
532 #endif /* EFSYS_OPT_NAMES */
534 #define EFX_MAC_STATS_SIZE 0x400
537 * Upload mac statistics supported by the hardware into the given buffer.
539 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes,
542 * The hardware will only DMA statistics that it understands (of course).
543 * Drivers should not make any assumptions about which statistics are
544 * supported, especially when the statistics are generated by firmware.
546 * Thus, drivers should zero this buffer before use, so that not-understood
547 * statistics read back as zero.
549 extern __checkReturn efx_rc_t
550 efx_mac_stats_upload(
552 __in efsys_mem_t *esmp);
554 extern __checkReturn efx_rc_t
555 efx_mac_stats_periodic(
557 __in efsys_mem_t *esmp,
558 __in uint16_t period_ms,
559 __in boolean_t events);
561 extern __checkReturn efx_rc_t
562 efx_mac_stats_update(
564 __in efsys_mem_t *esmp,
565 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
566 __inout_opt uint32_t *generationp);
568 #endif /* EFSYS_OPT_MAC_STATS */
572 typedef enum efx_mon_type_e {
586 __in efx_nic_t *enp);
588 #endif /* EFSYS_OPT_NAMES */
590 extern __checkReturn efx_rc_t
592 __in efx_nic_t *enp);
594 #if EFSYS_OPT_MON_STATS
596 #define EFX_MON_STATS_PAGE_SIZE 0x100
597 #define EFX_MON_MASK_ELEMENT_SIZE 32
599 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock c79c86b62a144846 */
600 typedef enum efx_mon_stat_e {
607 EFX_MON_STAT_EXT_TEMP,
608 EFX_MON_STAT_INT_TEMP,
611 EFX_MON_STAT_INT_COOLING,
612 EFX_MON_STAT_EXT_COOLING,
620 EFX_MON_STAT_AOE_TEMP,
621 EFX_MON_STAT_PSU_AOE_TEMP,
622 EFX_MON_STAT_PSU_TEMP,
628 EFX_MON_STAT_VAOE_IN,
630 EFX_MON_STAT_IAOE_IN,
631 EFX_MON_STAT_NIC_POWER,
635 EFX_MON_STAT_0_9V_ADC,
636 EFX_MON_STAT_INT_TEMP2,
637 EFX_MON_STAT_VREG_TEMP,
638 EFX_MON_STAT_VREG_0_9V_TEMP,
639 EFX_MON_STAT_VREG_1_2V_TEMP,
640 EFX_MON_STAT_INT_VPTAT,
641 EFX_MON_STAT_INT_ADC_TEMP,
642 EFX_MON_STAT_EXT_VPTAT,
643 EFX_MON_STAT_EXT_ADC_TEMP,
644 EFX_MON_STAT_AMBIENT_TEMP,
645 EFX_MON_STAT_AIRFLOW,
646 EFX_MON_STAT_VDD08D_VSS08D_CSR,
647 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
648 EFX_MON_STAT_HOTPOINT_TEMP,
649 EFX_MON_STAT_PHY_POWER_SWITCH_PORT0,
650 EFX_MON_STAT_PHY_POWER_SWITCH_PORT1,
651 EFX_MON_STAT_MUM_VCC,
654 EFX_MON_STAT_0V9_A_TEMP,
657 EFX_MON_STAT_0V9_B_TEMP,
658 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
659 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,
660 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
661 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,
662 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
663 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
664 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,
665 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,
666 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
667 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
668 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,
669 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,
673 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
675 typedef enum efx_mon_stat_state_e {
676 EFX_MON_STAT_STATE_OK = 0,
677 EFX_MON_STAT_STATE_WARNING = 1,
678 EFX_MON_STAT_STATE_FATAL = 2,
679 EFX_MON_STAT_STATE_BROKEN = 3,
680 EFX_MON_STAT_STATE_NO_READING = 4,
681 } efx_mon_stat_state_t;
683 typedef struct efx_mon_stat_value_s {
686 } efx_mon_stat_value_t;
693 __in efx_mon_stat_t id);
695 #endif /* EFSYS_OPT_NAMES */
697 extern __checkReturn efx_rc_t
698 efx_mon_stats_update(
700 __in efsys_mem_t *esmp,
701 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
703 #endif /* EFSYS_OPT_MON_STATS */
707 __in efx_nic_t *enp);
711 #define PMA_PMD_MMD 1
716 #define CL22EXT_MMD 29
718 #define MAXMMD ((1 << 5) - 1)
720 extern __checkReturn efx_rc_t
722 __in efx_nic_t *enp);
724 #if EFSYS_OPT_PHY_LED_CONTROL
726 typedef enum efx_phy_led_mode_e {
727 EFX_PHY_LED_DEFAULT = 0,
732 } efx_phy_led_mode_t;
734 extern __checkReturn efx_rc_t
737 __in efx_phy_led_mode_t mode);
739 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
741 extern __checkReturn efx_rc_t
743 __in efx_nic_t *enp);
745 #if EFSYS_OPT_LOOPBACK
747 typedef enum efx_loopback_type_e {
748 EFX_LOOPBACK_OFF = 0,
749 EFX_LOOPBACK_DATA = 1,
750 EFX_LOOPBACK_GMAC = 2,
751 EFX_LOOPBACK_XGMII = 3,
752 EFX_LOOPBACK_XGXS = 4,
753 EFX_LOOPBACK_XAUI = 5,
754 EFX_LOOPBACK_GMII = 6,
755 EFX_LOOPBACK_SGMII = 7,
756 EFX_LOOPBACK_XGBR = 8,
757 EFX_LOOPBACK_XFI = 9,
758 EFX_LOOPBACK_XAUI_FAR = 10,
759 EFX_LOOPBACK_GMII_FAR = 11,
760 EFX_LOOPBACK_SGMII_FAR = 12,
761 EFX_LOOPBACK_XFI_FAR = 13,
762 EFX_LOOPBACK_GPHY = 14,
763 EFX_LOOPBACK_PHY_XS = 15,
764 EFX_LOOPBACK_PCS = 16,
765 EFX_LOOPBACK_PMA_PMD = 17,
766 EFX_LOOPBACK_XPORT = 18,
767 EFX_LOOPBACK_XGMII_WS = 19,
768 EFX_LOOPBACK_XAUI_WS = 20,
769 EFX_LOOPBACK_XAUI_WS_FAR = 21,
770 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
771 EFX_LOOPBACK_GMII_WS = 23,
772 EFX_LOOPBACK_XFI_WS = 24,
773 EFX_LOOPBACK_XFI_WS_FAR = 25,
774 EFX_LOOPBACK_PHYXS_WS = 26,
775 EFX_LOOPBACK_PMA_INT = 27,
776 EFX_LOOPBACK_SD_NEAR = 28,
777 EFX_LOOPBACK_SD_FAR = 29,
778 EFX_LOOPBACK_PMA_INT_WS = 30,
779 EFX_LOOPBACK_SD_FEP2_WS = 31,
780 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
781 EFX_LOOPBACK_SD_FEP_WS = 33,
782 EFX_LOOPBACK_SD_FES_WS = 34,
784 } efx_loopback_type_t;
786 typedef enum efx_loopback_kind_e {
787 EFX_LOOPBACK_KIND_OFF = 0,
788 EFX_LOOPBACK_KIND_ALL,
789 EFX_LOOPBACK_KIND_MAC,
790 EFX_LOOPBACK_KIND_PHY,
792 } efx_loopback_kind_t;
796 __in efx_loopback_kind_t loopback_kind,
797 __out efx_qword_t *maskp);
799 extern __checkReturn efx_rc_t
800 efx_port_loopback_set(
802 __in efx_link_mode_t link_mode,
803 __in efx_loopback_type_t type);
807 extern __checkReturn const char *
808 efx_loopback_type_name(
810 __in efx_loopback_type_t type);
812 #endif /* EFSYS_OPT_NAMES */
814 #endif /* EFSYS_OPT_LOOPBACK */
816 extern __checkReturn efx_rc_t
819 __out_opt efx_link_mode_t *link_modep);
823 __in efx_nic_t *enp);
825 typedef enum efx_phy_cap_type_e {
826 EFX_PHY_CAP_INVALID = 0,
833 EFX_PHY_CAP_10000FDX,
837 EFX_PHY_CAP_40000FDX,
839 } efx_phy_cap_type_t;
842 #define EFX_PHY_CAP_CURRENT 0x00000000
843 #define EFX_PHY_CAP_DEFAULT 0x00000001
844 #define EFX_PHY_CAP_PERM 0x00000002
850 __out uint32_t *maskp);
852 extern __checkReturn efx_rc_t
860 __out uint32_t *maskp);
862 extern __checkReturn efx_rc_t
865 __out uint32_t *ouip);
867 typedef enum efx_phy_media_type_e {
868 EFX_PHY_MEDIA_INVALID = 0,
873 EFX_PHY_MEDIA_SFP_PLUS,
874 EFX_PHY_MEDIA_BASE_T,
875 EFX_PHY_MEDIA_QSFP_PLUS,
877 } efx_phy_media_type_t;
879 /* Get the type of medium currently used. If the board has ports for
880 * modules, a module is present, and we recognise the media type of
881 * the module, then this will be the media type of the module.
882 * Otherwise it will be the media type of the port.
885 efx_phy_media_type_get(
887 __out efx_phy_media_type_t *typep);
889 #if EFSYS_OPT_PHY_STATS
891 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
892 typedef enum efx_phy_stat_e {
894 EFX_PHY_STAT_PMA_PMD_LINK_UP,
895 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
896 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
897 EFX_PHY_STAT_PMA_PMD_REV_A,
898 EFX_PHY_STAT_PMA_PMD_REV_B,
899 EFX_PHY_STAT_PMA_PMD_REV_C,
900 EFX_PHY_STAT_PMA_PMD_REV_D,
901 EFX_PHY_STAT_PCS_LINK_UP,
902 EFX_PHY_STAT_PCS_RX_FAULT,
903 EFX_PHY_STAT_PCS_TX_FAULT,
904 EFX_PHY_STAT_PCS_BER,
905 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
906 EFX_PHY_STAT_PHY_XS_LINK_UP,
907 EFX_PHY_STAT_PHY_XS_RX_FAULT,
908 EFX_PHY_STAT_PHY_XS_TX_FAULT,
909 EFX_PHY_STAT_PHY_XS_ALIGN,
910 EFX_PHY_STAT_PHY_XS_SYNC_A,
911 EFX_PHY_STAT_PHY_XS_SYNC_B,
912 EFX_PHY_STAT_PHY_XS_SYNC_C,
913 EFX_PHY_STAT_PHY_XS_SYNC_D,
914 EFX_PHY_STAT_AN_LINK_UP,
915 EFX_PHY_STAT_AN_MASTER,
916 EFX_PHY_STAT_AN_LOCAL_RX_OK,
917 EFX_PHY_STAT_AN_REMOTE_RX_OK,
918 EFX_PHY_STAT_CL22EXT_LINK_UP,
923 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
924 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
925 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
926 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
927 EFX_PHY_STAT_AN_COMPLETE,
928 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
929 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
930 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
931 EFX_PHY_STAT_PCS_FW_VERSION_0,
932 EFX_PHY_STAT_PCS_FW_VERSION_1,
933 EFX_PHY_STAT_PCS_FW_VERSION_2,
934 EFX_PHY_STAT_PCS_FW_VERSION_3,
935 EFX_PHY_STAT_PCS_FW_BUILD_YY,
936 EFX_PHY_STAT_PCS_FW_BUILD_MM,
937 EFX_PHY_STAT_PCS_FW_BUILD_DD,
938 EFX_PHY_STAT_PCS_OP_MODE,
942 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
949 __in efx_phy_stat_t stat);
951 #endif /* EFSYS_OPT_NAMES */
953 #define EFX_PHY_STATS_SIZE 0x100
955 extern __checkReturn efx_rc_t
956 efx_phy_stats_update(
958 __in efsys_mem_t *esmp,
959 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
961 #endif /* EFSYS_OPT_PHY_STATS */
963 #if EFSYS_OPT_PHY_PROPS
970 __in unsigned int id);
972 #endif /* EFSYS_OPT_NAMES */
974 #define EFX_PHY_PROP_DEFAULT 0x00000001
976 extern __checkReturn efx_rc_t
979 __in unsigned int id,
981 __out uint32_t *valp);
983 extern __checkReturn efx_rc_t
986 __in unsigned int id,
989 #endif /* EFSYS_OPT_PHY_PROPS */
993 typedef enum efx_bist_type_e {
994 EFX_BIST_TYPE_UNKNOWN,
995 EFX_BIST_TYPE_PHY_NORMAL,
996 EFX_BIST_TYPE_PHY_CABLE_SHORT,
997 EFX_BIST_TYPE_PHY_CABLE_LONG,
998 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
999 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus*/
1000 EFX_BIST_TYPE_REG, /* Test the register memories */
1001 EFX_BIST_TYPE_NTYPES,
1004 typedef enum efx_bist_result_e {
1005 EFX_BIST_RESULT_UNKNOWN,
1006 EFX_BIST_RESULT_RUNNING,
1007 EFX_BIST_RESULT_PASSED,
1008 EFX_BIST_RESULT_FAILED,
1009 } efx_bist_result_t;
1011 typedef enum efx_phy_cable_status_e {
1012 EFX_PHY_CABLE_STATUS_OK,
1013 EFX_PHY_CABLE_STATUS_INVALID,
1014 EFX_PHY_CABLE_STATUS_OPEN,
1015 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1016 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1017 EFX_PHY_CABLE_STATUS_BUSY,
1018 } efx_phy_cable_status_t;
1020 typedef enum efx_bist_value_e {
1021 EFX_BIST_PHY_CABLE_LENGTH_A,
1022 EFX_BIST_PHY_CABLE_LENGTH_B,
1023 EFX_BIST_PHY_CABLE_LENGTH_C,
1024 EFX_BIST_PHY_CABLE_LENGTH_D,
1025 EFX_BIST_PHY_CABLE_STATUS_A,
1026 EFX_BIST_PHY_CABLE_STATUS_B,
1027 EFX_BIST_PHY_CABLE_STATUS_C,
1028 EFX_BIST_PHY_CABLE_STATUS_D,
1029 EFX_BIST_FAULT_CODE,
1030 /* Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1035 EFX_BIST_MEM_EXPECT,
1036 EFX_BIST_MEM_ACTUAL,
1038 EFX_BIST_MEM_ECC_PARITY,
1039 EFX_BIST_MEM_ECC_FATAL,
1043 extern __checkReturn efx_rc_t
1044 efx_bist_enable_offline(
1045 __in efx_nic_t *enp);
1047 extern __checkReturn efx_rc_t
1049 __in efx_nic_t *enp,
1050 __in efx_bist_type_t type);
1052 extern __checkReturn efx_rc_t
1054 __in efx_nic_t *enp,
1055 __in efx_bist_type_t type,
1056 __out efx_bist_result_t *resultp,
1057 __out_opt uint32_t *value_maskp,
1058 __out_ecount_opt(count) unsigned long *valuesp,
1063 __in efx_nic_t *enp,
1064 __in efx_bist_type_t type);
1066 #endif /* EFSYS_OPT_BIST */
1068 #define EFX_FEATURE_IPV6 0x00000001
1069 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1070 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1071 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1072 #define EFX_FEATURE_WOL 0x00000010
1073 #define EFX_FEATURE_MCDI 0x00000020
1074 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1075 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1076 #define EFX_FEATURE_TURBO 0x00000100
1077 #define EFX_FEATURE_MCDI_DMA 0x00000200
1078 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1079 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1080 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1082 typedef struct efx_nic_cfg_s {
1083 uint32_t enc_board_type;
1084 uint32_t enc_phy_type;
1086 char enc_phy_name[21];
1088 char enc_phy_revision[21];
1089 efx_mon_type_t enc_mon_type;
1090 #if EFSYS_OPT_MON_STATS
1091 uint32_t enc_mon_stat_dma_buf_size;
1092 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1094 unsigned int enc_features;
1095 uint8_t enc_mac_addr[6];
1096 uint8_t enc_port; /* PHY port number */
1097 uint32_t enc_func_flags;
1098 uint32_t enc_intr_vec_base;
1099 uint32_t enc_intr_limit;
1100 uint32_t enc_evq_limit;
1101 uint32_t enc_txq_limit;
1102 uint32_t enc_rxq_limit;
1103 uint32_t enc_buftbl_limit;
1104 uint32_t enc_piobuf_limit;
1105 uint32_t enc_piobuf_size;
1106 uint32_t enc_evq_timer_quantum_ns;
1107 uint32_t enc_evq_timer_max_us;
1108 uint32_t enc_clk_mult;
1109 uint32_t enc_rx_prefix_size;
1110 uint32_t enc_rx_buf_align_start;
1111 uint32_t enc_rx_buf_align_end;
1112 #if EFSYS_OPT_LOOPBACK
1113 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1114 #endif /* EFSYS_OPT_LOOPBACK */
1115 #if EFSYS_OPT_PHY_FLAGS
1116 uint32_t enc_phy_flags_mask;
1117 #endif /* EFSYS_OPT_PHY_FLAGS */
1118 #if EFSYS_OPT_PHY_LED_CONTROL
1119 uint32_t enc_led_mask;
1120 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1121 #if EFSYS_OPT_PHY_STATS
1122 uint64_t enc_phy_stat_mask;
1123 #endif /* EFSYS_OPT_PHY_STATS */
1124 #if EFSYS_OPT_PHY_PROPS
1125 unsigned int enc_phy_nprops;
1126 #endif /* EFSYS_OPT_PHY_PROPS */
1128 uint8_t enc_mcdi_mdio_channel;
1129 #if EFSYS_OPT_PHY_STATS
1130 uint32_t enc_mcdi_phy_stat_mask;
1131 #endif /* EFSYS_OPT_PHY_STATS */
1132 #endif /* EFSYS_OPT_SIENA */
1133 #if (EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON)
1134 #if EFSYS_OPT_MON_STATS
1135 uint32_t *enc_mcdi_sensor_maskp;
1136 uint32_t enc_mcdi_sensor_mask_size;
1137 #endif /* EFSYS_OPT_MON_STATS */
1138 #endif /* (EFSYS_OPT_SIENA | EFSYS_OPT_HUNTINGTON) */
1140 uint32_t enc_bist_mask;
1141 #endif /* EFSYS_OPT_BIST */
1142 #if EFSYS_OPT_HUNTINGTON
1145 uint32_t enc_privilege_mask;
1146 #endif /* EFSYS_OPT_HUNTINGTON */
1147 boolean_t enc_bug26807_workaround;
1148 boolean_t enc_bug35388_workaround;
1149 boolean_t enc_bug41750_workaround;
1150 boolean_t enc_rx_batching_enabled;
1151 /* Maximum number of descriptors completed in an rx event. */
1152 uint32_t enc_rx_batch_max;
1153 /* Number of rx descriptors the hardware requires for a push. */
1154 uint32_t enc_rx_push_align;
1156 * Maximum number of bytes into the packet the TCP header can start for
1157 * the hardware to apply TSO packet edits.
1159 uint32_t enc_tx_tso_tcp_header_offset_limit;
1160 boolean_t enc_fw_assisted_tso_enabled;
1161 boolean_t enc_hw_tx_insert_vlan_enabled;
1162 /* Datapath firmware vadapter/vport/vswitch support */
1163 boolean_t enc_datapath_cap_evb;
1164 /* External port identifier */
1165 uint8_t enc_external_port;
1168 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1169 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1171 #define EFX_PCI_FUNCTION(_encp) \
1172 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1174 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1176 extern const efx_nic_cfg_t *
1178 __in efx_nic_t *enp);
1180 /* Driver resource limits (minimum required/maximum usable). */
1181 typedef struct efx_drv_limits_s
1183 uint32_t edl_min_evq_count;
1184 uint32_t edl_max_evq_count;
1186 uint32_t edl_min_rxq_count;
1187 uint32_t edl_max_rxq_count;
1189 uint32_t edl_min_txq_count;
1190 uint32_t edl_max_txq_count;
1192 /* PIO blocks (sub-allocated from piobuf) */
1193 uint32_t edl_min_pio_alloc_size;
1194 uint32_t edl_max_pio_alloc_count;
1197 extern __checkReturn efx_rc_t
1198 efx_nic_set_drv_limits(
1199 __inout efx_nic_t *enp,
1200 __in efx_drv_limits_t *edlp);
1202 typedef enum efx_nic_region_e {
1203 EFX_REGION_VI, /* Memory BAR UC mapping */
1204 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1207 extern __checkReturn efx_rc_t
1208 efx_nic_get_bar_region(
1209 __in efx_nic_t *enp,
1210 __in efx_nic_region_t region,
1211 __out uint32_t *offsetp,
1212 __out size_t *sizep);
1214 extern __checkReturn efx_rc_t
1215 efx_nic_get_vi_pool(
1216 __in efx_nic_t *enp,
1217 __out uint32_t *evq_countp,
1218 __out uint32_t *rxq_countp,
1219 __out uint32_t *txq_countp);
1224 typedef enum efx_vpd_tag_e {
1231 typedef uint16_t efx_vpd_keyword_t;
1233 typedef struct efx_vpd_value_s {
1234 efx_vpd_tag_t evv_tag;
1235 efx_vpd_keyword_t evv_keyword;
1237 uint8_t evv_value[0x100];
1241 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1243 extern __checkReturn efx_rc_t
1245 __in efx_nic_t *enp);
1247 extern __checkReturn efx_rc_t
1249 __in efx_nic_t *enp,
1250 __out size_t *sizep);
1252 extern __checkReturn efx_rc_t
1254 __in efx_nic_t *enp,
1255 __out_bcount(size) caddr_t data,
1258 extern __checkReturn efx_rc_t
1260 __in efx_nic_t *enp,
1261 __in_bcount(size) caddr_t data,
1264 extern __checkReturn efx_rc_t
1266 __in efx_nic_t *enp,
1267 __in_bcount(size) caddr_t data,
1270 extern __checkReturn efx_rc_t
1272 __in efx_nic_t *enp,
1273 __in_bcount(size) caddr_t data,
1275 __inout efx_vpd_value_t *evvp);
1277 extern __checkReturn efx_rc_t
1279 __in efx_nic_t *enp,
1280 __inout_bcount(size) caddr_t data,
1282 __in efx_vpd_value_t *evvp);
1284 extern __checkReturn efx_rc_t
1286 __in efx_nic_t *enp,
1287 __inout_bcount(size) caddr_t data,
1289 __out efx_vpd_value_t *evvp,
1290 __inout unsigned int *contp);
1292 extern __checkReturn efx_rc_t
1294 __in efx_nic_t *enp,
1295 __in_bcount(size) caddr_t data,
1300 __in efx_nic_t *enp);
1302 #endif /* EFSYS_OPT_VPD */
1308 typedef enum efx_nvram_type_e {
1309 EFX_NVRAM_INVALID = 0,
1311 EFX_NVRAM_BOOTROM_CFG,
1312 EFX_NVRAM_MC_FIRMWARE,
1313 EFX_NVRAM_MC_GOLDEN,
1319 EFX_NVRAM_FPGA_BACKUP,
1320 EFX_NVRAM_DYNAMIC_CFG,
1324 extern __checkReturn efx_rc_t
1326 __in efx_nic_t *enp);
1330 extern __checkReturn efx_rc_t
1332 __in efx_nic_t *enp);
1334 #endif /* EFSYS_OPT_DIAG */
1336 extern __checkReturn efx_rc_t
1338 __in efx_nic_t *enp,
1339 __in efx_nvram_type_t type,
1340 __out size_t *sizep);
1342 extern __checkReturn efx_rc_t
1344 __in efx_nic_t *enp,
1345 __in efx_nvram_type_t type,
1346 __out_opt size_t *pref_chunkp);
1349 efx_nvram_rw_finish(
1350 __in efx_nic_t *enp,
1351 __in efx_nvram_type_t type);
1353 extern __checkReturn efx_rc_t
1354 efx_nvram_get_version(
1355 __in efx_nic_t *enp,
1356 __in efx_nvram_type_t type,
1357 __out uint32_t *subtypep,
1358 __out_ecount(4) uint16_t version[4]);
1360 extern __checkReturn efx_rc_t
1361 efx_nvram_read_chunk(
1362 __in efx_nic_t *enp,
1363 __in efx_nvram_type_t type,
1364 __in unsigned int offset,
1365 __out_bcount(size) caddr_t data,
1368 extern __checkReturn efx_rc_t
1369 efx_nvram_set_version(
1370 __in efx_nic_t *enp,
1371 __in efx_nvram_type_t type,
1372 __in_ecount(4) uint16_t version[4]);
1374 /* Validate contents of TLV formatted partition */
1375 extern __checkReturn efx_rc_t
1376 efx_nvram_tlv_validate(
1377 __in efx_nic_t *enp,
1378 __in uint32_t partn,
1379 __in_bcount(partn_size) caddr_t partn_data,
1380 __in size_t partn_size);
1382 extern __checkReturn efx_rc_t
1384 __in efx_nic_t *enp,
1385 __in efx_nvram_type_t type);
1387 extern __checkReturn efx_rc_t
1388 efx_nvram_write_chunk(
1389 __in efx_nic_t *enp,
1390 __in efx_nvram_type_t type,
1391 __in unsigned int offset,
1392 __in_bcount(size) caddr_t data,
1397 __in efx_nic_t *enp);
1399 #endif /* EFSYS_OPT_NVRAM */
1401 #if EFSYS_OPT_BOOTCFG
1405 __in efx_nic_t *enp,
1406 __out_bcount(size) caddr_t data,
1411 __in efx_nic_t *enp,
1412 __in_bcount(size) caddr_t data,
1415 #endif /* EFSYS_OPT_BOOTCFG */
1419 typedef enum efx_wol_type_e {
1420 EFX_WOL_TYPE_INVALID,
1422 EFX_WOL_TYPE_BITMAP,
1427 typedef enum efx_lightsout_offload_type_e {
1428 EFX_LIGHTSOUT_OFFLOAD_TYPE_INVALID,
1429 EFX_LIGHTSOUT_OFFLOAD_TYPE_ARP,
1430 EFX_LIGHTSOUT_OFFLOAD_TYPE_NS,
1431 } efx_lightsout_offload_type_t;
1433 #define EFX_WOL_BITMAP_MASK_SIZE (48)
1434 #define EFX_WOL_BITMAP_VALUE_SIZE (128)
1436 typedef union efx_wol_param_u {
1438 uint8_t mac_addr[6];
1441 uint8_t mask[EFX_WOL_BITMAP_MASK_SIZE]; /* 1 bit per byte */
1442 uint8_t value[EFX_WOL_BITMAP_VALUE_SIZE]; /* value to match */
1447 typedef union efx_lightsout_offload_param_u {
1449 uint8_t mac_addr[6];
1453 uint8_t mac_addr[6];
1454 uint32_t solicited_node[4];
1457 } efx_lightsout_offload_param_t;
1459 extern __checkReturn efx_rc_t
1461 __in efx_nic_t *enp);
1463 extern __checkReturn efx_rc_t
1464 efx_wol_filter_clear(
1465 __in efx_nic_t *enp);
1467 extern __checkReturn efx_rc_t
1469 __in efx_nic_t *enp,
1470 __in efx_wol_type_t type,
1471 __in efx_wol_param_t *paramp,
1472 __out uint32_t *filter_idp);
1474 extern __checkReturn efx_rc_t
1475 efx_wol_filter_remove(
1476 __in efx_nic_t *enp,
1477 __in uint32_t filter_id);
1479 extern __checkReturn efx_rc_t
1480 efx_lightsout_offload_add(
1481 __in efx_nic_t *enp,
1482 __in efx_lightsout_offload_type_t type,
1483 __in efx_lightsout_offload_param_t *paramp,
1484 __out uint32_t *filter_idp);
1486 extern __checkReturn efx_rc_t
1487 efx_lightsout_offload_remove(
1488 __in efx_nic_t *enp,
1489 __in efx_lightsout_offload_type_t type,
1490 __in uint32_t filter_id);
1494 __in efx_nic_t *enp);
1496 #endif /* EFSYS_OPT_WOL */
1500 typedef enum efx_pattern_type_t {
1501 EFX_PATTERN_BYTE_INCREMENT = 0,
1502 EFX_PATTERN_ALL_THE_SAME,
1503 EFX_PATTERN_BIT_ALTERNATE,
1504 EFX_PATTERN_BYTE_ALTERNATE,
1505 EFX_PATTERN_BYTE_CHANGING,
1506 EFX_PATTERN_BIT_SWEEP,
1508 } efx_pattern_type_t;
1511 (*efx_sram_pattern_fn_t)(
1513 __in boolean_t negate,
1514 __out efx_qword_t *eqp);
1516 extern __checkReturn efx_rc_t
1518 __in efx_nic_t *enp,
1519 __in efx_pattern_type_t type);
1521 #endif /* EFSYS_OPT_DIAG */
1523 extern __checkReturn efx_rc_t
1524 efx_sram_buf_tbl_set(
1525 __in efx_nic_t *enp,
1527 __in efsys_mem_t *esmp,
1531 efx_sram_buf_tbl_clear(
1532 __in efx_nic_t *enp,
1536 #define EFX_BUF_TBL_SIZE 0x20000
1538 #define EFX_BUF_SIZE 4096
1542 typedef struct efx_evq_s efx_evq_t;
1544 #if EFSYS_OPT_QSTATS
1546 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1547 typedef enum efx_ev_qstat_e {
1553 EV_RX_PAUSE_FRM_ERR,
1554 EV_RX_BUF_OWNER_ID_ERR,
1555 EV_RX_IPV4_HDR_CHKSUM_ERR,
1556 EV_RX_TCP_UDP_CHKSUM_ERR,
1560 EV_RX_MCAST_HASH_MATCH,
1577 EV_DRIVER_SRM_UPD_DONE,
1578 EV_DRIVER_TX_DESCQ_FLS_DONE,
1579 EV_DRIVER_RX_DESCQ_FLS_DONE,
1580 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1581 EV_DRIVER_RX_DSC_ERROR,
1582 EV_DRIVER_TX_DSC_ERROR,
1588 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1590 #endif /* EFSYS_OPT_QSTATS */
1592 extern __checkReturn efx_rc_t
1594 __in efx_nic_t *enp);
1598 __in efx_nic_t *enp);
1600 #define EFX_EVQ_MAXNEVS 32768
1601 #define EFX_EVQ_MINNEVS 512
1603 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
1604 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1606 extern __checkReturn efx_rc_t
1608 __in efx_nic_t *enp,
1609 __in unsigned int index,
1610 __in efsys_mem_t *esmp,
1613 __deref_out efx_evq_t **eepp);
1617 __in efx_evq_t *eep,
1618 __in uint16_t data);
1620 typedef __checkReturn boolean_t
1621 (*efx_initialized_ev_t)(
1622 __in_opt void *arg);
1624 #define EFX_PKT_UNICAST 0x0004
1625 #define EFX_PKT_START 0x0008
1627 #define EFX_PKT_VLAN_TAGGED 0x0010
1628 #define EFX_CKSUM_TCPUDP 0x0020
1629 #define EFX_CKSUM_IPV4 0x0040
1630 #define EFX_PKT_CONT 0x0080
1632 #define EFX_CHECK_VLAN 0x0100
1633 #define EFX_PKT_TCP 0x0200
1634 #define EFX_PKT_UDP 0x0400
1635 #define EFX_PKT_IPV4 0x0800
1637 #define EFX_PKT_IPV6 0x1000
1638 #define EFX_PKT_PREFIX_LEN 0x2000
1639 #define EFX_ADDR_MISMATCH 0x4000
1640 #define EFX_DISCARD 0x8000
1642 #define EFX_EV_RX_NLABELS 32
1643 #define EFX_EV_TX_NLABELS 32
1645 typedef __checkReturn boolean_t
1648 __in uint32_t label,
1651 __in uint16_t flags);
1653 typedef __checkReturn boolean_t
1656 __in uint32_t label,
1659 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
1660 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
1661 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
1662 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
1663 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
1664 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
1665 #define EFX_EXCEPTION_RX_ERROR 0x00000007
1666 #define EFX_EXCEPTION_TX_ERROR 0x00000008
1667 #define EFX_EXCEPTION_EV_ERROR 0x00000009
1669 typedef __checkReturn boolean_t
1670 (*efx_exception_ev_t)(
1672 __in uint32_t label,
1673 __in uint32_t data);
1675 typedef __checkReturn boolean_t
1676 (*efx_rxq_flush_done_ev_t)(
1678 __in uint32_t rxq_index);
1680 typedef __checkReturn boolean_t
1681 (*efx_rxq_flush_failed_ev_t)(
1683 __in uint32_t rxq_index);
1685 typedef __checkReturn boolean_t
1686 (*efx_txq_flush_done_ev_t)(
1688 __in uint32_t txq_index);
1690 typedef __checkReturn boolean_t
1691 (*efx_software_ev_t)(
1693 __in uint16_t magic);
1695 typedef __checkReturn boolean_t
1698 __in uint32_t code);
1700 #define EFX_SRAM_CLEAR 0
1701 #define EFX_SRAM_UPDATE 1
1702 #define EFX_SRAM_ILLEGAL_CLEAR 2
1704 typedef __checkReturn boolean_t
1705 (*efx_wake_up_ev_t)(
1707 __in uint32_t label);
1709 typedef __checkReturn boolean_t
1712 __in uint32_t label);
1714 typedef __checkReturn boolean_t
1715 (*efx_link_change_ev_t)(
1717 __in efx_link_mode_t link_mode);
1719 #if EFSYS_OPT_MON_STATS
1721 typedef __checkReturn boolean_t
1722 (*efx_monitor_ev_t)(
1724 __in efx_mon_stat_t id,
1725 __in efx_mon_stat_value_t value);
1727 #endif /* EFSYS_OPT_MON_STATS */
1729 #if EFSYS_OPT_MAC_STATS
1731 typedef __checkReturn boolean_t
1732 (*efx_mac_stats_ev_t)(
1734 __in uint32_t generation
1737 #endif /* EFSYS_OPT_MAC_STATS */
1739 typedef struct efx_ev_callbacks_s {
1740 efx_initialized_ev_t eec_initialized;
1743 efx_exception_ev_t eec_exception;
1744 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
1745 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
1746 efx_txq_flush_done_ev_t eec_txq_flush_done;
1747 efx_software_ev_t eec_software;
1748 efx_sram_ev_t eec_sram;
1749 efx_wake_up_ev_t eec_wake_up;
1750 efx_timer_ev_t eec_timer;
1751 efx_link_change_ev_t eec_link_change;
1752 #if EFSYS_OPT_MON_STATS
1753 efx_monitor_ev_t eec_monitor;
1754 #endif /* EFSYS_OPT_MON_STATS */
1755 #if EFSYS_OPT_MAC_STATS
1756 efx_mac_stats_ev_t eec_mac_stats;
1757 #endif /* EFSYS_OPT_MAC_STATS */
1758 } efx_ev_callbacks_t;
1760 extern __checkReturn boolean_t
1762 __in efx_evq_t *eep,
1763 __in unsigned int count);
1765 #if EFSYS_OPT_EV_PREFETCH
1769 __in efx_evq_t *eep,
1770 __in unsigned int count);
1772 #endif /* EFSYS_OPT_EV_PREFETCH */
1776 __in efx_evq_t *eep,
1777 __inout unsigned int *countp,
1778 __in const efx_ev_callbacks_t *eecp,
1779 __in_opt void *arg);
1781 extern __checkReturn efx_rc_t
1783 __in efx_evq_t *eep,
1784 __in unsigned int us);
1786 extern __checkReturn efx_rc_t
1788 __in efx_evq_t *eep,
1789 __in unsigned int count);
1791 #if EFSYS_OPT_QSTATS
1797 __in efx_nic_t *enp,
1798 __in unsigned int id);
1800 #endif /* EFSYS_OPT_NAMES */
1803 efx_ev_qstats_update(
1804 __in efx_evq_t *eep,
1805 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
1807 #endif /* EFSYS_OPT_QSTATS */
1811 __in efx_evq_t *eep);
1815 extern __checkReturn efx_rc_t
1817 __inout efx_nic_t *enp);
1821 __in efx_nic_t *enp);
1823 #if EFSYS_OPT_RX_HDR_SPLIT
1824 __checkReturn efx_rc_t
1825 efx_rx_hdr_split_enable(
1826 __in efx_nic_t *enp,
1827 __in unsigned int hdr_buf_size,
1828 __in unsigned int pld_buf_size);
1830 #endif /* EFSYS_OPT_RX_HDR_SPLIT */
1832 #if EFSYS_OPT_RX_SCATTER
1833 __checkReturn efx_rc_t
1834 efx_rx_scatter_enable(
1835 __in efx_nic_t *enp,
1836 __in unsigned int buf_size);
1837 #endif /* EFSYS_OPT_RX_SCATTER */
1839 #if EFSYS_OPT_RX_SCALE
1841 typedef enum efx_rx_hash_alg_e {
1842 EFX_RX_HASHALG_LFSR = 0,
1843 EFX_RX_HASHALG_TOEPLITZ
1844 } efx_rx_hash_alg_t;
1846 typedef enum efx_rx_hash_type_e {
1847 EFX_RX_HASH_IPV4 = 0,
1848 EFX_RX_HASH_TCPIPV4,
1850 EFX_RX_HASH_TCPIPV6,
1851 } efx_rx_hash_type_t;
1853 typedef enum efx_rx_hash_support_e {
1854 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
1855 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
1856 } efx_rx_hash_support_t;
1858 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
1859 #define EFX_MAXRSS 64 /* RX indirection entry range */
1860 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
1862 typedef enum efx_rx_scale_support_e {
1863 EFX_RX_SCALE_UNAVAILABLE = 0, /* Not supported */
1864 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
1865 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
1866 } efx_rx_scale_support_t;
1868 extern __checkReturn efx_rc_t
1869 efx_rx_hash_support_get(
1870 __in efx_nic_t *enp,
1871 __out efx_rx_hash_support_t *supportp);
1874 extern __checkReturn efx_rc_t
1875 efx_rx_scale_support_get(
1876 __in efx_nic_t *enp,
1877 __out efx_rx_scale_support_t *supportp);
1879 extern __checkReturn efx_rc_t
1880 efx_rx_scale_mode_set(
1881 __in efx_nic_t *enp,
1882 __in efx_rx_hash_alg_t alg,
1883 __in efx_rx_hash_type_t type,
1884 __in boolean_t insert);
1886 extern __checkReturn efx_rc_t
1887 efx_rx_scale_tbl_set(
1888 __in efx_nic_t *enp,
1889 __in_ecount(n) unsigned int *table,
1892 extern __checkReturn efx_rc_t
1893 efx_rx_scale_key_set(
1894 __in efx_nic_t *enp,
1895 __in_ecount(n) uint8_t *key,
1899 efx_psuedo_hdr_hash_get(
1900 __in efx_nic_t *enp,
1901 __in efx_rx_hash_alg_t func,
1902 __in uint8_t *buffer);
1904 #endif /* EFSYS_OPT_RX_SCALE */
1906 extern __checkReturn efx_rc_t
1907 efx_psuedo_hdr_pkt_length_get(
1908 __in efx_nic_t *enp,
1909 __in uint8_t *buffer,
1910 __out uint16_t *pkt_lengthp);
1912 #define EFX_RXQ_MAXNDESCS 4096
1913 #define EFX_RXQ_MINNDESCS 512
1915 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
1916 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1917 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
1918 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
1920 typedef enum efx_rxq_type_e {
1921 EFX_RXQ_TYPE_DEFAULT,
1922 EFX_RXQ_TYPE_SPLIT_HEADER,
1923 EFX_RXQ_TYPE_SPLIT_PAYLOAD,
1924 EFX_RXQ_TYPE_SCATTER,
1928 extern __checkReturn efx_rc_t
1930 __in efx_nic_t *enp,
1931 __in unsigned int index,
1932 __in unsigned int label,
1933 __in efx_rxq_type_t type,
1934 __in efsys_mem_t *esmp,
1937 __in efx_evq_t *eep,
1938 __deref_out efx_rxq_t **erpp);
1940 typedef struct efx_buffer_s {
1941 efsys_dma_addr_t eb_addr;
1946 typedef struct efx_desc_s {
1952 __in efx_rxq_t *erp,
1953 __in_ecount(n) efsys_dma_addr_t *addrp,
1955 __in unsigned int n,
1956 __in unsigned int completed,
1957 __in unsigned int added);
1961 __in efx_rxq_t *erp,
1962 __in unsigned int added,
1963 __inout unsigned int *pushedp);
1965 extern __checkReturn efx_rc_t
1967 __in efx_rxq_t *erp);
1971 __in efx_rxq_t *erp);
1975 __in efx_rxq_t *erp);
1979 typedef struct efx_txq_s efx_txq_t;
1981 #if EFSYS_OPT_QSTATS
1983 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
1984 typedef enum efx_tx_qstat_e {
1990 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
1992 #endif /* EFSYS_OPT_QSTATS */
1994 extern __checkReturn efx_rc_t
1996 __in efx_nic_t *enp);
2000 __in efx_nic_t *enp);
2002 #define EFX_BUG35388_WORKAROUND(_encp) \
2003 (((_encp) == NULL) ? 1 : ((_encp)->enc_bug35388_workaround != 0))
2005 #define EFX_TXQ_MAXNDESCS(_encp) \
2006 ((EFX_BUG35388_WORKAROUND(_encp)) ? 2048 : 4096)
2008 #define EFX_TXQ_MINNDESCS 512
2010 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2011 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2012 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2013 #define EFX_TXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
2015 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2017 extern __checkReturn efx_rc_t
2019 __in efx_nic_t *enp,
2020 __in unsigned int index,
2021 __in unsigned int label,
2022 __in efsys_mem_t *esmp,
2025 __in uint16_t flags,
2026 __in efx_evq_t *eep,
2027 __deref_out efx_txq_t **etpp,
2028 __out unsigned int *addedp);
2030 extern __checkReturn efx_rc_t
2032 __in efx_txq_t *etp,
2033 __in_ecount(n) efx_buffer_t *eb,
2034 __in unsigned int n,
2035 __in unsigned int completed,
2036 __inout unsigned int *addedp);
2038 extern __checkReturn efx_rc_t
2040 __in efx_txq_t *etp,
2041 __in unsigned int ns);
2045 __in efx_txq_t *etp,
2046 __in unsigned int added,
2047 __in unsigned int pushed);
2049 extern __checkReturn efx_rc_t
2051 __in efx_txq_t *etp);
2055 __in efx_txq_t *etp);
2057 extern __checkReturn efx_rc_t
2059 __in efx_txq_t *etp);
2062 efx_tx_qpio_disable(
2063 __in efx_txq_t *etp);
2065 extern __checkReturn efx_rc_t
2067 __in efx_txq_t *etp,
2068 __in_ecount(buf_length) uint8_t *buffer,
2069 __in size_t buf_length,
2070 __in size_t pio_buf_offset);
2072 extern __checkReturn efx_rc_t
2074 __in efx_txq_t *etp,
2075 __in size_t pkt_length,
2076 __in unsigned int completed,
2077 __inout unsigned int *addedp);
2079 extern __checkReturn efx_rc_t
2081 __in efx_txq_t *etp,
2082 __in_ecount(n) efx_desc_t *ed,
2083 __in unsigned int n,
2084 __in unsigned int completed,
2085 __inout unsigned int *addedp);
2088 efx_tx_qdesc_dma_create(
2089 __in efx_txq_t *etp,
2090 __in efsys_dma_addr_t addr,
2093 __out efx_desc_t *edp);
2096 efx_tx_qdesc_tso_create(
2097 __in efx_txq_t *etp,
2098 __in uint16_t ipv4_id,
2099 __in uint32_t tcp_seq,
2100 __in uint8_t tcp_flags,
2101 __out efx_desc_t *edp);
2104 efx_tx_qdesc_vlantci_create(
2105 __in efx_txq_t *etp,
2107 __out efx_desc_t *edp);
2109 #if EFSYS_OPT_QSTATS
2115 __in efx_nic_t *etp,
2116 __in unsigned int id);
2118 #endif /* EFSYS_OPT_NAMES */
2121 efx_tx_qstats_update(
2122 __in efx_txq_t *etp,
2123 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
2125 #endif /* EFSYS_OPT_QSTATS */
2129 __in efx_txq_t *etp);
2134 #if EFSYS_OPT_FILTER
2136 #define EFX_ETHER_TYPE_IPV4 0x0800
2137 #define EFX_ETHER_TYPE_IPV6 0x86DD
2139 #define EFX_IPPROTO_TCP 6
2140 #define EFX_IPPROTO_UDP 17
2142 typedef enum efx_filter_flag_e {
2143 EFX_FILTER_FLAG_RX_RSS = 0x01, /* use RSS to spread across
2144 * multiple queues */
2145 EFX_FILTER_FLAG_RX_SCATTER = 0x02, /* enable RX scatter */
2146 EFX_FILTER_FLAG_RX_OVER_AUTO = 0x04, /* Override an automatic filter
2147 * (priority EFX_FILTER_PRI_AUTO).
2148 * May only be set by the filter
2149 * implementation for each type.
2150 * A removal request will
2151 * restore the automatic filter
2153 EFX_FILTER_FLAG_RX = 0x08, /* Filter is for RX */
2154 EFX_FILTER_FLAG_TX = 0x10, /* Filter is for TX */
2155 } efx_filter_flag_t;
2157 typedef enum efx_filter_match_flags_e {
2158 EFX_FILTER_MATCH_REM_HOST = 0x0001, /* Match by remote IP host
2160 EFX_FILTER_MATCH_LOC_HOST = 0x0002, /* Match by local IP host
2162 EFX_FILTER_MATCH_REM_MAC = 0x0004, /* Match by remote MAC address */
2163 EFX_FILTER_MATCH_REM_PORT = 0x0008, /* Match by remote TCP/UDP port */
2164 EFX_FILTER_MATCH_LOC_MAC = 0x0010, /* Match by remote TCP/UDP port */
2165 EFX_FILTER_MATCH_LOC_PORT = 0x0020, /* Match by local TCP/UDP port */
2166 EFX_FILTER_MATCH_ETHER_TYPE = 0x0040, /* Match by Ether-type */
2167 EFX_FILTER_MATCH_INNER_VID = 0x0080, /* Match by inner VLAN ID */
2168 EFX_FILTER_MATCH_OUTER_VID = 0x0100, /* Match by outer VLAN ID */
2169 EFX_FILTER_MATCH_IP_PROTO = 0x0200, /* Match by IP transport
2171 EFX_FILTER_MATCH_LOC_MAC_IG = 0x0400, /* Match by local MAC address
2172 * I/G bit. Used for RX default
2173 * unicast and multicast/
2174 * broadcast filters. */
2175 } efx_filter_match_flags_t;
2177 typedef enum efx_filter_priority_s {
2178 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
2179 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
2180 * address list or hardware
2181 * requirements. This may only be used
2182 * by the filter implementation for
2184 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
2185 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
2186 * client (e.g. SR-IOV, HyperV VMQ etc.)
2188 } efx_filter_priority_t;
2191 * FIXME: All these fields are assumed to be in little-endian byte order.
2192 * It may be better for some to be big-endian. See bug42804.
2195 typedef struct efx_filter_spec_s {
2196 uint32_t efs_match_flags:12;
2197 uint32_t efs_priority:2;
2198 uint32_t efs_flags:6;
2199 uint32_t efs_dmaq_id:12;
2200 uint32_t efs_rss_context;
2201 uint16_t efs_outer_vid;
2202 uint16_t efs_inner_vid;
2203 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
2204 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
2205 uint16_t efs_ether_type;
2206 uint8_t efs_ip_proto;
2207 uint16_t efs_loc_port;
2208 uint16_t efs_rem_port;
2209 efx_oword_t efs_rem_host;
2210 efx_oword_t efs_loc_host;
2211 } efx_filter_spec_t;
2214 /* Default values for use in filter specifications */
2215 #define EFX_FILTER_SPEC_RSS_CONTEXT_DEFAULT 0xffffffff
2216 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
2217 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
2219 extern __checkReturn efx_rc_t
2221 __in efx_nic_t *enp);
2225 __in efx_nic_t *enp);
2227 extern __checkReturn efx_rc_t
2229 __in efx_nic_t *enp,
2230 __inout efx_filter_spec_t *spec);
2232 extern __checkReturn efx_rc_t
2234 __in efx_nic_t *enp,
2235 __inout efx_filter_spec_t *spec);
2237 extern __checkReturn efx_rc_t
2239 __in efx_nic_t *enp);
2241 extern __checkReturn efx_rc_t
2242 efx_filter_supported_filters(
2243 __in efx_nic_t *enp,
2244 __out uint32_t *list,
2245 __out size_t *length);
2248 efx_filter_spec_init_rx(
2249 __inout efx_filter_spec_t *spec,
2250 __in efx_filter_priority_t priority,
2251 __in efx_filter_flag_t flags,
2252 __in efx_rxq_t *erp);
2255 efx_filter_spec_init_tx(
2256 __inout efx_filter_spec_t *spec,
2257 __in efx_txq_t *etp);
2259 extern __checkReturn efx_rc_t
2260 efx_filter_spec_set_ipv4_local(
2261 __inout efx_filter_spec_t *spec,
2264 __in uint16_t port);
2266 extern __checkReturn efx_rc_t
2267 efx_filter_spec_set_ipv4_full(
2268 __inout efx_filter_spec_t *spec,
2270 __in uint32_t lhost,
2271 __in uint16_t lport,
2272 __in uint32_t rhost,
2273 __in uint16_t rport);
2275 extern __checkReturn efx_rc_t
2276 efx_filter_spec_set_eth_local(
2277 __inout efx_filter_spec_t *spec,
2279 __in const uint8_t *addr);
2281 extern __checkReturn efx_rc_t
2282 efx_filter_spec_set_uc_def(
2283 __inout efx_filter_spec_t *spec);
2285 extern __checkReturn efx_rc_t
2286 efx_filter_spec_set_mc_def(
2287 __inout efx_filter_spec_t *spec);
2289 #endif /* EFSYS_OPT_FILTER */
2293 extern __checkReturn uint32_t
2295 __in_ecount(count) uint32_t const *input,
2297 __in uint32_t init);
2299 extern __checkReturn uint32_t
2301 __in_ecount(length) uint8_t const *input,
2303 __in uint32_t init);
2310 #endif /* _SYS_EFX_H */