2 * Copyright (c) 2006-2015 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
37 #include "efx_phy_ids.h"
43 #define EFX_STATIC_ASSERT(_cond) \
44 ((void)sizeof(char[(_cond) ? 1 : -1]))
46 #define EFX_ARRAY_SIZE(_array) \
47 (sizeof(_array) / sizeof((_array)[0]))
49 #define EFX_FIELD_OFFSET(_type, _field) \
50 ((size_t) &(((_type *)0)->_field))
54 typedef __success(return == 0) int efx_rc_t;
59 typedef enum efx_family_e {
63 EFX_FAMILY_HUNTINGTON,
68 extern __checkReturn efx_rc_t
72 __out efx_family_t *efp);
74 extern __checkReturn efx_rc_t
76 __in efsys_bar_t *esbp,
77 __out efx_family_t *efp);
79 #define EFX_PCI_VENID_SFC 0x1924
81 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
83 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
84 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
85 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
87 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
88 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
89 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
91 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
92 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
94 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
95 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
96 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
105 EFX_ERR_BUFID_DC_OOB,
118 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
119 extern __checkReturn uint32_t
121 __in uint32_t crc_init,
122 __in_ecount(length) uint8_t const *input,
126 /* Type prototypes */
128 typedef struct efx_rxq_s efx_rxq_t;
132 typedef struct efx_nic_s efx_nic_t;
134 #define EFX_NIC_FUNC_PRIMARY 0x00000001
135 #define EFX_NIC_FUNC_LINKCTRL 0x00000002
136 #define EFX_NIC_FUNC_TRUSTED 0x00000004
139 extern __checkReturn efx_rc_t
141 __in efx_family_t family,
142 __in efsys_identifier_t *esip,
143 __in efsys_bar_t *esbp,
144 __in efsys_lock_t *eslp,
145 __deref_out efx_nic_t **enpp);
147 extern __checkReturn efx_rc_t
149 __in efx_nic_t *enp);
151 #if EFSYS_OPT_PCIE_TUNE
153 extern __checkReturn efx_rc_t
156 unsigned int nlanes);
158 extern __checkReturn efx_rc_t
159 efx_nic_pcie_extended_sync(
160 __in efx_nic_t *enp);
162 #endif /* EFSYS_OPT_PCIE_TUNE */
164 extern __checkReturn efx_rc_t
166 __in efx_nic_t *enp);
168 extern __checkReturn efx_rc_t
170 __in efx_nic_t *enp);
174 extern __checkReturn efx_rc_t
175 efx_nic_register_test(
176 __in efx_nic_t *enp);
178 #endif /* EFSYS_OPT_DIAG */
182 __in efx_nic_t *enp);
186 __in efx_nic_t *enp);
190 __in efx_nic_t *enp);
194 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
195 /* Huntington and Medford require MCDIv2 commands */
196 #define WITH_MCDI_V2 1
199 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
201 typedef enum efx_mcdi_exception_e {
202 EFX_MCDI_EXCEPTION_MC_REBOOT,
203 EFX_MCDI_EXCEPTION_MC_BADASSERT,
204 } efx_mcdi_exception_t;
206 #if EFSYS_OPT_MCDI_LOGGING
207 typedef enum efx_log_msg_e
210 EFX_LOG_MCDI_REQUEST,
211 EFX_LOG_MCDI_RESPONSE,
213 #endif /* EFSYS_OPT_MCDI_LOGGING */
215 typedef struct efx_mcdi_transport_s {
217 efsys_mem_t *emt_dma_mem;
218 void (*emt_execute)(void *, efx_mcdi_req_t *);
219 void (*emt_ev_cpl)(void *);
220 void (*emt_exception)(void *, efx_mcdi_exception_t);
221 #if EFSYS_OPT_MCDI_LOGGING
222 void (*emt_logger)(void *, efx_log_msg_t,
223 void *, size_t, void *, size_t);
224 #endif /* EFSYS_OPT_MCDI_LOGGING */
225 #if EFSYS_OPT_MCDI_PROXY_AUTH
226 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
227 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
228 } efx_mcdi_transport_t;
230 extern __checkReturn efx_rc_t
233 __in const efx_mcdi_transport_t *mtp);
235 extern __checkReturn efx_rc_t
237 __in efx_nic_t *enp);
241 __in efx_nic_t *enp);
244 efx_mcdi_request_start(
246 __in efx_mcdi_req_t *emrp,
247 __in boolean_t ev_cpl);
249 extern __checkReturn boolean_t
250 efx_mcdi_request_poll(
251 __in efx_nic_t *enp);
253 extern __checkReturn boolean_t
254 efx_mcdi_request_abort(
255 __in efx_nic_t *enp);
259 __in efx_nic_t *enp);
261 #endif /* EFSYS_OPT_MCDI */
265 #define EFX_NINTR_FALCON 64
266 #define EFX_NINTR_SIENA 1024
268 typedef enum efx_intr_type_e {
269 EFX_INTR_INVALID = 0,
275 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
277 extern __checkReturn efx_rc_t
280 __in efx_intr_type_t type,
281 __in efsys_mem_t *esmp);
285 __in efx_nic_t *enp);
289 __in efx_nic_t *enp);
292 efx_intr_disable_unlocked(
293 __in efx_nic_t *enp);
295 #define EFX_INTR_NEVQS 32
297 extern __checkReturn efx_rc_t
300 __in unsigned int level);
303 efx_intr_status_line(
305 __out boolean_t *fatalp,
306 __out uint32_t *maskp);
309 efx_intr_status_message(
311 __in unsigned int message,
312 __out boolean_t *fatalp);
316 __in efx_nic_t *enp);
320 __in efx_nic_t *enp);
324 #if EFSYS_OPT_MAC_STATS
326 /* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */
327 typedef enum efx_mac_stat_e {
330 EFX_MAC_RX_UNICST_PKTS,
331 EFX_MAC_RX_MULTICST_PKTS,
332 EFX_MAC_RX_BRDCST_PKTS,
333 EFX_MAC_RX_PAUSE_PKTS,
334 EFX_MAC_RX_LE_64_PKTS,
335 EFX_MAC_RX_65_TO_127_PKTS,
336 EFX_MAC_RX_128_TO_255_PKTS,
337 EFX_MAC_RX_256_TO_511_PKTS,
338 EFX_MAC_RX_512_TO_1023_PKTS,
339 EFX_MAC_RX_1024_TO_15XX_PKTS,
340 EFX_MAC_RX_GE_15XX_PKTS,
342 EFX_MAC_RX_FCS_ERRORS,
343 EFX_MAC_RX_DROP_EVENTS,
344 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
345 EFX_MAC_RX_SYMBOL_ERRORS,
346 EFX_MAC_RX_ALIGN_ERRORS,
347 EFX_MAC_RX_INTERNAL_ERRORS,
348 EFX_MAC_RX_JABBER_PKTS,
349 EFX_MAC_RX_LANE0_CHAR_ERR,
350 EFX_MAC_RX_LANE1_CHAR_ERR,
351 EFX_MAC_RX_LANE2_CHAR_ERR,
352 EFX_MAC_RX_LANE3_CHAR_ERR,
353 EFX_MAC_RX_LANE0_DISP_ERR,
354 EFX_MAC_RX_LANE1_DISP_ERR,
355 EFX_MAC_RX_LANE2_DISP_ERR,
356 EFX_MAC_RX_LANE3_DISP_ERR,
357 EFX_MAC_RX_MATCH_FAULT,
358 EFX_MAC_RX_NODESC_DROP_CNT,
361 EFX_MAC_TX_UNICST_PKTS,
362 EFX_MAC_TX_MULTICST_PKTS,
363 EFX_MAC_TX_BRDCST_PKTS,
364 EFX_MAC_TX_PAUSE_PKTS,
365 EFX_MAC_TX_LE_64_PKTS,
366 EFX_MAC_TX_65_TO_127_PKTS,
367 EFX_MAC_TX_128_TO_255_PKTS,
368 EFX_MAC_TX_256_TO_511_PKTS,
369 EFX_MAC_TX_512_TO_1023_PKTS,
370 EFX_MAC_TX_1024_TO_15XX_PKTS,
371 EFX_MAC_TX_GE_15XX_PKTS,
373 EFX_MAC_TX_SGL_COL_PKTS,
374 EFX_MAC_TX_MULT_COL_PKTS,
375 EFX_MAC_TX_EX_COL_PKTS,
376 EFX_MAC_TX_LATE_COL_PKTS,
378 EFX_MAC_TX_EX_DEF_PKTS,
379 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
380 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
381 EFX_MAC_PM_TRUNC_VFIFO_FULL,
382 EFX_MAC_PM_DISCARD_VFIFO_FULL,
383 EFX_MAC_PM_TRUNC_QBB,
384 EFX_MAC_PM_DISCARD_QBB,
385 EFX_MAC_PM_DISCARD_MAPPING,
386 EFX_MAC_RXDP_Q_DISABLED_PKTS,
387 EFX_MAC_RXDP_DI_DROPPED_PKTS,
388 EFX_MAC_RXDP_STREAMING_PKTS,
389 EFX_MAC_RXDP_HLB_FETCH,
390 EFX_MAC_RXDP_HLB_WAIT,
391 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
392 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
393 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
394 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
395 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
396 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
397 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
398 EFX_MAC_VADAPTER_RX_BAD_BYTES,
399 EFX_MAC_VADAPTER_RX_OVERFLOW,
400 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
401 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
402 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
403 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
404 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
405 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
406 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
407 EFX_MAC_VADAPTER_TX_BAD_BYTES,
408 EFX_MAC_VADAPTER_TX_OVERFLOW,
412 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
414 #endif /* EFSYS_OPT_MAC_STATS */
416 typedef enum efx_link_mode_e {
417 EFX_LINK_UNKNOWN = 0,
430 #define EFX_MAC_ADDR_LEN 6
432 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t*)_address)[0] & 0x01)
434 #define EFX_MAC_MULTICAST_LIST_MAX 256
436 #define EFX_MAC_SDU_MAX 9202
438 #define EFX_MAC_PDU(_sdu) \
443 + /* bug16011 */ 16), \
446 #define EFX_MAC_PDU_MIN 60
447 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
449 extern __checkReturn efx_rc_t
454 extern __checkReturn efx_rc_t
459 extern __checkReturn efx_rc_t
462 __in boolean_t all_unicst,
463 __in boolean_t mulcst,
464 __in boolean_t all_mulcst,
465 __in boolean_t brdcst);
467 extern __checkReturn efx_rc_t
468 efx_mac_multicast_list_set(
470 __in_ecount(6*count) uint8_t const *addrs,
473 extern __checkReturn efx_rc_t
474 efx_mac_filter_default_rxq_set(
477 __in boolean_t using_rss);
480 efx_mac_filter_default_rxq_clear(
481 __in efx_nic_t *enp);
483 extern __checkReturn efx_rc_t
486 __in boolean_t enabled);
488 extern __checkReturn efx_rc_t
491 __out boolean_t *mac_upp);
493 #define EFX_FCNTL_RESPOND 0x00000001
494 #define EFX_FCNTL_GENERATE 0x00000002
496 extern __checkReturn efx_rc_t
499 __in unsigned int fcntl,
500 __in boolean_t autoneg);
505 __out unsigned int *fcntl_wantedp,
506 __out unsigned int *fcntl_linkp);
508 #define EFX_MAC_HASH_BITS (1 << 8)
510 extern __checkReturn efx_rc_t
512 __in efx_nic_t *enp);
516 __in efx_nic_t *enp);
518 extern __checkReturn efx_rc_t
521 __in boolean_t unicst,
522 __in boolean_t brdcst);
524 extern __checkReturn efx_rc_t
527 __in_ecount(EFX_MAC_HASH_BITS) unsigned int const *bucket);
529 #if EFSYS_OPT_MCAST_FILTER_LIST
530 extern __checkReturn efx_rc_t
531 efx_pktfilter_mcast_list_set(
533 __in uint8_t const *addrs,
535 #endif /* EFSYS_OPT_MCAST_FILTER_LIST */
537 extern __checkReturn efx_rc_t
538 efx_pktfilter_mcast_all(
539 __in efx_nic_t *enp);
541 #if EFSYS_OPT_MAC_STATS
545 extern __checkReturn const char *
548 __in unsigned int id);
550 #endif /* EFSYS_OPT_NAMES */
552 #define EFX_MAC_STATS_SIZE 0x400
555 * Upload mac statistics supported by the hardware into the given buffer.
557 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes,
560 * The hardware will only DMA statistics that it understands (of course).
561 * Drivers should not make any assumptions about which statistics are
562 * supported, especially when the statistics are generated by firmware.
564 * Thus, drivers should zero this buffer before use, so that not-understood
565 * statistics read back as zero.
567 extern __checkReturn efx_rc_t
568 efx_mac_stats_upload(
570 __in efsys_mem_t *esmp);
572 extern __checkReturn efx_rc_t
573 efx_mac_stats_periodic(
575 __in efsys_mem_t *esmp,
576 __in uint16_t period_ms,
577 __in boolean_t events);
579 extern __checkReturn efx_rc_t
580 efx_mac_stats_update(
582 __in efsys_mem_t *esmp,
583 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
584 __inout_opt uint32_t *generationp);
586 #endif /* EFSYS_OPT_MAC_STATS */
590 typedef enum efx_mon_type_e {
605 __in efx_nic_t *enp);
607 #endif /* EFSYS_OPT_NAMES */
609 extern __checkReturn efx_rc_t
611 __in efx_nic_t *enp);
613 #if EFSYS_OPT_MON_STATS
615 #define EFX_MON_STATS_PAGE_SIZE 0x100
616 #define EFX_MON_MASK_ELEMENT_SIZE 32
618 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock c09b13f732431f23 */
619 typedef enum efx_mon_stat_e {
626 EFX_MON_STAT_EXT_TEMP,
627 EFX_MON_STAT_INT_TEMP,
630 EFX_MON_STAT_INT_COOLING,
631 EFX_MON_STAT_EXT_COOLING,
639 EFX_MON_STAT_AOE_TEMP,
640 EFX_MON_STAT_PSU_AOE_TEMP,
641 EFX_MON_STAT_PSU_TEMP,
647 EFX_MON_STAT_VAOE_IN,
649 EFX_MON_STAT_IAOE_IN,
650 EFX_MON_STAT_NIC_POWER,
654 EFX_MON_STAT_0_9V_ADC,
655 EFX_MON_STAT_INT_TEMP2,
656 EFX_MON_STAT_VREG_TEMP,
657 EFX_MON_STAT_VREG_0_9V_TEMP,
658 EFX_MON_STAT_VREG_1_2V_TEMP,
659 EFX_MON_STAT_INT_VPTAT,
660 EFX_MON_STAT_INT_ADC_TEMP,
661 EFX_MON_STAT_EXT_VPTAT,
662 EFX_MON_STAT_EXT_ADC_TEMP,
663 EFX_MON_STAT_AMBIENT_TEMP,
664 EFX_MON_STAT_AIRFLOW,
665 EFX_MON_STAT_VDD08D_VSS08D_CSR,
666 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
667 EFX_MON_STAT_HOTPOINT_TEMP,
668 EFX_MON_STAT_PHY_POWER_SWITCH_PORT0,
669 EFX_MON_STAT_PHY_POWER_SWITCH_PORT1,
670 EFX_MON_STAT_MUM_VCC,
673 EFX_MON_STAT_0V9_A_TEMP,
676 EFX_MON_STAT_0V9_B_TEMP,
677 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
678 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,
679 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
680 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,
681 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
682 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
683 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,
684 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,
685 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
686 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
687 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,
688 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,
689 EFX_MON_STAT_SODIMM_VOUT,
690 EFX_MON_STAT_SODIMM_0_TEMP,
691 EFX_MON_STAT_SODIMM_1_TEMP,
692 EFX_MON_STAT_PHY0_VCC,
693 EFX_MON_STAT_PHY1_VCC,
694 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
698 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
700 typedef enum efx_mon_stat_state_e {
701 EFX_MON_STAT_STATE_OK = 0,
702 EFX_MON_STAT_STATE_WARNING = 1,
703 EFX_MON_STAT_STATE_FATAL = 2,
704 EFX_MON_STAT_STATE_BROKEN = 3,
705 EFX_MON_STAT_STATE_NO_READING = 4,
706 } efx_mon_stat_state_t;
708 typedef struct efx_mon_stat_value_s {
711 } efx_mon_stat_value_t;
718 __in efx_mon_stat_t id);
720 #endif /* EFSYS_OPT_NAMES */
722 extern __checkReturn efx_rc_t
723 efx_mon_stats_update(
725 __in efsys_mem_t *esmp,
726 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
728 #endif /* EFSYS_OPT_MON_STATS */
732 __in efx_nic_t *enp);
736 #define PMA_PMD_MMD 1
741 #define CL22EXT_MMD 29
743 #define MAXMMD ((1 << 5) - 1)
745 extern __checkReturn efx_rc_t
747 __in efx_nic_t *enp);
749 #if EFSYS_OPT_PHY_LED_CONTROL
751 typedef enum efx_phy_led_mode_e {
752 EFX_PHY_LED_DEFAULT = 0,
757 } efx_phy_led_mode_t;
759 extern __checkReturn efx_rc_t
762 __in efx_phy_led_mode_t mode);
764 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
766 extern __checkReturn efx_rc_t
768 __in efx_nic_t *enp);
770 #if EFSYS_OPT_LOOPBACK
772 typedef enum efx_loopback_type_e {
773 EFX_LOOPBACK_OFF = 0,
774 EFX_LOOPBACK_DATA = 1,
775 EFX_LOOPBACK_GMAC = 2,
776 EFX_LOOPBACK_XGMII = 3,
777 EFX_LOOPBACK_XGXS = 4,
778 EFX_LOOPBACK_XAUI = 5,
779 EFX_LOOPBACK_GMII = 6,
780 EFX_LOOPBACK_SGMII = 7,
781 EFX_LOOPBACK_XGBR = 8,
782 EFX_LOOPBACK_XFI = 9,
783 EFX_LOOPBACK_XAUI_FAR = 10,
784 EFX_LOOPBACK_GMII_FAR = 11,
785 EFX_LOOPBACK_SGMII_FAR = 12,
786 EFX_LOOPBACK_XFI_FAR = 13,
787 EFX_LOOPBACK_GPHY = 14,
788 EFX_LOOPBACK_PHY_XS = 15,
789 EFX_LOOPBACK_PCS = 16,
790 EFX_LOOPBACK_PMA_PMD = 17,
791 EFX_LOOPBACK_XPORT = 18,
792 EFX_LOOPBACK_XGMII_WS = 19,
793 EFX_LOOPBACK_XAUI_WS = 20,
794 EFX_LOOPBACK_XAUI_WS_FAR = 21,
795 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
796 EFX_LOOPBACK_GMII_WS = 23,
797 EFX_LOOPBACK_XFI_WS = 24,
798 EFX_LOOPBACK_XFI_WS_FAR = 25,
799 EFX_LOOPBACK_PHYXS_WS = 26,
800 EFX_LOOPBACK_PMA_INT = 27,
801 EFX_LOOPBACK_SD_NEAR = 28,
802 EFX_LOOPBACK_SD_FAR = 29,
803 EFX_LOOPBACK_PMA_INT_WS = 30,
804 EFX_LOOPBACK_SD_FEP2_WS = 31,
805 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
806 EFX_LOOPBACK_SD_FEP_WS = 33,
807 EFX_LOOPBACK_SD_FES_WS = 34,
809 } efx_loopback_type_t;
811 typedef enum efx_loopback_kind_e {
812 EFX_LOOPBACK_KIND_OFF = 0,
813 EFX_LOOPBACK_KIND_ALL,
814 EFX_LOOPBACK_KIND_MAC,
815 EFX_LOOPBACK_KIND_PHY,
817 } efx_loopback_kind_t;
821 __in efx_loopback_kind_t loopback_kind,
822 __out efx_qword_t *maskp);
824 extern __checkReturn efx_rc_t
825 efx_port_loopback_set(
827 __in efx_link_mode_t link_mode,
828 __in efx_loopback_type_t type);
832 extern __checkReturn const char *
833 efx_loopback_type_name(
835 __in efx_loopback_type_t type);
837 #endif /* EFSYS_OPT_NAMES */
839 #endif /* EFSYS_OPT_LOOPBACK */
841 extern __checkReturn efx_rc_t
844 __out_opt efx_link_mode_t *link_modep);
848 __in efx_nic_t *enp);
850 typedef enum efx_phy_cap_type_e {
851 EFX_PHY_CAP_INVALID = 0,
858 EFX_PHY_CAP_10000FDX,
862 EFX_PHY_CAP_40000FDX,
864 } efx_phy_cap_type_t;
867 #define EFX_PHY_CAP_CURRENT 0x00000000
868 #define EFX_PHY_CAP_DEFAULT 0x00000001
869 #define EFX_PHY_CAP_PERM 0x00000002
875 __out uint32_t *maskp);
877 extern __checkReturn efx_rc_t
885 __out uint32_t *maskp);
887 extern __checkReturn efx_rc_t
890 __out uint32_t *ouip);
892 typedef enum efx_phy_media_type_e {
893 EFX_PHY_MEDIA_INVALID = 0,
898 EFX_PHY_MEDIA_SFP_PLUS,
899 EFX_PHY_MEDIA_BASE_T,
900 EFX_PHY_MEDIA_QSFP_PLUS,
902 } efx_phy_media_type_t;
904 /* Get the type of medium currently used. If the board has ports for
905 * modules, a module is present, and we recognise the media type of
906 * the module, then this will be the media type of the module.
907 * Otherwise it will be the media type of the port.
910 efx_phy_media_type_get(
912 __out efx_phy_media_type_t *typep);
914 #if EFSYS_OPT_PHY_STATS
916 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
917 typedef enum efx_phy_stat_e {
919 EFX_PHY_STAT_PMA_PMD_LINK_UP,
920 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
921 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
922 EFX_PHY_STAT_PMA_PMD_REV_A,
923 EFX_PHY_STAT_PMA_PMD_REV_B,
924 EFX_PHY_STAT_PMA_PMD_REV_C,
925 EFX_PHY_STAT_PMA_PMD_REV_D,
926 EFX_PHY_STAT_PCS_LINK_UP,
927 EFX_PHY_STAT_PCS_RX_FAULT,
928 EFX_PHY_STAT_PCS_TX_FAULT,
929 EFX_PHY_STAT_PCS_BER,
930 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
931 EFX_PHY_STAT_PHY_XS_LINK_UP,
932 EFX_PHY_STAT_PHY_XS_RX_FAULT,
933 EFX_PHY_STAT_PHY_XS_TX_FAULT,
934 EFX_PHY_STAT_PHY_XS_ALIGN,
935 EFX_PHY_STAT_PHY_XS_SYNC_A,
936 EFX_PHY_STAT_PHY_XS_SYNC_B,
937 EFX_PHY_STAT_PHY_XS_SYNC_C,
938 EFX_PHY_STAT_PHY_XS_SYNC_D,
939 EFX_PHY_STAT_AN_LINK_UP,
940 EFX_PHY_STAT_AN_MASTER,
941 EFX_PHY_STAT_AN_LOCAL_RX_OK,
942 EFX_PHY_STAT_AN_REMOTE_RX_OK,
943 EFX_PHY_STAT_CL22EXT_LINK_UP,
948 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
949 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
950 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
951 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
952 EFX_PHY_STAT_AN_COMPLETE,
953 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
954 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
955 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
956 EFX_PHY_STAT_PCS_FW_VERSION_0,
957 EFX_PHY_STAT_PCS_FW_VERSION_1,
958 EFX_PHY_STAT_PCS_FW_VERSION_2,
959 EFX_PHY_STAT_PCS_FW_VERSION_3,
960 EFX_PHY_STAT_PCS_FW_BUILD_YY,
961 EFX_PHY_STAT_PCS_FW_BUILD_MM,
962 EFX_PHY_STAT_PCS_FW_BUILD_DD,
963 EFX_PHY_STAT_PCS_OP_MODE,
967 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
974 __in efx_phy_stat_t stat);
976 #endif /* EFSYS_OPT_NAMES */
978 #define EFX_PHY_STATS_SIZE 0x100
980 extern __checkReturn efx_rc_t
981 efx_phy_stats_update(
983 __in efsys_mem_t *esmp,
984 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
986 #endif /* EFSYS_OPT_PHY_STATS */
988 #if EFSYS_OPT_PHY_PROPS
995 __in unsigned int id);
997 #endif /* EFSYS_OPT_NAMES */
999 #define EFX_PHY_PROP_DEFAULT 0x00000001
1001 extern __checkReturn efx_rc_t
1003 __in efx_nic_t *enp,
1004 __in unsigned int id,
1005 __in uint32_t flags,
1006 __out uint32_t *valp);
1008 extern __checkReturn efx_rc_t
1010 __in efx_nic_t *enp,
1011 __in unsigned int id,
1014 #endif /* EFSYS_OPT_PHY_PROPS */
1018 typedef enum efx_bist_type_e {
1019 EFX_BIST_TYPE_UNKNOWN,
1020 EFX_BIST_TYPE_PHY_NORMAL,
1021 EFX_BIST_TYPE_PHY_CABLE_SHORT,
1022 EFX_BIST_TYPE_PHY_CABLE_LONG,
1023 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
1024 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus*/
1025 EFX_BIST_TYPE_REG, /* Test the register memories */
1026 EFX_BIST_TYPE_NTYPES,
1029 typedef enum efx_bist_result_e {
1030 EFX_BIST_RESULT_UNKNOWN,
1031 EFX_BIST_RESULT_RUNNING,
1032 EFX_BIST_RESULT_PASSED,
1033 EFX_BIST_RESULT_FAILED,
1034 } efx_bist_result_t;
1036 typedef enum efx_phy_cable_status_e {
1037 EFX_PHY_CABLE_STATUS_OK,
1038 EFX_PHY_CABLE_STATUS_INVALID,
1039 EFX_PHY_CABLE_STATUS_OPEN,
1040 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1041 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1042 EFX_PHY_CABLE_STATUS_BUSY,
1043 } efx_phy_cable_status_t;
1045 typedef enum efx_bist_value_e {
1046 EFX_BIST_PHY_CABLE_LENGTH_A,
1047 EFX_BIST_PHY_CABLE_LENGTH_B,
1048 EFX_BIST_PHY_CABLE_LENGTH_C,
1049 EFX_BIST_PHY_CABLE_LENGTH_D,
1050 EFX_BIST_PHY_CABLE_STATUS_A,
1051 EFX_BIST_PHY_CABLE_STATUS_B,
1052 EFX_BIST_PHY_CABLE_STATUS_C,
1053 EFX_BIST_PHY_CABLE_STATUS_D,
1054 EFX_BIST_FAULT_CODE,
1055 /* Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1060 EFX_BIST_MEM_EXPECT,
1061 EFX_BIST_MEM_ACTUAL,
1063 EFX_BIST_MEM_ECC_PARITY,
1064 EFX_BIST_MEM_ECC_FATAL,
1068 extern __checkReturn efx_rc_t
1069 efx_bist_enable_offline(
1070 __in efx_nic_t *enp);
1072 extern __checkReturn efx_rc_t
1074 __in efx_nic_t *enp,
1075 __in efx_bist_type_t type);
1077 extern __checkReturn efx_rc_t
1079 __in efx_nic_t *enp,
1080 __in efx_bist_type_t type,
1081 __out efx_bist_result_t *resultp,
1082 __out_opt uint32_t *value_maskp,
1083 __out_ecount_opt(count) unsigned long *valuesp,
1088 __in efx_nic_t *enp,
1089 __in efx_bist_type_t type);
1091 #endif /* EFSYS_OPT_BIST */
1093 #define EFX_FEATURE_IPV6 0x00000001
1094 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1095 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1096 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1097 #define EFX_FEATURE_WOL 0x00000010
1098 #define EFX_FEATURE_MCDI 0x00000020
1099 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1100 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1101 #define EFX_FEATURE_TURBO 0x00000100
1102 #define EFX_FEATURE_MCDI_DMA 0x00000200
1103 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1104 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1105 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1107 typedef struct efx_nic_cfg_s {
1108 uint32_t enc_board_type;
1109 uint32_t enc_phy_type;
1111 char enc_phy_name[21];
1113 char enc_phy_revision[21];
1114 efx_mon_type_t enc_mon_type;
1115 #if EFSYS_OPT_MON_STATS
1116 uint32_t enc_mon_stat_dma_buf_size;
1117 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1119 unsigned int enc_features;
1120 uint8_t enc_mac_addr[6];
1121 uint8_t enc_port; /* PHY port number */
1122 uint32_t enc_func_flags;
1123 uint32_t enc_intr_vec_base;
1124 uint32_t enc_intr_limit;
1125 uint32_t enc_evq_limit;
1126 uint32_t enc_txq_limit;
1127 uint32_t enc_rxq_limit;
1128 uint32_t enc_buftbl_limit;
1129 uint32_t enc_piobuf_limit;
1130 uint32_t enc_piobuf_size;
1131 uint32_t enc_piobuf_min_alloc_size;
1132 uint32_t enc_evq_timer_quantum_ns;
1133 uint32_t enc_evq_timer_max_us;
1134 uint32_t enc_clk_mult;
1135 uint32_t enc_rx_prefix_size;
1136 uint32_t enc_rx_buf_align_start;
1137 uint32_t enc_rx_buf_align_end;
1138 #if EFSYS_OPT_LOOPBACK
1139 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1140 #endif /* EFSYS_OPT_LOOPBACK */
1141 #if EFSYS_OPT_PHY_FLAGS
1142 uint32_t enc_phy_flags_mask;
1143 #endif /* EFSYS_OPT_PHY_FLAGS */
1144 #if EFSYS_OPT_PHY_LED_CONTROL
1145 uint32_t enc_led_mask;
1146 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1147 #if EFSYS_OPT_PHY_STATS
1148 uint64_t enc_phy_stat_mask;
1149 #endif /* EFSYS_OPT_PHY_STATS */
1150 #if EFSYS_OPT_PHY_PROPS
1151 unsigned int enc_phy_nprops;
1152 #endif /* EFSYS_OPT_PHY_PROPS */
1154 uint8_t enc_mcdi_mdio_channel;
1155 #if EFSYS_OPT_PHY_STATS
1156 uint32_t enc_mcdi_phy_stat_mask;
1157 #endif /* EFSYS_OPT_PHY_STATS */
1158 #endif /* EFSYS_OPT_SIENA */
1159 #if (EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
1160 #if EFSYS_OPT_MON_STATS
1161 uint32_t *enc_mcdi_sensor_maskp;
1162 uint32_t enc_mcdi_sensor_mask_size;
1163 #endif /* EFSYS_OPT_MON_STATS */
1164 #endif /* (EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
1166 uint32_t enc_bist_mask;
1167 #endif /* EFSYS_OPT_BIST */
1168 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
1171 uint32_t enc_privilege_mask;
1172 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
1173 boolean_t enc_bug26807_workaround;
1174 boolean_t enc_bug35388_workaround;
1175 boolean_t enc_bug41750_workaround;
1176 boolean_t enc_rx_batching_enabled;
1177 /* Maximum number of descriptors completed in an rx event. */
1178 uint32_t enc_rx_batch_max;
1179 /* Number of rx descriptors the hardware requires for a push. */
1180 uint32_t enc_rx_push_align;
1182 * Maximum number of bytes into the packet the TCP header can start for
1183 * the hardware to apply TSO packet edits.
1185 uint32_t enc_tx_tso_tcp_header_offset_limit;
1186 boolean_t enc_fw_assisted_tso_enabled;
1187 boolean_t enc_hw_tx_insert_vlan_enabled;
1188 /* Datapath firmware vadapter/vport/vswitch support */
1189 boolean_t enc_datapath_cap_evb;
1190 boolean_t enc_rx_disable_scatter_supported;
1191 boolean_t enc_allow_set_mac_with_installed_filters;
1192 /* External port identifier */
1193 uint8_t enc_external_port;
1194 uint32_t enc_mcdi_max_payload_length;
1197 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1198 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1200 #define EFX_PCI_FUNCTION(_encp) \
1201 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1203 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1205 extern const efx_nic_cfg_t *
1207 __in efx_nic_t *enp);
1209 /* Driver resource limits (minimum required/maximum usable). */
1210 typedef struct efx_drv_limits_s
1212 uint32_t edl_min_evq_count;
1213 uint32_t edl_max_evq_count;
1215 uint32_t edl_min_rxq_count;
1216 uint32_t edl_max_rxq_count;
1218 uint32_t edl_min_txq_count;
1219 uint32_t edl_max_txq_count;
1221 /* PIO blocks (sub-allocated from piobuf) */
1222 uint32_t edl_min_pio_alloc_size;
1223 uint32_t edl_max_pio_alloc_count;
1226 extern __checkReturn efx_rc_t
1227 efx_nic_set_drv_limits(
1228 __inout efx_nic_t *enp,
1229 __in efx_drv_limits_t *edlp);
1231 typedef enum efx_nic_region_e {
1232 EFX_REGION_VI, /* Memory BAR UC mapping */
1233 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1236 extern __checkReturn efx_rc_t
1237 efx_nic_get_bar_region(
1238 __in efx_nic_t *enp,
1239 __in efx_nic_region_t region,
1240 __out uint32_t *offsetp,
1241 __out size_t *sizep);
1243 extern __checkReturn efx_rc_t
1244 efx_nic_get_vi_pool(
1245 __in efx_nic_t *enp,
1246 __out uint32_t *evq_countp,
1247 __out uint32_t *rxq_countp,
1248 __out uint32_t *txq_countp);
1253 typedef enum efx_vpd_tag_e {
1260 typedef uint16_t efx_vpd_keyword_t;
1262 typedef struct efx_vpd_value_s {
1263 efx_vpd_tag_t evv_tag;
1264 efx_vpd_keyword_t evv_keyword;
1266 uint8_t evv_value[0x100];
1270 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1272 extern __checkReturn efx_rc_t
1274 __in efx_nic_t *enp);
1276 extern __checkReturn efx_rc_t
1278 __in efx_nic_t *enp,
1279 __out size_t *sizep);
1281 extern __checkReturn efx_rc_t
1283 __in efx_nic_t *enp,
1284 __out_bcount(size) caddr_t data,
1287 extern __checkReturn efx_rc_t
1289 __in efx_nic_t *enp,
1290 __in_bcount(size) caddr_t data,
1293 extern __checkReturn efx_rc_t
1295 __in efx_nic_t *enp,
1296 __in_bcount(size) caddr_t data,
1299 extern __checkReturn efx_rc_t
1301 __in efx_nic_t *enp,
1302 __in_bcount(size) caddr_t data,
1304 __inout efx_vpd_value_t *evvp);
1306 extern __checkReturn efx_rc_t
1308 __in efx_nic_t *enp,
1309 __inout_bcount(size) caddr_t data,
1311 __in efx_vpd_value_t *evvp);
1313 extern __checkReturn efx_rc_t
1315 __in efx_nic_t *enp,
1316 __inout_bcount(size) caddr_t data,
1318 __out efx_vpd_value_t *evvp,
1319 __inout unsigned int *contp);
1321 extern __checkReturn efx_rc_t
1323 __in efx_nic_t *enp,
1324 __in_bcount(size) caddr_t data,
1329 __in efx_nic_t *enp);
1331 #endif /* EFSYS_OPT_VPD */
1337 typedef enum efx_nvram_type_e {
1338 EFX_NVRAM_INVALID = 0,
1340 EFX_NVRAM_BOOTROM_CFG,
1341 EFX_NVRAM_MC_FIRMWARE,
1342 EFX_NVRAM_MC_GOLDEN,
1348 EFX_NVRAM_FPGA_BACKUP,
1349 EFX_NVRAM_DYNAMIC_CFG,
1353 extern __checkReturn efx_rc_t
1355 __in efx_nic_t *enp);
1359 extern __checkReturn efx_rc_t
1361 __in efx_nic_t *enp);
1363 #endif /* EFSYS_OPT_DIAG */
1365 extern __checkReturn efx_rc_t
1367 __in efx_nic_t *enp,
1368 __in efx_nvram_type_t type,
1369 __out size_t *sizep);
1371 extern __checkReturn efx_rc_t
1373 __in efx_nic_t *enp,
1374 __in efx_nvram_type_t type,
1375 __out_opt size_t *pref_chunkp);
1378 efx_nvram_rw_finish(
1379 __in efx_nic_t *enp,
1380 __in efx_nvram_type_t type);
1382 extern __checkReturn efx_rc_t
1383 efx_nvram_get_version(
1384 __in efx_nic_t *enp,
1385 __in efx_nvram_type_t type,
1386 __out uint32_t *subtypep,
1387 __out_ecount(4) uint16_t version[4]);
1389 extern __checkReturn efx_rc_t
1390 efx_nvram_read_chunk(
1391 __in efx_nic_t *enp,
1392 __in efx_nvram_type_t type,
1393 __in unsigned int offset,
1394 __out_bcount(size) caddr_t data,
1397 extern __checkReturn efx_rc_t
1398 efx_nvram_set_version(
1399 __in efx_nic_t *enp,
1400 __in efx_nvram_type_t type,
1401 __in_ecount(4) uint16_t version[4]);
1403 /* Validate contents of TLV formatted partition */
1404 extern __checkReturn efx_rc_t
1405 efx_nvram_tlv_validate(
1406 __in efx_nic_t *enp,
1407 __in uint32_t partn,
1408 __in_bcount(partn_size) caddr_t partn_data,
1409 __in size_t partn_size);
1411 extern __checkReturn efx_rc_t
1413 __in efx_nic_t *enp,
1414 __in efx_nvram_type_t type);
1416 extern __checkReturn efx_rc_t
1417 efx_nvram_write_chunk(
1418 __in efx_nic_t *enp,
1419 __in efx_nvram_type_t type,
1420 __in unsigned int offset,
1421 __in_bcount(size) caddr_t data,
1426 __in efx_nic_t *enp);
1428 #endif /* EFSYS_OPT_NVRAM */
1430 #if EFSYS_OPT_BOOTCFG
1434 __in efx_nic_t *enp,
1435 __out_bcount(size) caddr_t data,
1440 __in efx_nic_t *enp,
1441 __in_bcount(size) caddr_t data,
1444 #endif /* EFSYS_OPT_BOOTCFG */
1448 typedef enum efx_wol_type_e {
1449 EFX_WOL_TYPE_INVALID,
1451 EFX_WOL_TYPE_BITMAP,
1456 typedef enum efx_lightsout_offload_type_e {
1457 EFX_LIGHTSOUT_OFFLOAD_TYPE_INVALID,
1458 EFX_LIGHTSOUT_OFFLOAD_TYPE_ARP,
1459 EFX_LIGHTSOUT_OFFLOAD_TYPE_NS,
1460 } efx_lightsout_offload_type_t;
1462 #define EFX_WOL_BITMAP_MASK_SIZE (48)
1463 #define EFX_WOL_BITMAP_VALUE_SIZE (128)
1465 typedef union efx_wol_param_u {
1467 uint8_t mac_addr[6];
1470 uint8_t mask[EFX_WOL_BITMAP_MASK_SIZE]; /* 1 bit per byte */
1471 uint8_t value[EFX_WOL_BITMAP_VALUE_SIZE]; /* value to match */
1476 typedef union efx_lightsout_offload_param_u {
1478 uint8_t mac_addr[6];
1482 uint8_t mac_addr[6];
1483 uint32_t solicited_node[4];
1486 } efx_lightsout_offload_param_t;
1488 extern __checkReturn efx_rc_t
1490 __in efx_nic_t *enp);
1492 extern __checkReturn efx_rc_t
1493 efx_wol_filter_clear(
1494 __in efx_nic_t *enp);
1496 extern __checkReturn efx_rc_t
1498 __in efx_nic_t *enp,
1499 __in efx_wol_type_t type,
1500 __in efx_wol_param_t *paramp,
1501 __out uint32_t *filter_idp);
1503 extern __checkReturn efx_rc_t
1504 efx_wol_filter_remove(
1505 __in efx_nic_t *enp,
1506 __in uint32_t filter_id);
1508 extern __checkReturn efx_rc_t
1509 efx_lightsout_offload_add(
1510 __in efx_nic_t *enp,
1511 __in efx_lightsout_offload_type_t type,
1512 __in efx_lightsout_offload_param_t *paramp,
1513 __out uint32_t *filter_idp);
1515 extern __checkReturn efx_rc_t
1516 efx_lightsout_offload_remove(
1517 __in efx_nic_t *enp,
1518 __in efx_lightsout_offload_type_t type,
1519 __in uint32_t filter_id);
1523 __in efx_nic_t *enp);
1525 #endif /* EFSYS_OPT_WOL */
1529 typedef enum efx_pattern_type_t {
1530 EFX_PATTERN_BYTE_INCREMENT = 0,
1531 EFX_PATTERN_ALL_THE_SAME,
1532 EFX_PATTERN_BIT_ALTERNATE,
1533 EFX_PATTERN_BYTE_ALTERNATE,
1534 EFX_PATTERN_BYTE_CHANGING,
1535 EFX_PATTERN_BIT_SWEEP,
1537 } efx_pattern_type_t;
1540 (*efx_sram_pattern_fn_t)(
1542 __in boolean_t negate,
1543 __out efx_qword_t *eqp);
1545 extern __checkReturn efx_rc_t
1547 __in efx_nic_t *enp,
1548 __in efx_pattern_type_t type);
1550 #endif /* EFSYS_OPT_DIAG */
1552 extern __checkReturn efx_rc_t
1553 efx_sram_buf_tbl_set(
1554 __in efx_nic_t *enp,
1556 __in efsys_mem_t *esmp,
1560 efx_sram_buf_tbl_clear(
1561 __in efx_nic_t *enp,
1565 #define EFX_BUF_TBL_SIZE 0x20000
1567 #define EFX_BUF_SIZE 4096
1571 typedef struct efx_evq_s efx_evq_t;
1573 #if EFSYS_OPT_QSTATS
1575 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1576 typedef enum efx_ev_qstat_e {
1582 EV_RX_PAUSE_FRM_ERR,
1583 EV_RX_BUF_OWNER_ID_ERR,
1584 EV_RX_IPV4_HDR_CHKSUM_ERR,
1585 EV_RX_TCP_UDP_CHKSUM_ERR,
1589 EV_RX_MCAST_HASH_MATCH,
1606 EV_DRIVER_SRM_UPD_DONE,
1607 EV_DRIVER_TX_DESCQ_FLS_DONE,
1608 EV_DRIVER_RX_DESCQ_FLS_DONE,
1609 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1610 EV_DRIVER_RX_DSC_ERROR,
1611 EV_DRIVER_TX_DSC_ERROR,
1617 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1619 #endif /* EFSYS_OPT_QSTATS */
1621 extern __checkReturn efx_rc_t
1623 __in efx_nic_t *enp);
1627 __in efx_nic_t *enp);
1629 #define EFX_EVQ_MAXNEVS 32768
1630 #define EFX_EVQ_MINNEVS 512
1632 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
1633 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1635 extern __checkReturn efx_rc_t
1637 __in efx_nic_t *enp,
1638 __in unsigned int index,
1639 __in efsys_mem_t *esmp,
1642 __deref_out efx_evq_t **eepp);
1646 __in efx_evq_t *eep,
1647 __in uint16_t data);
1649 typedef __checkReturn boolean_t
1650 (*efx_initialized_ev_t)(
1651 __in_opt void *arg);
1653 #define EFX_PKT_UNICAST 0x0004
1654 #define EFX_PKT_START 0x0008
1656 #define EFX_PKT_VLAN_TAGGED 0x0010
1657 #define EFX_CKSUM_TCPUDP 0x0020
1658 #define EFX_CKSUM_IPV4 0x0040
1659 #define EFX_PKT_CONT 0x0080
1661 #define EFX_CHECK_VLAN 0x0100
1662 #define EFX_PKT_TCP 0x0200
1663 #define EFX_PKT_UDP 0x0400
1664 #define EFX_PKT_IPV4 0x0800
1666 #define EFX_PKT_IPV6 0x1000
1667 #define EFX_PKT_PREFIX_LEN 0x2000
1668 #define EFX_ADDR_MISMATCH 0x4000
1669 #define EFX_DISCARD 0x8000
1671 #define EFX_EV_RX_NLABELS 32
1672 #define EFX_EV_TX_NLABELS 32
1674 typedef __checkReturn boolean_t
1677 __in uint32_t label,
1680 __in uint16_t flags);
1682 typedef __checkReturn boolean_t
1685 __in uint32_t label,
1688 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
1689 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
1690 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
1691 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
1692 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
1693 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
1694 #define EFX_EXCEPTION_RX_ERROR 0x00000007
1695 #define EFX_EXCEPTION_TX_ERROR 0x00000008
1696 #define EFX_EXCEPTION_EV_ERROR 0x00000009
1698 typedef __checkReturn boolean_t
1699 (*efx_exception_ev_t)(
1701 __in uint32_t label,
1702 __in uint32_t data);
1704 typedef __checkReturn boolean_t
1705 (*efx_rxq_flush_done_ev_t)(
1707 __in uint32_t rxq_index);
1709 typedef __checkReturn boolean_t
1710 (*efx_rxq_flush_failed_ev_t)(
1712 __in uint32_t rxq_index);
1714 typedef __checkReturn boolean_t
1715 (*efx_txq_flush_done_ev_t)(
1717 __in uint32_t txq_index);
1719 typedef __checkReturn boolean_t
1720 (*efx_software_ev_t)(
1722 __in uint16_t magic);
1724 typedef __checkReturn boolean_t
1727 __in uint32_t code);
1729 #define EFX_SRAM_CLEAR 0
1730 #define EFX_SRAM_UPDATE 1
1731 #define EFX_SRAM_ILLEGAL_CLEAR 2
1733 typedef __checkReturn boolean_t
1734 (*efx_wake_up_ev_t)(
1736 __in uint32_t label);
1738 typedef __checkReturn boolean_t
1741 __in uint32_t label);
1743 typedef __checkReturn boolean_t
1744 (*efx_link_change_ev_t)(
1746 __in efx_link_mode_t link_mode);
1748 #if EFSYS_OPT_MON_STATS
1750 typedef __checkReturn boolean_t
1751 (*efx_monitor_ev_t)(
1753 __in efx_mon_stat_t id,
1754 __in efx_mon_stat_value_t value);
1756 #endif /* EFSYS_OPT_MON_STATS */
1758 #if EFSYS_OPT_MAC_STATS
1760 typedef __checkReturn boolean_t
1761 (*efx_mac_stats_ev_t)(
1763 __in uint32_t generation
1766 #endif /* EFSYS_OPT_MAC_STATS */
1768 typedef struct efx_ev_callbacks_s {
1769 efx_initialized_ev_t eec_initialized;
1772 efx_exception_ev_t eec_exception;
1773 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
1774 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
1775 efx_txq_flush_done_ev_t eec_txq_flush_done;
1776 efx_software_ev_t eec_software;
1777 efx_sram_ev_t eec_sram;
1778 efx_wake_up_ev_t eec_wake_up;
1779 efx_timer_ev_t eec_timer;
1780 efx_link_change_ev_t eec_link_change;
1781 #if EFSYS_OPT_MON_STATS
1782 efx_monitor_ev_t eec_monitor;
1783 #endif /* EFSYS_OPT_MON_STATS */
1784 #if EFSYS_OPT_MAC_STATS
1785 efx_mac_stats_ev_t eec_mac_stats;
1786 #endif /* EFSYS_OPT_MAC_STATS */
1787 } efx_ev_callbacks_t;
1789 extern __checkReturn boolean_t
1791 __in efx_evq_t *eep,
1792 __in unsigned int count);
1794 #if EFSYS_OPT_EV_PREFETCH
1798 __in efx_evq_t *eep,
1799 __in unsigned int count);
1801 #endif /* EFSYS_OPT_EV_PREFETCH */
1805 __in efx_evq_t *eep,
1806 __inout unsigned int *countp,
1807 __in const efx_ev_callbacks_t *eecp,
1808 __in_opt void *arg);
1810 extern __checkReturn efx_rc_t
1812 __in efx_evq_t *eep,
1813 __in unsigned int us);
1815 extern __checkReturn efx_rc_t
1817 __in efx_evq_t *eep,
1818 __in unsigned int count);
1820 #if EFSYS_OPT_QSTATS
1826 __in efx_nic_t *enp,
1827 __in unsigned int id);
1829 #endif /* EFSYS_OPT_NAMES */
1832 efx_ev_qstats_update(
1833 __in efx_evq_t *eep,
1834 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
1836 #endif /* EFSYS_OPT_QSTATS */
1840 __in efx_evq_t *eep);
1844 extern __checkReturn efx_rc_t
1846 __inout efx_nic_t *enp);
1850 __in efx_nic_t *enp);
1852 #if EFSYS_OPT_RX_HDR_SPLIT
1853 __checkReturn efx_rc_t
1854 efx_rx_hdr_split_enable(
1855 __in efx_nic_t *enp,
1856 __in unsigned int hdr_buf_size,
1857 __in unsigned int pld_buf_size);
1859 #endif /* EFSYS_OPT_RX_HDR_SPLIT */
1861 #if EFSYS_OPT_RX_SCATTER
1862 __checkReturn efx_rc_t
1863 efx_rx_scatter_enable(
1864 __in efx_nic_t *enp,
1865 __in unsigned int buf_size);
1866 #endif /* EFSYS_OPT_RX_SCATTER */
1868 #if EFSYS_OPT_RX_SCALE
1870 typedef enum efx_rx_hash_alg_e {
1871 EFX_RX_HASHALG_LFSR = 0,
1872 EFX_RX_HASHALG_TOEPLITZ
1873 } efx_rx_hash_alg_t;
1875 typedef enum efx_rx_hash_type_e {
1876 EFX_RX_HASH_IPV4 = 0,
1877 EFX_RX_HASH_TCPIPV4,
1879 EFX_RX_HASH_TCPIPV6,
1880 } efx_rx_hash_type_t;
1882 typedef enum efx_rx_hash_support_e {
1883 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
1884 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
1885 } efx_rx_hash_support_t;
1887 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
1888 #define EFX_MAXRSS 64 /* RX indirection entry range */
1889 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
1891 typedef enum efx_rx_scale_support_e {
1892 EFX_RX_SCALE_UNAVAILABLE = 0, /* Not supported */
1893 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
1894 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
1895 } efx_rx_scale_support_t;
1897 extern __checkReturn efx_rc_t
1898 efx_rx_hash_support_get(
1899 __in efx_nic_t *enp,
1900 __out efx_rx_hash_support_t *supportp);
1903 extern __checkReturn efx_rc_t
1904 efx_rx_scale_support_get(
1905 __in efx_nic_t *enp,
1906 __out efx_rx_scale_support_t *supportp);
1908 extern __checkReturn efx_rc_t
1909 efx_rx_scale_mode_set(
1910 __in efx_nic_t *enp,
1911 __in efx_rx_hash_alg_t alg,
1912 __in efx_rx_hash_type_t type,
1913 __in boolean_t insert);
1915 extern __checkReturn efx_rc_t
1916 efx_rx_scale_tbl_set(
1917 __in efx_nic_t *enp,
1918 __in_ecount(n) unsigned int *table,
1921 extern __checkReturn efx_rc_t
1922 efx_rx_scale_key_set(
1923 __in efx_nic_t *enp,
1924 __in_ecount(n) uint8_t *key,
1928 efx_psuedo_hdr_hash_get(
1929 __in efx_nic_t *enp,
1930 __in efx_rx_hash_alg_t func,
1931 __in uint8_t *buffer);
1933 #endif /* EFSYS_OPT_RX_SCALE */
1935 extern __checkReturn efx_rc_t
1936 efx_psuedo_hdr_pkt_length_get(
1937 __in efx_nic_t *enp,
1938 __in uint8_t *buffer,
1939 __out uint16_t *pkt_lengthp);
1941 #define EFX_RXQ_MAXNDESCS 4096
1942 #define EFX_RXQ_MINNDESCS 512
1944 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
1945 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1946 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
1947 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
1949 typedef enum efx_rxq_type_e {
1950 EFX_RXQ_TYPE_DEFAULT,
1951 EFX_RXQ_TYPE_SPLIT_HEADER,
1952 EFX_RXQ_TYPE_SPLIT_PAYLOAD,
1953 EFX_RXQ_TYPE_SCATTER,
1957 extern __checkReturn efx_rc_t
1959 __in efx_nic_t *enp,
1960 __in unsigned int index,
1961 __in unsigned int label,
1962 __in efx_rxq_type_t type,
1963 __in efsys_mem_t *esmp,
1966 __in efx_evq_t *eep,
1967 __deref_out efx_rxq_t **erpp);
1969 typedef struct efx_buffer_s {
1970 efsys_dma_addr_t eb_addr;
1975 typedef struct efx_desc_s {
1981 __in efx_rxq_t *erp,
1982 __in_ecount(n) efsys_dma_addr_t *addrp,
1984 __in unsigned int n,
1985 __in unsigned int completed,
1986 __in unsigned int added);
1990 __in efx_rxq_t *erp,
1991 __in unsigned int added,
1992 __inout unsigned int *pushedp);
1994 extern __checkReturn efx_rc_t
1996 __in efx_rxq_t *erp);
2000 __in efx_rxq_t *erp);
2004 __in efx_rxq_t *erp);
2008 typedef struct efx_txq_s efx_txq_t;
2010 #if EFSYS_OPT_QSTATS
2012 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
2013 typedef enum efx_tx_qstat_e {
2019 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
2021 #endif /* EFSYS_OPT_QSTATS */
2023 extern __checkReturn efx_rc_t
2025 __in efx_nic_t *enp);
2029 __in efx_nic_t *enp);
2031 #define EFX_BUG35388_WORKAROUND(_encp) \
2032 (((_encp) == NULL) ? 1 : ((_encp)->enc_bug35388_workaround != 0))
2034 #define EFX_TXQ_MAXNDESCS(_encp) \
2035 ((EFX_BUG35388_WORKAROUND(_encp)) ? 2048 : 4096)
2037 #define EFX_TXQ_MINNDESCS 512
2039 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2040 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2041 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2042 #define EFX_TXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
2044 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2046 #define EFX_TXQ_CKSUM_IPV4 0x0001
2047 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
2049 extern __checkReturn efx_rc_t
2051 __in efx_nic_t *enp,
2052 __in unsigned int index,
2053 __in unsigned int label,
2054 __in efsys_mem_t *esmp,
2057 __in uint16_t flags,
2058 __in efx_evq_t *eep,
2059 __deref_out efx_txq_t **etpp,
2060 __out unsigned int *addedp);
2062 extern __checkReturn efx_rc_t
2064 __in efx_txq_t *etp,
2065 __in_ecount(n) efx_buffer_t *eb,
2066 __in unsigned int n,
2067 __in unsigned int completed,
2068 __inout unsigned int *addedp);
2070 extern __checkReturn efx_rc_t
2072 __in efx_txq_t *etp,
2073 __in unsigned int ns);
2077 __in efx_txq_t *etp,
2078 __in unsigned int added,
2079 __in unsigned int pushed);
2081 extern __checkReturn efx_rc_t
2083 __in efx_txq_t *etp);
2087 __in efx_txq_t *etp);
2089 extern __checkReturn efx_rc_t
2091 __in efx_txq_t *etp);
2094 efx_tx_qpio_disable(
2095 __in efx_txq_t *etp);
2097 extern __checkReturn efx_rc_t
2099 __in efx_txq_t *etp,
2100 __in_ecount(buf_length) uint8_t *buffer,
2101 __in size_t buf_length,
2102 __in size_t pio_buf_offset);
2104 extern __checkReturn efx_rc_t
2106 __in efx_txq_t *etp,
2107 __in size_t pkt_length,
2108 __in unsigned int completed,
2109 __inout unsigned int *addedp);
2111 extern __checkReturn efx_rc_t
2113 __in efx_txq_t *etp,
2114 __in_ecount(n) efx_desc_t *ed,
2115 __in unsigned int n,
2116 __in unsigned int completed,
2117 __inout unsigned int *addedp);
2120 efx_tx_qdesc_dma_create(
2121 __in efx_txq_t *etp,
2122 __in efsys_dma_addr_t addr,
2125 __out efx_desc_t *edp);
2128 efx_tx_qdesc_tso_create(
2129 __in efx_txq_t *etp,
2130 __in uint16_t ipv4_id,
2131 __in uint32_t tcp_seq,
2132 __in uint8_t tcp_flags,
2133 __out efx_desc_t *edp);
2136 efx_tx_qdesc_vlantci_create(
2137 __in efx_txq_t *etp,
2139 __out efx_desc_t *edp);
2141 #if EFSYS_OPT_QSTATS
2147 __in efx_nic_t *etp,
2148 __in unsigned int id);
2150 #endif /* EFSYS_OPT_NAMES */
2153 efx_tx_qstats_update(
2154 __in efx_txq_t *etp,
2155 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
2157 #endif /* EFSYS_OPT_QSTATS */
2161 __in efx_txq_t *etp);
2166 #if EFSYS_OPT_FILTER
2168 #define EFX_ETHER_TYPE_IPV4 0x0800
2169 #define EFX_ETHER_TYPE_IPV6 0x86DD
2171 #define EFX_IPPROTO_TCP 6
2172 #define EFX_IPPROTO_UDP 17
2174 typedef enum efx_filter_flag_e {
2175 EFX_FILTER_FLAG_RX_RSS = 0x01, /* use RSS to spread across
2176 * multiple queues */
2177 EFX_FILTER_FLAG_RX_SCATTER = 0x02, /* enable RX scatter */
2178 EFX_FILTER_FLAG_RX_OVER_AUTO = 0x04, /* Override an automatic filter
2179 * (priority EFX_FILTER_PRI_AUTO).
2180 * May only be set by the filter
2181 * implementation for each type.
2182 * A removal request will
2183 * restore the automatic filter
2185 EFX_FILTER_FLAG_RX = 0x08, /* Filter is for RX */
2186 EFX_FILTER_FLAG_TX = 0x10, /* Filter is for TX */
2187 } efx_filter_flag_t;
2189 typedef enum efx_filter_match_flags_e {
2190 EFX_FILTER_MATCH_REM_HOST = 0x0001, /* Match by remote IP host
2192 EFX_FILTER_MATCH_LOC_HOST = 0x0002, /* Match by local IP host
2194 EFX_FILTER_MATCH_REM_MAC = 0x0004, /* Match by remote MAC address */
2195 EFX_FILTER_MATCH_REM_PORT = 0x0008, /* Match by remote TCP/UDP port */
2196 EFX_FILTER_MATCH_LOC_MAC = 0x0010, /* Match by remote TCP/UDP port */
2197 EFX_FILTER_MATCH_LOC_PORT = 0x0020, /* Match by local TCP/UDP port */
2198 EFX_FILTER_MATCH_ETHER_TYPE = 0x0040, /* Match by Ether-type */
2199 EFX_FILTER_MATCH_INNER_VID = 0x0080, /* Match by inner VLAN ID */
2200 EFX_FILTER_MATCH_OUTER_VID = 0x0100, /* Match by outer VLAN ID */
2201 EFX_FILTER_MATCH_IP_PROTO = 0x0200, /* Match by IP transport
2203 EFX_FILTER_MATCH_LOC_MAC_IG = 0x0400, /* Match by local MAC address
2204 * I/G bit. Used for RX default
2205 * unicast and multicast/
2206 * broadcast filters. */
2207 } efx_filter_match_flags_t;
2209 typedef enum efx_filter_priority_s {
2210 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
2211 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
2212 * address list or hardware
2213 * requirements. This may only be used
2214 * by the filter implementation for
2216 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
2217 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
2218 * client (e.g. SR-IOV, HyperV VMQ etc.)
2220 } efx_filter_priority_t;
2223 * FIXME: All these fields are assumed to be in little-endian byte order.
2224 * It may be better for some to be big-endian. See bug42804.
2227 typedef struct efx_filter_spec_s {
2228 uint32_t efs_match_flags:12;
2229 uint32_t efs_priority:2;
2230 uint32_t efs_flags:6;
2231 uint32_t efs_dmaq_id:12;
2232 uint32_t efs_rss_context;
2233 uint16_t efs_outer_vid;
2234 uint16_t efs_inner_vid;
2235 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
2236 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
2237 uint16_t efs_ether_type;
2238 uint8_t efs_ip_proto;
2239 uint16_t efs_loc_port;
2240 uint16_t efs_rem_port;
2241 efx_oword_t efs_rem_host;
2242 efx_oword_t efs_loc_host;
2243 } efx_filter_spec_t;
2246 /* Default values for use in filter specifications */
2247 #define EFX_FILTER_SPEC_RSS_CONTEXT_DEFAULT 0xffffffff
2248 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
2249 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
2251 extern __checkReturn efx_rc_t
2253 __in efx_nic_t *enp);
2257 __in efx_nic_t *enp);
2259 extern __checkReturn efx_rc_t
2261 __in efx_nic_t *enp,
2262 __inout efx_filter_spec_t *spec);
2264 extern __checkReturn efx_rc_t
2266 __in efx_nic_t *enp,
2267 __inout efx_filter_spec_t *spec);
2269 extern __checkReturn efx_rc_t
2271 __in efx_nic_t *enp);
2273 extern __checkReturn efx_rc_t
2274 efx_filter_supported_filters(
2275 __in efx_nic_t *enp,
2276 __out uint32_t *list,
2277 __out size_t *length);
2280 efx_filter_spec_init_rx(
2281 __inout efx_filter_spec_t *spec,
2282 __in efx_filter_priority_t priority,
2283 __in efx_filter_flag_t flags,
2284 __in efx_rxq_t *erp);
2287 efx_filter_spec_init_tx(
2288 __inout efx_filter_spec_t *spec,
2289 __in efx_txq_t *etp);
2291 extern __checkReturn efx_rc_t
2292 efx_filter_spec_set_ipv4_local(
2293 __inout efx_filter_spec_t *spec,
2296 __in uint16_t port);
2298 extern __checkReturn efx_rc_t
2299 efx_filter_spec_set_ipv4_full(
2300 __inout efx_filter_spec_t *spec,
2302 __in uint32_t lhost,
2303 __in uint16_t lport,
2304 __in uint32_t rhost,
2305 __in uint16_t rport);
2307 extern __checkReturn efx_rc_t
2308 efx_filter_spec_set_eth_local(
2309 __inout efx_filter_spec_t *spec,
2311 __in const uint8_t *addr);
2313 extern __checkReturn efx_rc_t
2314 efx_filter_spec_set_uc_def(
2315 __inout efx_filter_spec_t *spec);
2317 extern __checkReturn efx_rc_t
2318 efx_filter_spec_set_mc_def(
2319 __inout efx_filter_spec_t *spec);
2321 #endif /* EFSYS_OPT_FILTER */
2325 extern __checkReturn uint32_t
2327 __in_ecount(count) uint32_t const *input,
2329 __in uint32_t init);
2331 extern __checkReturn uint32_t
2333 __in_ecount(length) uint8_t const *input,
2335 __in uint32_t init);
2342 #endif /* _SYS_EFX_H */