2 * Copyright (c) 2006-2015 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
37 #include "efx_check.h"
38 #include "efx_phy_ids.h"
44 #define EFX_STATIC_ASSERT(_cond) \
45 ((void)sizeof(char[(_cond) ? 1 : -1]))
47 #define EFX_ARRAY_SIZE(_array) \
48 (sizeof(_array) / sizeof((_array)[0]))
50 #define EFX_FIELD_OFFSET(_type, _field) \
51 ((size_t) &(((_type *)0)->_field))
55 typedef __success(return == 0) int efx_rc_t;
60 typedef enum efx_family_e {
62 EFX_FAMILY_FALCON, /* Obsolete and not supported */
64 EFX_FAMILY_HUNTINGTON,
69 extern __checkReturn efx_rc_t
73 __out efx_family_t *efp);
76 #define EFX_PCI_VENID_SFC 0x1924
78 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
80 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
81 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
82 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
84 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
85 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
86 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
88 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
89 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
91 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
92 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
93 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
102 EFX_ERR_BUFID_DC_OOB,
115 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
116 extern __checkReturn uint32_t
118 __in uint32_t crc_init,
119 __in_ecount(length) uint8_t const *input,
123 /* Type prototypes */
125 typedef struct efx_rxq_s efx_rxq_t;
129 typedef struct efx_nic_s efx_nic_t;
131 #define EFX_NIC_FUNC_PRIMARY 0x00000001
132 #define EFX_NIC_FUNC_LINKCTRL 0x00000002
133 #define EFX_NIC_FUNC_TRUSTED 0x00000004
136 extern __checkReturn efx_rc_t
138 __in efx_family_t family,
139 __in efsys_identifier_t *esip,
140 __in efsys_bar_t *esbp,
141 __in efsys_lock_t *eslp,
142 __deref_out efx_nic_t **enpp);
144 extern __checkReturn efx_rc_t
146 __in efx_nic_t *enp);
148 extern __checkReturn efx_rc_t
150 __in efx_nic_t *enp);
152 extern __checkReturn efx_rc_t
154 __in efx_nic_t *enp);
158 extern __checkReturn efx_rc_t
159 efx_nic_register_test(
160 __in efx_nic_t *enp);
162 #endif /* EFSYS_OPT_DIAG */
166 __in efx_nic_t *enp);
170 __in efx_nic_t *enp);
174 __in efx_nic_t *enp);
176 #define EFX_PCIE_LINK_SPEED_GEN1 1
177 #define EFX_PCIE_LINK_SPEED_GEN2 2
178 #define EFX_PCIE_LINK_SPEED_GEN3 3
180 typedef enum efx_pcie_link_performance_e {
181 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
182 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
183 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
184 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
185 } efx_pcie_link_performance_t;
187 extern __checkReturn efx_rc_t
188 efx_nic_calculate_pcie_link_bandwidth(
189 __in uint32_t pcie_link_width,
190 __in uint32_t pcie_link_gen,
191 __out uint32_t *bandwidth_mbpsp);
193 extern __checkReturn efx_rc_t
194 efx_nic_check_pcie_link_speed(
196 __in uint32_t pcie_link_width,
197 __in uint32_t pcie_link_gen,
198 __out efx_pcie_link_performance_t *resultp);
202 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
203 /* Huntington and Medford require MCDIv2 commands */
204 #define WITH_MCDI_V2 1
207 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
209 typedef enum efx_mcdi_exception_e {
210 EFX_MCDI_EXCEPTION_MC_REBOOT,
211 EFX_MCDI_EXCEPTION_MC_BADASSERT,
212 } efx_mcdi_exception_t;
214 #if EFSYS_OPT_MCDI_LOGGING
215 typedef enum efx_log_msg_e
218 EFX_LOG_MCDI_REQUEST,
219 EFX_LOG_MCDI_RESPONSE,
221 #endif /* EFSYS_OPT_MCDI_LOGGING */
223 typedef struct efx_mcdi_transport_s {
225 efsys_mem_t *emt_dma_mem;
226 void (*emt_execute)(void *, efx_mcdi_req_t *);
227 void (*emt_ev_cpl)(void *);
228 void (*emt_exception)(void *, efx_mcdi_exception_t);
229 #if EFSYS_OPT_MCDI_LOGGING
230 void (*emt_logger)(void *, efx_log_msg_t,
231 void *, size_t, void *, size_t);
232 #endif /* EFSYS_OPT_MCDI_LOGGING */
233 #if EFSYS_OPT_MCDI_PROXY_AUTH
234 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
235 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
236 } efx_mcdi_transport_t;
238 extern __checkReturn efx_rc_t
241 __in const efx_mcdi_transport_t *mtp);
243 extern __checkReturn efx_rc_t
245 __in efx_nic_t *enp);
249 __in efx_nic_t *enp);
252 efx_mcdi_request_start(
254 __in efx_mcdi_req_t *emrp,
255 __in boolean_t ev_cpl);
257 extern __checkReturn boolean_t
258 efx_mcdi_request_poll(
259 __in efx_nic_t *enp);
261 extern __checkReturn boolean_t
262 efx_mcdi_request_abort(
263 __in efx_nic_t *enp);
267 __in efx_nic_t *enp);
269 #endif /* EFSYS_OPT_MCDI */
273 #define EFX_NINTR_SIENA 1024
275 typedef enum efx_intr_type_e {
276 EFX_INTR_INVALID = 0,
282 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
284 extern __checkReturn efx_rc_t
287 __in efx_intr_type_t type,
288 __in efsys_mem_t *esmp);
292 __in efx_nic_t *enp);
296 __in efx_nic_t *enp);
299 efx_intr_disable_unlocked(
300 __in efx_nic_t *enp);
302 #define EFX_INTR_NEVQS 32
304 extern __checkReturn efx_rc_t
307 __in unsigned int level);
310 efx_intr_status_line(
312 __out boolean_t *fatalp,
313 __out uint32_t *maskp);
316 efx_intr_status_message(
318 __in unsigned int message,
319 __out boolean_t *fatalp);
323 __in efx_nic_t *enp);
327 __in efx_nic_t *enp);
331 #if EFSYS_OPT_MAC_STATS
333 /* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */
334 typedef enum efx_mac_stat_e {
337 EFX_MAC_RX_UNICST_PKTS,
338 EFX_MAC_RX_MULTICST_PKTS,
339 EFX_MAC_RX_BRDCST_PKTS,
340 EFX_MAC_RX_PAUSE_PKTS,
341 EFX_MAC_RX_LE_64_PKTS,
342 EFX_MAC_RX_65_TO_127_PKTS,
343 EFX_MAC_RX_128_TO_255_PKTS,
344 EFX_MAC_RX_256_TO_511_PKTS,
345 EFX_MAC_RX_512_TO_1023_PKTS,
346 EFX_MAC_RX_1024_TO_15XX_PKTS,
347 EFX_MAC_RX_GE_15XX_PKTS,
349 EFX_MAC_RX_FCS_ERRORS,
350 EFX_MAC_RX_DROP_EVENTS,
351 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
352 EFX_MAC_RX_SYMBOL_ERRORS,
353 EFX_MAC_RX_ALIGN_ERRORS,
354 EFX_MAC_RX_INTERNAL_ERRORS,
355 EFX_MAC_RX_JABBER_PKTS,
356 EFX_MAC_RX_LANE0_CHAR_ERR,
357 EFX_MAC_RX_LANE1_CHAR_ERR,
358 EFX_MAC_RX_LANE2_CHAR_ERR,
359 EFX_MAC_RX_LANE3_CHAR_ERR,
360 EFX_MAC_RX_LANE0_DISP_ERR,
361 EFX_MAC_RX_LANE1_DISP_ERR,
362 EFX_MAC_RX_LANE2_DISP_ERR,
363 EFX_MAC_RX_LANE3_DISP_ERR,
364 EFX_MAC_RX_MATCH_FAULT,
365 EFX_MAC_RX_NODESC_DROP_CNT,
368 EFX_MAC_TX_UNICST_PKTS,
369 EFX_MAC_TX_MULTICST_PKTS,
370 EFX_MAC_TX_BRDCST_PKTS,
371 EFX_MAC_TX_PAUSE_PKTS,
372 EFX_MAC_TX_LE_64_PKTS,
373 EFX_MAC_TX_65_TO_127_PKTS,
374 EFX_MAC_TX_128_TO_255_PKTS,
375 EFX_MAC_TX_256_TO_511_PKTS,
376 EFX_MAC_TX_512_TO_1023_PKTS,
377 EFX_MAC_TX_1024_TO_15XX_PKTS,
378 EFX_MAC_TX_GE_15XX_PKTS,
380 EFX_MAC_TX_SGL_COL_PKTS,
381 EFX_MAC_TX_MULT_COL_PKTS,
382 EFX_MAC_TX_EX_COL_PKTS,
383 EFX_MAC_TX_LATE_COL_PKTS,
385 EFX_MAC_TX_EX_DEF_PKTS,
386 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
387 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
388 EFX_MAC_PM_TRUNC_VFIFO_FULL,
389 EFX_MAC_PM_DISCARD_VFIFO_FULL,
390 EFX_MAC_PM_TRUNC_QBB,
391 EFX_MAC_PM_DISCARD_QBB,
392 EFX_MAC_PM_DISCARD_MAPPING,
393 EFX_MAC_RXDP_Q_DISABLED_PKTS,
394 EFX_MAC_RXDP_DI_DROPPED_PKTS,
395 EFX_MAC_RXDP_STREAMING_PKTS,
396 EFX_MAC_RXDP_HLB_FETCH,
397 EFX_MAC_RXDP_HLB_WAIT,
398 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
399 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
400 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
401 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
402 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
403 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
404 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
405 EFX_MAC_VADAPTER_RX_BAD_BYTES,
406 EFX_MAC_VADAPTER_RX_OVERFLOW,
407 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
408 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
409 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
410 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
411 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
412 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
413 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
414 EFX_MAC_VADAPTER_TX_BAD_BYTES,
415 EFX_MAC_VADAPTER_TX_OVERFLOW,
419 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
421 #endif /* EFSYS_OPT_MAC_STATS */
423 typedef enum efx_link_mode_e {
424 EFX_LINK_UNKNOWN = 0,
437 #define EFX_MAC_ADDR_LEN 6
439 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t*)_address)[0] & 0x01)
441 #define EFX_MAC_MULTICAST_LIST_MAX 256
443 #define EFX_MAC_SDU_MAX 9202
445 #define EFX_MAC_PDU(_sdu) \
450 + /* bug16011 */ 16), \
453 #define EFX_MAC_PDU_MIN 60
454 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
456 extern __checkReturn efx_rc_t
461 extern __checkReturn efx_rc_t
466 extern __checkReturn efx_rc_t
469 __in boolean_t all_unicst,
470 __in boolean_t mulcst,
471 __in boolean_t all_mulcst,
472 __in boolean_t brdcst);
474 extern __checkReturn efx_rc_t
475 efx_mac_multicast_list_set(
477 __in_ecount(6*count) uint8_t const *addrs,
480 extern __checkReturn efx_rc_t
481 efx_mac_filter_default_rxq_set(
484 __in boolean_t using_rss);
487 efx_mac_filter_default_rxq_clear(
488 __in efx_nic_t *enp);
490 extern __checkReturn efx_rc_t
493 __in boolean_t enabled);
495 extern __checkReturn efx_rc_t
498 __out boolean_t *mac_upp);
500 #define EFX_FCNTL_RESPOND 0x00000001
501 #define EFX_FCNTL_GENERATE 0x00000002
503 extern __checkReturn efx_rc_t
506 __in unsigned int fcntl,
507 __in boolean_t autoneg);
512 __out unsigned int *fcntl_wantedp,
513 __out unsigned int *fcntl_linkp);
516 #if EFSYS_OPT_MAC_STATS
520 extern __checkReturn const char *
523 __in unsigned int id);
525 #endif /* EFSYS_OPT_NAMES */
527 #define EFX_MAC_STATS_SIZE 0x400
530 * Upload mac statistics supported by the hardware into the given buffer.
532 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes,
535 * The hardware will only DMA statistics that it understands (of course).
536 * Drivers should not make any assumptions about which statistics are
537 * supported, especially when the statistics are generated by firmware.
539 * Thus, drivers should zero this buffer before use, so that not-understood
540 * statistics read back as zero.
542 extern __checkReturn efx_rc_t
543 efx_mac_stats_upload(
545 __in efsys_mem_t *esmp);
547 extern __checkReturn efx_rc_t
548 efx_mac_stats_periodic(
550 __in efsys_mem_t *esmp,
551 __in uint16_t period_ms,
552 __in boolean_t events);
554 extern __checkReturn efx_rc_t
555 efx_mac_stats_update(
557 __in efsys_mem_t *esmp,
558 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
559 __inout_opt uint32_t *generationp);
561 #endif /* EFSYS_OPT_MAC_STATS */
565 typedef enum efx_mon_type_e {
577 __in efx_nic_t *enp);
579 #endif /* EFSYS_OPT_NAMES */
581 extern __checkReturn efx_rc_t
583 __in efx_nic_t *enp);
585 #if EFSYS_OPT_MON_STATS
587 #define EFX_MON_STATS_PAGE_SIZE 0x100
588 #define EFX_MON_MASK_ELEMENT_SIZE 32
590 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 5d4ee5185e419abe */
591 typedef enum efx_mon_stat_e {
598 EFX_MON_STAT_EXT_TEMP,
599 EFX_MON_STAT_INT_TEMP,
602 EFX_MON_STAT_INT_COOLING,
603 EFX_MON_STAT_EXT_COOLING,
611 EFX_MON_STAT_AOE_TEMP,
612 EFX_MON_STAT_PSU_AOE_TEMP,
613 EFX_MON_STAT_PSU_TEMP,
619 EFX_MON_STAT_VAOE_IN,
621 EFX_MON_STAT_IAOE_IN,
622 EFX_MON_STAT_NIC_POWER,
626 EFX_MON_STAT_0_9V_ADC,
627 EFX_MON_STAT_INT_TEMP2,
628 EFX_MON_STAT_VREG_TEMP,
629 EFX_MON_STAT_VREG_0_9V_TEMP,
630 EFX_MON_STAT_VREG_1_2V_TEMP,
631 EFX_MON_STAT_INT_VPTAT,
632 EFX_MON_STAT_INT_ADC_TEMP,
633 EFX_MON_STAT_EXT_VPTAT,
634 EFX_MON_STAT_EXT_ADC_TEMP,
635 EFX_MON_STAT_AMBIENT_TEMP,
636 EFX_MON_STAT_AIRFLOW,
637 EFX_MON_STAT_VDD08D_VSS08D_CSR,
638 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
639 EFX_MON_STAT_HOTPOINT_TEMP,
640 EFX_MON_STAT_PHY_POWER_SWITCH_PORT0,
641 EFX_MON_STAT_PHY_POWER_SWITCH_PORT1,
642 EFX_MON_STAT_MUM_VCC,
645 EFX_MON_STAT_0V9_A_TEMP,
648 EFX_MON_STAT_0V9_B_TEMP,
649 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
650 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,
651 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
652 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,
653 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
654 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
655 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,
656 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,
657 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
658 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
659 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,
660 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,
661 EFX_MON_STAT_SODIMM_VOUT,
662 EFX_MON_STAT_SODIMM_0_TEMP,
663 EFX_MON_STAT_SODIMM_1_TEMP,
664 EFX_MON_STAT_PHY0_VCC,
665 EFX_MON_STAT_PHY1_VCC,
666 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
667 EFX_MON_STAT_BOARD_FRONT_TEMP,
668 EFX_MON_STAT_BOARD_BACK_TEMP,
672 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
674 typedef enum efx_mon_stat_state_e {
675 EFX_MON_STAT_STATE_OK = 0,
676 EFX_MON_STAT_STATE_WARNING = 1,
677 EFX_MON_STAT_STATE_FATAL = 2,
678 EFX_MON_STAT_STATE_BROKEN = 3,
679 EFX_MON_STAT_STATE_NO_READING = 4,
680 } efx_mon_stat_state_t;
682 typedef struct efx_mon_stat_value_s {
685 } efx_mon_stat_value_t;
692 __in efx_mon_stat_t id);
694 #endif /* EFSYS_OPT_NAMES */
696 extern __checkReturn efx_rc_t
697 efx_mon_stats_update(
699 __in efsys_mem_t *esmp,
700 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
702 #endif /* EFSYS_OPT_MON_STATS */
706 __in efx_nic_t *enp);
710 extern __checkReturn efx_rc_t
712 __in efx_nic_t *enp);
714 #if EFSYS_OPT_PHY_LED_CONTROL
716 typedef enum efx_phy_led_mode_e {
717 EFX_PHY_LED_DEFAULT = 0,
722 } efx_phy_led_mode_t;
724 extern __checkReturn efx_rc_t
727 __in efx_phy_led_mode_t mode);
729 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
731 extern __checkReturn efx_rc_t
733 __in efx_nic_t *enp);
735 #if EFSYS_OPT_LOOPBACK
737 typedef enum efx_loopback_type_e {
738 EFX_LOOPBACK_OFF = 0,
739 EFX_LOOPBACK_DATA = 1,
740 EFX_LOOPBACK_GMAC = 2,
741 EFX_LOOPBACK_XGMII = 3,
742 EFX_LOOPBACK_XGXS = 4,
743 EFX_LOOPBACK_XAUI = 5,
744 EFX_LOOPBACK_GMII = 6,
745 EFX_LOOPBACK_SGMII = 7,
746 EFX_LOOPBACK_XGBR = 8,
747 EFX_LOOPBACK_XFI = 9,
748 EFX_LOOPBACK_XAUI_FAR = 10,
749 EFX_LOOPBACK_GMII_FAR = 11,
750 EFX_LOOPBACK_SGMII_FAR = 12,
751 EFX_LOOPBACK_XFI_FAR = 13,
752 EFX_LOOPBACK_GPHY = 14,
753 EFX_LOOPBACK_PHY_XS = 15,
754 EFX_LOOPBACK_PCS = 16,
755 EFX_LOOPBACK_PMA_PMD = 17,
756 EFX_LOOPBACK_XPORT = 18,
757 EFX_LOOPBACK_XGMII_WS = 19,
758 EFX_LOOPBACK_XAUI_WS = 20,
759 EFX_LOOPBACK_XAUI_WS_FAR = 21,
760 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
761 EFX_LOOPBACK_GMII_WS = 23,
762 EFX_LOOPBACK_XFI_WS = 24,
763 EFX_LOOPBACK_XFI_WS_FAR = 25,
764 EFX_LOOPBACK_PHYXS_WS = 26,
765 EFX_LOOPBACK_PMA_INT = 27,
766 EFX_LOOPBACK_SD_NEAR = 28,
767 EFX_LOOPBACK_SD_FAR = 29,
768 EFX_LOOPBACK_PMA_INT_WS = 30,
769 EFX_LOOPBACK_SD_FEP2_WS = 31,
770 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
771 EFX_LOOPBACK_SD_FEP_WS = 33,
772 EFX_LOOPBACK_SD_FES_WS = 34,
774 } efx_loopback_type_t;
776 typedef enum efx_loopback_kind_e {
777 EFX_LOOPBACK_KIND_OFF = 0,
778 EFX_LOOPBACK_KIND_ALL,
779 EFX_LOOPBACK_KIND_MAC,
780 EFX_LOOPBACK_KIND_PHY,
782 } efx_loopback_kind_t;
786 __in efx_loopback_kind_t loopback_kind,
787 __out efx_qword_t *maskp);
789 extern __checkReturn efx_rc_t
790 efx_port_loopback_set(
792 __in efx_link_mode_t link_mode,
793 __in efx_loopback_type_t type);
797 extern __checkReturn const char *
798 efx_loopback_type_name(
800 __in efx_loopback_type_t type);
802 #endif /* EFSYS_OPT_NAMES */
804 #endif /* EFSYS_OPT_LOOPBACK */
806 extern __checkReturn efx_rc_t
809 __out_opt efx_link_mode_t *link_modep);
813 __in efx_nic_t *enp);
815 typedef enum efx_phy_cap_type_e {
816 EFX_PHY_CAP_INVALID = 0,
823 EFX_PHY_CAP_10000FDX,
827 EFX_PHY_CAP_40000FDX,
829 } efx_phy_cap_type_t;
832 #define EFX_PHY_CAP_CURRENT 0x00000000
833 #define EFX_PHY_CAP_DEFAULT 0x00000001
834 #define EFX_PHY_CAP_PERM 0x00000002
840 __out uint32_t *maskp);
842 extern __checkReturn efx_rc_t
850 __out uint32_t *maskp);
852 extern __checkReturn efx_rc_t
855 __out uint32_t *ouip);
857 typedef enum efx_phy_media_type_e {
858 EFX_PHY_MEDIA_INVALID = 0,
863 EFX_PHY_MEDIA_SFP_PLUS,
864 EFX_PHY_MEDIA_BASE_T,
865 EFX_PHY_MEDIA_QSFP_PLUS,
867 } efx_phy_media_type_t;
869 /* Get the type of medium currently used. If the board has ports for
870 * modules, a module is present, and we recognise the media type of
871 * the module, then this will be the media type of the module.
872 * Otherwise it will be the media type of the port.
875 efx_phy_media_type_get(
877 __out efx_phy_media_type_t *typep);
880 efx_phy_module_get_info(
882 __in uint8_t dev_addr,
885 __out_bcount(len) uint8_t *data);
887 #if EFSYS_OPT_PHY_STATS
889 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
890 typedef enum efx_phy_stat_e {
892 EFX_PHY_STAT_PMA_PMD_LINK_UP,
893 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
894 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
895 EFX_PHY_STAT_PMA_PMD_REV_A,
896 EFX_PHY_STAT_PMA_PMD_REV_B,
897 EFX_PHY_STAT_PMA_PMD_REV_C,
898 EFX_PHY_STAT_PMA_PMD_REV_D,
899 EFX_PHY_STAT_PCS_LINK_UP,
900 EFX_PHY_STAT_PCS_RX_FAULT,
901 EFX_PHY_STAT_PCS_TX_FAULT,
902 EFX_PHY_STAT_PCS_BER,
903 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
904 EFX_PHY_STAT_PHY_XS_LINK_UP,
905 EFX_PHY_STAT_PHY_XS_RX_FAULT,
906 EFX_PHY_STAT_PHY_XS_TX_FAULT,
907 EFX_PHY_STAT_PHY_XS_ALIGN,
908 EFX_PHY_STAT_PHY_XS_SYNC_A,
909 EFX_PHY_STAT_PHY_XS_SYNC_B,
910 EFX_PHY_STAT_PHY_XS_SYNC_C,
911 EFX_PHY_STAT_PHY_XS_SYNC_D,
912 EFX_PHY_STAT_AN_LINK_UP,
913 EFX_PHY_STAT_AN_MASTER,
914 EFX_PHY_STAT_AN_LOCAL_RX_OK,
915 EFX_PHY_STAT_AN_REMOTE_RX_OK,
916 EFX_PHY_STAT_CL22EXT_LINK_UP,
921 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
922 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
923 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
924 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
925 EFX_PHY_STAT_AN_COMPLETE,
926 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
927 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
928 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
929 EFX_PHY_STAT_PCS_FW_VERSION_0,
930 EFX_PHY_STAT_PCS_FW_VERSION_1,
931 EFX_PHY_STAT_PCS_FW_VERSION_2,
932 EFX_PHY_STAT_PCS_FW_VERSION_3,
933 EFX_PHY_STAT_PCS_FW_BUILD_YY,
934 EFX_PHY_STAT_PCS_FW_BUILD_MM,
935 EFX_PHY_STAT_PCS_FW_BUILD_DD,
936 EFX_PHY_STAT_PCS_OP_MODE,
940 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
947 __in efx_phy_stat_t stat);
949 #endif /* EFSYS_OPT_NAMES */
951 #define EFX_PHY_STATS_SIZE 0x100
953 extern __checkReturn efx_rc_t
954 efx_phy_stats_update(
956 __in efsys_mem_t *esmp,
957 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
959 #endif /* EFSYS_OPT_PHY_STATS */
964 typedef enum efx_bist_type_e {
965 EFX_BIST_TYPE_UNKNOWN,
966 EFX_BIST_TYPE_PHY_NORMAL,
967 EFX_BIST_TYPE_PHY_CABLE_SHORT,
968 EFX_BIST_TYPE_PHY_CABLE_LONG,
969 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
970 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus*/
971 EFX_BIST_TYPE_REG, /* Test the register memories */
972 EFX_BIST_TYPE_NTYPES,
975 typedef enum efx_bist_result_e {
976 EFX_BIST_RESULT_UNKNOWN,
977 EFX_BIST_RESULT_RUNNING,
978 EFX_BIST_RESULT_PASSED,
979 EFX_BIST_RESULT_FAILED,
982 typedef enum efx_phy_cable_status_e {
983 EFX_PHY_CABLE_STATUS_OK,
984 EFX_PHY_CABLE_STATUS_INVALID,
985 EFX_PHY_CABLE_STATUS_OPEN,
986 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
987 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
988 EFX_PHY_CABLE_STATUS_BUSY,
989 } efx_phy_cable_status_t;
991 typedef enum efx_bist_value_e {
992 EFX_BIST_PHY_CABLE_LENGTH_A,
993 EFX_BIST_PHY_CABLE_LENGTH_B,
994 EFX_BIST_PHY_CABLE_LENGTH_C,
995 EFX_BIST_PHY_CABLE_LENGTH_D,
996 EFX_BIST_PHY_CABLE_STATUS_A,
997 EFX_BIST_PHY_CABLE_STATUS_B,
998 EFX_BIST_PHY_CABLE_STATUS_C,
999 EFX_BIST_PHY_CABLE_STATUS_D,
1000 EFX_BIST_FAULT_CODE,
1001 /* Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1006 EFX_BIST_MEM_EXPECT,
1007 EFX_BIST_MEM_ACTUAL,
1009 EFX_BIST_MEM_ECC_PARITY,
1010 EFX_BIST_MEM_ECC_FATAL,
1014 extern __checkReturn efx_rc_t
1015 efx_bist_enable_offline(
1016 __in efx_nic_t *enp);
1018 extern __checkReturn efx_rc_t
1020 __in efx_nic_t *enp,
1021 __in efx_bist_type_t type);
1023 extern __checkReturn efx_rc_t
1025 __in efx_nic_t *enp,
1026 __in efx_bist_type_t type,
1027 __out efx_bist_result_t *resultp,
1028 __out_opt uint32_t *value_maskp,
1029 __out_ecount_opt(count) unsigned long *valuesp,
1034 __in efx_nic_t *enp,
1035 __in efx_bist_type_t type);
1037 #endif /* EFSYS_OPT_BIST */
1039 #define EFX_FEATURE_IPV6 0x00000001
1040 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1041 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1042 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1043 #define EFX_FEATURE_WOL 0x00000010
1044 #define EFX_FEATURE_MCDI 0x00000020
1045 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1046 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1047 #define EFX_FEATURE_TURBO 0x00000100
1048 #define EFX_FEATURE_MCDI_DMA 0x00000200
1049 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1050 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1051 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1052 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1054 typedef struct efx_nic_cfg_s {
1055 uint32_t enc_board_type;
1056 uint32_t enc_phy_type;
1058 char enc_phy_name[21];
1060 char enc_phy_revision[21];
1061 efx_mon_type_t enc_mon_type;
1062 #if EFSYS_OPT_MON_STATS
1063 uint32_t enc_mon_stat_dma_buf_size;
1064 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1066 unsigned int enc_features;
1067 uint8_t enc_mac_addr[6];
1068 uint8_t enc_port; /* PHY port number */
1069 uint32_t enc_func_flags;
1070 uint32_t enc_intr_vec_base;
1071 uint32_t enc_intr_limit;
1072 uint32_t enc_evq_limit;
1073 uint32_t enc_txq_limit;
1074 uint32_t enc_rxq_limit;
1075 uint32_t enc_buftbl_limit;
1076 uint32_t enc_piobuf_limit;
1077 uint32_t enc_piobuf_size;
1078 uint32_t enc_piobuf_min_alloc_size;
1079 uint32_t enc_evq_timer_quantum_ns;
1080 uint32_t enc_evq_timer_max_us;
1081 uint32_t enc_clk_mult;
1082 uint32_t enc_rx_prefix_size;
1083 uint32_t enc_rx_buf_align_start;
1084 uint32_t enc_rx_buf_align_end;
1085 #if EFSYS_OPT_LOOPBACK
1086 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1087 #endif /* EFSYS_OPT_LOOPBACK */
1088 #if EFSYS_OPT_PHY_FLAGS
1089 uint32_t enc_phy_flags_mask;
1090 #endif /* EFSYS_OPT_PHY_FLAGS */
1091 #if EFSYS_OPT_PHY_LED_CONTROL
1092 uint32_t enc_led_mask;
1093 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1094 #if EFSYS_OPT_PHY_STATS
1095 uint64_t enc_phy_stat_mask;
1096 #endif /* EFSYS_OPT_PHY_STATS */
1098 uint8_t enc_mcdi_mdio_channel;
1099 #if EFSYS_OPT_PHY_STATS
1100 uint32_t enc_mcdi_phy_stat_mask;
1101 #endif /* EFSYS_OPT_PHY_STATS */
1102 #endif /* EFSYS_OPT_SIENA */
1103 #if (EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
1104 #if EFSYS_OPT_MON_STATS
1105 uint32_t *enc_mcdi_sensor_maskp;
1106 uint32_t enc_mcdi_sensor_mask_size;
1107 #endif /* EFSYS_OPT_MON_STATS */
1108 #endif /* (EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
1110 uint32_t enc_bist_mask;
1111 #endif /* EFSYS_OPT_BIST */
1112 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
1115 uint32_t enc_privilege_mask;
1116 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
1117 boolean_t enc_bug26807_workaround;
1118 boolean_t enc_bug35388_workaround;
1119 boolean_t enc_bug41750_workaround;
1120 boolean_t enc_rx_batching_enabled;
1121 /* Maximum number of descriptors completed in an rx event. */
1122 uint32_t enc_rx_batch_max;
1123 /* Number of rx descriptors the hardware requires for a push. */
1124 uint32_t enc_rx_push_align;
1126 * Maximum number of bytes into the packet the TCP header can start for
1127 * the hardware to apply TSO packet edits.
1129 uint32_t enc_tx_tso_tcp_header_offset_limit;
1130 boolean_t enc_fw_assisted_tso_enabled;
1131 boolean_t enc_fw_assisted_tso_v2_enabled;
1132 boolean_t enc_hw_tx_insert_vlan_enabled;
1133 /* Datapath firmware vadapter/vport/vswitch support */
1134 boolean_t enc_datapath_cap_evb;
1135 boolean_t enc_rx_disable_scatter_supported;
1136 boolean_t enc_allow_set_mac_with_installed_filters;
1137 boolean_t enc_enhanced_set_mac_supported;
1138 /* External port identifier */
1139 uint8_t enc_external_port;
1140 uint32_t enc_mcdi_max_payload_length;
1141 /* VPD may be per-PF or global */
1142 boolean_t enc_vpd_is_global;
1143 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1144 uint32_t enc_required_pcie_bandwidth_mbps;
1145 uint32_t enc_max_pcie_link_gen;
1148 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1149 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1151 #define EFX_PCI_FUNCTION(_encp) \
1152 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1154 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1156 extern const efx_nic_cfg_t *
1158 __in efx_nic_t *enp);
1160 /* Driver resource limits (minimum required/maximum usable). */
1161 typedef struct efx_drv_limits_s
1163 uint32_t edl_min_evq_count;
1164 uint32_t edl_max_evq_count;
1166 uint32_t edl_min_rxq_count;
1167 uint32_t edl_max_rxq_count;
1169 uint32_t edl_min_txq_count;
1170 uint32_t edl_max_txq_count;
1172 /* PIO blocks (sub-allocated from piobuf) */
1173 uint32_t edl_min_pio_alloc_size;
1174 uint32_t edl_max_pio_alloc_count;
1177 extern __checkReturn efx_rc_t
1178 efx_nic_set_drv_limits(
1179 __inout efx_nic_t *enp,
1180 __in efx_drv_limits_t *edlp);
1182 typedef enum efx_nic_region_e {
1183 EFX_REGION_VI, /* Memory BAR UC mapping */
1184 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1187 extern __checkReturn efx_rc_t
1188 efx_nic_get_bar_region(
1189 __in efx_nic_t *enp,
1190 __in efx_nic_region_t region,
1191 __out uint32_t *offsetp,
1192 __out size_t *sizep);
1194 extern __checkReturn efx_rc_t
1195 efx_nic_get_vi_pool(
1196 __in efx_nic_t *enp,
1197 __out uint32_t *evq_countp,
1198 __out uint32_t *rxq_countp,
1199 __out uint32_t *txq_countp);
1204 typedef enum efx_vpd_tag_e {
1211 typedef uint16_t efx_vpd_keyword_t;
1213 typedef struct efx_vpd_value_s {
1214 efx_vpd_tag_t evv_tag;
1215 efx_vpd_keyword_t evv_keyword;
1217 uint8_t evv_value[0x100];
1221 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1223 extern __checkReturn efx_rc_t
1225 __in efx_nic_t *enp);
1227 extern __checkReturn efx_rc_t
1229 __in efx_nic_t *enp,
1230 __out size_t *sizep);
1232 extern __checkReturn efx_rc_t
1234 __in efx_nic_t *enp,
1235 __out_bcount(size) caddr_t data,
1238 extern __checkReturn efx_rc_t
1240 __in efx_nic_t *enp,
1241 __in_bcount(size) caddr_t data,
1244 extern __checkReturn efx_rc_t
1246 __in efx_nic_t *enp,
1247 __in_bcount(size) caddr_t data,
1250 extern __checkReturn efx_rc_t
1252 __in efx_nic_t *enp,
1253 __in_bcount(size) caddr_t data,
1255 __inout efx_vpd_value_t *evvp);
1257 extern __checkReturn efx_rc_t
1259 __in efx_nic_t *enp,
1260 __inout_bcount(size) caddr_t data,
1262 __in efx_vpd_value_t *evvp);
1264 extern __checkReturn efx_rc_t
1266 __in efx_nic_t *enp,
1267 __inout_bcount(size) caddr_t data,
1269 __out efx_vpd_value_t *evvp,
1270 __inout unsigned int *contp);
1272 extern __checkReturn efx_rc_t
1274 __in efx_nic_t *enp,
1275 __in_bcount(size) caddr_t data,
1280 __in efx_nic_t *enp);
1282 #endif /* EFSYS_OPT_VPD */
1288 typedef enum efx_nvram_type_e {
1289 EFX_NVRAM_INVALID = 0,
1291 EFX_NVRAM_BOOTROM_CFG,
1292 EFX_NVRAM_MC_FIRMWARE,
1293 EFX_NVRAM_MC_GOLDEN,
1299 EFX_NVRAM_FPGA_BACKUP,
1300 EFX_NVRAM_DYNAMIC_CFG,
1305 extern __checkReturn efx_rc_t
1307 __in efx_nic_t *enp);
1311 extern __checkReturn efx_rc_t
1313 __in efx_nic_t *enp);
1315 #endif /* EFSYS_OPT_DIAG */
1317 extern __checkReturn efx_rc_t
1319 __in efx_nic_t *enp,
1320 __in efx_nvram_type_t type,
1321 __out size_t *sizep);
1323 extern __checkReturn efx_rc_t
1325 __in efx_nic_t *enp,
1326 __in efx_nvram_type_t type,
1327 __out_opt size_t *pref_chunkp);
1330 efx_nvram_rw_finish(
1331 __in efx_nic_t *enp,
1332 __in efx_nvram_type_t type);
1334 extern __checkReturn efx_rc_t
1335 efx_nvram_get_version(
1336 __in efx_nic_t *enp,
1337 __in efx_nvram_type_t type,
1338 __out uint32_t *subtypep,
1339 __out_ecount(4) uint16_t version[4]);
1341 extern __checkReturn efx_rc_t
1342 efx_nvram_read_chunk(
1343 __in efx_nic_t *enp,
1344 __in efx_nvram_type_t type,
1345 __in unsigned int offset,
1346 __out_bcount(size) caddr_t data,
1349 extern __checkReturn efx_rc_t
1350 efx_nvram_set_version(
1351 __in efx_nic_t *enp,
1352 __in efx_nvram_type_t type,
1353 __in_ecount(4) uint16_t version[4]);
1355 extern __checkReturn efx_rc_t
1357 __in efx_nic_t *enp,
1358 __in efx_nvram_type_t type,
1359 __in_bcount(partn_size) caddr_t partn_data,
1360 __in size_t partn_size);
1362 extern __checkReturn efx_rc_t
1364 __in efx_nic_t *enp,
1365 __in efx_nvram_type_t type);
1367 extern __checkReturn efx_rc_t
1368 efx_nvram_write_chunk(
1369 __in efx_nic_t *enp,
1370 __in efx_nvram_type_t type,
1371 __in unsigned int offset,
1372 __in_bcount(size) caddr_t data,
1377 __in efx_nic_t *enp);
1379 #endif /* EFSYS_OPT_NVRAM */
1381 #if EFSYS_OPT_BOOTCFG
1385 __in efx_nic_t *enp,
1386 __out_bcount(size) caddr_t data,
1391 __in efx_nic_t *enp,
1392 __in_bcount(size) caddr_t data,
1395 #endif /* EFSYS_OPT_BOOTCFG */
1399 typedef enum efx_wol_type_e {
1400 EFX_WOL_TYPE_INVALID,
1402 EFX_WOL_TYPE_BITMAP,
1407 typedef enum efx_lightsout_offload_type_e {
1408 EFX_LIGHTSOUT_OFFLOAD_TYPE_INVALID,
1409 EFX_LIGHTSOUT_OFFLOAD_TYPE_ARP,
1410 EFX_LIGHTSOUT_OFFLOAD_TYPE_NS,
1411 } efx_lightsout_offload_type_t;
1413 #define EFX_WOL_BITMAP_MASK_SIZE (48)
1414 #define EFX_WOL_BITMAP_VALUE_SIZE (128)
1416 typedef union efx_wol_param_u {
1418 uint8_t mac_addr[6];
1421 uint8_t mask[EFX_WOL_BITMAP_MASK_SIZE]; /* 1 bit per byte */
1422 uint8_t value[EFX_WOL_BITMAP_VALUE_SIZE]; /* value to match */
1427 typedef union efx_lightsout_offload_param_u {
1429 uint8_t mac_addr[6];
1433 uint8_t mac_addr[6];
1434 uint32_t solicited_node[4];
1437 } efx_lightsout_offload_param_t;
1439 extern __checkReturn efx_rc_t
1441 __in efx_nic_t *enp);
1443 extern __checkReturn efx_rc_t
1444 efx_wol_filter_clear(
1445 __in efx_nic_t *enp);
1447 extern __checkReturn efx_rc_t
1449 __in efx_nic_t *enp,
1450 __in efx_wol_type_t type,
1451 __in efx_wol_param_t *paramp,
1452 __out uint32_t *filter_idp);
1454 extern __checkReturn efx_rc_t
1455 efx_wol_filter_remove(
1456 __in efx_nic_t *enp,
1457 __in uint32_t filter_id);
1459 extern __checkReturn efx_rc_t
1460 efx_lightsout_offload_add(
1461 __in efx_nic_t *enp,
1462 __in efx_lightsout_offload_type_t type,
1463 __in efx_lightsout_offload_param_t *paramp,
1464 __out uint32_t *filter_idp);
1466 extern __checkReturn efx_rc_t
1467 efx_lightsout_offload_remove(
1468 __in efx_nic_t *enp,
1469 __in efx_lightsout_offload_type_t type,
1470 __in uint32_t filter_id);
1474 __in efx_nic_t *enp);
1476 #endif /* EFSYS_OPT_WOL */
1480 typedef enum efx_pattern_type_t {
1481 EFX_PATTERN_BYTE_INCREMENT = 0,
1482 EFX_PATTERN_ALL_THE_SAME,
1483 EFX_PATTERN_BIT_ALTERNATE,
1484 EFX_PATTERN_BYTE_ALTERNATE,
1485 EFX_PATTERN_BYTE_CHANGING,
1486 EFX_PATTERN_BIT_SWEEP,
1488 } efx_pattern_type_t;
1491 (*efx_sram_pattern_fn_t)(
1493 __in boolean_t negate,
1494 __out efx_qword_t *eqp);
1496 extern __checkReturn efx_rc_t
1498 __in efx_nic_t *enp,
1499 __in efx_pattern_type_t type);
1501 #endif /* EFSYS_OPT_DIAG */
1503 extern __checkReturn efx_rc_t
1504 efx_sram_buf_tbl_set(
1505 __in efx_nic_t *enp,
1507 __in efsys_mem_t *esmp,
1511 efx_sram_buf_tbl_clear(
1512 __in efx_nic_t *enp,
1516 #define EFX_BUF_TBL_SIZE 0x20000
1518 #define EFX_BUF_SIZE 4096
1522 typedef struct efx_evq_s efx_evq_t;
1524 #if EFSYS_OPT_QSTATS
1526 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1527 typedef enum efx_ev_qstat_e {
1533 EV_RX_PAUSE_FRM_ERR,
1534 EV_RX_BUF_OWNER_ID_ERR,
1535 EV_RX_IPV4_HDR_CHKSUM_ERR,
1536 EV_RX_TCP_UDP_CHKSUM_ERR,
1540 EV_RX_MCAST_HASH_MATCH,
1557 EV_DRIVER_SRM_UPD_DONE,
1558 EV_DRIVER_TX_DESCQ_FLS_DONE,
1559 EV_DRIVER_RX_DESCQ_FLS_DONE,
1560 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1561 EV_DRIVER_RX_DSC_ERROR,
1562 EV_DRIVER_TX_DSC_ERROR,
1568 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1570 #endif /* EFSYS_OPT_QSTATS */
1572 extern __checkReturn efx_rc_t
1574 __in efx_nic_t *enp);
1578 __in efx_nic_t *enp);
1580 #define EFX_EVQ_MAXNEVS 32768
1581 #define EFX_EVQ_MINNEVS 512
1583 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
1584 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1586 extern __checkReturn efx_rc_t
1588 __in efx_nic_t *enp,
1589 __in unsigned int index,
1590 __in efsys_mem_t *esmp,
1593 __deref_out efx_evq_t **eepp);
1597 __in efx_evq_t *eep,
1598 __in uint16_t data);
1600 typedef __checkReturn boolean_t
1601 (*efx_initialized_ev_t)(
1602 __in_opt void *arg);
1604 #define EFX_PKT_UNICAST 0x0004
1605 #define EFX_PKT_START 0x0008
1607 #define EFX_PKT_VLAN_TAGGED 0x0010
1608 #define EFX_CKSUM_TCPUDP 0x0020
1609 #define EFX_CKSUM_IPV4 0x0040
1610 #define EFX_PKT_CONT 0x0080
1612 #define EFX_CHECK_VLAN 0x0100
1613 #define EFX_PKT_TCP 0x0200
1614 #define EFX_PKT_UDP 0x0400
1615 #define EFX_PKT_IPV4 0x0800
1617 #define EFX_PKT_IPV6 0x1000
1618 #define EFX_PKT_PREFIX_LEN 0x2000
1619 #define EFX_ADDR_MISMATCH 0x4000
1620 #define EFX_DISCARD 0x8000
1622 #define EFX_EV_RX_NLABELS 32
1623 #define EFX_EV_TX_NLABELS 32
1625 typedef __checkReturn boolean_t
1628 __in uint32_t label,
1631 __in uint16_t flags);
1633 typedef __checkReturn boolean_t
1636 __in uint32_t label,
1639 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
1640 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
1641 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
1642 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
1643 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
1644 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
1645 #define EFX_EXCEPTION_RX_ERROR 0x00000007
1646 #define EFX_EXCEPTION_TX_ERROR 0x00000008
1647 #define EFX_EXCEPTION_EV_ERROR 0x00000009
1649 typedef __checkReturn boolean_t
1650 (*efx_exception_ev_t)(
1652 __in uint32_t label,
1653 __in uint32_t data);
1655 typedef __checkReturn boolean_t
1656 (*efx_rxq_flush_done_ev_t)(
1658 __in uint32_t rxq_index);
1660 typedef __checkReturn boolean_t
1661 (*efx_rxq_flush_failed_ev_t)(
1663 __in uint32_t rxq_index);
1665 typedef __checkReturn boolean_t
1666 (*efx_txq_flush_done_ev_t)(
1668 __in uint32_t txq_index);
1670 typedef __checkReturn boolean_t
1671 (*efx_software_ev_t)(
1673 __in uint16_t magic);
1675 typedef __checkReturn boolean_t
1678 __in uint32_t code);
1680 #define EFX_SRAM_CLEAR 0
1681 #define EFX_SRAM_UPDATE 1
1682 #define EFX_SRAM_ILLEGAL_CLEAR 2
1684 typedef __checkReturn boolean_t
1685 (*efx_wake_up_ev_t)(
1687 __in uint32_t label);
1689 typedef __checkReturn boolean_t
1692 __in uint32_t label);
1694 typedef __checkReturn boolean_t
1695 (*efx_link_change_ev_t)(
1697 __in efx_link_mode_t link_mode);
1699 #if EFSYS_OPT_MON_STATS
1701 typedef __checkReturn boolean_t
1702 (*efx_monitor_ev_t)(
1704 __in efx_mon_stat_t id,
1705 __in efx_mon_stat_value_t value);
1707 #endif /* EFSYS_OPT_MON_STATS */
1709 #if EFSYS_OPT_MAC_STATS
1711 typedef __checkReturn boolean_t
1712 (*efx_mac_stats_ev_t)(
1714 __in uint32_t generation
1717 #endif /* EFSYS_OPT_MAC_STATS */
1719 typedef struct efx_ev_callbacks_s {
1720 efx_initialized_ev_t eec_initialized;
1723 efx_exception_ev_t eec_exception;
1724 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
1725 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
1726 efx_txq_flush_done_ev_t eec_txq_flush_done;
1727 efx_software_ev_t eec_software;
1728 efx_sram_ev_t eec_sram;
1729 efx_wake_up_ev_t eec_wake_up;
1730 efx_timer_ev_t eec_timer;
1731 efx_link_change_ev_t eec_link_change;
1732 #if EFSYS_OPT_MON_STATS
1733 efx_monitor_ev_t eec_monitor;
1734 #endif /* EFSYS_OPT_MON_STATS */
1735 #if EFSYS_OPT_MAC_STATS
1736 efx_mac_stats_ev_t eec_mac_stats;
1737 #endif /* EFSYS_OPT_MAC_STATS */
1738 } efx_ev_callbacks_t;
1740 extern __checkReturn boolean_t
1742 __in efx_evq_t *eep,
1743 __in unsigned int count);
1745 #if EFSYS_OPT_EV_PREFETCH
1749 __in efx_evq_t *eep,
1750 __in unsigned int count);
1752 #endif /* EFSYS_OPT_EV_PREFETCH */
1756 __in efx_evq_t *eep,
1757 __inout unsigned int *countp,
1758 __in const efx_ev_callbacks_t *eecp,
1759 __in_opt void *arg);
1761 extern __checkReturn efx_rc_t
1763 __in efx_evq_t *eep,
1764 __in unsigned int us);
1766 extern __checkReturn efx_rc_t
1768 __in efx_evq_t *eep,
1769 __in unsigned int count);
1771 #if EFSYS_OPT_QSTATS
1777 __in efx_nic_t *enp,
1778 __in unsigned int id);
1780 #endif /* EFSYS_OPT_NAMES */
1783 efx_ev_qstats_update(
1784 __in efx_evq_t *eep,
1785 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
1787 #endif /* EFSYS_OPT_QSTATS */
1791 __in efx_evq_t *eep);
1795 extern __checkReturn efx_rc_t
1797 __inout efx_nic_t *enp);
1801 __in efx_nic_t *enp);
1803 #if EFSYS_OPT_RX_SCATTER
1804 __checkReturn efx_rc_t
1805 efx_rx_scatter_enable(
1806 __in efx_nic_t *enp,
1807 __in unsigned int buf_size);
1808 #endif /* EFSYS_OPT_RX_SCATTER */
1810 #if EFSYS_OPT_RX_SCALE
1812 typedef enum efx_rx_hash_alg_e {
1813 EFX_RX_HASHALG_LFSR = 0,
1814 EFX_RX_HASHALG_TOEPLITZ
1815 } efx_rx_hash_alg_t;
1817 typedef enum efx_rx_hash_type_e {
1818 EFX_RX_HASH_IPV4 = 0,
1819 EFX_RX_HASH_TCPIPV4,
1821 EFX_RX_HASH_TCPIPV6,
1822 } efx_rx_hash_type_t;
1824 typedef enum efx_rx_hash_support_e {
1825 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
1826 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
1827 } efx_rx_hash_support_t;
1829 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
1830 #define EFX_MAXRSS 64 /* RX indirection entry range */
1831 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
1833 typedef enum efx_rx_scale_support_e {
1834 EFX_RX_SCALE_UNAVAILABLE = 0, /* Not supported */
1835 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
1836 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
1837 } efx_rx_scale_support_t;
1839 extern __checkReturn efx_rc_t
1840 efx_rx_hash_support_get(
1841 __in efx_nic_t *enp,
1842 __out efx_rx_hash_support_t *supportp);
1845 extern __checkReturn efx_rc_t
1846 efx_rx_scale_support_get(
1847 __in efx_nic_t *enp,
1848 __out efx_rx_scale_support_t *supportp);
1850 extern __checkReturn efx_rc_t
1851 efx_rx_scale_mode_set(
1852 __in efx_nic_t *enp,
1853 __in efx_rx_hash_alg_t alg,
1854 __in efx_rx_hash_type_t type,
1855 __in boolean_t insert);
1857 extern __checkReturn efx_rc_t
1858 efx_rx_scale_tbl_set(
1859 __in efx_nic_t *enp,
1860 __in_ecount(n) unsigned int *table,
1863 extern __checkReturn efx_rc_t
1864 efx_rx_scale_key_set(
1865 __in efx_nic_t *enp,
1866 __in_ecount(n) uint8_t *key,
1869 extern __checkReturn uint32_t
1870 efx_psuedo_hdr_hash_get(
1871 __in efx_nic_t *enp,
1872 __in efx_rx_hash_alg_t func,
1873 __in uint8_t *buffer);
1875 #endif /* EFSYS_OPT_RX_SCALE */
1877 extern __checkReturn efx_rc_t
1878 efx_psuedo_hdr_pkt_length_get(
1879 __in efx_nic_t *enp,
1880 __in uint8_t *buffer,
1881 __out uint16_t *pkt_lengthp);
1883 #define EFX_RXQ_MAXNDESCS 4096
1884 #define EFX_RXQ_MINNDESCS 512
1886 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
1887 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1888 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
1889 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
1891 typedef enum efx_rxq_type_e {
1892 EFX_RXQ_TYPE_DEFAULT,
1893 EFX_RXQ_TYPE_SCATTER,
1897 extern __checkReturn efx_rc_t
1899 __in efx_nic_t *enp,
1900 __in unsigned int index,
1901 __in unsigned int label,
1902 __in efx_rxq_type_t type,
1903 __in efsys_mem_t *esmp,
1906 __in efx_evq_t *eep,
1907 __deref_out efx_rxq_t **erpp);
1909 typedef struct efx_buffer_s {
1910 efsys_dma_addr_t eb_addr;
1915 typedef struct efx_desc_s {
1921 __in efx_rxq_t *erp,
1922 __in_ecount(n) efsys_dma_addr_t *addrp,
1924 __in unsigned int n,
1925 __in unsigned int completed,
1926 __in unsigned int added);
1930 __in efx_rxq_t *erp,
1931 __in unsigned int added,
1932 __inout unsigned int *pushedp);
1934 extern __checkReturn efx_rc_t
1936 __in efx_rxq_t *erp);
1940 __in efx_rxq_t *erp);
1944 __in efx_rxq_t *erp);
1948 typedef struct efx_txq_s efx_txq_t;
1950 #if EFSYS_OPT_QSTATS
1952 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
1953 typedef enum efx_tx_qstat_e {
1959 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
1961 #endif /* EFSYS_OPT_QSTATS */
1963 extern __checkReturn efx_rc_t
1965 __in efx_nic_t *enp);
1969 __in efx_nic_t *enp);
1971 #define EFX_BUG35388_WORKAROUND(_encp) \
1972 (((_encp) == NULL) ? 1 : ((_encp)->enc_bug35388_workaround != 0))
1974 #define EFX_TXQ_MAXNDESCS(_encp) \
1975 ((EFX_BUG35388_WORKAROUND(_encp)) ? 2048 : 4096)
1977 #define EFX_TXQ_MINNDESCS 512
1979 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
1980 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1981 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
1982 #define EFX_TXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
1984 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
1986 #define EFX_TXQ_CKSUM_IPV4 0x0001
1987 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
1988 #define EFX_TXQ_FATSOV2 0x0004
1990 extern __checkReturn efx_rc_t
1992 __in efx_nic_t *enp,
1993 __in unsigned int index,
1994 __in unsigned int label,
1995 __in efsys_mem_t *esmp,
1998 __in uint16_t flags,
1999 __in efx_evq_t *eep,
2000 __deref_out efx_txq_t **etpp,
2001 __out unsigned int *addedp);
2003 extern __checkReturn efx_rc_t
2005 __in efx_txq_t *etp,
2006 __in_ecount(n) efx_buffer_t *eb,
2007 __in unsigned int n,
2008 __in unsigned int completed,
2009 __inout unsigned int *addedp);
2011 extern __checkReturn efx_rc_t
2013 __in efx_txq_t *etp,
2014 __in unsigned int ns);
2018 __in efx_txq_t *etp,
2019 __in unsigned int added,
2020 __in unsigned int pushed);
2022 extern __checkReturn efx_rc_t
2024 __in efx_txq_t *etp);
2028 __in efx_txq_t *etp);
2030 extern __checkReturn efx_rc_t
2032 __in efx_txq_t *etp);
2035 efx_tx_qpio_disable(
2036 __in efx_txq_t *etp);
2038 extern __checkReturn efx_rc_t
2040 __in efx_txq_t *etp,
2041 __in_ecount(buf_length) uint8_t *buffer,
2042 __in size_t buf_length,
2043 __in size_t pio_buf_offset);
2045 extern __checkReturn efx_rc_t
2047 __in efx_txq_t *etp,
2048 __in size_t pkt_length,
2049 __in unsigned int completed,
2050 __inout unsigned int *addedp);
2052 extern __checkReturn efx_rc_t
2054 __in efx_txq_t *etp,
2055 __in_ecount(n) efx_desc_t *ed,
2056 __in unsigned int n,
2057 __in unsigned int completed,
2058 __inout unsigned int *addedp);
2061 efx_tx_qdesc_dma_create(
2062 __in efx_txq_t *etp,
2063 __in efsys_dma_addr_t addr,
2066 __out efx_desc_t *edp);
2069 efx_tx_qdesc_tso_create(
2070 __in efx_txq_t *etp,
2071 __in uint16_t ipv4_id,
2072 __in uint32_t tcp_seq,
2073 __in uint8_t tcp_flags,
2074 __out efx_desc_t *edp);
2076 /* Number of FATSOv2 option descriptors */
2077 #define EFX_TX_FATSOV2_OPT_NDESCS 2
2079 /* Maximum number of DMA segments per TSO packet (not superframe) */
2080 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
2083 efx_tx_qdesc_tso2_create(
2084 __in efx_txq_t *etp,
2085 __in uint16_t ipv4_id,
2086 __in uint32_t tcp_seq,
2087 __in uint16_t tcp_mss,
2088 __out_ecount(count) efx_desc_t *edp,
2092 efx_tx_qdesc_vlantci_create(
2093 __in efx_txq_t *etp,
2095 __out efx_desc_t *edp);
2097 #if EFSYS_OPT_QSTATS
2103 __in efx_nic_t *etp,
2104 __in unsigned int id);
2106 #endif /* EFSYS_OPT_NAMES */
2109 efx_tx_qstats_update(
2110 __in efx_txq_t *etp,
2111 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
2113 #endif /* EFSYS_OPT_QSTATS */
2117 __in efx_txq_t *etp);
2122 #if EFSYS_OPT_FILTER
2124 #define EFX_ETHER_TYPE_IPV4 0x0800
2125 #define EFX_ETHER_TYPE_IPV6 0x86DD
2127 #define EFX_IPPROTO_TCP 6
2128 #define EFX_IPPROTO_UDP 17
2130 typedef enum efx_filter_flag_e {
2131 EFX_FILTER_FLAG_RX_RSS = 0x01, /* use RSS to spread across
2132 * multiple queues */
2133 EFX_FILTER_FLAG_RX_SCATTER = 0x02, /* enable RX scatter */
2134 EFX_FILTER_FLAG_RX_OVER_AUTO = 0x04, /* Override an automatic filter
2135 * (priority EFX_FILTER_PRI_AUTO).
2136 * May only be set by the filter
2137 * implementation for each type.
2138 * A removal request will
2139 * restore the automatic filter
2141 EFX_FILTER_FLAG_RX = 0x08, /* Filter is for RX */
2142 EFX_FILTER_FLAG_TX = 0x10, /* Filter is for TX */
2143 } efx_filter_flag_t;
2145 typedef enum efx_filter_match_flags_e {
2146 EFX_FILTER_MATCH_REM_HOST = 0x0001, /* Match by remote IP host
2148 EFX_FILTER_MATCH_LOC_HOST = 0x0002, /* Match by local IP host
2150 EFX_FILTER_MATCH_REM_MAC = 0x0004, /* Match by remote MAC address */
2151 EFX_FILTER_MATCH_REM_PORT = 0x0008, /* Match by remote TCP/UDP port */
2152 EFX_FILTER_MATCH_LOC_MAC = 0x0010, /* Match by remote TCP/UDP port */
2153 EFX_FILTER_MATCH_LOC_PORT = 0x0020, /* Match by local TCP/UDP port */
2154 EFX_FILTER_MATCH_ETHER_TYPE = 0x0040, /* Match by Ether-type */
2155 EFX_FILTER_MATCH_INNER_VID = 0x0080, /* Match by inner VLAN ID */
2156 EFX_FILTER_MATCH_OUTER_VID = 0x0100, /* Match by outer VLAN ID */
2157 EFX_FILTER_MATCH_IP_PROTO = 0x0200, /* Match by IP transport
2159 EFX_FILTER_MATCH_LOC_MAC_IG = 0x0400, /* Match by local MAC address
2160 * I/G bit. Used for RX default
2161 * unicast and multicast/
2162 * broadcast filters. */
2163 } efx_filter_match_flags_t;
2165 typedef enum efx_filter_priority_s {
2166 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
2167 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
2168 * address list or hardware
2169 * requirements. This may only be used
2170 * by the filter implementation for
2172 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
2173 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
2174 * client (e.g. SR-IOV, HyperV VMQ etc.)
2176 } efx_filter_priority_t;
2179 * FIXME: All these fields are assumed to be in little-endian byte order.
2180 * It may be better for some to be big-endian. See bug42804.
2183 typedef struct efx_filter_spec_s {
2184 uint32_t efs_match_flags:12;
2185 uint32_t efs_priority:2;
2186 uint32_t efs_flags:6;
2187 uint32_t efs_dmaq_id:12;
2188 uint32_t efs_rss_context;
2189 uint16_t efs_outer_vid;
2190 uint16_t efs_inner_vid;
2191 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
2192 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
2193 uint16_t efs_ether_type;
2194 uint8_t efs_ip_proto;
2195 uint16_t efs_loc_port;
2196 uint16_t efs_rem_port;
2197 efx_oword_t efs_rem_host;
2198 efx_oword_t efs_loc_host;
2199 } efx_filter_spec_t;
2202 /* Default values for use in filter specifications */
2203 #define EFX_FILTER_SPEC_RSS_CONTEXT_DEFAULT 0xffffffff
2204 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
2205 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
2207 extern __checkReturn efx_rc_t
2209 __in efx_nic_t *enp);
2213 __in efx_nic_t *enp);
2215 extern __checkReturn efx_rc_t
2217 __in efx_nic_t *enp,
2218 __inout efx_filter_spec_t *spec);
2220 extern __checkReturn efx_rc_t
2222 __in efx_nic_t *enp,
2223 __inout efx_filter_spec_t *spec);
2225 extern __checkReturn efx_rc_t
2227 __in efx_nic_t *enp);
2229 extern __checkReturn efx_rc_t
2230 efx_filter_supported_filters(
2231 __in efx_nic_t *enp,
2232 __out uint32_t *list,
2233 __out size_t *length);
2236 efx_filter_spec_init_rx(
2237 __out efx_filter_spec_t *spec,
2238 __in efx_filter_priority_t priority,
2239 __in efx_filter_flag_t flags,
2240 __in efx_rxq_t *erp);
2243 efx_filter_spec_init_tx(
2244 __out efx_filter_spec_t *spec,
2245 __in efx_txq_t *etp);
2247 extern __checkReturn efx_rc_t
2248 efx_filter_spec_set_ipv4_local(
2249 __inout efx_filter_spec_t *spec,
2252 __in uint16_t port);
2254 extern __checkReturn efx_rc_t
2255 efx_filter_spec_set_ipv4_full(
2256 __inout efx_filter_spec_t *spec,
2258 __in uint32_t lhost,
2259 __in uint16_t lport,
2260 __in uint32_t rhost,
2261 __in uint16_t rport);
2263 extern __checkReturn efx_rc_t
2264 efx_filter_spec_set_eth_local(
2265 __inout efx_filter_spec_t *spec,
2267 __in const uint8_t *addr);
2269 extern __checkReturn efx_rc_t
2270 efx_filter_spec_set_uc_def(
2271 __inout efx_filter_spec_t *spec);
2273 extern __checkReturn efx_rc_t
2274 efx_filter_spec_set_mc_def(
2275 __inout efx_filter_spec_t *spec);
2277 #endif /* EFSYS_OPT_FILTER */
2281 extern __checkReturn uint32_t
2283 __in_ecount(count) uint32_t const *input,
2285 __in uint32_t init);
2287 extern __checkReturn uint32_t
2289 __in_ecount(length) uint8_t const *input,
2291 __in uint32_t init);
2293 #if EFSYS_OPT_LICENSING
2297 typedef struct efx_key_stats_s {
2299 uint32_t eks_invalid;
2300 uint32_t eks_blacklisted;
2301 uint32_t eks_unverifiable;
2302 uint32_t eks_wrong_node;
2303 uint32_t eks_licensed_apps_lo;
2304 uint32_t eks_licensed_apps_hi;
2305 uint32_t eks_licensed_features_lo;
2306 uint32_t eks_licensed_features_hi;
2309 extern __checkReturn efx_rc_t
2311 __in efx_nic_t *enp);
2315 __in efx_nic_t *enp);
2317 extern __checkReturn boolean_t
2318 efx_lic_check_support(
2319 __in efx_nic_t *enp);
2321 extern __checkReturn efx_rc_t
2322 efx_lic_update_licenses(
2323 __in efx_nic_t *enp);
2325 extern __checkReturn efx_rc_t
2326 efx_lic_get_key_stats(
2327 __in efx_nic_t *enp,
2328 __out efx_key_stats_t *ksp);
2330 extern __checkReturn efx_rc_t
2332 __in efx_nic_t *enp,
2333 __in uint64_t app_id,
2334 __out boolean_t *licensedp);
2336 extern __checkReturn efx_rc_t
2338 __in efx_nic_t *enp,
2339 __in size_t buffer_size,
2340 __out uint32_t *typep,
2341 __out size_t *lengthp,
2342 __out_opt uint8_t *bufferp);
2345 extern __checkReturn efx_rc_t
2347 __in efx_nic_t *enp,
2348 __in_bcount(buffer_size)
2350 __in size_t buffer_size,
2351 __out uint32_t *startp
2354 extern __checkReturn efx_rc_t
2356 __in efx_nic_t *enp,
2357 __in_bcount(buffer_size)
2359 __in size_t buffer_size,
2360 __in uint32_t offset,
2361 __out uint32_t *endp
2364 extern __checkReturn __success(return != B_FALSE) boolean_t
2366 __in efx_nic_t *enp,
2367 __in_bcount(buffer_size)
2369 __in size_t buffer_size,
2370 __in uint32_t offset,
2371 __out uint32_t *startp,
2372 __out uint32_t *lengthp
2375 extern __checkReturn __success(return != B_FALSE) boolean_t
2376 efx_lic_validate_key(
2377 __in efx_nic_t *enp,
2378 __in_bcount(length) caddr_t keyp,
2379 __in uint32_t length
2382 extern __checkReturn efx_rc_t
2384 __in efx_nic_t *enp,
2385 __in_bcount(buffer_size)
2387 __in size_t buffer_size,
2388 __in uint32_t offset,
2389 __in uint32_t length,
2390 __out_bcount_part(key_max_size, *lengthp)
2392 __in size_t key_max_size,
2393 __out uint32_t *lengthp
2396 extern __checkReturn efx_rc_t
2398 __in efx_nic_t *enp,
2399 __in_bcount(buffer_size)
2401 __in size_t buffer_size,
2402 __in uint32_t offset,
2403 __in_bcount(length) caddr_t keyp,
2404 __in uint32_t length,
2405 __out uint32_t *lengthp
2408 __checkReturn efx_rc_t
2410 __in efx_nic_t *enp,
2411 __in_bcount(buffer_size)
2413 __in size_t buffer_size,
2414 __in uint32_t offset,
2415 __in uint32_t length,
2417 __out uint32_t *deltap
2420 extern __checkReturn efx_rc_t
2421 efx_lic_create_partition(
2422 __in efx_nic_t *enp,
2423 __in_bcount(buffer_size)
2425 __in size_t buffer_size
2428 extern __checkReturn efx_rc_t
2429 efx_lic_finish_partition(
2430 __in efx_nic_t *enp,
2431 __in_bcount(buffer_size)
2433 __in size_t buffer_size
2436 #endif /* EFSYS_OPT_LICENSING */
2444 #endif /* _SYS_EFX_H */