2 * Copyright (c) 2006-2015 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
37 #include "efx_phy_ids.h"
43 #define EFX_STATIC_ASSERT(_cond) \
44 ((void)sizeof(char[(_cond) ? 1 : -1]))
46 #define EFX_ARRAY_SIZE(_array) \
47 (sizeof(_array) / sizeof((_array)[0]))
49 #define EFX_FIELD_OFFSET(_type, _field) \
50 ((size_t) &(((_type *)0)->_field))
54 typedef __success(return == 0) int efx_rc_t;
59 typedef enum efx_family_e {
63 EFX_FAMILY_HUNTINGTON,
68 extern __checkReturn efx_rc_t
72 __out efx_family_t *efp);
74 extern __checkReturn efx_rc_t
76 __in efsys_bar_t *esbp,
77 __out efx_family_t *efp);
79 #define EFX_PCI_VENID_SFC 0x1924
81 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
83 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
84 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
85 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
87 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
88 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
89 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
91 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
92 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
94 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
95 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
96 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
105 EFX_ERR_BUFID_DC_OOB,
118 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
119 extern __checkReturn uint32_t
121 __in uint32_t crc_init,
122 __in_ecount(length) uint8_t const *input,
126 /* Type prototypes */
128 typedef struct efx_rxq_s efx_rxq_t;
132 typedef struct efx_nic_s efx_nic_t;
134 #define EFX_NIC_FUNC_PRIMARY 0x00000001
135 #define EFX_NIC_FUNC_LINKCTRL 0x00000002
136 #define EFX_NIC_FUNC_TRUSTED 0x00000004
139 extern __checkReturn efx_rc_t
141 __in efx_family_t family,
142 __in efsys_identifier_t *esip,
143 __in efsys_bar_t *esbp,
144 __in efsys_lock_t *eslp,
145 __deref_out efx_nic_t **enpp);
147 extern __checkReturn efx_rc_t
149 __in efx_nic_t *enp);
151 #if EFSYS_OPT_PCIE_TUNE
153 extern __checkReturn efx_rc_t
156 unsigned int nlanes);
158 extern __checkReturn efx_rc_t
159 efx_nic_pcie_extended_sync(
160 __in efx_nic_t *enp);
162 #endif /* EFSYS_OPT_PCIE_TUNE */
164 extern __checkReturn efx_rc_t
166 __in efx_nic_t *enp);
168 extern __checkReturn efx_rc_t
170 __in efx_nic_t *enp);
174 extern __checkReturn efx_rc_t
175 efx_nic_register_test(
176 __in efx_nic_t *enp);
178 #endif /* EFSYS_OPT_DIAG */
182 __in efx_nic_t *enp);
186 __in efx_nic_t *enp);
190 __in efx_nic_t *enp);
194 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
195 /* Huntington and Medford require MCDIv2 commands */
196 #define WITH_MCDI_V2 1
199 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
201 typedef enum efx_mcdi_exception_e {
202 EFX_MCDI_EXCEPTION_MC_REBOOT,
203 EFX_MCDI_EXCEPTION_MC_BADASSERT,
204 } efx_mcdi_exception_t;
206 #if EFSYS_OPT_MCDI_LOGGING
207 typedef enum efx_log_msg_e
210 EFX_LOG_MCDI_REQUEST,
211 EFX_LOG_MCDI_RESPONSE,
213 #endif /* EFSYS_OPT_MCDI_LOGGING */
215 typedef struct efx_mcdi_transport_s {
217 efsys_mem_t *emt_dma_mem;
218 void (*emt_execute)(void *, efx_mcdi_req_t *);
219 void (*emt_ev_cpl)(void *);
220 void (*emt_exception)(void *, efx_mcdi_exception_t);
221 #if EFSYS_OPT_MCDI_LOGGING
222 void (*emt_logger)(void *, efx_log_msg_t,
223 void *, size_t, void *, size_t);
224 #endif /* EFSYS_OPT_MCDI_LOGGING */
225 #if EFSYS_OPT_MCDI_PROXY_AUTH
226 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
227 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
228 } efx_mcdi_transport_t;
230 extern __checkReturn efx_rc_t
233 __in const efx_mcdi_transport_t *mtp);
235 extern __checkReturn efx_rc_t
237 __in efx_nic_t *enp);
241 __in efx_nic_t *enp);
244 efx_mcdi_request_start(
246 __in efx_mcdi_req_t *emrp,
247 __in boolean_t ev_cpl);
249 extern __checkReturn boolean_t
250 efx_mcdi_request_poll(
251 __in efx_nic_t *enp);
253 extern __checkReturn boolean_t
254 efx_mcdi_request_abort(
255 __in efx_nic_t *enp);
259 __in efx_nic_t *enp);
261 #endif /* EFSYS_OPT_MCDI */
265 #define EFX_NINTR_FALCON 64
266 #define EFX_NINTR_SIENA 1024
268 typedef enum efx_intr_type_e {
269 EFX_INTR_INVALID = 0,
275 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
277 extern __checkReturn efx_rc_t
280 __in efx_intr_type_t type,
281 __in efsys_mem_t *esmp);
285 __in efx_nic_t *enp);
289 __in efx_nic_t *enp);
292 efx_intr_disable_unlocked(
293 __in efx_nic_t *enp);
295 #define EFX_INTR_NEVQS 32
297 extern __checkReturn efx_rc_t
300 __in unsigned int level);
303 efx_intr_status_line(
305 __out boolean_t *fatalp,
306 __out uint32_t *maskp);
309 efx_intr_status_message(
311 __in unsigned int message,
312 __out boolean_t *fatalp);
316 __in efx_nic_t *enp);
320 __in efx_nic_t *enp);
324 #if EFSYS_OPT_MAC_STATS
326 /* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */
327 typedef enum efx_mac_stat_e {
330 EFX_MAC_RX_UNICST_PKTS,
331 EFX_MAC_RX_MULTICST_PKTS,
332 EFX_MAC_RX_BRDCST_PKTS,
333 EFX_MAC_RX_PAUSE_PKTS,
334 EFX_MAC_RX_LE_64_PKTS,
335 EFX_MAC_RX_65_TO_127_PKTS,
336 EFX_MAC_RX_128_TO_255_PKTS,
337 EFX_MAC_RX_256_TO_511_PKTS,
338 EFX_MAC_RX_512_TO_1023_PKTS,
339 EFX_MAC_RX_1024_TO_15XX_PKTS,
340 EFX_MAC_RX_GE_15XX_PKTS,
342 EFX_MAC_RX_FCS_ERRORS,
343 EFX_MAC_RX_DROP_EVENTS,
344 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
345 EFX_MAC_RX_SYMBOL_ERRORS,
346 EFX_MAC_RX_ALIGN_ERRORS,
347 EFX_MAC_RX_INTERNAL_ERRORS,
348 EFX_MAC_RX_JABBER_PKTS,
349 EFX_MAC_RX_LANE0_CHAR_ERR,
350 EFX_MAC_RX_LANE1_CHAR_ERR,
351 EFX_MAC_RX_LANE2_CHAR_ERR,
352 EFX_MAC_RX_LANE3_CHAR_ERR,
353 EFX_MAC_RX_LANE0_DISP_ERR,
354 EFX_MAC_RX_LANE1_DISP_ERR,
355 EFX_MAC_RX_LANE2_DISP_ERR,
356 EFX_MAC_RX_LANE3_DISP_ERR,
357 EFX_MAC_RX_MATCH_FAULT,
358 EFX_MAC_RX_NODESC_DROP_CNT,
361 EFX_MAC_TX_UNICST_PKTS,
362 EFX_MAC_TX_MULTICST_PKTS,
363 EFX_MAC_TX_BRDCST_PKTS,
364 EFX_MAC_TX_PAUSE_PKTS,
365 EFX_MAC_TX_LE_64_PKTS,
366 EFX_MAC_TX_65_TO_127_PKTS,
367 EFX_MAC_TX_128_TO_255_PKTS,
368 EFX_MAC_TX_256_TO_511_PKTS,
369 EFX_MAC_TX_512_TO_1023_PKTS,
370 EFX_MAC_TX_1024_TO_15XX_PKTS,
371 EFX_MAC_TX_GE_15XX_PKTS,
373 EFX_MAC_TX_SGL_COL_PKTS,
374 EFX_MAC_TX_MULT_COL_PKTS,
375 EFX_MAC_TX_EX_COL_PKTS,
376 EFX_MAC_TX_LATE_COL_PKTS,
378 EFX_MAC_TX_EX_DEF_PKTS,
379 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
380 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
381 EFX_MAC_PM_TRUNC_VFIFO_FULL,
382 EFX_MAC_PM_DISCARD_VFIFO_FULL,
383 EFX_MAC_PM_TRUNC_QBB,
384 EFX_MAC_PM_DISCARD_QBB,
385 EFX_MAC_PM_DISCARD_MAPPING,
386 EFX_MAC_RXDP_Q_DISABLED_PKTS,
387 EFX_MAC_RXDP_DI_DROPPED_PKTS,
388 EFX_MAC_RXDP_STREAMING_PKTS,
389 EFX_MAC_RXDP_HLB_FETCH,
390 EFX_MAC_RXDP_HLB_WAIT,
391 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
392 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
393 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
394 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
395 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
396 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
397 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
398 EFX_MAC_VADAPTER_RX_BAD_BYTES,
399 EFX_MAC_VADAPTER_RX_OVERFLOW,
400 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
401 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
402 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
403 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
404 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
405 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
406 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
407 EFX_MAC_VADAPTER_TX_BAD_BYTES,
408 EFX_MAC_VADAPTER_TX_OVERFLOW,
412 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
414 #endif /* EFSYS_OPT_MAC_STATS */
416 typedef enum efx_link_mode_e {
417 EFX_LINK_UNKNOWN = 0,
430 #define EFX_MAC_ADDR_LEN 6
432 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t*)_address)[0] & 0x01)
434 #define EFX_MAC_MULTICAST_LIST_MAX 256
436 #define EFX_MAC_SDU_MAX 9202
438 #define EFX_MAC_PDU(_sdu) \
443 + /* bug16011 */ 16), \
446 #define EFX_MAC_PDU_MIN 60
447 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
449 extern __checkReturn efx_rc_t
454 extern __checkReturn efx_rc_t
459 extern __checkReturn efx_rc_t
462 __in boolean_t all_unicst,
463 __in boolean_t mulcst,
464 __in boolean_t all_mulcst,
465 __in boolean_t brdcst);
467 extern __checkReturn efx_rc_t
468 efx_mac_multicast_list_set(
470 __in_ecount(6*count) uint8_t const *addrs,
473 extern __checkReturn efx_rc_t
474 efx_mac_filter_default_rxq_set(
477 __in boolean_t using_rss);
480 efx_mac_filter_default_rxq_clear(
481 __in efx_nic_t *enp);
483 extern __checkReturn efx_rc_t
486 __in boolean_t enabled);
488 extern __checkReturn efx_rc_t
491 __out boolean_t *mac_upp);
493 #define EFX_FCNTL_RESPOND 0x00000001
494 #define EFX_FCNTL_GENERATE 0x00000002
496 extern __checkReturn efx_rc_t
499 __in unsigned int fcntl,
500 __in boolean_t autoneg);
505 __out unsigned int *fcntl_wantedp,
506 __out unsigned int *fcntl_linkp);
508 #define EFX_MAC_HASH_BITS (1 << 8)
510 extern __checkReturn efx_rc_t
512 __in efx_nic_t *enp);
516 __in efx_nic_t *enp);
518 extern __checkReturn efx_rc_t
521 __in boolean_t unicst,
522 __in boolean_t brdcst);
524 extern __checkReturn efx_rc_t
527 __in_ecount(EFX_MAC_HASH_BITS) unsigned int const *bucket);
529 #if EFSYS_OPT_MCAST_FILTER_LIST
530 extern __checkReturn efx_rc_t
531 efx_pktfilter_mcast_list_set(
533 __in uint8_t const *addrs,
535 #endif /* EFSYS_OPT_MCAST_FILTER_LIST */
537 extern __checkReturn efx_rc_t
538 efx_pktfilter_mcast_all(
539 __in efx_nic_t *enp);
541 #if EFSYS_OPT_MAC_STATS
545 extern __checkReturn const char *
548 __in unsigned int id);
550 #endif /* EFSYS_OPT_NAMES */
552 #define EFX_MAC_STATS_SIZE 0x400
555 * Upload mac statistics supported by the hardware into the given buffer.
557 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes,
560 * The hardware will only DMA statistics that it understands (of course).
561 * Drivers should not make any assumptions about which statistics are
562 * supported, especially when the statistics are generated by firmware.
564 * Thus, drivers should zero this buffer before use, so that not-understood
565 * statistics read back as zero.
567 extern __checkReturn efx_rc_t
568 efx_mac_stats_upload(
570 __in efsys_mem_t *esmp);
572 extern __checkReturn efx_rc_t
573 efx_mac_stats_periodic(
575 __in efsys_mem_t *esmp,
576 __in uint16_t period_ms,
577 __in boolean_t events);
579 extern __checkReturn efx_rc_t
580 efx_mac_stats_update(
582 __in efsys_mem_t *esmp,
583 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
584 __inout_opt uint32_t *generationp);
586 #endif /* EFSYS_OPT_MAC_STATS */
590 typedef enum efx_mon_type_e {
604 __in efx_nic_t *enp);
606 #endif /* EFSYS_OPT_NAMES */
608 extern __checkReturn efx_rc_t
610 __in efx_nic_t *enp);
612 #if EFSYS_OPT_MON_STATS
614 #define EFX_MON_STATS_PAGE_SIZE 0x100
615 #define EFX_MON_MASK_ELEMENT_SIZE 32
617 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock c79c86b62a144846 */
618 typedef enum efx_mon_stat_e {
625 EFX_MON_STAT_EXT_TEMP,
626 EFX_MON_STAT_INT_TEMP,
629 EFX_MON_STAT_INT_COOLING,
630 EFX_MON_STAT_EXT_COOLING,
638 EFX_MON_STAT_AOE_TEMP,
639 EFX_MON_STAT_PSU_AOE_TEMP,
640 EFX_MON_STAT_PSU_TEMP,
646 EFX_MON_STAT_VAOE_IN,
648 EFX_MON_STAT_IAOE_IN,
649 EFX_MON_STAT_NIC_POWER,
653 EFX_MON_STAT_0_9V_ADC,
654 EFX_MON_STAT_INT_TEMP2,
655 EFX_MON_STAT_VREG_TEMP,
656 EFX_MON_STAT_VREG_0_9V_TEMP,
657 EFX_MON_STAT_VREG_1_2V_TEMP,
658 EFX_MON_STAT_INT_VPTAT,
659 EFX_MON_STAT_INT_ADC_TEMP,
660 EFX_MON_STAT_EXT_VPTAT,
661 EFX_MON_STAT_EXT_ADC_TEMP,
662 EFX_MON_STAT_AMBIENT_TEMP,
663 EFX_MON_STAT_AIRFLOW,
664 EFX_MON_STAT_VDD08D_VSS08D_CSR,
665 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
666 EFX_MON_STAT_HOTPOINT_TEMP,
667 EFX_MON_STAT_PHY_POWER_SWITCH_PORT0,
668 EFX_MON_STAT_PHY_POWER_SWITCH_PORT1,
669 EFX_MON_STAT_MUM_VCC,
672 EFX_MON_STAT_0V9_A_TEMP,
675 EFX_MON_STAT_0V9_B_TEMP,
676 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
677 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,
678 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
679 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,
680 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
681 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
682 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,
683 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,
684 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
685 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
686 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,
687 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,
691 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
693 typedef enum efx_mon_stat_state_e {
694 EFX_MON_STAT_STATE_OK = 0,
695 EFX_MON_STAT_STATE_WARNING = 1,
696 EFX_MON_STAT_STATE_FATAL = 2,
697 EFX_MON_STAT_STATE_BROKEN = 3,
698 EFX_MON_STAT_STATE_NO_READING = 4,
699 } efx_mon_stat_state_t;
701 typedef struct efx_mon_stat_value_s {
704 } efx_mon_stat_value_t;
711 __in efx_mon_stat_t id);
713 #endif /* EFSYS_OPT_NAMES */
715 extern __checkReturn efx_rc_t
716 efx_mon_stats_update(
718 __in efsys_mem_t *esmp,
719 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
721 #endif /* EFSYS_OPT_MON_STATS */
725 __in efx_nic_t *enp);
729 #define PMA_PMD_MMD 1
734 #define CL22EXT_MMD 29
736 #define MAXMMD ((1 << 5) - 1)
738 extern __checkReturn efx_rc_t
740 __in efx_nic_t *enp);
742 #if EFSYS_OPT_PHY_LED_CONTROL
744 typedef enum efx_phy_led_mode_e {
745 EFX_PHY_LED_DEFAULT = 0,
750 } efx_phy_led_mode_t;
752 extern __checkReturn efx_rc_t
755 __in efx_phy_led_mode_t mode);
757 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
759 extern __checkReturn efx_rc_t
761 __in efx_nic_t *enp);
763 #if EFSYS_OPT_LOOPBACK
765 typedef enum efx_loopback_type_e {
766 EFX_LOOPBACK_OFF = 0,
767 EFX_LOOPBACK_DATA = 1,
768 EFX_LOOPBACK_GMAC = 2,
769 EFX_LOOPBACK_XGMII = 3,
770 EFX_LOOPBACK_XGXS = 4,
771 EFX_LOOPBACK_XAUI = 5,
772 EFX_LOOPBACK_GMII = 6,
773 EFX_LOOPBACK_SGMII = 7,
774 EFX_LOOPBACK_XGBR = 8,
775 EFX_LOOPBACK_XFI = 9,
776 EFX_LOOPBACK_XAUI_FAR = 10,
777 EFX_LOOPBACK_GMII_FAR = 11,
778 EFX_LOOPBACK_SGMII_FAR = 12,
779 EFX_LOOPBACK_XFI_FAR = 13,
780 EFX_LOOPBACK_GPHY = 14,
781 EFX_LOOPBACK_PHY_XS = 15,
782 EFX_LOOPBACK_PCS = 16,
783 EFX_LOOPBACK_PMA_PMD = 17,
784 EFX_LOOPBACK_XPORT = 18,
785 EFX_LOOPBACK_XGMII_WS = 19,
786 EFX_LOOPBACK_XAUI_WS = 20,
787 EFX_LOOPBACK_XAUI_WS_FAR = 21,
788 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
789 EFX_LOOPBACK_GMII_WS = 23,
790 EFX_LOOPBACK_XFI_WS = 24,
791 EFX_LOOPBACK_XFI_WS_FAR = 25,
792 EFX_LOOPBACK_PHYXS_WS = 26,
793 EFX_LOOPBACK_PMA_INT = 27,
794 EFX_LOOPBACK_SD_NEAR = 28,
795 EFX_LOOPBACK_SD_FAR = 29,
796 EFX_LOOPBACK_PMA_INT_WS = 30,
797 EFX_LOOPBACK_SD_FEP2_WS = 31,
798 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
799 EFX_LOOPBACK_SD_FEP_WS = 33,
800 EFX_LOOPBACK_SD_FES_WS = 34,
802 } efx_loopback_type_t;
804 typedef enum efx_loopback_kind_e {
805 EFX_LOOPBACK_KIND_OFF = 0,
806 EFX_LOOPBACK_KIND_ALL,
807 EFX_LOOPBACK_KIND_MAC,
808 EFX_LOOPBACK_KIND_PHY,
810 } efx_loopback_kind_t;
814 __in efx_loopback_kind_t loopback_kind,
815 __out efx_qword_t *maskp);
817 extern __checkReturn efx_rc_t
818 efx_port_loopback_set(
820 __in efx_link_mode_t link_mode,
821 __in efx_loopback_type_t type);
825 extern __checkReturn const char *
826 efx_loopback_type_name(
828 __in efx_loopback_type_t type);
830 #endif /* EFSYS_OPT_NAMES */
832 #endif /* EFSYS_OPT_LOOPBACK */
834 extern __checkReturn efx_rc_t
837 __out_opt efx_link_mode_t *link_modep);
841 __in efx_nic_t *enp);
843 typedef enum efx_phy_cap_type_e {
844 EFX_PHY_CAP_INVALID = 0,
851 EFX_PHY_CAP_10000FDX,
855 EFX_PHY_CAP_40000FDX,
857 } efx_phy_cap_type_t;
860 #define EFX_PHY_CAP_CURRENT 0x00000000
861 #define EFX_PHY_CAP_DEFAULT 0x00000001
862 #define EFX_PHY_CAP_PERM 0x00000002
868 __out uint32_t *maskp);
870 extern __checkReturn efx_rc_t
878 __out uint32_t *maskp);
880 extern __checkReturn efx_rc_t
883 __out uint32_t *ouip);
885 typedef enum efx_phy_media_type_e {
886 EFX_PHY_MEDIA_INVALID = 0,
891 EFX_PHY_MEDIA_SFP_PLUS,
892 EFX_PHY_MEDIA_BASE_T,
893 EFX_PHY_MEDIA_QSFP_PLUS,
895 } efx_phy_media_type_t;
897 /* Get the type of medium currently used. If the board has ports for
898 * modules, a module is present, and we recognise the media type of
899 * the module, then this will be the media type of the module.
900 * Otherwise it will be the media type of the port.
903 efx_phy_media_type_get(
905 __out efx_phy_media_type_t *typep);
907 #if EFSYS_OPT_PHY_STATS
909 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
910 typedef enum efx_phy_stat_e {
912 EFX_PHY_STAT_PMA_PMD_LINK_UP,
913 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
914 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
915 EFX_PHY_STAT_PMA_PMD_REV_A,
916 EFX_PHY_STAT_PMA_PMD_REV_B,
917 EFX_PHY_STAT_PMA_PMD_REV_C,
918 EFX_PHY_STAT_PMA_PMD_REV_D,
919 EFX_PHY_STAT_PCS_LINK_UP,
920 EFX_PHY_STAT_PCS_RX_FAULT,
921 EFX_PHY_STAT_PCS_TX_FAULT,
922 EFX_PHY_STAT_PCS_BER,
923 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
924 EFX_PHY_STAT_PHY_XS_LINK_UP,
925 EFX_PHY_STAT_PHY_XS_RX_FAULT,
926 EFX_PHY_STAT_PHY_XS_TX_FAULT,
927 EFX_PHY_STAT_PHY_XS_ALIGN,
928 EFX_PHY_STAT_PHY_XS_SYNC_A,
929 EFX_PHY_STAT_PHY_XS_SYNC_B,
930 EFX_PHY_STAT_PHY_XS_SYNC_C,
931 EFX_PHY_STAT_PHY_XS_SYNC_D,
932 EFX_PHY_STAT_AN_LINK_UP,
933 EFX_PHY_STAT_AN_MASTER,
934 EFX_PHY_STAT_AN_LOCAL_RX_OK,
935 EFX_PHY_STAT_AN_REMOTE_RX_OK,
936 EFX_PHY_STAT_CL22EXT_LINK_UP,
941 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
942 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
943 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
944 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
945 EFX_PHY_STAT_AN_COMPLETE,
946 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
947 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
948 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
949 EFX_PHY_STAT_PCS_FW_VERSION_0,
950 EFX_PHY_STAT_PCS_FW_VERSION_1,
951 EFX_PHY_STAT_PCS_FW_VERSION_2,
952 EFX_PHY_STAT_PCS_FW_VERSION_3,
953 EFX_PHY_STAT_PCS_FW_BUILD_YY,
954 EFX_PHY_STAT_PCS_FW_BUILD_MM,
955 EFX_PHY_STAT_PCS_FW_BUILD_DD,
956 EFX_PHY_STAT_PCS_OP_MODE,
960 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
967 __in efx_phy_stat_t stat);
969 #endif /* EFSYS_OPT_NAMES */
971 #define EFX_PHY_STATS_SIZE 0x100
973 extern __checkReturn efx_rc_t
974 efx_phy_stats_update(
976 __in efsys_mem_t *esmp,
977 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
979 #endif /* EFSYS_OPT_PHY_STATS */
981 #if EFSYS_OPT_PHY_PROPS
988 __in unsigned int id);
990 #endif /* EFSYS_OPT_NAMES */
992 #define EFX_PHY_PROP_DEFAULT 0x00000001
994 extern __checkReturn efx_rc_t
997 __in unsigned int id,
999 __out uint32_t *valp);
1001 extern __checkReturn efx_rc_t
1003 __in efx_nic_t *enp,
1004 __in unsigned int id,
1007 #endif /* EFSYS_OPT_PHY_PROPS */
1011 typedef enum efx_bist_type_e {
1012 EFX_BIST_TYPE_UNKNOWN,
1013 EFX_BIST_TYPE_PHY_NORMAL,
1014 EFX_BIST_TYPE_PHY_CABLE_SHORT,
1015 EFX_BIST_TYPE_PHY_CABLE_LONG,
1016 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
1017 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus*/
1018 EFX_BIST_TYPE_REG, /* Test the register memories */
1019 EFX_BIST_TYPE_NTYPES,
1022 typedef enum efx_bist_result_e {
1023 EFX_BIST_RESULT_UNKNOWN,
1024 EFX_BIST_RESULT_RUNNING,
1025 EFX_BIST_RESULT_PASSED,
1026 EFX_BIST_RESULT_FAILED,
1027 } efx_bist_result_t;
1029 typedef enum efx_phy_cable_status_e {
1030 EFX_PHY_CABLE_STATUS_OK,
1031 EFX_PHY_CABLE_STATUS_INVALID,
1032 EFX_PHY_CABLE_STATUS_OPEN,
1033 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1034 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1035 EFX_PHY_CABLE_STATUS_BUSY,
1036 } efx_phy_cable_status_t;
1038 typedef enum efx_bist_value_e {
1039 EFX_BIST_PHY_CABLE_LENGTH_A,
1040 EFX_BIST_PHY_CABLE_LENGTH_B,
1041 EFX_BIST_PHY_CABLE_LENGTH_C,
1042 EFX_BIST_PHY_CABLE_LENGTH_D,
1043 EFX_BIST_PHY_CABLE_STATUS_A,
1044 EFX_BIST_PHY_CABLE_STATUS_B,
1045 EFX_BIST_PHY_CABLE_STATUS_C,
1046 EFX_BIST_PHY_CABLE_STATUS_D,
1047 EFX_BIST_FAULT_CODE,
1048 /* Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1053 EFX_BIST_MEM_EXPECT,
1054 EFX_BIST_MEM_ACTUAL,
1056 EFX_BIST_MEM_ECC_PARITY,
1057 EFX_BIST_MEM_ECC_FATAL,
1061 extern __checkReturn efx_rc_t
1062 efx_bist_enable_offline(
1063 __in efx_nic_t *enp);
1065 extern __checkReturn efx_rc_t
1067 __in efx_nic_t *enp,
1068 __in efx_bist_type_t type);
1070 extern __checkReturn efx_rc_t
1072 __in efx_nic_t *enp,
1073 __in efx_bist_type_t type,
1074 __out efx_bist_result_t *resultp,
1075 __out_opt uint32_t *value_maskp,
1076 __out_ecount_opt(count) unsigned long *valuesp,
1081 __in efx_nic_t *enp,
1082 __in efx_bist_type_t type);
1084 #endif /* EFSYS_OPT_BIST */
1086 #define EFX_FEATURE_IPV6 0x00000001
1087 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1088 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1089 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1090 #define EFX_FEATURE_WOL 0x00000010
1091 #define EFX_FEATURE_MCDI 0x00000020
1092 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1093 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1094 #define EFX_FEATURE_TURBO 0x00000100
1095 #define EFX_FEATURE_MCDI_DMA 0x00000200
1096 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1097 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1098 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1100 typedef struct efx_nic_cfg_s {
1101 uint32_t enc_board_type;
1102 uint32_t enc_phy_type;
1104 char enc_phy_name[21];
1106 char enc_phy_revision[21];
1107 efx_mon_type_t enc_mon_type;
1108 #if EFSYS_OPT_MON_STATS
1109 uint32_t enc_mon_stat_dma_buf_size;
1110 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1112 unsigned int enc_features;
1113 uint8_t enc_mac_addr[6];
1114 uint8_t enc_port; /* PHY port number */
1115 uint32_t enc_func_flags;
1116 uint32_t enc_intr_vec_base;
1117 uint32_t enc_intr_limit;
1118 uint32_t enc_evq_limit;
1119 uint32_t enc_txq_limit;
1120 uint32_t enc_rxq_limit;
1121 uint32_t enc_buftbl_limit;
1122 uint32_t enc_piobuf_limit;
1123 uint32_t enc_piobuf_size;
1124 uint32_t enc_evq_timer_quantum_ns;
1125 uint32_t enc_evq_timer_max_us;
1126 uint32_t enc_clk_mult;
1127 uint32_t enc_rx_prefix_size;
1128 uint32_t enc_rx_buf_align_start;
1129 uint32_t enc_rx_buf_align_end;
1130 #if EFSYS_OPT_LOOPBACK
1131 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1132 #endif /* EFSYS_OPT_LOOPBACK */
1133 #if EFSYS_OPT_PHY_FLAGS
1134 uint32_t enc_phy_flags_mask;
1135 #endif /* EFSYS_OPT_PHY_FLAGS */
1136 #if EFSYS_OPT_PHY_LED_CONTROL
1137 uint32_t enc_led_mask;
1138 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1139 #if EFSYS_OPT_PHY_STATS
1140 uint64_t enc_phy_stat_mask;
1141 #endif /* EFSYS_OPT_PHY_STATS */
1142 #if EFSYS_OPT_PHY_PROPS
1143 unsigned int enc_phy_nprops;
1144 #endif /* EFSYS_OPT_PHY_PROPS */
1146 uint8_t enc_mcdi_mdio_channel;
1147 #if EFSYS_OPT_PHY_STATS
1148 uint32_t enc_mcdi_phy_stat_mask;
1149 #endif /* EFSYS_OPT_PHY_STATS */
1150 #endif /* EFSYS_OPT_SIENA */
1151 #if (EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON)
1152 #if EFSYS_OPT_MON_STATS
1153 uint32_t *enc_mcdi_sensor_maskp;
1154 uint32_t enc_mcdi_sensor_mask_size;
1155 #endif /* EFSYS_OPT_MON_STATS */
1156 #endif /* (EFSYS_OPT_SIENA | EFSYS_OPT_HUNTINGTON) */
1158 uint32_t enc_bist_mask;
1159 #endif /* EFSYS_OPT_BIST */
1160 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
1163 uint32_t enc_privilege_mask;
1164 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
1165 boolean_t enc_bug26807_workaround;
1166 boolean_t enc_bug35388_workaround;
1167 boolean_t enc_bug41750_workaround;
1168 boolean_t enc_rx_batching_enabled;
1169 /* Maximum number of descriptors completed in an rx event. */
1170 uint32_t enc_rx_batch_max;
1171 /* Number of rx descriptors the hardware requires for a push. */
1172 uint32_t enc_rx_push_align;
1174 * Maximum number of bytes into the packet the TCP header can start for
1175 * the hardware to apply TSO packet edits.
1177 uint32_t enc_tx_tso_tcp_header_offset_limit;
1178 boolean_t enc_fw_assisted_tso_enabled;
1179 boolean_t enc_hw_tx_insert_vlan_enabled;
1180 /* Datapath firmware vadapter/vport/vswitch support */
1181 boolean_t enc_datapath_cap_evb;
1182 boolean_t enc_rx_disable_scatter_supported;
1183 boolean_t enc_allow_set_mac_with_installed_filters;
1184 /* External port identifier */
1185 uint8_t enc_external_port;
1186 uint32_t enc_mcdi_max_payload_length;
1189 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1190 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1192 #define EFX_PCI_FUNCTION(_encp) \
1193 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1195 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1197 extern const efx_nic_cfg_t *
1199 __in efx_nic_t *enp);
1201 /* Driver resource limits (minimum required/maximum usable). */
1202 typedef struct efx_drv_limits_s
1204 uint32_t edl_min_evq_count;
1205 uint32_t edl_max_evq_count;
1207 uint32_t edl_min_rxq_count;
1208 uint32_t edl_max_rxq_count;
1210 uint32_t edl_min_txq_count;
1211 uint32_t edl_max_txq_count;
1213 /* PIO blocks (sub-allocated from piobuf) */
1214 uint32_t edl_min_pio_alloc_size;
1215 uint32_t edl_max_pio_alloc_count;
1218 extern __checkReturn efx_rc_t
1219 efx_nic_set_drv_limits(
1220 __inout efx_nic_t *enp,
1221 __in efx_drv_limits_t *edlp);
1223 typedef enum efx_nic_region_e {
1224 EFX_REGION_VI, /* Memory BAR UC mapping */
1225 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1228 extern __checkReturn efx_rc_t
1229 efx_nic_get_bar_region(
1230 __in efx_nic_t *enp,
1231 __in efx_nic_region_t region,
1232 __out uint32_t *offsetp,
1233 __out size_t *sizep);
1235 extern __checkReturn efx_rc_t
1236 efx_nic_get_vi_pool(
1237 __in efx_nic_t *enp,
1238 __out uint32_t *evq_countp,
1239 __out uint32_t *rxq_countp,
1240 __out uint32_t *txq_countp);
1245 typedef enum efx_vpd_tag_e {
1252 typedef uint16_t efx_vpd_keyword_t;
1254 typedef struct efx_vpd_value_s {
1255 efx_vpd_tag_t evv_tag;
1256 efx_vpd_keyword_t evv_keyword;
1258 uint8_t evv_value[0x100];
1262 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1264 extern __checkReturn efx_rc_t
1266 __in efx_nic_t *enp);
1268 extern __checkReturn efx_rc_t
1270 __in efx_nic_t *enp,
1271 __out size_t *sizep);
1273 extern __checkReturn efx_rc_t
1275 __in efx_nic_t *enp,
1276 __out_bcount(size) caddr_t data,
1279 extern __checkReturn efx_rc_t
1281 __in efx_nic_t *enp,
1282 __in_bcount(size) caddr_t data,
1285 extern __checkReturn efx_rc_t
1287 __in efx_nic_t *enp,
1288 __in_bcount(size) caddr_t data,
1291 extern __checkReturn efx_rc_t
1293 __in efx_nic_t *enp,
1294 __in_bcount(size) caddr_t data,
1296 __inout efx_vpd_value_t *evvp);
1298 extern __checkReturn efx_rc_t
1300 __in efx_nic_t *enp,
1301 __inout_bcount(size) caddr_t data,
1303 __in efx_vpd_value_t *evvp);
1305 extern __checkReturn efx_rc_t
1307 __in efx_nic_t *enp,
1308 __inout_bcount(size) caddr_t data,
1310 __out efx_vpd_value_t *evvp,
1311 __inout unsigned int *contp);
1313 extern __checkReturn efx_rc_t
1315 __in efx_nic_t *enp,
1316 __in_bcount(size) caddr_t data,
1321 __in efx_nic_t *enp);
1323 #endif /* EFSYS_OPT_VPD */
1329 typedef enum efx_nvram_type_e {
1330 EFX_NVRAM_INVALID = 0,
1332 EFX_NVRAM_BOOTROM_CFG,
1333 EFX_NVRAM_MC_FIRMWARE,
1334 EFX_NVRAM_MC_GOLDEN,
1340 EFX_NVRAM_FPGA_BACKUP,
1341 EFX_NVRAM_DYNAMIC_CFG,
1345 extern __checkReturn efx_rc_t
1347 __in efx_nic_t *enp);
1351 extern __checkReturn efx_rc_t
1353 __in efx_nic_t *enp);
1355 #endif /* EFSYS_OPT_DIAG */
1357 extern __checkReturn efx_rc_t
1359 __in efx_nic_t *enp,
1360 __in efx_nvram_type_t type,
1361 __out size_t *sizep);
1363 extern __checkReturn efx_rc_t
1365 __in efx_nic_t *enp,
1366 __in efx_nvram_type_t type,
1367 __out_opt size_t *pref_chunkp);
1370 efx_nvram_rw_finish(
1371 __in efx_nic_t *enp,
1372 __in efx_nvram_type_t type);
1374 extern __checkReturn efx_rc_t
1375 efx_nvram_get_version(
1376 __in efx_nic_t *enp,
1377 __in efx_nvram_type_t type,
1378 __out uint32_t *subtypep,
1379 __out_ecount(4) uint16_t version[4]);
1381 extern __checkReturn efx_rc_t
1382 efx_nvram_read_chunk(
1383 __in efx_nic_t *enp,
1384 __in efx_nvram_type_t type,
1385 __in unsigned int offset,
1386 __out_bcount(size) caddr_t data,
1389 extern __checkReturn efx_rc_t
1390 efx_nvram_set_version(
1391 __in efx_nic_t *enp,
1392 __in efx_nvram_type_t type,
1393 __in_ecount(4) uint16_t version[4]);
1395 /* Validate contents of TLV formatted partition */
1396 extern __checkReturn efx_rc_t
1397 efx_nvram_tlv_validate(
1398 __in efx_nic_t *enp,
1399 __in uint32_t partn,
1400 __in_bcount(partn_size) caddr_t partn_data,
1401 __in size_t partn_size);
1403 extern __checkReturn efx_rc_t
1405 __in efx_nic_t *enp,
1406 __in efx_nvram_type_t type);
1408 extern __checkReturn efx_rc_t
1409 efx_nvram_write_chunk(
1410 __in efx_nic_t *enp,
1411 __in efx_nvram_type_t type,
1412 __in unsigned int offset,
1413 __in_bcount(size) caddr_t data,
1418 __in efx_nic_t *enp);
1420 #endif /* EFSYS_OPT_NVRAM */
1422 #if EFSYS_OPT_BOOTCFG
1426 __in efx_nic_t *enp,
1427 __out_bcount(size) caddr_t data,
1432 __in efx_nic_t *enp,
1433 __in_bcount(size) caddr_t data,
1436 #endif /* EFSYS_OPT_BOOTCFG */
1440 typedef enum efx_wol_type_e {
1441 EFX_WOL_TYPE_INVALID,
1443 EFX_WOL_TYPE_BITMAP,
1448 typedef enum efx_lightsout_offload_type_e {
1449 EFX_LIGHTSOUT_OFFLOAD_TYPE_INVALID,
1450 EFX_LIGHTSOUT_OFFLOAD_TYPE_ARP,
1451 EFX_LIGHTSOUT_OFFLOAD_TYPE_NS,
1452 } efx_lightsout_offload_type_t;
1454 #define EFX_WOL_BITMAP_MASK_SIZE (48)
1455 #define EFX_WOL_BITMAP_VALUE_SIZE (128)
1457 typedef union efx_wol_param_u {
1459 uint8_t mac_addr[6];
1462 uint8_t mask[EFX_WOL_BITMAP_MASK_SIZE]; /* 1 bit per byte */
1463 uint8_t value[EFX_WOL_BITMAP_VALUE_SIZE]; /* value to match */
1468 typedef union efx_lightsout_offload_param_u {
1470 uint8_t mac_addr[6];
1474 uint8_t mac_addr[6];
1475 uint32_t solicited_node[4];
1478 } efx_lightsout_offload_param_t;
1480 extern __checkReturn efx_rc_t
1482 __in efx_nic_t *enp);
1484 extern __checkReturn efx_rc_t
1485 efx_wol_filter_clear(
1486 __in efx_nic_t *enp);
1488 extern __checkReturn efx_rc_t
1490 __in efx_nic_t *enp,
1491 __in efx_wol_type_t type,
1492 __in efx_wol_param_t *paramp,
1493 __out uint32_t *filter_idp);
1495 extern __checkReturn efx_rc_t
1496 efx_wol_filter_remove(
1497 __in efx_nic_t *enp,
1498 __in uint32_t filter_id);
1500 extern __checkReturn efx_rc_t
1501 efx_lightsout_offload_add(
1502 __in efx_nic_t *enp,
1503 __in efx_lightsout_offload_type_t type,
1504 __in efx_lightsout_offload_param_t *paramp,
1505 __out uint32_t *filter_idp);
1507 extern __checkReturn efx_rc_t
1508 efx_lightsout_offload_remove(
1509 __in efx_nic_t *enp,
1510 __in efx_lightsout_offload_type_t type,
1511 __in uint32_t filter_id);
1515 __in efx_nic_t *enp);
1517 #endif /* EFSYS_OPT_WOL */
1521 typedef enum efx_pattern_type_t {
1522 EFX_PATTERN_BYTE_INCREMENT = 0,
1523 EFX_PATTERN_ALL_THE_SAME,
1524 EFX_PATTERN_BIT_ALTERNATE,
1525 EFX_PATTERN_BYTE_ALTERNATE,
1526 EFX_PATTERN_BYTE_CHANGING,
1527 EFX_PATTERN_BIT_SWEEP,
1529 } efx_pattern_type_t;
1532 (*efx_sram_pattern_fn_t)(
1534 __in boolean_t negate,
1535 __out efx_qword_t *eqp);
1537 extern __checkReturn efx_rc_t
1539 __in efx_nic_t *enp,
1540 __in efx_pattern_type_t type);
1542 #endif /* EFSYS_OPT_DIAG */
1544 extern __checkReturn efx_rc_t
1545 efx_sram_buf_tbl_set(
1546 __in efx_nic_t *enp,
1548 __in efsys_mem_t *esmp,
1552 efx_sram_buf_tbl_clear(
1553 __in efx_nic_t *enp,
1557 #define EFX_BUF_TBL_SIZE 0x20000
1559 #define EFX_BUF_SIZE 4096
1563 typedef struct efx_evq_s efx_evq_t;
1565 #if EFSYS_OPT_QSTATS
1567 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1568 typedef enum efx_ev_qstat_e {
1574 EV_RX_PAUSE_FRM_ERR,
1575 EV_RX_BUF_OWNER_ID_ERR,
1576 EV_RX_IPV4_HDR_CHKSUM_ERR,
1577 EV_RX_TCP_UDP_CHKSUM_ERR,
1581 EV_RX_MCAST_HASH_MATCH,
1598 EV_DRIVER_SRM_UPD_DONE,
1599 EV_DRIVER_TX_DESCQ_FLS_DONE,
1600 EV_DRIVER_RX_DESCQ_FLS_DONE,
1601 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1602 EV_DRIVER_RX_DSC_ERROR,
1603 EV_DRIVER_TX_DSC_ERROR,
1609 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1611 #endif /* EFSYS_OPT_QSTATS */
1613 extern __checkReturn efx_rc_t
1615 __in efx_nic_t *enp);
1619 __in efx_nic_t *enp);
1621 #define EFX_EVQ_MAXNEVS 32768
1622 #define EFX_EVQ_MINNEVS 512
1624 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
1625 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1627 extern __checkReturn efx_rc_t
1629 __in efx_nic_t *enp,
1630 __in unsigned int index,
1631 __in efsys_mem_t *esmp,
1634 __deref_out efx_evq_t **eepp);
1638 __in efx_evq_t *eep,
1639 __in uint16_t data);
1641 typedef __checkReturn boolean_t
1642 (*efx_initialized_ev_t)(
1643 __in_opt void *arg);
1645 #define EFX_PKT_UNICAST 0x0004
1646 #define EFX_PKT_START 0x0008
1648 #define EFX_PKT_VLAN_TAGGED 0x0010
1649 #define EFX_CKSUM_TCPUDP 0x0020
1650 #define EFX_CKSUM_IPV4 0x0040
1651 #define EFX_PKT_CONT 0x0080
1653 #define EFX_CHECK_VLAN 0x0100
1654 #define EFX_PKT_TCP 0x0200
1655 #define EFX_PKT_UDP 0x0400
1656 #define EFX_PKT_IPV4 0x0800
1658 #define EFX_PKT_IPV6 0x1000
1659 #define EFX_PKT_PREFIX_LEN 0x2000
1660 #define EFX_ADDR_MISMATCH 0x4000
1661 #define EFX_DISCARD 0x8000
1663 #define EFX_EV_RX_NLABELS 32
1664 #define EFX_EV_TX_NLABELS 32
1666 typedef __checkReturn boolean_t
1669 __in uint32_t label,
1672 __in uint16_t flags);
1674 typedef __checkReturn boolean_t
1677 __in uint32_t label,
1680 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
1681 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
1682 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
1683 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
1684 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
1685 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
1686 #define EFX_EXCEPTION_RX_ERROR 0x00000007
1687 #define EFX_EXCEPTION_TX_ERROR 0x00000008
1688 #define EFX_EXCEPTION_EV_ERROR 0x00000009
1690 typedef __checkReturn boolean_t
1691 (*efx_exception_ev_t)(
1693 __in uint32_t label,
1694 __in uint32_t data);
1696 typedef __checkReturn boolean_t
1697 (*efx_rxq_flush_done_ev_t)(
1699 __in uint32_t rxq_index);
1701 typedef __checkReturn boolean_t
1702 (*efx_rxq_flush_failed_ev_t)(
1704 __in uint32_t rxq_index);
1706 typedef __checkReturn boolean_t
1707 (*efx_txq_flush_done_ev_t)(
1709 __in uint32_t txq_index);
1711 typedef __checkReturn boolean_t
1712 (*efx_software_ev_t)(
1714 __in uint16_t magic);
1716 typedef __checkReturn boolean_t
1719 __in uint32_t code);
1721 #define EFX_SRAM_CLEAR 0
1722 #define EFX_SRAM_UPDATE 1
1723 #define EFX_SRAM_ILLEGAL_CLEAR 2
1725 typedef __checkReturn boolean_t
1726 (*efx_wake_up_ev_t)(
1728 __in uint32_t label);
1730 typedef __checkReturn boolean_t
1733 __in uint32_t label);
1735 typedef __checkReturn boolean_t
1736 (*efx_link_change_ev_t)(
1738 __in efx_link_mode_t link_mode);
1740 #if EFSYS_OPT_MON_STATS
1742 typedef __checkReturn boolean_t
1743 (*efx_monitor_ev_t)(
1745 __in efx_mon_stat_t id,
1746 __in efx_mon_stat_value_t value);
1748 #endif /* EFSYS_OPT_MON_STATS */
1750 #if EFSYS_OPT_MAC_STATS
1752 typedef __checkReturn boolean_t
1753 (*efx_mac_stats_ev_t)(
1755 __in uint32_t generation
1758 #endif /* EFSYS_OPT_MAC_STATS */
1760 typedef struct efx_ev_callbacks_s {
1761 efx_initialized_ev_t eec_initialized;
1764 efx_exception_ev_t eec_exception;
1765 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
1766 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
1767 efx_txq_flush_done_ev_t eec_txq_flush_done;
1768 efx_software_ev_t eec_software;
1769 efx_sram_ev_t eec_sram;
1770 efx_wake_up_ev_t eec_wake_up;
1771 efx_timer_ev_t eec_timer;
1772 efx_link_change_ev_t eec_link_change;
1773 #if EFSYS_OPT_MON_STATS
1774 efx_monitor_ev_t eec_monitor;
1775 #endif /* EFSYS_OPT_MON_STATS */
1776 #if EFSYS_OPT_MAC_STATS
1777 efx_mac_stats_ev_t eec_mac_stats;
1778 #endif /* EFSYS_OPT_MAC_STATS */
1779 } efx_ev_callbacks_t;
1781 extern __checkReturn boolean_t
1783 __in efx_evq_t *eep,
1784 __in unsigned int count);
1786 #if EFSYS_OPT_EV_PREFETCH
1790 __in efx_evq_t *eep,
1791 __in unsigned int count);
1793 #endif /* EFSYS_OPT_EV_PREFETCH */
1797 __in efx_evq_t *eep,
1798 __inout unsigned int *countp,
1799 __in const efx_ev_callbacks_t *eecp,
1800 __in_opt void *arg);
1802 extern __checkReturn efx_rc_t
1804 __in efx_evq_t *eep,
1805 __in unsigned int us);
1807 extern __checkReturn efx_rc_t
1809 __in efx_evq_t *eep,
1810 __in unsigned int count);
1812 #if EFSYS_OPT_QSTATS
1818 __in efx_nic_t *enp,
1819 __in unsigned int id);
1821 #endif /* EFSYS_OPT_NAMES */
1824 efx_ev_qstats_update(
1825 __in efx_evq_t *eep,
1826 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
1828 #endif /* EFSYS_OPT_QSTATS */
1832 __in efx_evq_t *eep);
1836 extern __checkReturn efx_rc_t
1838 __inout efx_nic_t *enp);
1842 __in efx_nic_t *enp);
1844 #if EFSYS_OPT_RX_HDR_SPLIT
1845 __checkReturn efx_rc_t
1846 efx_rx_hdr_split_enable(
1847 __in efx_nic_t *enp,
1848 __in unsigned int hdr_buf_size,
1849 __in unsigned int pld_buf_size);
1851 #endif /* EFSYS_OPT_RX_HDR_SPLIT */
1853 #if EFSYS_OPT_RX_SCATTER
1854 __checkReturn efx_rc_t
1855 efx_rx_scatter_enable(
1856 __in efx_nic_t *enp,
1857 __in unsigned int buf_size);
1858 #endif /* EFSYS_OPT_RX_SCATTER */
1860 #if EFSYS_OPT_RX_SCALE
1862 typedef enum efx_rx_hash_alg_e {
1863 EFX_RX_HASHALG_LFSR = 0,
1864 EFX_RX_HASHALG_TOEPLITZ
1865 } efx_rx_hash_alg_t;
1867 typedef enum efx_rx_hash_type_e {
1868 EFX_RX_HASH_IPV4 = 0,
1869 EFX_RX_HASH_TCPIPV4,
1871 EFX_RX_HASH_TCPIPV6,
1872 } efx_rx_hash_type_t;
1874 typedef enum efx_rx_hash_support_e {
1875 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
1876 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
1877 } efx_rx_hash_support_t;
1879 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
1880 #define EFX_MAXRSS 64 /* RX indirection entry range */
1881 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
1883 typedef enum efx_rx_scale_support_e {
1884 EFX_RX_SCALE_UNAVAILABLE = 0, /* Not supported */
1885 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
1886 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
1887 } efx_rx_scale_support_t;
1889 extern __checkReturn efx_rc_t
1890 efx_rx_hash_support_get(
1891 __in efx_nic_t *enp,
1892 __out efx_rx_hash_support_t *supportp);
1895 extern __checkReturn efx_rc_t
1896 efx_rx_scale_support_get(
1897 __in efx_nic_t *enp,
1898 __out efx_rx_scale_support_t *supportp);
1900 extern __checkReturn efx_rc_t
1901 efx_rx_scale_mode_set(
1902 __in efx_nic_t *enp,
1903 __in efx_rx_hash_alg_t alg,
1904 __in efx_rx_hash_type_t type,
1905 __in boolean_t insert);
1907 extern __checkReturn efx_rc_t
1908 efx_rx_scale_tbl_set(
1909 __in efx_nic_t *enp,
1910 __in_ecount(n) unsigned int *table,
1913 extern __checkReturn efx_rc_t
1914 efx_rx_scale_key_set(
1915 __in efx_nic_t *enp,
1916 __in_ecount(n) uint8_t *key,
1920 efx_psuedo_hdr_hash_get(
1921 __in efx_nic_t *enp,
1922 __in efx_rx_hash_alg_t func,
1923 __in uint8_t *buffer);
1925 #endif /* EFSYS_OPT_RX_SCALE */
1927 extern __checkReturn efx_rc_t
1928 efx_psuedo_hdr_pkt_length_get(
1929 __in efx_nic_t *enp,
1930 __in uint8_t *buffer,
1931 __out uint16_t *pkt_lengthp);
1933 #define EFX_RXQ_MAXNDESCS 4096
1934 #define EFX_RXQ_MINNDESCS 512
1936 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
1937 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1938 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
1939 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
1941 typedef enum efx_rxq_type_e {
1942 EFX_RXQ_TYPE_DEFAULT,
1943 EFX_RXQ_TYPE_SPLIT_HEADER,
1944 EFX_RXQ_TYPE_SPLIT_PAYLOAD,
1945 EFX_RXQ_TYPE_SCATTER,
1949 extern __checkReturn efx_rc_t
1951 __in efx_nic_t *enp,
1952 __in unsigned int index,
1953 __in unsigned int label,
1954 __in efx_rxq_type_t type,
1955 __in efsys_mem_t *esmp,
1958 __in efx_evq_t *eep,
1959 __deref_out efx_rxq_t **erpp);
1961 typedef struct efx_buffer_s {
1962 efsys_dma_addr_t eb_addr;
1967 typedef struct efx_desc_s {
1973 __in efx_rxq_t *erp,
1974 __in_ecount(n) efsys_dma_addr_t *addrp,
1976 __in unsigned int n,
1977 __in unsigned int completed,
1978 __in unsigned int added);
1982 __in efx_rxq_t *erp,
1983 __in unsigned int added,
1984 __inout unsigned int *pushedp);
1986 extern __checkReturn efx_rc_t
1988 __in efx_rxq_t *erp);
1992 __in efx_rxq_t *erp);
1996 __in efx_rxq_t *erp);
2000 typedef struct efx_txq_s efx_txq_t;
2002 #if EFSYS_OPT_QSTATS
2004 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
2005 typedef enum efx_tx_qstat_e {
2011 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
2013 #endif /* EFSYS_OPT_QSTATS */
2015 extern __checkReturn efx_rc_t
2017 __in efx_nic_t *enp);
2021 __in efx_nic_t *enp);
2023 #define EFX_BUG35388_WORKAROUND(_encp) \
2024 (((_encp) == NULL) ? 1 : ((_encp)->enc_bug35388_workaround != 0))
2026 #define EFX_TXQ_MAXNDESCS(_encp) \
2027 ((EFX_BUG35388_WORKAROUND(_encp)) ? 2048 : 4096)
2029 #define EFX_TXQ_MINNDESCS 512
2031 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2032 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2033 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2034 #define EFX_TXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
2036 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2038 #define EFX_TXQ_CKSUM_IPV4 0x0001
2039 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
2041 extern __checkReturn efx_rc_t
2043 __in efx_nic_t *enp,
2044 __in unsigned int index,
2045 __in unsigned int label,
2046 __in efsys_mem_t *esmp,
2049 __in uint16_t flags,
2050 __in efx_evq_t *eep,
2051 __deref_out efx_txq_t **etpp,
2052 __out unsigned int *addedp);
2054 extern __checkReturn efx_rc_t
2056 __in efx_txq_t *etp,
2057 __in_ecount(n) efx_buffer_t *eb,
2058 __in unsigned int n,
2059 __in unsigned int completed,
2060 __inout unsigned int *addedp);
2062 extern __checkReturn efx_rc_t
2064 __in efx_txq_t *etp,
2065 __in unsigned int ns);
2069 __in efx_txq_t *etp,
2070 __in unsigned int added,
2071 __in unsigned int pushed);
2073 extern __checkReturn efx_rc_t
2075 __in efx_txq_t *etp);
2079 __in efx_txq_t *etp);
2081 extern __checkReturn efx_rc_t
2083 __in efx_txq_t *etp);
2086 efx_tx_qpio_disable(
2087 __in efx_txq_t *etp);
2089 extern __checkReturn efx_rc_t
2091 __in efx_txq_t *etp,
2092 __in_ecount(buf_length) uint8_t *buffer,
2093 __in size_t buf_length,
2094 __in size_t pio_buf_offset);
2096 extern __checkReturn efx_rc_t
2098 __in efx_txq_t *etp,
2099 __in size_t pkt_length,
2100 __in unsigned int completed,
2101 __inout unsigned int *addedp);
2103 extern __checkReturn efx_rc_t
2105 __in efx_txq_t *etp,
2106 __in_ecount(n) efx_desc_t *ed,
2107 __in unsigned int n,
2108 __in unsigned int completed,
2109 __inout unsigned int *addedp);
2112 efx_tx_qdesc_dma_create(
2113 __in efx_txq_t *etp,
2114 __in efsys_dma_addr_t addr,
2117 __out efx_desc_t *edp);
2120 efx_tx_qdesc_tso_create(
2121 __in efx_txq_t *etp,
2122 __in uint16_t ipv4_id,
2123 __in uint32_t tcp_seq,
2124 __in uint8_t tcp_flags,
2125 __out efx_desc_t *edp);
2128 efx_tx_qdesc_vlantci_create(
2129 __in efx_txq_t *etp,
2131 __out efx_desc_t *edp);
2133 #if EFSYS_OPT_QSTATS
2139 __in efx_nic_t *etp,
2140 __in unsigned int id);
2142 #endif /* EFSYS_OPT_NAMES */
2145 efx_tx_qstats_update(
2146 __in efx_txq_t *etp,
2147 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
2149 #endif /* EFSYS_OPT_QSTATS */
2153 __in efx_txq_t *etp);
2158 #if EFSYS_OPT_FILTER
2160 #define EFX_ETHER_TYPE_IPV4 0x0800
2161 #define EFX_ETHER_TYPE_IPV6 0x86DD
2163 #define EFX_IPPROTO_TCP 6
2164 #define EFX_IPPROTO_UDP 17
2166 typedef enum efx_filter_flag_e {
2167 EFX_FILTER_FLAG_RX_RSS = 0x01, /* use RSS to spread across
2168 * multiple queues */
2169 EFX_FILTER_FLAG_RX_SCATTER = 0x02, /* enable RX scatter */
2170 EFX_FILTER_FLAG_RX_OVER_AUTO = 0x04, /* Override an automatic filter
2171 * (priority EFX_FILTER_PRI_AUTO).
2172 * May only be set by the filter
2173 * implementation for each type.
2174 * A removal request will
2175 * restore the automatic filter
2177 EFX_FILTER_FLAG_RX = 0x08, /* Filter is for RX */
2178 EFX_FILTER_FLAG_TX = 0x10, /* Filter is for TX */
2179 } efx_filter_flag_t;
2181 typedef enum efx_filter_match_flags_e {
2182 EFX_FILTER_MATCH_REM_HOST = 0x0001, /* Match by remote IP host
2184 EFX_FILTER_MATCH_LOC_HOST = 0x0002, /* Match by local IP host
2186 EFX_FILTER_MATCH_REM_MAC = 0x0004, /* Match by remote MAC address */
2187 EFX_FILTER_MATCH_REM_PORT = 0x0008, /* Match by remote TCP/UDP port */
2188 EFX_FILTER_MATCH_LOC_MAC = 0x0010, /* Match by remote TCP/UDP port */
2189 EFX_FILTER_MATCH_LOC_PORT = 0x0020, /* Match by local TCP/UDP port */
2190 EFX_FILTER_MATCH_ETHER_TYPE = 0x0040, /* Match by Ether-type */
2191 EFX_FILTER_MATCH_INNER_VID = 0x0080, /* Match by inner VLAN ID */
2192 EFX_FILTER_MATCH_OUTER_VID = 0x0100, /* Match by outer VLAN ID */
2193 EFX_FILTER_MATCH_IP_PROTO = 0x0200, /* Match by IP transport
2195 EFX_FILTER_MATCH_LOC_MAC_IG = 0x0400, /* Match by local MAC address
2196 * I/G bit. Used for RX default
2197 * unicast and multicast/
2198 * broadcast filters. */
2199 } efx_filter_match_flags_t;
2201 typedef enum efx_filter_priority_s {
2202 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
2203 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
2204 * address list or hardware
2205 * requirements. This may only be used
2206 * by the filter implementation for
2208 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
2209 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
2210 * client (e.g. SR-IOV, HyperV VMQ etc.)
2212 } efx_filter_priority_t;
2215 * FIXME: All these fields are assumed to be in little-endian byte order.
2216 * It may be better for some to be big-endian. See bug42804.
2219 typedef struct efx_filter_spec_s {
2220 uint32_t efs_match_flags:12;
2221 uint32_t efs_priority:2;
2222 uint32_t efs_flags:6;
2223 uint32_t efs_dmaq_id:12;
2224 uint32_t efs_rss_context;
2225 uint16_t efs_outer_vid;
2226 uint16_t efs_inner_vid;
2227 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
2228 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
2229 uint16_t efs_ether_type;
2230 uint8_t efs_ip_proto;
2231 uint16_t efs_loc_port;
2232 uint16_t efs_rem_port;
2233 efx_oword_t efs_rem_host;
2234 efx_oword_t efs_loc_host;
2235 } efx_filter_spec_t;
2238 /* Default values for use in filter specifications */
2239 #define EFX_FILTER_SPEC_RSS_CONTEXT_DEFAULT 0xffffffff
2240 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
2241 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
2243 extern __checkReturn efx_rc_t
2245 __in efx_nic_t *enp);
2249 __in efx_nic_t *enp);
2251 extern __checkReturn efx_rc_t
2253 __in efx_nic_t *enp,
2254 __inout efx_filter_spec_t *spec);
2256 extern __checkReturn efx_rc_t
2258 __in efx_nic_t *enp,
2259 __inout efx_filter_spec_t *spec);
2261 extern __checkReturn efx_rc_t
2263 __in efx_nic_t *enp);
2265 extern __checkReturn efx_rc_t
2266 efx_filter_supported_filters(
2267 __in efx_nic_t *enp,
2268 __out uint32_t *list,
2269 __out size_t *length);
2272 efx_filter_spec_init_rx(
2273 __inout efx_filter_spec_t *spec,
2274 __in efx_filter_priority_t priority,
2275 __in efx_filter_flag_t flags,
2276 __in efx_rxq_t *erp);
2279 efx_filter_spec_init_tx(
2280 __inout efx_filter_spec_t *spec,
2281 __in efx_txq_t *etp);
2283 extern __checkReturn efx_rc_t
2284 efx_filter_spec_set_ipv4_local(
2285 __inout efx_filter_spec_t *spec,
2288 __in uint16_t port);
2290 extern __checkReturn efx_rc_t
2291 efx_filter_spec_set_ipv4_full(
2292 __inout efx_filter_spec_t *spec,
2294 __in uint32_t lhost,
2295 __in uint16_t lport,
2296 __in uint32_t rhost,
2297 __in uint16_t rport);
2299 extern __checkReturn efx_rc_t
2300 efx_filter_spec_set_eth_local(
2301 __inout efx_filter_spec_t *spec,
2303 __in const uint8_t *addr);
2305 extern __checkReturn efx_rc_t
2306 efx_filter_spec_set_uc_def(
2307 __inout efx_filter_spec_t *spec);
2309 extern __checkReturn efx_rc_t
2310 efx_filter_spec_set_mc_def(
2311 __inout efx_filter_spec_t *spec);
2313 #endif /* EFSYS_OPT_FILTER */
2317 extern __checkReturn uint32_t
2319 __in_ecount(count) uint32_t const *input,
2321 __in uint32_t init);
2323 extern __checkReturn uint32_t
2325 __in_ecount(length) uint8_t const *input,
2327 __in uint32_t init);
2334 #endif /* _SYS_EFX_H */