2 * Copyright (c) 2006-2015 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
37 #include "efx_check.h"
38 #include "efx_phy_ids.h"
44 #define EFX_STATIC_ASSERT(_cond) \
45 ((void)sizeof(char[(_cond) ? 1 : -1]))
47 #define EFX_ARRAY_SIZE(_array) \
48 (sizeof(_array) / sizeof((_array)[0]))
50 #define EFX_FIELD_OFFSET(_type, _field) \
51 ((size_t) &(((_type *)0)->_field))
55 typedef __success(return == 0) int efx_rc_t;
60 typedef enum efx_family_e {
62 EFX_FAMILY_FALCON, /* Obsolete and not supported */
64 EFX_FAMILY_HUNTINGTON,
69 extern __checkReturn efx_rc_t
73 __out efx_family_t *efp);
76 #define EFX_PCI_VENID_SFC 0x1924
78 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
80 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
81 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
82 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
84 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
85 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
86 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
88 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
89 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
91 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
92 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
93 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
102 EFX_ERR_BUFID_DC_OOB,
115 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
116 extern __checkReturn uint32_t
118 __in uint32_t crc_init,
119 __in_ecount(length) uint8_t const *input,
123 /* Type prototypes */
125 typedef struct efx_rxq_s efx_rxq_t;
129 typedef struct efx_nic_s efx_nic_t;
131 #define EFX_NIC_FUNC_PRIMARY 0x00000001
132 #define EFX_NIC_FUNC_LINKCTRL 0x00000002
133 #define EFX_NIC_FUNC_TRUSTED 0x00000004
136 extern __checkReturn efx_rc_t
138 __in efx_family_t family,
139 __in efsys_identifier_t *esip,
140 __in efsys_bar_t *esbp,
141 __in efsys_lock_t *eslp,
142 __deref_out efx_nic_t **enpp);
144 extern __checkReturn efx_rc_t
146 __in efx_nic_t *enp);
148 extern __checkReturn efx_rc_t
150 __in efx_nic_t *enp);
152 extern __checkReturn efx_rc_t
154 __in efx_nic_t *enp);
158 extern __checkReturn efx_rc_t
159 efx_nic_register_test(
160 __in efx_nic_t *enp);
162 #endif /* EFSYS_OPT_DIAG */
166 __in efx_nic_t *enp);
170 __in efx_nic_t *enp);
174 __in efx_nic_t *enp);
178 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
179 /* Huntington and Medford require MCDIv2 commands */
180 #define WITH_MCDI_V2 1
183 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
185 typedef enum efx_mcdi_exception_e {
186 EFX_MCDI_EXCEPTION_MC_REBOOT,
187 EFX_MCDI_EXCEPTION_MC_BADASSERT,
188 } efx_mcdi_exception_t;
190 #if EFSYS_OPT_MCDI_LOGGING
191 typedef enum efx_log_msg_e
194 EFX_LOG_MCDI_REQUEST,
195 EFX_LOG_MCDI_RESPONSE,
197 #endif /* EFSYS_OPT_MCDI_LOGGING */
199 typedef struct efx_mcdi_transport_s {
201 efsys_mem_t *emt_dma_mem;
202 void (*emt_execute)(void *, efx_mcdi_req_t *);
203 void (*emt_ev_cpl)(void *);
204 void (*emt_exception)(void *, efx_mcdi_exception_t);
205 #if EFSYS_OPT_MCDI_LOGGING
206 void (*emt_logger)(void *, efx_log_msg_t,
207 void *, size_t, void *, size_t);
208 #endif /* EFSYS_OPT_MCDI_LOGGING */
209 #if EFSYS_OPT_MCDI_PROXY_AUTH
210 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
211 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
212 } efx_mcdi_transport_t;
214 extern __checkReturn efx_rc_t
217 __in const efx_mcdi_transport_t *mtp);
219 extern __checkReturn efx_rc_t
221 __in efx_nic_t *enp);
225 __in efx_nic_t *enp);
228 efx_mcdi_request_start(
230 __in efx_mcdi_req_t *emrp,
231 __in boolean_t ev_cpl);
233 extern __checkReturn boolean_t
234 efx_mcdi_request_poll(
235 __in efx_nic_t *enp);
237 extern __checkReturn boolean_t
238 efx_mcdi_request_abort(
239 __in efx_nic_t *enp);
243 __in efx_nic_t *enp);
245 #endif /* EFSYS_OPT_MCDI */
249 #define EFX_NINTR_SIENA 1024
251 typedef enum efx_intr_type_e {
252 EFX_INTR_INVALID = 0,
258 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
260 extern __checkReturn efx_rc_t
263 __in efx_intr_type_t type,
264 __in efsys_mem_t *esmp);
268 __in efx_nic_t *enp);
272 __in efx_nic_t *enp);
275 efx_intr_disable_unlocked(
276 __in efx_nic_t *enp);
278 #define EFX_INTR_NEVQS 32
280 extern __checkReturn efx_rc_t
283 __in unsigned int level);
286 efx_intr_status_line(
288 __out boolean_t *fatalp,
289 __out uint32_t *maskp);
292 efx_intr_status_message(
294 __in unsigned int message,
295 __out boolean_t *fatalp);
299 __in efx_nic_t *enp);
303 __in efx_nic_t *enp);
307 #if EFSYS_OPT_MAC_STATS
309 /* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */
310 typedef enum efx_mac_stat_e {
313 EFX_MAC_RX_UNICST_PKTS,
314 EFX_MAC_RX_MULTICST_PKTS,
315 EFX_MAC_RX_BRDCST_PKTS,
316 EFX_MAC_RX_PAUSE_PKTS,
317 EFX_MAC_RX_LE_64_PKTS,
318 EFX_MAC_RX_65_TO_127_PKTS,
319 EFX_MAC_RX_128_TO_255_PKTS,
320 EFX_MAC_RX_256_TO_511_PKTS,
321 EFX_MAC_RX_512_TO_1023_PKTS,
322 EFX_MAC_RX_1024_TO_15XX_PKTS,
323 EFX_MAC_RX_GE_15XX_PKTS,
325 EFX_MAC_RX_FCS_ERRORS,
326 EFX_MAC_RX_DROP_EVENTS,
327 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
328 EFX_MAC_RX_SYMBOL_ERRORS,
329 EFX_MAC_RX_ALIGN_ERRORS,
330 EFX_MAC_RX_INTERNAL_ERRORS,
331 EFX_MAC_RX_JABBER_PKTS,
332 EFX_MAC_RX_LANE0_CHAR_ERR,
333 EFX_MAC_RX_LANE1_CHAR_ERR,
334 EFX_MAC_RX_LANE2_CHAR_ERR,
335 EFX_MAC_RX_LANE3_CHAR_ERR,
336 EFX_MAC_RX_LANE0_DISP_ERR,
337 EFX_MAC_RX_LANE1_DISP_ERR,
338 EFX_MAC_RX_LANE2_DISP_ERR,
339 EFX_MAC_RX_LANE3_DISP_ERR,
340 EFX_MAC_RX_MATCH_FAULT,
341 EFX_MAC_RX_NODESC_DROP_CNT,
344 EFX_MAC_TX_UNICST_PKTS,
345 EFX_MAC_TX_MULTICST_PKTS,
346 EFX_MAC_TX_BRDCST_PKTS,
347 EFX_MAC_TX_PAUSE_PKTS,
348 EFX_MAC_TX_LE_64_PKTS,
349 EFX_MAC_TX_65_TO_127_PKTS,
350 EFX_MAC_TX_128_TO_255_PKTS,
351 EFX_MAC_TX_256_TO_511_PKTS,
352 EFX_MAC_TX_512_TO_1023_PKTS,
353 EFX_MAC_TX_1024_TO_15XX_PKTS,
354 EFX_MAC_TX_GE_15XX_PKTS,
356 EFX_MAC_TX_SGL_COL_PKTS,
357 EFX_MAC_TX_MULT_COL_PKTS,
358 EFX_MAC_TX_EX_COL_PKTS,
359 EFX_MAC_TX_LATE_COL_PKTS,
361 EFX_MAC_TX_EX_DEF_PKTS,
362 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
363 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
364 EFX_MAC_PM_TRUNC_VFIFO_FULL,
365 EFX_MAC_PM_DISCARD_VFIFO_FULL,
366 EFX_MAC_PM_TRUNC_QBB,
367 EFX_MAC_PM_DISCARD_QBB,
368 EFX_MAC_PM_DISCARD_MAPPING,
369 EFX_MAC_RXDP_Q_DISABLED_PKTS,
370 EFX_MAC_RXDP_DI_DROPPED_PKTS,
371 EFX_MAC_RXDP_STREAMING_PKTS,
372 EFX_MAC_RXDP_HLB_FETCH,
373 EFX_MAC_RXDP_HLB_WAIT,
374 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
375 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
376 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
377 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
378 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
379 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
380 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
381 EFX_MAC_VADAPTER_RX_BAD_BYTES,
382 EFX_MAC_VADAPTER_RX_OVERFLOW,
383 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
384 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
385 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
386 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
387 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
388 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
389 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
390 EFX_MAC_VADAPTER_TX_BAD_BYTES,
391 EFX_MAC_VADAPTER_TX_OVERFLOW,
395 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
397 #endif /* EFSYS_OPT_MAC_STATS */
399 typedef enum efx_link_mode_e {
400 EFX_LINK_UNKNOWN = 0,
413 #define EFX_MAC_ADDR_LEN 6
415 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t*)_address)[0] & 0x01)
417 #define EFX_MAC_MULTICAST_LIST_MAX 256
419 #define EFX_MAC_SDU_MAX 9202
421 #define EFX_MAC_PDU(_sdu) \
426 + /* bug16011 */ 16), \
429 #define EFX_MAC_PDU_MIN 60
430 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
432 extern __checkReturn efx_rc_t
437 extern __checkReturn efx_rc_t
442 extern __checkReturn efx_rc_t
445 __in boolean_t all_unicst,
446 __in boolean_t mulcst,
447 __in boolean_t all_mulcst,
448 __in boolean_t brdcst);
450 extern __checkReturn efx_rc_t
451 efx_mac_multicast_list_set(
453 __in_ecount(6*count) uint8_t const *addrs,
456 extern __checkReturn efx_rc_t
457 efx_mac_filter_default_rxq_set(
460 __in boolean_t using_rss);
463 efx_mac_filter_default_rxq_clear(
464 __in efx_nic_t *enp);
466 extern __checkReturn efx_rc_t
469 __in boolean_t enabled);
471 extern __checkReturn efx_rc_t
474 __out boolean_t *mac_upp);
476 #define EFX_FCNTL_RESPOND 0x00000001
477 #define EFX_FCNTL_GENERATE 0x00000002
479 extern __checkReturn efx_rc_t
482 __in unsigned int fcntl,
483 __in boolean_t autoneg);
488 __out unsigned int *fcntl_wantedp,
489 __out unsigned int *fcntl_linkp);
492 #if EFSYS_OPT_MAC_STATS
496 extern __checkReturn const char *
499 __in unsigned int id);
501 #endif /* EFSYS_OPT_NAMES */
503 #define EFX_MAC_STATS_SIZE 0x400
506 * Upload mac statistics supported by the hardware into the given buffer.
508 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes,
511 * The hardware will only DMA statistics that it understands (of course).
512 * Drivers should not make any assumptions about which statistics are
513 * supported, especially when the statistics are generated by firmware.
515 * Thus, drivers should zero this buffer before use, so that not-understood
516 * statistics read back as zero.
518 extern __checkReturn efx_rc_t
519 efx_mac_stats_upload(
521 __in efsys_mem_t *esmp);
523 extern __checkReturn efx_rc_t
524 efx_mac_stats_periodic(
526 __in efsys_mem_t *esmp,
527 __in uint16_t period_ms,
528 __in boolean_t events);
530 extern __checkReturn efx_rc_t
531 efx_mac_stats_update(
533 __in efsys_mem_t *esmp,
534 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
535 __inout_opt uint32_t *generationp);
537 #endif /* EFSYS_OPT_MAC_STATS */
541 typedef enum efx_mon_type_e {
553 __in efx_nic_t *enp);
555 #endif /* EFSYS_OPT_NAMES */
557 extern __checkReturn efx_rc_t
559 __in efx_nic_t *enp);
561 #if EFSYS_OPT_MON_STATS
563 #define EFX_MON_STATS_PAGE_SIZE 0x100
564 #define EFX_MON_MASK_ELEMENT_SIZE 32
566 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 5d4ee5185e419abe */
567 typedef enum efx_mon_stat_e {
574 EFX_MON_STAT_EXT_TEMP,
575 EFX_MON_STAT_INT_TEMP,
578 EFX_MON_STAT_INT_COOLING,
579 EFX_MON_STAT_EXT_COOLING,
587 EFX_MON_STAT_AOE_TEMP,
588 EFX_MON_STAT_PSU_AOE_TEMP,
589 EFX_MON_STAT_PSU_TEMP,
595 EFX_MON_STAT_VAOE_IN,
597 EFX_MON_STAT_IAOE_IN,
598 EFX_MON_STAT_NIC_POWER,
602 EFX_MON_STAT_0_9V_ADC,
603 EFX_MON_STAT_INT_TEMP2,
604 EFX_MON_STAT_VREG_TEMP,
605 EFX_MON_STAT_VREG_0_9V_TEMP,
606 EFX_MON_STAT_VREG_1_2V_TEMP,
607 EFX_MON_STAT_INT_VPTAT,
608 EFX_MON_STAT_INT_ADC_TEMP,
609 EFX_MON_STAT_EXT_VPTAT,
610 EFX_MON_STAT_EXT_ADC_TEMP,
611 EFX_MON_STAT_AMBIENT_TEMP,
612 EFX_MON_STAT_AIRFLOW,
613 EFX_MON_STAT_VDD08D_VSS08D_CSR,
614 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
615 EFX_MON_STAT_HOTPOINT_TEMP,
616 EFX_MON_STAT_PHY_POWER_SWITCH_PORT0,
617 EFX_MON_STAT_PHY_POWER_SWITCH_PORT1,
618 EFX_MON_STAT_MUM_VCC,
621 EFX_MON_STAT_0V9_A_TEMP,
624 EFX_MON_STAT_0V9_B_TEMP,
625 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
626 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,
627 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
628 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,
629 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
630 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
631 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,
632 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,
633 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
634 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
635 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,
636 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,
637 EFX_MON_STAT_SODIMM_VOUT,
638 EFX_MON_STAT_SODIMM_0_TEMP,
639 EFX_MON_STAT_SODIMM_1_TEMP,
640 EFX_MON_STAT_PHY0_VCC,
641 EFX_MON_STAT_PHY1_VCC,
642 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
643 EFX_MON_STAT_BOARD_FRONT_TEMP,
644 EFX_MON_STAT_BOARD_BACK_TEMP,
648 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
650 typedef enum efx_mon_stat_state_e {
651 EFX_MON_STAT_STATE_OK = 0,
652 EFX_MON_STAT_STATE_WARNING = 1,
653 EFX_MON_STAT_STATE_FATAL = 2,
654 EFX_MON_STAT_STATE_BROKEN = 3,
655 EFX_MON_STAT_STATE_NO_READING = 4,
656 } efx_mon_stat_state_t;
658 typedef struct efx_mon_stat_value_s {
661 } efx_mon_stat_value_t;
668 __in efx_mon_stat_t id);
670 #endif /* EFSYS_OPT_NAMES */
672 extern __checkReturn efx_rc_t
673 efx_mon_stats_update(
675 __in efsys_mem_t *esmp,
676 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
678 #endif /* EFSYS_OPT_MON_STATS */
682 __in efx_nic_t *enp);
686 extern __checkReturn efx_rc_t
688 __in efx_nic_t *enp);
690 #if EFSYS_OPT_PHY_LED_CONTROL
692 typedef enum efx_phy_led_mode_e {
693 EFX_PHY_LED_DEFAULT = 0,
698 } efx_phy_led_mode_t;
700 extern __checkReturn efx_rc_t
703 __in efx_phy_led_mode_t mode);
705 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
707 extern __checkReturn efx_rc_t
709 __in efx_nic_t *enp);
711 #if EFSYS_OPT_LOOPBACK
713 typedef enum efx_loopback_type_e {
714 EFX_LOOPBACK_OFF = 0,
715 EFX_LOOPBACK_DATA = 1,
716 EFX_LOOPBACK_GMAC = 2,
717 EFX_LOOPBACK_XGMII = 3,
718 EFX_LOOPBACK_XGXS = 4,
719 EFX_LOOPBACK_XAUI = 5,
720 EFX_LOOPBACK_GMII = 6,
721 EFX_LOOPBACK_SGMII = 7,
722 EFX_LOOPBACK_XGBR = 8,
723 EFX_LOOPBACK_XFI = 9,
724 EFX_LOOPBACK_XAUI_FAR = 10,
725 EFX_LOOPBACK_GMII_FAR = 11,
726 EFX_LOOPBACK_SGMII_FAR = 12,
727 EFX_LOOPBACK_XFI_FAR = 13,
728 EFX_LOOPBACK_GPHY = 14,
729 EFX_LOOPBACK_PHY_XS = 15,
730 EFX_LOOPBACK_PCS = 16,
731 EFX_LOOPBACK_PMA_PMD = 17,
732 EFX_LOOPBACK_XPORT = 18,
733 EFX_LOOPBACK_XGMII_WS = 19,
734 EFX_LOOPBACK_XAUI_WS = 20,
735 EFX_LOOPBACK_XAUI_WS_FAR = 21,
736 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
737 EFX_LOOPBACK_GMII_WS = 23,
738 EFX_LOOPBACK_XFI_WS = 24,
739 EFX_LOOPBACK_XFI_WS_FAR = 25,
740 EFX_LOOPBACK_PHYXS_WS = 26,
741 EFX_LOOPBACK_PMA_INT = 27,
742 EFX_LOOPBACK_SD_NEAR = 28,
743 EFX_LOOPBACK_SD_FAR = 29,
744 EFX_LOOPBACK_PMA_INT_WS = 30,
745 EFX_LOOPBACK_SD_FEP2_WS = 31,
746 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
747 EFX_LOOPBACK_SD_FEP_WS = 33,
748 EFX_LOOPBACK_SD_FES_WS = 34,
750 } efx_loopback_type_t;
752 typedef enum efx_loopback_kind_e {
753 EFX_LOOPBACK_KIND_OFF = 0,
754 EFX_LOOPBACK_KIND_ALL,
755 EFX_LOOPBACK_KIND_MAC,
756 EFX_LOOPBACK_KIND_PHY,
758 } efx_loopback_kind_t;
762 __in efx_loopback_kind_t loopback_kind,
763 __out efx_qword_t *maskp);
765 extern __checkReturn efx_rc_t
766 efx_port_loopback_set(
768 __in efx_link_mode_t link_mode,
769 __in efx_loopback_type_t type);
773 extern __checkReturn const char *
774 efx_loopback_type_name(
776 __in efx_loopback_type_t type);
778 #endif /* EFSYS_OPT_NAMES */
780 #endif /* EFSYS_OPT_LOOPBACK */
782 extern __checkReturn efx_rc_t
785 __out_opt efx_link_mode_t *link_modep);
789 __in efx_nic_t *enp);
791 typedef enum efx_phy_cap_type_e {
792 EFX_PHY_CAP_INVALID = 0,
799 EFX_PHY_CAP_10000FDX,
803 EFX_PHY_CAP_40000FDX,
805 } efx_phy_cap_type_t;
808 #define EFX_PHY_CAP_CURRENT 0x00000000
809 #define EFX_PHY_CAP_DEFAULT 0x00000001
810 #define EFX_PHY_CAP_PERM 0x00000002
816 __out uint32_t *maskp);
818 extern __checkReturn efx_rc_t
826 __out uint32_t *maskp);
828 extern __checkReturn efx_rc_t
831 __out uint32_t *ouip);
833 typedef enum efx_phy_media_type_e {
834 EFX_PHY_MEDIA_INVALID = 0,
839 EFX_PHY_MEDIA_SFP_PLUS,
840 EFX_PHY_MEDIA_BASE_T,
841 EFX_PHY_MEDIA_QSFP_PLUS,
843 } efx_phy_media_type_t;
845 /* Get the type of medium currently used. If the board has ports for
846 * modules, a module is present, and we recognise the media type of
847 * the module, then this will be the media type of the module.
848 * Otherwise it will be the media type of the port.
851 efx_phy_media_type_get(
853 __out efx_phy_media_type_t *typep);
856 efx_phy_module_get_info(
858 __in uint8_t dev_addr,
861 __out_bcount(len) uint8_t *data);
863 #if EFSYS_OPT_PHY_STATS
865 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
866 typedef enum efx_phy_stat_e {
868 EFX_PHY_STAT_PMA_PMD_LINK_UP,
869 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
870 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
871 EFX_PHY_STAT_PMA_PMD_REV_A,
872 EFX_PHY_STAT_PMA_PMD_REV_B,
873 EFX_PHY_STAT_PMA_PMD_REV_C,
874 EFX_PHY_STAT_PMA_PMD_REV_D,
875 EFX_PHY_STAT_PCS_LINK_UP,
876 EFX_PHY_STAT_PCS_RX_FAULT,
877 EFX_PHY_STAT_PCS_TX_FAULT,
878 EFX_PHY_STAT_PCS_BER,
879 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
880 EFX_PHY_STAT_PHY_XS_LINK_UP,
881 EFX_PHY_STAT_PHY_XS_RX_FAULT,
882 EFX_PHY_STAT_PHY_XS_TX_FAULT,
883 EFX_PHY_STAT_PHY_XS_ALIGN,
884 EFX_PHY_STAT_PHY_XS_SYNC_A,
885 EFX_PHY_STAT_PHY_XS_SYNC_B,
886 EFX_PHY_STAT_PHY_XS_SYNC_C,
887 EFX_PHY_STAT_PHY_XS_SYNC_D,
888 EFX_PHY_STAT_AN_LINK_UP,
889 EFX_PHY_STAT_AN_MASTER,
890 EFX_PHY_STAT_AN_LOCAL_RX_OK,
891 EFX_PHY_STAT_AN_REMOTE_RX_OK,
892 EFX_PHY_STAT_CL22EXT_LINK_UP,
897 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
898 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
899 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
900 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
901 EFX_PHY_STAT_AN_COMPLETE,
902 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
903 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
904 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
905 EFX_PHY_STAT_PCS_FW_VERSION_0,
906 EFX_PHY_STAT_PCS_FW_VERSION_1,
907 EFX_PHY_STAT_PCS_FW_VERSION_2,
908 EFX_PHY_STAT_PCS_FW_VERSION_3,
909 EFX_PHY_STAT_PCS_FW_BUILD_YY,
910 EFX_PHY_STAT_PCS_FW_BUILD_MM,
911 EFX_PHY_STAT_PCS_FW_BUILD_DD,
912 EFX_PHY_STAT_PCS_OP_MODE,
916 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
923 __in efx_phy_stat_t stat);
925 #endif /* EFSYS_OPT_NAMES */
927 #define EFX_PHY_STATS_SIZE 0x100
929 extern __checkReturn efx_rc_t
930 efx_phy_stats_update(
932 __in efsys_mem_t *esmp,
933 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
935 #endif /* EFSYS_OPT_PHY_STATS */
940 typedef enum efx_bist_type_e {
941 EFX_BIST_TYPE_UNKNOWN,
942 EFX_BIST_TYPE_PHY_NORMAL,
943 EFX_BIST_TYPE_PHY_CABLE_SHORT,
944 EFX_BIST_TYPE_PHY_CABLE_LONG,
945 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
946 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus*/
947 EFX_BIST_TYPE_REG, /* Test the register memories */
948 EFX_BIST_TYPE_NTYPES,
951 typedef enum efx_bist_result_e {
952 EFX_BIST_RESULT_UNKNOWN,
953 EFX_BIST_RESULT_RUNNING,
954 EFX_BIST_RESULT_PASSED,
955 EFX_BIST_RESULT_FAILED,
958 typedef enum efx_phy_cable_status_e {
959 EFX_PHY_CABLE_STATUS_OK,
960 EFX_PHY_CABLE_STATUS_INVALID,
961 EFX_PHY_CABLE_STATUS_OPEN,
962 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
963 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
964 EFX_PHY_CABLE_STATUS_BUSY,
965 } efx_phy_cable_status_t;
967 typedef enum efx_bist_value_e {
968 EFX_BIST_PHY_CABLE_LENGTH_A,
969 EFX_BIST_PHY_CABLE_LENGTH_B,
970 EFX_BIST_PHY_CABLE_LENGTH_C,
971 EFX_BIST_PHY_CABLE_LENGTH_D,
972 EFX_BIST_PHY_CABLE_STATUS_A,
973 EFX_BIST_PHY_CABLE_STATUS_B,
974 EFX_BIST_PHY_CABLE_STATUS_C,
975 EFX_BIST_PHY_CABLE_STATUS_D,
977 /* Memory BIST specific values. These match to the MC_CMD_BIST_POLL
985 EFX_BIST_MEM_ECC_PARITY,
986 EFX_BIST_MEM_ECC_FATAL,
990 extern __checkReturn efx_rc_t
991 efx_bist_enable_offline(
992 __in efx_nic_t *enp);
994 extern __checkReturn efx_rc_t
997 __in efx_bist_type_t type);
999 extern __checkReturn efx_rc_t
1001 __in efx_nic_t *enp,
1002 __in efx_bist_type_t type,
1003 __out efx_bist_result_t *resultp,
1004 __out_opt uint32_t *value_maskp,
1005 __out_ecount_opt(count) unsigned long *valuesp,
1010 __in efx_nic_t *enp,
1011 __in efx_bist_type_t type);
1013 #endif /* EFSYS_OPT_BIST */
1015 #define EFX_FEATURE_IPV6 0x00000001
1016 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1017 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1018 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1019 #define EFX_FEATURE_WOL 0x00000010
1020 #define EFX_FEATURE_MCDI 0x00000020
1021 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1022 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1023 #define EFX_FEATURE_TURBO 0x00000100
1024 #define EFX_FEATURE_MCDI_DMA 0x00000200
1025 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1026 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1027 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1028 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1030 typedef struct efx_nic_cfg_s {
1031 uint32_t enc_board_type;
1032 uint32_t enc_phy_type;
1034 char enc_phy_name[21];
1036 char enc_phy_revision[21];
1037 efx_mon_type_t enc_mon_type;
1038 #if EFSYS_OPT_MON_STATS
1039 uint32_t enc_mon_stat_dma_buf_size;
1040 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1042 unsigned int enc_features;
1043 uint8_t enc_mac_addr[6];
1044 uint8_t enc_port; /* PHY port number */
1045 uint32_t enc_func_flags;
1046 uint32_t enc_intr_vec_base;
1047 uint32_t enc_intr_limit;
1048 uint32_t enc_evq_limit;
1049 uint32_t enc_txq_limit;
1050 uint32_t enc_rxq_limit;
1051 uint32_t enc_buftbl_limit;
1052 uint32_t enc_piobuf_limit;
1053 uint32_t enc_piobuf_size;
1054 uint32_t enc_piobuf_min_alloc_size;
1055 uint32_t enc_evq_timer_quantum_ns;
1056 uint32_t enc_evq_timer_max_us;
1057 uint32_t enc_clk_mult;
1058 uint32_t enc_rx_prefix_size;
1059 uint32_t enc_rx_buf_align_start;
1060 uint32_t enc_rx_buf_align_end;
1061 #if EFSYS_OPT_LOOPBACK
1062 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1063 #endif /* EFSYS_OPT_LOOPBACK */
1064 #if EFSYS_OPT_PHY_FLAGS
1065 uint32_t enc_phy_flags_mask;
1066 #endif /* EFSYS_OPT_PHY_FLAGS */
1067 #if EFSYS_OPT_PHY_LED_CONTROL
1068 uint32_t enc_led_mask;
1069 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1070 #if EFSYS_OPT_PHY_STATS
1071 uint64_t enc_phy_stat_mask;
1072 #endif /* EFSYS_OPT_PHY_STATS */
1074 uint8_t enc_mcdi_mdio_channel;
1075 #if EFSYS_OPT_PHY_STATS
1076 uint32_t enc_mcdi_phy_stat_mask;
1077 #endif /* EFSYS_OPT_PHY_STATS */
1078 #endif /* EFSYS_OPT_SIENA */
1079 #if (EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
1080 #if EFSYS_OPT_MON_STATS
1081 uint32_t *enc_mcdi_sensor_maskp;
1082 uint32_t enc_mcdi_sensor_mask_size;
1083 #endif /* EFSYS_OPT_MON_STATS */
1084 #endif /* (EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
1086 uint32_t enc_bist_mask;
1087 #endif /* EFSYS_OPT_BIST */
1088 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
1091 uint32_t enc_privilege_mask;
1092 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
1093 boolean_t enc_bug26807_workaround;
1094 boolean_t enc_bug35388_workaround;
1095 boolean_t enc_bug41750_workaround;
1096 boolean_t enc_rx_batching_enabled;
1097 /* Maximum number of descriptors completed in an rx event. */
1098 uint32_t enc_rx_batch_max;
1099 /* Number of rx descriptors the hardware requires for a push. */
1100 uint32_t enc_rx_push_align;
1102 * Maximum number of bytes into the packet the TCP header can start for
1103 * the hardware to apply TSO packet edits.
1105 uint32_t enc_tx_tso_tcp_header_offset_limit;
1106 boolean_t enc_fw_assisted_tso_enabled;
1107 boolean_t enc_fw_assisted_tso_v2_enabled;
1108 boolean_t enc_hw_tx_insert_vlan_enabled;
1109 /* Datapath firmware vadapter/vport/vswitch support */
1110 boolean_t enc_datapath_cap_evb;
1111 boolean_t enc_rx_disable_scatter_supported;
1112 boolean_t enc_allow_set_mac_with_installed_filters;
1113 boolean_t enc_enhanced_set_mac_supported;
1114 /* External port identifier */
1115 uint8_t enc_external_port;
1116 uint32_t enc_mcdi_max_payload_length;
1117 /* VPD may be per-PF or global */
1118 boolean_t enc_vpd_is_global;
1121 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1122 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1124 #define EFX_PCI_FUNCTION(_encp) \
1125 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1127 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1129 extern const efx_nic_cfg_t *
1131 __in efx_nic_t *enp);
1133 /* Driver resource limits (minimum required/maximum usable). */
1134 typedef struct efx_drv_limits_s
1136 uint32_t edl_min_evq_count;
1137 uint32_t edl_max_evq_count;
1139 uint32_t edl_min_rxq_count;
1140 uint32_t edl_max_rxq_count;
1142 uint32_t edl_min_txq_count;
1143 uint32_t edl_max_txq_count;
1145 /* PIO blocks (sub-allocated from piobuf) */
1146 uint32_t edl_min_pio_alloc_size;
1147 uint32_t edl_max_pio_alloc_count;
1150 extern __checkReturn efx_rc_t
1151 efx_nic_set_drv_limits(
1152 __inout efx_nic_t *enp,
1153 __in efx_drv_limits_t *edlp);
1155 typedef enum efx_nic_region_e {
1156 EFX_REGION_VI, /* Memory BAR UC mapping */
1157 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1160 extern __checkReturn efx_rc_t
1161 efx_nic_get_bar_region(
1162 __in efx_nic_t *enp,
1163 __in efx_nic_region_t region,
1164 __out uint32_t *offsetp,
1165 __out size_t *sizep);
1167 extern __checkReturn efx_rc_t
1168 efx_nic_get_vi_pool(
1169 __in efx_nic_t *enp,
1170 __out uint32_t *evq_countp,
1171 __out uint32_t *rxq_countp,
1172 __out uint32_t *txq_countp);
1177 typedef enum efx_vpd_tag_e {
1184 typedef uint16_t efx_vpd_keyword_t;
1186 typedef struct efx_vpd_value_s {
1187 efx_vpd_tag_t evv_tag;
1188 efx_vpd_keyword_t evv_keyword;
1190 uint8_t evv_value[0x100];
1194 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1196 extern __checkReturn efx_rc_t
1198 __in efx_nic_t *enp);
1200 extern __checkReturn efx_rc_t
1202 __in efx_nic_t *enp,
1203 __out size_t *sizep);
1205 extern __checkReturn efx_rc_t
1207 __in efx_nic_t *enp,
1208 __out_bcount(size) caddr_t data,
1211 extern __checkReturn efx_rc_t
1213 __in efx_nic_t *enp,
1214 __in_bcount(size) caddr_t data,
1217 extern __checkReturn efx_rc_t
1219 __in efx_nic_t *enp,
1220 __in_bcount(size) caddr_t data,
1223 extern __checkReturn efx_rc_t
1225 __in efx_nic_t *enp,
1226 __in_bcount(size) caddr_t data,
1228 __inout efx_vpd_value_t *evvp);
1230 extern __checkReturn efx_rc_t
1232 __in efx_nic_t *enp,
1233 __inout_bcount(size) caddr_t data,
1235 __in efx_vpd_value_t *evvp);
1237 extern __checkReturn efx_rc_t
1239 __in efx_nic_t *enp,
1240 __inout_bcount(size) caddr_t data,
1242 __out efx_vpd_value_t *evvp,
1243 __inout unsigned int *contp);
1245 extern __checkReturn efx_rc_t
1247 __in efx_nic_t *enp,
1248 __in_bcount(size) caddr_t data,
1253 __in efx_nic_t *enp);
1255 #endif /* EFSYS_OPT_VPD */
1261 typedef enum efx_nvram_type_e {
1262 EFX_NVRAM_INVALID = 0,
1264 EFX_NVRAM_BOOTROM_CFG,
1265 EFX_NVRAM_MC_FIRMWARE,
1266 EFX_NVRAM_MC_GOLDEN,
1272 EFX_NVRAM_FPGA_BACKUP,
1273 EFX_NVRAM_DYNAMIC_CFG,
1278 extern __checkReturn efx_rc_t
1280 __in efx_nic_t *enp);
1284 extern __checkReturn efx_rc_t
1286 __in efx_nic_t *enp);
1288 #endif /* EFSYS_OPT_DIAG */
1290 extern __checkReturn efx_rc_t
1292 __in efx_nic_t *enp,
1293 __in efx_nvram_type_t type,
1294 __out size_t *sizep);
1296 extern __checkReturn efx_rc_t
1298 __in efx_nic_t *enp,
1299 __in efx_nvram_type_t type,
1300 __out_opt size_t *pref_chunkp);
1303 efx_nvram_rw_finish(
1304 __in efx_nic_t *enp,
1305 __in efx_nvram_type_t type);
1307 extern __checkReturn efx_rc_t
1308 efx_nvram_get_version(
1309 __in efx_nic_t *enp,
1310 __in efx_nvram_type_t type,
1311 __out uint32_t *subtypep,
1312 __out_ecount(4) uint16_t version[4]);
1314 extern __checkReturn efx_rc_t
1315 efx_nvram_read_chunk(
1316 __in efx_nic_t *enp,
1317 __in efx_nvram_type_t type,
1318 __in unsigned int offset,
1319 __out_bcount(size) caddr_t data,
1322 extern __checkReturn efx_rc_t
1323 efx_nvram_set_version(
1324 __in efx_nic_t *enp,
1325 __in efx_nvram_type_t type,
1326 __in_ecount(4) uint16_t version[4]);
1328 extern __checkReturn efx_rc_t
1330 __in efx_nic_t *enp,
1331 __in efx_nvram_type_t type,
1332 __in_bcount(partn_size) caddr_t partn_data,
1333 __in size_t partn_size);
1335 extern __checkReturn efx_rc_t
1337 __in efx_nic_t *enp,
1338 __in efx_nvram_type_t type);
1340 extern __checkReturn efx_rc_t
1341 efx_nvram_write_chunk(
1342 __in efx_nic_t *enp,
1343 __in efx_nvram_type_t type,
1344 __in unsigned int offset,
1345 __in_bcount(size) caddr_t data,
1350 __in efx_nic_t *enp);
1352 #endif /* EFSYS_OPT_NVRAM */
1354 #if EFSYS_OPT_BOOTCFG
1358 __in efx_nic_t *enp,
1359 __out_bcount(size) caddr_t data,
1364 __in efx_nic_t *enp,
1365 __in_bcount(size) caddr_t data,
1368 #endif /* EFSYS_OPT_BOOTCFG */
1372 typedef enum efx_wol_type_e {
1373 EFX_WOL_TYPE_INVALID,
1375 EFX_WOL_TYPE_BITMAP,
1380 typedef enum efx_lightsout_offload_type_e {
1381 EFX_LIGHTSOUT_OFFLOAD_TYPE_INVALID,
1382 EFX_LIGHTSOUT_OFFLOAD_TYPE_ARP,
1383 EFX_LIGHTSOUT_OFFLOAD_TYPE_NS,
1384 } efx_lightsout_offload_type_t;
1386 #define EFX_WOL_BITMAP_MASK_SIZE (48)
1387 #define EFX_WOL_BITMAP_VALUE_SIZE (128)
1389 typedef union efx_wol_param_u {
1391 uint8_t mac_addr[6];
1394 uint8_t mask[EFX_WOL_BITMAP_MASK_SIZE]; /* 1 bit per byte */
1395 uint8_t value[EFX_WOL_BITMAP_VALUE_SIZE]; /* value to match */
1400 typedef union efx_lightsout_offload_param_u {
1402 uint8_t mac_addr[6];
1406 uint8_t mac_addr[6];
1407 uint32_t solicited_node[4];
1410 } efx_lightsout_offload_param_t;
1412 extern __checkReturn efx_rc_t
1414 __in efx_nic_t *enp);
1416 extern __checkReturn efx_rc_t
1417 efx_wol_filter_clear(
1418 __in efx_nic_t *enp);
1420 extern __checkReturn efx_rc_t
1422 __in efx_nic_t *enp,
1423 __in efx_wol_type_t type,
1424 __in efx_wol_param_t *paramp,
1425 __out uint32_t *filter_idp);
1427 extern __checkReturn efx_rc_t
1428 efx_wol_filter_remove(
1429 __in efx_nic_t *enp,
1430 __in uint32_t filter_id);
1432 extern __checkReturn efx_rc_t
1433 efx_lightsout_offload_add(
1434 __in efx_nic_t *enp,
1435 __in efx_lightsout_offload_type_t type,
1436 __in efx_lightsout_offload_param_t *paramp,
1437 __out uint32_t *filter_idp);
1439 extern __checkReturn efx_rc_t
1440 efx_lightsout_offload_remove(
1441 __in efx_nic_t *enp,
1442 __in efx_lightsout_offload_type_t type,
1443 __in uint32_t filter_id);
1447 __in efx_nic_t *enp);
1449 #endif /* EFSYS_OPT_WOL */
1453 typedef enum efx_pattern_type_t {
1454 EFX_PATTERN_BYTE_INCREMENT = 0,
1455 EFX_PATTERN_ALL_THE_SAME,
1456 EFX_PATTERN_BIT_ALTERNATE,
1457 EFX_PATTERN_BYTE_ALTERNATE,
1458 EFX_PATTERN_BYTE_CHANGING,
1459 EFX_PATTERN_BIT_SWEEP,
1461 } efx_pattern_type_t;
1464 (*efx_sram_pattern_fn_t)(
1466 __in boolean_t negate,
1467 __out efx_qword_t *eqp);
1469 extern __checkReturn efx_rc_t
1471 __in efx_nic_t *enp,
1472 __in efx_pattern_type_t type);
1474 #endif /* EFSYS_OPT_DIAG */
1476 extern __checkReturn efx_rc_t
1477 efx_sram_buf_tbl_set(
1478 __in efx_nic_t *enp,
1480 __in efsys_mem_t *esmp,
1484 efx_sram_buf_tbl_clear(
1485 __in efx_nic_t *enp,
1489 #define EFX_BUF_TBL_SIZE 0x20000
1491 #define EFX_BUF_SIZE 4096
1495 typedef struct efx_evq_s efx_evq_t;
1497 #if EFSYS_OPT_QSTATS
1499 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1500 typedef enum efx_ev_qstat_e {
1506 EV_RX_PAUSE_FRM_ERR,
1507 EV_RX_BUF_OWNER_ID_ERR,
1508 EV_RX_IPV4_HDR_CHKSUM_ERR,
1509 EV_RX_TCP_UDP_CHKSUM_ERR,
1513 EV_RX_MCAST_HASH_MATCH,
1530 EV_DRIVER_SRM_UPD_DONE,
1531 EV_DRIVER_TX_DESCQ_FLS_DONE,
1532 EV_DRIVER_RX_DESCQ_FLS_DONE,
1533 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1534 EV_DRIVER_RX_DSC_ERROR,
1535 EV_DRIVER_TX_DSC_ERROR,
1541 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1543 #endif /* EFSYS_OPT_QSTATS */
1545 extern __checkReturn efx_rc_t
1547 __in efx_nic_t *enp);
1551 __in efx_nic_t *enp);
1553 #define EFX_EVQ_MAXNEVS 32768
1554 #define EFX_EVQ_MINNEVS 512
1556 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
1557 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1559 extern __checkReturn efx_rc_t
1561 __in efx_nic_t *enp,
1562 __in unsigned int index,
1563 __in efsys_mem_t *esmp,
1566 __deref_out efx_evq_t **eepp);
1570 __in efx_evq_t *eep,
1571 __in uint16_t data);
1573 typedef __checkReturn boolean_t
1574 (*efx_initialized_ev_t)(
1575 __in_opt void *arg);
1577 #define EFX_PKT_UNICAST 0x0004
1578 #define EFX_PKT_START 0x0008
1580 #define EFX_PKT_VLAN_TAGGED 0x0010
1581 #define EFX_CKSUM_TCPUDP 0x0020
1582 #define EFX_CKSUM_IPV4 0x0040
1583 #define EFX_PKT_CONT 0x0080
1585 #define EFX_CHECK_VLAN 0x0100
1586 #define EFX_PKT_TCP 0x0200
1587 #define EFX_PKT_UDP 0x0400
1588 #define EFX_PKT_IPV4 0x0800
1590 #define EFX_PKT_IPV6 0x1000
1591 #define EFX_PKT_PREFIX_LEN 0x2000
1592 #define EFX_ADDR_MISMATCH 0x4000
1593 #define EFX_DISCARD 0x8000
1595 #define EFX_EV_RX_NLABELS 32
1596 #define EFX_EV_TX_NLABELS 32
1598 typedef __checkReturn boolean_t
1601 __in uint32_t label,
1604 __in uint16_t flags);
1606 typedef __checkReturn boolean_t
1609 __in uint32_t label,
1612 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
1613 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
1614 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
1615 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
1616 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
1617 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
1618 #define EFX_EXCEPTION_RX_ERROR 0x00000007
1619 #define EFX_EXCEPTION_TX_ERROR 0x00000008
1620 #define EFX_EXCEPTION_EV_ERROR 0x00000009
1622 typedef __checkReturn boolean_t
1623 (*efx_exception_ev_t)(
1625 __in uint32_t label,
1626 __in uint32_t data);
1628 typedef __checkReturn boolean_t
1629 (*efx_rxq_flush_done_ev_t)(
1631 __in uint32_t rxq_index);
1633 typedef __checkReturn boolean_t
1634 (*efx_rxq_flush_failed_ev_t)(
1636 __in uint32_t rxq_index);
1638 typedef __checkReturn boolean_t
1639 (*efx_txq_flush_done_ev_t)(
1641 __in uint32_t txq_index);
1643 typedef __checkReturn boolean_t
1644 (*efx_software_ev_t)(
1646 __in uint16_t magic);
1648 typedef __checkReturn boolean_t
1651 __in uint32_t code);
1653 #define EFX_SRAM_CLEAR 0
1654 #define EFX_SRAM_UPDATE 1
1655 #define EFX_SRAM_ILLEGAL_CLEAR 2
1657 typedef __checkReturn boolean_t
1658 (*efx_wake_up_ev_t)(
1660 __in uint32_t label);
1662 typedef __checkReturn boolean_t
1665 __in uint32_t label);
1667 typedef __checkReturn boolean_t
1668 (*efx_link_change_ev_t)(
1670 __in efx_link_mode_t link_mode);
1672 #if EFSYS_OPT_MON_STATS
1674 typedef __checkReturn boolean_t
1675 (*efx_monitor_ev_t)(
1677 __in efx_mon_stat_t id,
1678 __in efx_mon_stat_value_t value);
1680 #endif /* EFSYS_OPT_MON_STATS */
1682 #if EFSYS_OPT_MAC_STATS
1684 typedef __checkReturn boolean_t
1685 (*efx_mac_stats_ev_t)(
1687 __in uint32_t generation
1690 #endif /* EFSYS_OPT_MAC_STATS */
1692 typedef struct efx_ev_callbacks_s {
1693 efx_initialized_ev_t eec_initialized;
1696 efx_exception_ev_t eec_exception;
1697 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
1698 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
1699 efx_txq_flush_done_ev_t eec_txq_flush_done;
1700 efx_software_ev_t eec_software;
1701 efx_sram_ev_t eec_sram;
1702 efx_wake_up_ev_t eec_wake_up;
1703 efx_timer_ev_t eec_timer;
1704 efx_link_change_ev_t eec_link_change;
1705 #if EFSYS_OPT_MON_STATS
1706 efx_monitor_ev_t eec_monitor;
1707 #endif /* EFSYS_OPT_MON_STATS */
1708 #if EFSYS_OPT_MAC_STATS
1709 efx_mac_stats_ev_t eec_mac_stats;
1710 #endif /* EFSYS_OPT_MAC_STATS */
1711 } efx_ev_callbacks_t;
1713 extern __checkReturn boolean_t
1715 __in efx_evq_t *eep,
1716 __in unsigned int count);
1718 #if EFSYS_OPT_EV_PREFETCH
1722 __in efx_evq_t *eep,
1723 __in unsigned int count);
1725 #endif /* EFSYS_OPT_EV_PREFETCH */
1729 __in efx_evq_t *eep,
1730 __inout unsigned int *countp,
1731 __in const efx_ev_callbacks_t *eecp,
1732 __in_opt void *arg);
1734 extern __checkReturn efx_rc_t
1736 __in efx_evq_t *eep,
1737 __in unsigned int us);
1739 extern __checkReturn efx_rc_t
1741 __in efx_evq_t *eep,
1742 __in unsigned int count);
1744 #if EFSYS_OPT_QSTATS
1750 __in efx_nic_t *enp,
1751 __in unsigned int id);
1753 #endif /* EFSYS_OPT_NAMES */
1756 efx_ev_qstats_update(
1757 __in efx_evq_t *eep,
1758 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
1760 #endif /* EFSYS_OPT_QSTATS */
1764 __in efx_evq_t *eep);
1768 extern __checkReturn efx_rc_t
1770 __inout efx_nic_t *enp);
1774 __in efx_nic_t *enp);
1776 #if EFSYS_OPT_RX_SCATTER
1777 __checkReturn efx_rc_t
1778 efx_rx_scatter_enable(
1779 __in efx_nic_t *enp,
1780 __in unsigned int buf_size);
1781 #endif /* EFSYS_OPT_RX_SCATTER */
1783 #if EFSYS_OPT_RX_SCALE
1785 typedef enum efx_rx_hash_alg_e {
1786 EFX_RX_HASHALG_LFSR = 0,
1787 EFX_RX_HASHALG_TOEPLITZ
1788 } efx_rx_hash_alg_t;
1790 typedef enum efx_rx_hash_type_e {
1791 EFX_RX_HASH_IPV4 = 0,
1792 EFX_RX_HASH_TCPIPV4,
1794 EFX_RX_HASH_TCPIPV6,
1795 } efx_rx_hash_type_t;
1797 typedef enum efx_rx_hash_support_e {
1798 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
1799 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
1800 } efx_rx_hash_support_t;
1802 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
1803 #define EFX_MAXRSS 64 /* RX indirection entry range */
1804 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
1806 typedef enum efx_rx_scale_support_e {
1807 EFX_RX_SCALE_UNAVAILABLE = 0, /* Not supported */
1808 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
1809 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
1810 } efx_rx_scale_support_t;
1812 extern __checkReturn efx_rc_t
1813 efx_rx_hash_support_get(
1814 __in efx_nic_t *enp,
1815 __out efx_rx_hash_support_t *supportp);
1818 extern __checkReturn efx_rc_t
1819 efx_rx_scale_support_get(
1820 __in efx_nic_t *enp,
1821 __out efx_rx_scale_support_t *supportp);
1823 extern __checkReturn efx_rc_t
1824 efx_rx_scale_mode_set(
1825 __in efx_nic_t *enp,
1826 __in efx_rx_hash_alg_t alg,
1827 __in efx_rx_hash_type_t type,
1828 __in boolean_t insert);
1830 extern __checkReturn efx_rc_t
1831 efx_rx_scale_tbl_set(
1832 __in efx_nic_t *enp,
1833 __in_ecount(n) unsigned int *table,
1836 extern __checkReturn efx_rc_t
1837 efx_rx_scale_key_set(
1838 __in efx_nic_t *enp,
1839 __in_ecount(n) uint8_t *key,
1842 extern __checkReturn uint32_t
1843 efx_psuedo_hdr_hash_get(
1844 __in efx_nic_t *enp,
1845 __in efx_rx_hash_alg_t func,
1846 __in uint8_t *buffer);
1848 #endif /* EFSYS_OPT_RX_SCALE */
1850 extern __checkReturn efx_rc_t
1851 efx_psuedo_hdr_pkt_length_get(
1852 __in efx_nic_t *enp,
1853 __in uint8_t *buffer,
1854 __out uint16_t *pkt_lengthp);
1856 #define EFX_RXQ_MAXNDESCS 4096
1857 #define EFX_RXQ_MINNDESCS 512
1859 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
1860 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1861 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
1862 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
1864 typedef enum efx_rxq_type_e {
1865 EFX_RXQ_TYPE_DEFAULT,
1866 EFX_RXQ_TYPE_SCATTER,
1870 extern __checkReturn efx_rc_t
1872 __in efx_nic_t *enp,
1873 __in unsigned int index,
1874 __in unsigned int label,
1875 __in efx_rxq_type_t type,
1876 __in efsys_mem_t *esmp,
1879 __in efx_evq_t *eep,
1880 __deref_out efx_rxq_t **erpp);
1882 typedef struct efx_buffer_s {
1883 efsys_dma_addr_t eb_addr;
1888 typedef struct efx_desc_s {
1894 __in efx_rxq_t *erp,
1895 __in_ecount(n) efsys_dma_addr_t *addrp,
1897 __in unsigned int n,
1898 __in unsigned int completed,
1899 __in unsigned int added);
1903 __in efx_rxq_t *erp,
1904 __in unsigned int added,
1905 __inout unsigned int *pushedp);
1907 extern __checkReturn efx_rc_t
1909 __in efx_rxq_t *erp);
1913 __in efx_rxq_t *erp);
1917 __in efx_rxq_t *erp);
1921 typedef struct efx_txq_s efx_txq_t;
1923 #if EFSYS_OPT_QSTATS
1925 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
1926 typedef enum efx_tx_qstat_e {
1932 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
1934 #endif /* EFSYS_OPT_QSTATS */
1936 extern __checkReturn efx_rc_t
1938 __in efx_nic_t *enp);
1942 __in efx_nic_t *enp);
1944 #define EFX_BUG35388_WORKAROUND(_encp) \
1945 (((_encp) == NULL) ? 1 : ((_encp)->enc_bug35388_workaround != 0))
1947 #define EFX_TXQ_MAXNDESCS(_encp) \
1948 ((EFX_BUG35388_WORKAROUND(_encp)) ? 2048 : 4096)
1950 #define EFX_TXQ_MINNDESCS 512
1952 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
1953 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1954 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
1955 #define EFX_TXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
1957 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
1959 #define EFX_TXQ_CKSUM_IPV4 0x0001
1960 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
1961 #define EFX_TXQ_FATSOV2 0x0004
1963 extern __checkReturn efx_rc_t
1965 __in efx_nic_t *enp,
1966 __in unsigned int index,
1967 __in unsigned int label,
1968 __in efsys_mem_t *esmp,
1971 __in uint16_t flags,
1972 __in efx_evq_t *eep,
1973 __deref_out efx_txq_t **etpp,
1974 __out unsigned int *addedp);
1976 extern __checkReturn efx_rc_t
1978 __in efx_txq_t *etp,
1979 __in_ecount(n) efx_buffer_t *eb,
1980 __in unsigned int n,
1981 __in unsigned int completed,
1982 __inout unsigned int *addedp);
1984 extern __checkReturn efx_rc_t
1986 __in efx_txq_t *etp,
1987 __in unsigned int ns);
1991 __in efx_txq_t *etp,
1992 __in unsigned int added,
1993 __in unsigned int pushed);
1995 extern __checkReturn efx_rc_t
1997 __in efx_txq_t *etp);
2001 __in efx_txq_t *etp);
2003 extern __checkReturn efx_rc_t
2005 __in efx_txq_t *etp);
2008 efx_tx_qpio_disable(
2009 __in efx_txq_t *etp);
2011 extern __checkReturn efx_rc_t
2013 __in efx_txq_t *etp,
2014 __in_ecount(buf_length) uint8_t *buffer,
2015 __in size_t buf_length,
2016 __in size_t pio_buf_offset);
2018 extern __checkReturn efx_rc_t
2020 __in efx_txq_t *etp,
2021 __in size_t pkt_length,
2022 __in unsigned int completed,
2023 __inout unsigned int *addedp);
2025 extern __checkReturn efx_rc_t
2027 __in efx_txq_t *etp,
2028 __in_ecount(n) efx_desc_t *ed,
2029 __in unsigned int n,
2030 __in unsigned int completed,
2031 __inout unsigned int *addedp);
2034 efx_tx_qdesc_dma_create(
2035 __in efx_txq_t *etp,
2036 __in efsys_dma_addr_t addr,
2039 __out efx_desc_t *edp);
2042 efx_tx_qdesc_tso_create(
2043 __in efx_txq_t *etp,
2044 __in uint16_t ipv4_id,
2045 __in uint32_t tcp_seq,
2046 __in uint8_t tcp_flags,
2047 __out efx_desc_t *edp);
2049 /* Number of FATSOv2 option descriptors */
2050 #define EFX_TX_FATSOV2_OPT_NDESCS 2
2052 /* Maximum number of DMA segments per TSO packet (not superframe) */
2053 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
2056 efx_tx_qdesc_tso2_create(
2057 __in efx_txq_t *etp,
2058 __in uint16_t ipv4_id,
2059 __in uint32_t tcp_seq,
2060 __in uint16_t tcp_mss,
2061 __out_ecount(count) efx_desc_t *edp,
2065 efx_tx_qdesc_vlantci_create(
2066 __in efx_txq_t *etp,
2068 __out efx_desc_t *edp);
2070 #if EFSYS_OPT_QSTATS
2076 __in efx_nic_t *etp,
2077 __in unsigned int id);
2079 #endif /* EFSYS_OPT_NAMES */
2082 efx_tx_qstats_update(
2083 __in efx_txq_t *etp,
2084 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
2086 #endif /* EFSYS_OPT_QSTATS */
2090 __in efx_txq_t *etp);
2095 #if EFSYS_OPT_FILTER
2097 #define EFX_ETHER_TYPE_IPV4 0x0800
2098 #define EFX_ETHER_TYPE_IPV6 0x86DD
2100 #define EFX_IPPROTO_TCP 6
2101 #define EFX_IPPROTO_UDP 17
2103 typedef enum efx_filter_flag_e {
2104 EFX_FILTER_FLAG_RX_RSS = 0x01, /* use RSS to spread across
2105 * multiple queues */
2106 EFX_FILTER_FLAG_RX_SCATTER = 0x02, /* enable RX scatter */
2107 EFX_FILTER_FLAG_RX_OVER_AUTO = 0x04, /* Override an automatic filter
2108 * (priority EFX_FILTER_PRI_AUTO).
2109 * May only be set by the filter
2110 * implementation for each type.
2111 * A removal request will
2112 * restore the automatic filter
2114 EFX_FILTER_FLAG_RX = 0x08, /* Filter is for RX */
2115 EFX_FILTER_FLAG_TX = 0x10, /* Filter is for TX */
2116 } efx_filter_flag_t;
2118 typedef enum efx_filter_match_flags_e {
2119 EFX_FILTER_MATCH_REM_HOST = 0x0001, /* Match by remote IP host
2121 EFX_FILTER_MATCH_LOC_HOST = 0x0002, /* Match by local IP host
2123 EFX_FILTER_MATCH_REM_MAC = 0x0004, /* Match by remote MAC address */
2124 EFX_FILTER_MATCH_REM_PORT = 0x0008, /* Match by remote TCP/UDP port */
2125 EFX_FILTER_MATCH_LOC_MAC = 0x0010, /* Match by remote TCP/UDP port */
2126 EFX_FILTER_MATCH_LOC_PORT = 0x0020, /* Match by local TCP/UDP port */
2127 EFX_FILTER_MATCH_ETHER_TYPE = 0x0040, /* Match by Ether-type */
2128 EFX_FILTER_MATCH_INNER_VID = 0x0080, /* Match by inner VLAN ID */
2129 EFX_FILTER_MATCH_OUTER_VID = 0x0100, /* Match by outer VLAN ID */
2130 EFX_FILTER_MATCH_IP_PROTO = 0x0200, /* Match by IP transport
2132 EFX_FILTER_MATCH_LOC_MAC_IG = 0x0400, /* Match by local MAC address
2133 * I/G bit. Used for RX default
2134 * unicast and multicast/
2135 * broadcast filters. */
2136 } efx_filter_match_flags_t;
2138 typedef enum efx_filter_priority_s {
2139 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
2140 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
2141 * address list or hardware
2142 * requirements. This may only be used
2143 * by the filter implementation for
2145 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
2146 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
2147 * client (e.g. SR-IOV, HyperV VMQ etc.)
2149 } efx_filter_priority_t;
2152 * FIXME: All these fields are assumed to be in little-endian byte order.
2153 * It may be better for some to be big-endian. See bug42804.
2156 typedef struct efx_filter_spec_s {
2157 uint32_t efs_match_flags:12;
2158 uint32_t efs_priority:2;
2159 uint32_t efs_flags:6;
2160 uint32_t efs_dmaq_id:12;
2161 uint32_t efs_rss_context;
2162 uint16_t efs_outer_vid;
2163 uint16_t efs_inner_vid;
2164 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
2165 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
2166 uint16_t efs_ether_type;
2167 uint8_t efs_ip_proto;
2168 uint16_t efs_loc_port;
2169 uint16_t efs_rem_port;
2170 efx_oword_t efs_rem_host;
2171 efx_oword_t efs_loc_host;
2172 } efx_filter_spec_t;
2175 /* Default values for use in filter specifications */
2176 #define EFX_FILTER_SPEC_RSS_CONTEXT_DEFAULT 0xffffffff
2177 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
2178 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
2180 extern __checkReturn efx_rc_t
2182 __in efx_nic_t *enp);
2186 __in efx_nic_t *enp);
2188 extern __checkReturn efx_rc_t
2190 __in efx_nic_t *enp,
2191 __inout efx_filter_spec_t *spec);
2193 extern __checkReturn efx_rc_t
2195 __in efx_nic_t *enp,
2196 __inout efx_filter_spec_t *spec);
2198 extern __checkReturn efx_rc_t
2200 __in efx_nic_t *enp);
2202 extern __checkReturn efx_rc_t
2203 efx_filter_supported_filters(
2204 __in efx_nic_t *enp,
2205 __out uint32_t *list,
2206 __out size_t *length);
2209 efx_filter_spec_init_rx(
2210 __out efx_filter_spec_t *spec,
2211 __in efx_filter_priority_t priority,
2212 __in efx_filter_flag_t flags,
2213 __in efx_rxq_t *erp);
2216 efx_filter_spec_init_tx(
2217 __out efx_filter_spec_t *spec,
2218 __in efx_txq_t *etp);
2220 extern __checkReturn efx_rc_t
2221 efx_filter_spec_set_ipv4_local(
2222 __inout efx_filter_spec_t *spec,
2225 __in uint16_t port);
2227 extern __checkReturn efx_rc_t
2228 efx_filter_spec_set_ipv4_full(
2229 __inout efx_filter_spec_t *spec,
2231 __in uint32_t lhost,
2232 __in uint16_t lport,
2233 __in uint32_t rhost,
2234 __in uint16_t rport);
2236 extern __checkReturn efx_rc_t
2237 efx_filter_spec_set_eth_local(
2238 __inout efx_filter_spec_t *spec,
2240 __in const uint8_t *addr);
2242 extern __checkReturn efx_rc_t
2243 efx_filter_spec_set_uc_def(
2244 __inout efx_filter_spec_t *spec);
2246 extern __checkReturn efx_rc_t
2247 efx_filter_spec_set_mc_def(
2248 __inout efx_filter_spec_t *spec);
2250 #endif /* EFSYS_OPT_FILTER */
2254 extern __checkReturn uint32_t
2256 __in_ecount(count) uint32_t const *input,
2258 __in uint32_t init);
2260 extern __checkReturn uint32_t
2262 __in_ecount(length) uint8_t const *input,
2264 __in uint32_t init);
2266 #if EFSYS_OPT_LICENSING
2270 typedef struct efx_key_stats_s {
2272 uint32_t eks_invalid;
2273 uint32_t eks_blacklisted;
2274 uint32_t eks_unverifiable;
2275 uint32_t eks_wrong_node;
2276 uint32_t eks_licensed_apps_lo;
2277 uint32_t eks_licensed_apps_hi;
2278 uint32_t eks_licensed_features_lo;
2279 uint32_t eks_licensed_features_hi;
2282 extern __checkReturn efx_rc_t
2284 __in efx_nic_t *enp);
2288 __in efx_nic_t *enp);
2290 extern __checkReturn efx_rc_t
2291 efx_lic_update_licenses(
2292 __in efx_nic_t *enp);
2294 extern __checkReturn efx_rc_t
2295 efx_lic_get_key_stats(
2296 __in efx_nic_t *enp,
2297 __out efx_key_stats_t *ksp);
2299 extern __checkReturn efx_rc_t
2301 __in efx_nic_t *enp,
2302 __in uint64_t app_id,
2303 __out boolean_t *licensedp);
2305 extern __checkReturn efx_rc_t
2307 __in efx_nic_t *enp,
2308 __in size_t buffer_size,
2309 __out uint32_t *typep,
2310 __out size_t *lengthp,
2311 __out_opt uint8_t *bufferp);
2314 #endif /* EFSYS_OPT_LICENSING */
2322 #endif /* _SYS_EFX_H */