2 * Copyright (c) 2007-2015 Solarflare Communications Inc.
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31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
36 #include "efx_types.h"
42 #define EFX_EV_QSTAT_INCR(_eep, _stat) \
44 (_eep)->ee_stat[_stat]++; \
45 _NOTE(CONSTANTCONDITION) \
48 #define EFX_EV_QSTAT_INCR(_eep, _stat)
51 #define EFX_EV_PRESENT(_qword) \
52 (EFX_QWORD_FIELD((_qword), EFX_DWORD_0) != 0xffffffff && \
53 EFX_QWORD_FIELD((_qword), EFX_DWORD_1) != 0xffffffff)
57 #if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA
59 static __checkReturn int
67 static __checkReturn int
68 falconsiena_ev_qcreate(
70 __in unsigned int index,
71 __in efsys_mem_t *esmp,
77 falconsiena_ev_qdestroy(
80 static __checkReturn int
81 falconsiena_ev_qprime(
83 __in unsigned int count);
88 __inout unsigned int *countp,
89 __in const efx_ev_callbacks_t *eecp,
97 static __checkReturn int
98 falconsiena_ev_qmoderate(
100 __in unsigned int us);
104 falconsiena_ev_qstats_update(
106 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
110 #endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */
113 static efx_ev_ops_t __efx_ev_falcon_ops = {
114 falconsiena_ev_init, /* eevo_init */
115 falconsiena_ev_fini, /* eevo_fini */
116 falconsiena_ev_qcreate, /* eevo_qcreate */
117 falconsiena_ev_qdestroy, /* eevo_qdestroy */
118 falconsiena_ev_qprime, /* eevo_qprime */
119 falconsiena_ev_qpost, /* eevo_qpost */
120 falconsiena_ev_qmoderate, /* eevo_qmoderate */
122 falconsiena_ev_qstats_update, /* eevo_qstats_update */
125 #endif /* EFSYS_OPT_FALCON */
128 static efx_ev_ops_t __efx_ev_siena_ops = {
129 falconsiena_ev_init, /* eevo_init */
130 falconsiena_ev_fini, /* eevo_fini */
131 falconsiena_ev_qcreate, /* eevo_qcreate */
132 falconsiena_ev_qdestroy, /* eevo_qdestroy */
133 falconsiena_ev_qprime, /* eevo_qprime */
134 falconsiena_ev_qpost, /* eevo_qpost */
135 falconsiena_ev_qmoderate, /* eevo_qmoderate */
137 falconsiena_ev_qstats_update, /* eevo_qstats_update */
140 #endif /* EFSYS_OPT_SIENA */
142 #if EFSYS_OPT_HUNTINGTON
143 static efx_ev_ops_t __efx_ev_hunt_ops = {
144 hunt_ev_init, /* eevo_init */
145 hunt_ev_fini, /* eevo_fini */
146 hunt_ev_qcreate, /* eevo_qcreate */
147 hunt_ev_qdestroy, /* eevo_qdestroy */
148 hunt_ev_qprime, /* eevo_qprime */
149 hunt_ev_qpost, /* eevo_qpost */
150 hunt_ev_qmoderate, /* eevo_qmoderate */
152 hunt_ev_qstats_update, /* eevo_qstats_update */
155 #endif /* EFSYS_OPT_HUNTINGTON */
165 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
166 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
168 if (enp->en_mod_flags & EFX_MOD_EV) {
173 switch (enp->en_family) {
175 case EFX_FAMILY_FALCON:
176 eevop = (efx_ev_ops_t *)&__efx_ev_falcon_ops;
178 #endif /* EFSYS_OPT_FALCON */
181 case EFX_FAMILY_SIENA:
182 eevop = (efx_ev_ops_t *)&__efx_ev_siena_ops;
184 #endif /* EFSYS_OPT_SIENA */
186 #if EFSYS_OPT_HUNTINGTON
187 case EFX_FAMILY_HUNTINGTON:
188 eevop = (efx_ev_ops_t *)&__efx_ev_hunt_ops;
190 #endif /* EFSYS_OPT_HUNTINGTON */
198 EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
200 if ((rc = eevop->eevo_init(enp)) != 0)
203 enp->en_eevop = eevop;
204 enp->en_mod_flags |= EFX_MOD_EV;
211 EFSYS_PROBE1(fail1, int, rc);
213 enp->en_eevop = NULL;
214 enp->en_mod_flags &= ~EFX_MOD_EV;
222 efx_ev_ops_t *eevop = enp->en_eevop;
224 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
225 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
226 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
227 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
228 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
229 EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
231 eevop->eevo_fini(enp);
233 enp->en_eevop = NULL;
234 enp->en_mod_flags &= ~EFX_MOD_EV;
241 __in unsigned int index,
242 __in efsys_mem_t *esmp,
245 __deref_out efx_evq_t **eepp)
247 efx_ev_ops_t *eevop = enp->en_eevop;
248 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
252 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
253 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
255 EFSYS_ASSERT3U(enp->en_ev_qcount + 1, <, encp->enc_evq_limit);
257 /* Allocate an EVQ object */
258 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_evq_t), eep);
264 eep->ee_magic = EFX_EVQ_MAGIC;
266 eep->ee_index = index;
267 eep->ee_mask = n - 1;
270 if ((rc = eevop->eevo_qcreate(enp, index, esmp, n, id, eep)) != 0)
280 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
282 EFSYS_PROBE1(fail1, int, rc);
290 efx_nic_t *enp = eep->ee_enp;
291 efx_ev_ops_t *eevop = enp->en_eevop;
293 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
295 EFSYS_ASSERT(enp->en_ev_qcount != 0);
298 eevop->eevo_qdestroy(eep);
300 /* Free the EVQ object */
301 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
307 __in unsigned int count)
309 efx_nic_t *enp = eep->ee_enp;
310 efx_ev_ops_t *eevop = enp->en_eevop;
313 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
315 if (!(enp->en_mod_flags & EFX_MOD_INTR)) {
320 if ((rc = eevop->eevo_qprime(eep, count)) != 0)
328 EFSYS_PROBE1(fail1, int, rc);
332 __checkReturn boolean_t
335 __in unsigned int count)
340 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
342 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
343 EFSYS_MEM_READQ(eep->ee_esmp, offset, &qword);
345 return (EFX_EV_PRESENT(qword));
348 #if EFSYS_OPT_EV_PREFETCH
353 __in unsigned int count)
355 efx_nic_t *enp = eep->ee_enp;
358 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
360 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
361 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
364 #endif /* EFSYS_OPT_EV_PREFETCH */
369 __inout unsigned int *countp,
370 __in const efx_ev_callbacks_t *eecp,
373 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
376 * FIXME: Huntington will require support for hardware event batching
377 * and merging, which will need a different ev_qpoll implementation.
379 * Without those features the Falcon/Siena code can be used unchanged.
381 EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_LBN == FSF_AZ_EV_CODE_LBN);
382 EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_WIDTH == FSF_AZ_EV_CODE_WIDTH);
384 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_RX_EV == FSE_AZ_EV_CODE_RX_EV);
385 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_TX_EV == FSE_AZ_EV_CODE_TX_EV);
386 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRIVER_EV == FSE_AZ_EV_CODE_DRIVER_EV);
387 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRV_GEN_EV ==
388 FSE_AZ_EV_CODE_DRV_GEN_EV);
390 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_MCDI_EV ==
391 FSE_AZ_EV_CODE_MCDI_EVRESPONSE);
393 falconsiena_ev_qpoll(eep, countp, eecp, arg);
401 efx_nic_t *enp = eep->ee_enp;
402 efx_ev_ops_t *eevop = enp->en_eevop;
404 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
406 EFSYS_ASSERT(eevop != NULL &&
407 eevop->eevo_qpost != NULL);
409 eevop->eevo_qpost(eep, data);
415 __in unsigned int us)
417 efx_nic_t *enp = eep->ee_enp;
418 efx_ev_ops_t *eevop = enp->en_eevop;
421 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
423 if ((rc = eevop->eevo_qmoderate(eep, us)) != 0)
429 EFSYS_PROBE1(fail1, int, rc);
435 efx_ev_qstats_update(
437 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat)
439 { efx_nic_t *enp = eep->ee_enp;
440 efx_ev_ops_t *eevop = enp->en_eevop;
442 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
444 eevop->eevo_qstats_update(eep, stat);
447 #endif /* EFSYS_OPT_QSTATS */
449 #if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA
451 static __checkReturn int
458 * Program the event queue for receive and transmit queue
461 EFX_BAR_READO(enp, FR_AZ_DP_CTRL_REG, &oword);
462 EFX_SET_OWORD_FIELD(oword, FRF_AZ_FLS_EVQ_ID, 0);
463 EFX_BAR_WRITEO(enp, FR_AZ_DP_CTRL_REG, &oword);
469 static __checkReturn boolean_t
470 falconsiena_ev_rx_not_ok(
472 __in efx_qword_t *eqp,
475 __inout uint16_t *flagsp)
477 boolean_t ignore = B_FALSE;
479 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TOBE_DISC) != 0) {
480 EFX_EV_QSTAT_INCR(eep, EV_RX_TOBE_DISC);
481 EFSYS_PROBE(tobe_disc);
483 * Assume this is a unicast address mismatch, unless below
484 * we find either FSF_AZ_RX_EV_ETH_CRC_ERR or
485 * EV_RX_PAUSE_FRM_ERR is set.
487 (*flagsp) |= EFX_ADDR_MISMATCH;
490 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_FRM_TRUNC) != 0) {
491 EFSYS_PROBE2(frm_trunc, uint32_t, label, uint32_t, id);
492 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
493 (*flagsp) |= EFX_DISCARD;
495 #if (EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER)
497 * Lookout for payload queue ran dry errors and ignore them.
499 * Sadly for the header/data split cases, the descriptor
500 * pointer in this event refers to the header queue and
501 * therefore cannot be easily detected as duplicate.
502 * So we drop these and rely on the receive processing seeing
503 * a subsequent packet with FSF_AZ_RX_EV_SOP set to discard
504 * the partially received packet.
506 if ((EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) == 0) &&
507 (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) == 0) &&
508 (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT) == 0))
510 #endif /* EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER */
513 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_ETH_CRC_ERR) != 0) {
514 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
515 EFSYS_PROBE(crc_err);
516 (*flagsp) &= ~EFX_ADDR_MISMATCH;
517 (*flagsp) |= EFX_DISCARD;
520 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PAUSE_FRM_ERR) != 0) {
521 EFX_EV_QSTAT_INCR(eep, EV_RX_PAUSE_FRM_ERR);
522 EFSYS_PROBE(pause_frm_err);
523 (*flagsp) &= ~EFX_ADDR_MISMATCH;
524 (*flagsp) |= EFX_DISCARD;
527 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BUF_OWNER_ID_ERR) != 0) {
528 EFX_EV_QSTAT_INCR(eep, EV_RX_BUF_OWNER_ID_ERR);
529 EFSYS_PROBE(owner_id_err);
530 (*flagsp) |= EFX_DISCARD;
533 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR) != 0) {
534 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
535 EFSYS_PROBE(ipv4_err);
536 (*flagsp) &= ~EFX_CKSUM_IPV4;
539 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR) != 0) {
540 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
541 EFSYS_PROBE(udp_chk_err);
542 (*flagsp) &= ~EFX_CKSUM_TCPUDP;
545 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_FRAG_ERR) != 0) {
546 EFX_EV_QSTAT_INCR(eep, EV_RX_IP_FRAG_ERR);
549 * If IP is fragmented FSF_AZ_RX_EV_IP_FRAG_ERR is set. This
550 * causes FSF_AZ_RX_EV_PKT_OK to be clear. This is not an error
553 (*flagsp) &= ~(EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP);
559 static __checkReturn boolean_t
562 __in efx_qword_t *eqp,
563 __in const efx_ev_callbacks_t *eecp,
566 efx_nic_t *enp = eep->ee_enp;
571 #if (EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER)
573 boolean_t jumbo_cont;
574 #endif /* EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER */
579 boolean_t should_abort;
581 EFX_EV_QSTAT_INCR(eep, EV_RX);
583 /* Basic packet information */
584 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_DESC_PTR);
585 size = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT);
586 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_Q_LABEL);
587 ok = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_OK) != 0);
589 #if (EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER)
590 sop = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) != 0);
591 jumbo_cont = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) != 0);
592 #endif /* EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER */
594 hdr_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_HDR_TYPE);
596 is_v6 = (enp->en_family != EFX_FAMILY_FALCON &&
597 EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_IPV6_PKT) != 0);
600 * If packet is marked as OK and packet type is TCP/IP or
601 * UDP/IP or other IP, then we can rely on the hardware checksums.
604 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP:
605 flags = EFX_PKT_TCP | EFX_CKSUM_TCPUDP;
607 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6);
608 flags |= EFX_PKT_IPV6;
610 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4);
611 flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
615 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP:
616 flags = EFX_PKT_UDP | EFX_CKSUM_TCPUDP;
618 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6);
619 flags |= EFX_PKT_IPV6;
621 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4);
622 flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
626 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER:
628 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6);
629 flags = EFX_PKT_IPV6;
631 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4);
632 flags = EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
636 case FSE_AZ_RX_EV_HDR_TYPE_OTHER:
637 EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP);
642 EFSYS_ASSERT(B_FALSE);
647 #if EFSYS_OPT_RX_SCATTER || EFSYS_OPT_RX_HDR_SPLIT
648 /* Report scatter and header/lookahead split buffer flags */
650 flags |= EFX_PKT_START;
652 flags |= EFX_PKT_CONT;
653 #endif /* EFSYS_OPT_RX_SCATTER || EFSYS_OPT_RX_HDR_SPLIT */
655 /* Detect errors included in the FSF_AZ_RX_EV_PKT_OK indication */
657 ignore = falconsiena_ev_rx_not_ok(eep, eqp, label, id, &flags);
659 EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
660 uint32_t, size, uint16_t, flags);
666 /* If we're not discarding the packet then it is ok */
667 if (~flags & EFX_DISCARD)
668 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
670 /* Detect multicast packets that didn't match the filter */
671 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_PKT) != 0) {
672 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_PKT);
674 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_HASH_MATCH) != 0) {
675 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_HASH_MATCH);
677 EFSYS_PROBE(mcast_mismatch);
678 flags |= EFX_ADDR_MISMATCH;
681 flags |= EFX_PKT_UNICAST;
685 * The packet parser in Siena can abort parsing packets under
686 * certain error conditions, setting the PKT_NOT_PARSED bit
687 * (which clears PKT_OK). If this is set, then don't trust
688 * the PKT_TYPE field.
690 if (enp->en_family != EFX_FAMILY_FALCON && !ok) {
693 parse_err = EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_PKT_NOT_PARSED);
695 flags |= EFX_CHECK_VLAN;
698 if (~flags & EFX_CHECK_VLAN) {
701 pkt_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_TYPE);
702 if (pkt_type >= FSE_AZ_RX_EV_PKT_TYPE_VLAN)
703 flags |= EFX_PKT_VLAN_TAGGED;
706 EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
707 uint32_t, size, uint16_t, flags);
709 EFSYS_ASSERT(eecp->eec_rx != NULL);
710 should_abort = eecp->eec_rx(arg, label, id, size, flags);
712 return (should_abort);
715 static __checkReturn boolean_t
718 __in efx_qword_t *eqp,
719 __in const efx_ev_callbacks_t *eecp,
724 boolean_t should_abort;
726 EFX_EV_QSTAT_INCR(eep, EV_TX);
728 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0 &&
729 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) == 0 &&
730 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) == 0 &&
731 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) == 0) {
733 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_DESC_PTR);
734 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_Q_LABEL);
736 EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id);
738 EFSYS_ASSERT(eecp->eec_tx != NULL);
739 should_abort = eecp->eec_tx(arg, label, id);
741 return (should_abort);
744 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0)
745 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
746 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
747 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
749 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) != 0)
750 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_ERR);
752 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) != 0)
753 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_TOO_BIG);
755 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) != 0)
756 EFX_EV_QSTAT_INCR(eep, EV_TX_WQ_FF_FULL);
758 EFX_EV_QSTAT_INCR(eep, EV_TX_UNEXPECTED);
762 static __checkReturn boolean_t
763 falconsiena_ev_global(
765 __in efx_qword_t *eqp,
766 __in const efx_ev_callbacks_t *eecp,
769 efx_nic_t *enp = eep->ee_enp;
770 efx_port_t *epp = &(enp->en_port);
771 boolean_t should_abort;
773 EFX_EV_QSTAT_INCR(eep, EV_GLOBAL);
774 should_abort = B_FALSE;
776 /* Check for a link management event */
777 if (EFX_QWORD_FIELD(*eqp, FSF_BZ_GLB_EV_XG_MNT_INTR) != 0) {
778 EFX_EV_QSTAT_INCR(eep, EV_GLOBAL_MNT);
782 epp->ep_mac_poll_needed = B_TRUE;
785 return (should_abort);
788 static __checkReturn boolean_t
789 falconsiena_ev_driver(
791 __in efx_qword_t *eqp,
792 __in const efx_ev_callbacks_t *eecp,
795 boolean_t should_abort;
797 EFX_EV_QSTAT_INCR(eep, EV_DRIVER);
798 should_abort = B_FALSE;
800 switch (EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBCODE)) {
801 case FSE_AZ_TX_DESCQ_FLS_DONE_EV: {
804 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE);
806 txq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
808 EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index);
810 EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL);
811 should_abort = eecp->eec_txq_flush_done(arg, txq_index);
815 case FSE_AZ_RX_DESCQ_FLS_DONE_EV: {
819 rxq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
820 failed = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
822 EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL);
823 EFSYS_ASSERT(eecp->eec_rxq_flush_failed != NULL);
826 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_FAILED);
828 EFSYS_PROBE1(rx_descq_fls_failed, uint32_t, rxq_index);
830 should_abort = eecp->eec_rxq_flush_failed(arg,
833 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE);
835 EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index);
837 should_abort = eecp->eec_rxq_flush_done(arg, rxq_index);
842 case FSE_AZ_EVQ_INIT_DONE_EV:
843 EFSYS_ASSERT(eecp->eec_initialized != NULL);
844 should_abort = eecp->eec_initialized(arg);
848 case FSE_AZ_EVQ_NOT_EN_EV:
849 EFSYS_PROBE(evq_not_en);
852 case FSE_AZ_SRM_UPD_DONE_EV: {
855 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_SRM_UPD_DONE);
857 code = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
859 EFSYS_ASSERT(eecp->eec_sram != NULL);
860 should_abort = eecp->eec_sram(arg, code);
864 case FSE_AZ_WAKE_UP_EV: {
867 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
869 EFSYS_ASSERT(eecp->eec_wake_up != NULL);
870 should_abort = eecp->eec_wake_up(arg, id);
874 case FSE_AZ_TX_PKT_NON_TCP_UDP:
875 EFSYS_PROBE(tx_pkt_non_tcp_udp);
878 case FSE_AZ_TIMER_EV: {
881 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
883 EFSYS_ASSERT(eecp->eec_timer != NULL);
884 should_abort = eecp->eec_timer(arg, id);
888 case FSE_AZ_RX_DSC_ERROR_EV:
889 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DSC_ERROR);
891 EFSYS_PROBE(rx_dsc_error);
893 EFSYS_ASSERT(eecp->eec_exception != NULL);
894 should_abort = eecp->eec_exception(arg,
895 EFX_EXCEPTION_RX_DSC_ERROR, 0);
899 case FSE_AZ_TX_DSC_ERROR_EV:
900 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DSC_ERROR);
902 EFSYS_PROBE(tx_dsc_error);
904 EFSYS_ASSERT(eecp->eec_exception != NULL);
905 should_abort = eecp->eec_exception(arg,
906 EFX_EXCEPTION_TX_DSC_ERROR, 0);
914 return (should_abort);
917 static __checkReturn boolean_t
918 falconsiena_ev_drv_gen(
920 __in efx_qword_t *eqp,
921 __in const efx_ev_callbacks_t *eecp,
925 boolean_t should_abort;
927 EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN);
929 data = EFX_QWORD_FIELD(*eqp, FSF_AZ_EV_DATA_DW0);
930 if (data >= ((uint32_t)1 << 16)) {
931 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
932 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
933 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
937 EFSYS_ASSERT(eecp->eec_software != NULL);
938 should_abort = eecp->eec_software(arg, (uint16_t)data);
940 return (should_abort);
945 static __checkReturn boolean_t
948 __in efx_qword_t *eqp,
949 __in const efx_ev_callbacks_t *eecp,
952 efx_nic_t *enp = eep->ee_enp;
954 boolean_t should_abort = B_FALSE;
956 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
958 if (enp->en_family != EFX_FAMILY_SIENA)
961 EFSYS_ASSERT(eecp->eec_link_change != NULL);
962 EFSYS_ASSERT(eecp->eec_exception != NULL);
963 #if EFSYS_OPT_MON_STATS
964 EFSYS_ASSERT(eecp->eec_monitor != NULL);
967 EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE);
969 code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE);
971 case MCDI_EVENT_CODE_BADSSERT:
972 efx_mcdi_ev_death(enp, EINTR);
975 case MCDI_EVENT_CODE_CMDDONE:
977 MCDI_EV_FIELD(eqp, CMDDONE_SEQ),
978 MCDI_EV_FIELD(eqp, CMDDONE_DATALEN),
979 MCDI_EV_FIELD(eqp, CMDDONE_ERRNO));
982 case MCDI_EVENT_CODE_LINKCHANGE: {
983 efx_link_mode_t link_mode;
985 siena_phy_link_ev(enp, eqp, &link_mode);
986 should_abort = eecp->eec_link_change(arg, link_mode);
989 case MCDI_EVENT_CODE_SENSOREVT: {
990 #if EFSYS_OPT_MON_STATS
992 efx_mon_stat_value_t value;
995 if ((rc = mcdi_mon_ev(enp, eqp, &id, &value)) == 0)
996 should_abort = eecp->eec_monitor(arg, id, value);
997 else if (rc == ENOTSUP) {
998 should_abort = eecp->eec_exception(arg,
999 EFX_EXCEPTION_UNKNOWN_SENSOREVT,
1000 MCDI_EV_FIELD(eqp, DATA));
1002 EFSYS_ASSERT(rc == ENODEV); /* Wrong port */
1004 should_abort = B_FALSE;
1008 case MCDI_EVENT_CODE_SCHEDERR:
1009 /* Informational only */
1012 case MCDI_EVENT_CODE_REBOOT:
1013 efx_mcdi_ev_death(enp, EIO);
1016 case MCDI_EVENT_CODE_MAC_STATS_DMA:
1017 #if EFSYS_OPT_MAC_STATS
1018 if (eecp->eec_mac_stats != NULL) {
1019 eecp->eec_mac_stats(arg,
1020 MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION));
1025 case MCDI_EVENT_CODE_FWALERT: {
1026 uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON);
1028 if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS)
1029 should_abort = eecp->eec_exception(arg,
1030 EFX_EXCEPTION_FWALERT_SRAM,
1031 MCDI_EV_FIELD(eqp, FWALERT_DATA));
1033 should_abort = eecp->eec_exception(arg,
1034 EFX_EXCEPTION_UNKNOWN_FWALERT,
1035 MCDI_EV_FIELD(eqp, DATA));
1040 EFSYS_PROBE1(mc_pcol_error, int, code);
1045 return (should_abort);
1048 #endif /* EFSYS_OPT_MCDI */
1050 static __checkReturn int
1051 falconsiena_ev_qprime(
1052 __in efx_evq_t *eep,
1053 __in unsigned int count)
1055 efx_nic_t *enp = eep->ee_enp;
1059 rptr = count & eep->ee_mask;
1061 EFX_POPULATE_DWORD_1(dword, FRF_AZ_EVQ_RPTR, rptr);
1063 EFX_BAR_TBL_WRITED(enp, FR_AZ_EVQ_RPTR_REG, eep->ee_index,
1069 #define EFX_EV_BATCH 8
1072 falconsiena_ev_qpoll(
1073 __in efx_evq_t *eep,
1074 __inout unsigned int *countp,
1075 __in const efx_ev_callbacks_t *eecp,
1078 efx_qword_t ev[EFX_EV_BATCH];
1085 EFSYS_ASSERT(countp != NULL);
1086 EFSYS_ASSERT(eecp != NULL);
1090 /* Read up until the end of the batch period */
1091 batch = EFX_EV_BATCH - (count & (EFX_EV_BATCH - 1));
1092 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
1093 for (total = 0; total < batch; ++total) {
1094 EFSYS_MEM_READQ(eep->ee_esmp, offset, &(ev[total]));
1096 if (!EFX_EV_PRESENT(ev[total]))
1099 EFSYS_PROBE3(event, unsigned int, eep->ee_index,
1100 uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_1),
1101 uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_0));
1103 offset += sizeof (efx_qword_t);
1106 #if EFSYS_OPT_EV_PREFETCH && (EFSYS_OPT_EV_PREFETCH_PERIOD > 1)
1108 * Prefetch the next batch when we get within PREFETCH_PERIOD
1109 * of a completed batch. If the batch is smaller, then prefetch
1112 if (total == batch && total < EFSYS_OPT_EV_PREFETCH_PERIOD)
1113 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
1114 #endif /* EFSYS_OPT_EV_PREFETCH */
1116 /* Process the batch of events */
1117 for (index = 0; index < total; ++index) {
1118 boolean_t should_abort;
1121 #if EFSYS_OPT_EV_PREFETCH
1122 /* Prefetch if we've now reached the batch period */
1123 if (total == batch &&
1124 index + EFSYS_OPT_EV_PREFETCH_PERIOD == total) {
1125 offset = (count + batch) & eep->ee_mask;
1126 offset *= sizeof (efx_qword_t);
1128 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
1130 #endif /* EFSYS_OPT_EV_PREFETCH */
1132 EFX_EV_QSTAT_INCR(eep, EV_ALL);
1134 code = EFX_QWORD_FIELD(ev[index], FSF_AZ_EV_CODE);
1136 case FSE_AZ_EV_CODE_RX_EV:
1137 should_abort = eep->ee_rx(eep,
1138 &(ev[index]), eecp, arg);
1140 case FSE_AZ_EV_CODE_TX_EV:
1141 should_abort = eep->ee_tx(eep,
1142 &(ev[index]), eecp, arg);
1144 case FSE_AZ_EV_CODE_DRIVER_EV:
1145 should_abort = eep->ee_driver(eep,
1146 &(ev[index]), eecp, arg);
1148 case FSE_AZ_EV_CODE_DRV_GEN_EV:
1149 should_abort = eep->ee_drv_gen(eep,
1150 &(ev[index]), eecp, arg);
1153 case FSE_AZ_EV_CODE_MCDI_EVRESPONSE:
1154 should_abort = eep->ee_mcdi(eep,
1155 &(ev[index]), eecp, arg);
1158 case FSE_AZ_EV_CODE_GLOBAL_EV:
1159 if (eep->ee_global) {
1160 should_abort = eep->ee_global(eep,
1161 &(ev[index]), eecp, arg);
1164 /* else fallthrough */
1166 EFSYS_PROBE3(bad_event,
1167 unsigned int, eep->ee_index,
1169 EFX_QWORD_FIELD(ev[index], EFX_DWORD_1),
1171 EFX_QWORD_FIELD(ev[index], EFX_DWORD_0));
1173 EFSYS_ASSERT(eecp->eec_exception != NULL);
1174 (void) eecp->eec_exception(arg,
1175 EFX_EXCEPTION_EV_ERROR, code);
1176 should_abort = B_TRUE;
1179 /* Ignore subsequent events */
1186 * Now that the hardware has most likely moved onto dma'ing
1187 * into the next cache line, clear the processed events. Take
1188 * care to only clear out events that we've processed
1190 EFX_SET_QWORD(ev[0]);
1191 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
1192 for (index = 0; index < total; ++index) {
1193 EFSYS_MEM_WRITEQ(eep->ee_esmp, offset, &(ev[0]));
1194 offset += sizeof (efx_qword_t);
1199 } while (total == batch);
1205 falconsiena_ev_qpost(
1206 __in efx_evq_t *eep,
1209 efx_nic_t *enp = eep->ee_enp;
1213 EFX_POPULATE_QWORD_2(ev, FSF_AZ_EV_CODE, FSE_AZ_EV_CODE_DRV_GEN_EV,
1214 FSF_AZ_EV_DATA_DW0, (uint32_t)data);
1216 EFX_POPULATE_OWORD_3(oword, FRF_AZ_DRV_EV_QID, eep->ee_index,
1217 EFX_DWORD_0, EFX_QWORD_FIELD(ev, EFX_DWORD_0),
1218 EFX_DWORD_1, EFX_QWORD_FIELD(ev, EFX_DWORD_1));
1220 EFX_BAR_WRITEO(enp, FR_AZ_DRV_EV_REG, &oword);
1223 static __checkReturn int
1224 falconsiena_ev_qmoderate(
1225 __in efx_evq_t *eep,
1226 __in unsigned int us)
1228 efx_nic_t *enp = eep->ee_enp;
1229 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1230 unsigned int locked;
1234 if (us > encp->enc_evq_timer_max_us) {
1239 /* If the value is zero then disable the timer */
1241 if (enp->en_family == EFX_FAMILY_FALCON)
1242 EFX_POPULATE_DWORD_2(dword,
1243 FRF_AB_TC_TIMER_MODE, FFE_AB_TIMER_MODE_DIS,
1244 FRF_AB_TC_TIMER_VAL, 0);
1246 EFX_POPULATE_DWORD_2(dword,
1247 FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS,
1248 FRF_CZ_TC_TIMER_VAL, 0);
1252 /* Calculate the timer value in quanta */
1253 timer_val = us * 1000 / encp->enc_evq_timer_quantum_ns;
1255 /* Moderation value is base 0 so we need to deduct 1 */
1259 if (enp->en_family == EFX_FAMILY_FALCON)
1260 EFX_POPULATE_DWORD_2(dword,
1261 FRF_AB_TC_TIMER_MODE, FFE_AB_TIMER_MODE_INT_HLDOFF,
1262 FRF_AB_TIMER_VAL, timer_val);
1264 EFX_POPULATE_DWORD_2(dword,
1265 FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_INT_HLDOFF,
1266 FRF_CZ_TC_TIMER_VAL, timer_val);
1269 locked = (eep->ee_index == 0) ? 1 : 0;
1271 EFX_BAR_TBL_WRITED(enp, FR_BZ_TIMER_COMMAND_REGP0,
1272 eep->ee_index, &dword, locked);
1277 EFSYS_PROBE1(fail1, int, rc);
1282 static __checkReturn int
1283 falconsiena_ev_qcreate(
1284 __in efx_nic_t *enp,
1285 __in unsigned int index,
1286 __in efsys_mem_t *esmp,
1289 __in efx_evq_t *eep)
1291 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1296 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MAXNEVS));
1297 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MINNEVS));
1299 if (!ISP2(n) || (n < EFX_EVQ_MINNEVS) || (n > EFX_EVQ_MAXNEVS)) {
1303 if (index >= encp->enc_evq_limit) {
1307 #if EFSYS_OPT_RX_SCALE
1308 if (enp->en_intr.ei_type == EFX_INTR_LINE &&
1309 index >= EFX_MAXRSS_LEGACY) {
1314 for (size = 0; (1 << size) <= (EFX_EVQ_MAXNEVS / EFX_EVQ_MINNEVS);
1316 if ((1 << size) == (int)(n / EFX_EVQ_MINNEVS))
1318 if (id + (1 << size) >= encp->enc_buftbl_limit) {
1323 /* Set up the handler table */
1324 eep->ee_rx = falconsiena_ev_rx;
1325 eep->ee_tx = falconsiena_ev_tx;
1326 eep->ee_driver = falconsiena_ev_driver;
1327 eep->ee_global = falconsiena_ev_global;
1328 eep->ee_drv_gen = falconsiena_ev_drv_gen;
1330 eep->ee_mcdi = falconsiena_ev_mcdi;
1331 #endif /* EFSYS_OPT_MCDI */
1333 /* Set up the new event queue */
1334 if (enp->en_family != EFX_FAMILY_FALCON) {
1335 EFX_POPULATE_OWORD_1(oword, FRF_CZ_TIMER_Q_EN, 1);
1336 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, index, &oword, B_TRUE);
1339 EFX_POPULATE_OWORD_3(oword, FRF_AZ_EVQ_EN, 1, FRF_AZ_EVQ_SIZE, size,
1340 FRF_AZ_EVQ_BUF_BASE_ID, id);
1342 EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, index, &oword, B_TRUE);
1348 #if EFSYS_OPT_RX_SCALE
1355 EFSYS_PROBE1(fail1, int, rc);
1360 #endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */
1362 #if EFSYS_OPT_QSTATS
1364 /* START MKCONFIG GENERATED EfxEventQueueStatNamesBlock b693ddf85aee1bfd */
1365 static const char *__efx_ev_qstat_name[] = {
1372 "rx_buf_owner_id_err",
1373 "rx_ipv4_hdr_chksum_err",
1374 "rx_tcp_udp_chksum_err",
1378 "rx_mcast_hash_match",
1395 "driver_srm_upd_done",
1396 "driver_tx_descq_fls_done",
1397 "driver_rx_descq_fls_done",
1398 "driver_rx_descq_fls_failed",
1399 "driver_rx_dsc_error",
1400 "driver_tx_dsc_error",
1404 /* END MKCONFIG GENERATED EfxEventQueueStatNamesBlock */
1408 __in efx_nic_t *enp,
1409 __in unsigned int id)
1411 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
1412 EFSYS_ASSERT3U(id, <, EV_NQSTATS);
1414 return (__efx_ev_qstat_name[id]);
1416 #endif /* EFSYS_OPT_NAMES */
1417 #endif /* EFSYS_OPT_QSTATS */
1419 #if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA
1421 #if EFSYS_OPT_QSTATS
1423 falconsiena_ev_qstats_update(
1424 __in efx_evq_t *eep,
1425 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat)
1429 for (id = 0; id < EV_NQSTATS; id++) {
1430 efsys_stat_t *essp = &stat[id];
1432 EFSYS_STAT_INCR(essp, eep->ee_stat[id]);
1433 eep->ee_stat[id] = 0;
1436 #endif /* EFSYS_OPT_QSTATS */
1439 falconsiena_ev_qdestroy(
1440 __in efx_evq_t *eep)
1442 efx_nic_t *enp = eep->ee_enp;
1445 /* Purge event queue */
1446 EFX_ZERO_OWORD(oword);
1448 EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL,
1449 eep->ee_index, &oword, B_TRUE);
1451 if (enp->en_family != EFX_FAMILY_FALCON) {
1452 EFX_ZERO_OWORD(oword);
1453 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL,
1454 eep->ee_index, &oword, B_TRUE);
1459 falconsiena_ev_fini(
1460 __in efx_nic_t *enp)
1462 _NOTE(ARGUNUSED(enp))
1465 #endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */