2 * Copyright (c) 2007-2015 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
36 #if EFSYS_OPT_MON_MCDI
41 #define EFX_EV_QSTAT_INCR(_eep, _stat) \
43 (_eep)->ee_stat[_stat]++; \
44 _NOTE(CONSTANTCONDITION) \
47 #define EFX_EV_QSTAT_INCR(_eep, _stat)
50 #define EFX_EV_PRESENT(_qword) \
51 (EFX_QWORD_FIELD((_qword), EFX_DWORD_0) != 0xffffffff && \
52 EFX_QWORD_FIELD((_qword), EFX_DWORD_1) != 0xffffffff)
58 static __checkReturn efx_rc_t
66 static __checkReturn efx_rc_t
67 falconsiena_ev_qcreate(
69 __in unsigned int index,
70 __in efsys_mem_t *esmp,
76 falconsiena_ev_qdestroy(
79 static __checkReturn efx_rc_t
80 falconsiena_ev_qprime(
82 __in unsigned int count);
87 __inout unsigned int *countp,
88 __in const efx_ev_callbacks_t *eecp,
96 static __checkReturn efx_rc_t
97 falconsiena_ev_qmoderate(
99 __in unsigned int us);
103 falconsiena_ev_qstats_update(
105 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
109 #endif /* EFSYS_OPT_SIENA */
112 static efx_ev_ops_t __efx_ev_siena_ops = {
113 falconsiena_ev_init, /* eevo_init */
114 falconsiena_ev_fini, /* eevo_fini */
115 falconsiena_ev_qcreate, /* eevo_qcreate */
116 falconsiena_ev_qdestroy, /* eevo_qdestroy */
117 falconsiena_ev_qprime, /* eevo_qprime */
118 falconsiena_ev_qpost, /* eevo_qpost */
119 falconsiena_ev_qmoderate, /* eevo_qmoderate */
121 falconsiena_ev_qstats_update, /* eevo_qstats_update */
124 #endif /* EFSYS_OPT_SIENA */
126 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
127 static efx_ev_ops_t __efx_ev_ef10_ops = {
128 ef10_ev_init, /* eevo_init */
129 ef10_ev_fini, /* eevo_fini */
130 ef10_ev_qcreate, /* eevo_qcreate */
131 ef10_ev_qdestroy, /* eevo_qdestroy */
132 ef10_ev_qprime, /* eevo_qprime */
133 ef10_ev_qpost, /* eevo_qpost */
134 ef10_ev_qmoderate, /* eevo_qmoderate */
136 ef10_ev_qstats_update, /* eevo_qstats_update */
139 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
142 __checkReturn efx_rc_t
149 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
150 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
152 if (enp->en_mod_flags & EFX_MOD_EV) {
157 switch (enp->en_family) {
159 case EFX_FAMILY_SIENA:
160 eevop = (efx_ev_ops_t *)&__efx_ev_siena_ops;
162 #endif /* EFSYS_OPT_SIENA */
164 #if EFSYS_OPT_HUNTINGTON
165 case EFX_FAMILY_HUNTINGTON:
166 eevop = (efx_ev_ops_t *)&__efx_ev_ef10_ops;
168 #endif /* EFSYS_OPT_HUNTINGTON */
170 #if EFSYS_OPT_MEDFORD
171 case EFX_FAMILY_MEDFORD:
172 eevop = (efx_ev_ops_t *)&__efx_ev_ef10_ops;
174 #endif /* EFSYS_OPT_MEDFORD */
182 EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
184 if ((rc = eevop->eevo_init(enp)) != 0)
187 enp->en_eevop = eevop;
188 enp->en_mod_flags |= EFX_MOD_EV;
195 EFSYS_PROBE1(fail1, efx_rc_t, rc);
197 enp->en_eevop = NULL;
198 enp->en_mod_flags &= ~EFX_MOD_EV;
206 efx_ev_ops_t *eevop = enp->en_eevop;
208 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
209 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
210 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
211 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
212 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
213 EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
215 eevop->eevo_fini(enp);
217 enp->en_eevop = NULL;
218 enp->en_mod_flags &= ~EFX_MOD_EV;
222 __checkReturn efx_rc_t
225 __in unsigned int index,
226 __in efsys_mem_t *esmp,
229 __deref_out efx_evq_t **eepp)
231 efx_ev_ops_t *eevop = enp->en_eevop;
232 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
236 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
237 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
239 EFSYS_ASSERT3U(enp->en_ev_qcount + 1, <, encp->enc_evq_limit);
241 /* Allocate an EVQ object */
242 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_evq_t), eep);
248 eep->ee_magic = EFX_EVQ_MAGIC;
250 eep->ee_index = index;
251 eep->ee_mask = n - 1;
254 if ((rc = eevop->eevo_qcreate(enp, index, esmp, n, id, eep)) != 0)
264 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
266 EFSYS_PROBE1(fail1, efx_rc_t, rc);
274 efx_nic_t *enp = eep->ee_enp;
275 efx_ev_ops_t *eevop = enp->en_eevop;
277 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
279 EFSYS_ASSERT(enp->en_ev_qcount != 0);
282 eevop->eevo_qdestroy(eep);
284 /* Free the EVQ object */
285 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
288 __checkReturn efx_rc_t
291 __in unsigned int count)
293 efx_nic_t *enp = eep->ee_enp;
294 efx_ev_ops_t *eevop = enp->en_eevop;
297 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
299 if (!(enp->en_mod_flags & EFX_MOD_INTR)) {
304 if ((rc = eevop->eevo_qprime(eep, count)) != 0)
312 EFSYS_PROBE1(fail1, efx_rc_t, rc);
316 __checkReturn boolean_t
319 __in unsigned int count)
324 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
326 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
327 EFSYS_MEM_READQ(eep->ee_esmp, offset, &qword);
329 return (EFX_EV_PRESENT(qword));
332 #if EFSYS_OPT_EV_PREFETCH
337 __in unsigned int count)
339 efx_nic_t *enp = eep->ee_enp;
342 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
344 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
345 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
348 #endif /* EFSYS_OPT_EV_PREFETCH */
353 __inout unsigned int *countp,
354 __in const efx_ev_callbacks_t *eecp,
357 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
360 * FIXME: Huntington will require support for hardware event batching
361 * and merging, which will need a different ev_qpoll implementation.
363 * Without those features the Falcon/Siena code can be used unchanged.
365 EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_LBN == FSF_AZ_EV_CODE_LBN);
366 EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_WIDTH == FSF_AZ_EV_CODE_WIDTH);
368 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_RX_EV == FSE_AZ_EV_CODE_RX_EV);
369 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_TX_EV == FSE_AZ_EV_CODE_TX_EV);
370 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRIVER_EV == FSE_AZ_EV_CODE_DRIVER_EV);
371 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRV_GEN_EV ==
372 FSE_AZ_EV_CODE_DRV_GEN_EV);
374 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_MCDI_EV ==
375 FSE_AZ_EV_CODE_MCDI_EVRESPONSE);
377 falconsiena_ev_qpoll(eep, countp, eecp, arg);
385 efx_nic_t *enp = eep->ee_enp;
386 efx_ev_ops_t *eevop = enp->en_eevop;
388 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
390 EFSYS_ASSERT(eevop != NULL &&
391 eevop->eevo_qpost != NULL);
393 eevop->eevo_qpost(eep, data);
396 __checkReturn efx_rc_t
399 __in unsigned int us)
401 efx_nic_t *enp = eep->ee_enp;
402 efx_ev_ops_t *eevop = enp->en_eevop;
405 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
407 if ((rc = eevop->eevo_qmoderate(eep, us)) != 0)
413 EFSYS_PROBE1(fail1, efx_rc_t, rc);
419 efx_ev_qstats_update(
421 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat)
423 { efx_nic_t *enp = eep->ee_enp;
424 efx_ev_ops_t *eevop = enp->en_eevop;
426 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
428 eevop->eevo_qstats_update(eep, stat);
431 #endif /* EFSYS_OPT_QSTATS */
435 static __checkReturn efx_rc_t
442 * Program the event queue for receive and transmit queue
445 EFX_BAR_READO(enp, FR_AZ_DP_CTRL_REG, &oword);
446 EFX_SET_OWORD_FIELD(oword, FRF_AZ_FLS_EVQ_ID, 0);
447 EFX_BAR_WRITEO(enp, FR_AZ_DP_CTRL_REG, &oword);
453 static __checkReturn boolean_t
454 falconsiena_ev_rx_not_ok(
456 __in efx_qword_t *eqp,
459 __inout uint16_t *flagsp)
461 boolean_t ignore = B_FALSE;
463 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TOBE_DISC) != 0) {
464 EFX_EV_QSTAT_INCR(eep, EV_RX_TOBE_DISC);
465 EFSYS_PROBE(tobe_disc);
467 * Assume this is a unicast address mismatch, unless below
468 * we find either FSF_AZ_RX_EV_ETH_CRC_ERR or
469 * EV_RX_PAUSE_FRM_ERR is set.
471 (*flagsp) |= EFX_ADDR_MISMATCH;
474 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_FRM_TRUNC) != 0) {
475 EFSYS_PROBE2(frm_trunc, uint32_t, label, uint32_t, id);
476 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
477 (*flagsp) |= EFX_DISCARD;
479 #if EFSYS_OPT_RX_SCATTER
481 * Lookout for payload queue ran dry errors and ignore them.
483 * Sadly for the header/data split cases, the descriptor
484 * pointer in this event refers to the header queue and
485 * therefore cannot be easily detected as duplicate.
486 * So we drop these and rely on the receive processing seeing
487 * a subsequent packet with FSF_AZ_RX_EV_SOP set to discard
488 * the partially received packet.
490 if ((EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) == 0) &&
491 (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) == 0) &&
492 (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT) == 0))
494 #endif /* EFSYS_OPT_RX_SCATTER */
497 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_ETH_CRC_ERR) != 0) {
498 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
499 EFSYS_PROBE(crc_err);
500 (*flagsp) &= ~EFX_ADDR_MISMATCH;
501 (*flagsp) |= EFX_DISCARD;
504 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PAUSE_FRM_ERR) != 0) {
505 EFX_EV_QSTAT_INCR(eep, EV_RX_PAUSE_FRM_ERR);
506 EFSYS_PROBE(pause_frm_err);
507 (*flagsp) &= ~EFX_ADDR_MISMATCH;
508 (*flagsp) |= EFX_DISCARD;
511 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BUF_OWNER_ID_ERR) != 0) {
512 EFX_EV_QSTAT_INCR(eep, EV_RX_BUF_OWNER_ID_ERR);
513 EFSYS_PROBE(owner_id_err);
514 (*flagsp) |= EFX_DISCARD;
517 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR) != 0) {
518 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
519 EFSYS_PROBE(ipv4_err);
520 (*flagsp) &= ~EFX_CKSUM_IPV4;
523 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR) != 0) {
524 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
525 EFSYS_PROBE(udp_chk_err);
526 (*flagsp) &= ~EFX_CKSUM_TCPUDP;
529 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_FRAG_ERR) != 0) {
530 EFX_EV_QSTAT_INCR(eep, EV_RX_IP_FRAG_ERR);
533 * If IP is fragmented FSF_AZ_RX_EV_IP_FRAG_ERR is set. This
534 * causes FSF_AZ_RX_EV_PKT_OK to be clear. This is not an error
537 (*flagsp) &= ~(EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP);
543 static __checkReturn boolean_t
546 __in efx_qword_t *eqp,
547 __in const efx_ev_callbacks_t *eecp,
554 #if EFSYS_OPT_RX_SCATTER
556 boolean_t jumbo_cont;
557 #endif /* EFSYS_OPT_RX_SCATTER */
562 boolean_t should_abort;
564 EFX_EV_QSTAT_INCR(eep, EV_RX);
566 /* Basic packet information */
567 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_DESC_PTR);
568 size = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT);
569 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_Q_LABEL);
570 ok = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_OK) != 0);
572 #if EFSYS_OPT_RX_SCATTER
573 sop = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) != 0);
574 jumbo_cont = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) != 0);
575 #endif /* EFSYS_OPT_RX_SCATTER */
577 hdr_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_HDR_TYPE);
579 is_v6 = (EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_IPV6_PKT) != 0);
582 * If packet is marked as OK and packet type is TCP/IP or
583 * UDP/IP or other IP, then we can rely on the hardware checksums.
586 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP:
587 flags = EFX_PKT_TCP | EFX_CKSUM_TCPUDP;
589 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6);
590 flags |= EFX_PKT_IPV6;
592 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4);
593 flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
597 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP:
598 flags = EFX_PKT_UDP | EFX_CKSUM_TCPUDP;
600 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6);
601 flags |= EFX_PKT_IPV6;
603 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4);
604 flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
608 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER:
610 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6);
611 flags = EFX_PKT_IPV6;
613 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4);
614 flags = EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
618 case FSE_AZ_RX_EV_HDR_TYPE_OTHER:
619 EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP);
624 EFSYS_ASSERT(B_FALSE);
629 #if EFSYS_OPT_RX_SCATTER
630 /* Report scatter and header/lookahead split buffer flags */
632 flags |= EFX_PKT_START;
634 flags |= EFX_PKT_CONT;
635 #endif /* EFSYS_OPT_RX_SCATTER */
637 /* Detect errors included in the FSF_AZ_RX_EV_PKT_OK indication */
639 ignore = falconsiena_ev_rx_not_ok(eep, eqp, label, id, &flags);
641 EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
642 uint32_t, size, uint16_t, flags);
648 /* If we're not discarding the packet then it is ok */
649 if (~flags & EFX_DISCARD)
650 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
652 /* Detect multicast packets that didn't match the filter */
653 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_PKT) != 0) {
654 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_PKT);
656 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_HASH_MATCH) != 0) {
657 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_HASH_MATCH);
659 EFSYS_PROBE(mcast_mismatch);
660 flags |= EFX_ADDR_MISMATCH;
663 flags |= EFX_PKT_UNICAST;
667 * The packet parser in Siena can abort parsing packets under
668 * certain error conditions, setting the PKT_NOT_PARSED bit
669 * (which clears PKT_OK). If this is set, then don't trust
670 * the PKT_TYPE field.
675 parse_err = EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_PKT_NOT_PARSED);
677 flags |= EFX_CHECK_VLAN;
680 if (~flags & EFX_CHECK_VLAN) {
683 pkt_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_TYPE);
684 if (pkt_type >= FSE_AZ_RX_EV_PKT_TYPE_VLAN)
685 flags |= EFX_PKT_VLAN_TAGGED;
688 EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
689 uint32_t, size, uint16_t, flags);
691 EFSYS_ASSERT(eecp->eec_rx != NULL);
692 should_abort = eecp->eec_rx(arg, label, id, size, flags);
694 return (should_abort);
697 static __checkReturn boolean_t
700 __in efx_qword_t *eqp,
701 __in const efx_ev_callbacks_t *eecp,
706 boolean_t should_abort;
708 EFX_EV_QSTAT_INCR(eep, EV_TX);
710 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0 &&
711 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) == 0 &&
712 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) == 0 &&
713 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) == 0) {
715 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_DESC_PTR);
716 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_Q_LABEL);
718 EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id);
720 EFSYS_ASSERT(eecp->eec_tx != NULL);
721 should_abort = eecp->eec_tx(arg, label, id);
723 return (should_abort);
726 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0)
727 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
728 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
729 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
731 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) != 0)
732 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_ERR);
734 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) != 0)
735 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_TOO_BIG);
737 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) != 0)
738 EFX_EV_QSTAT_INCR(eep, EV_TX_WQ_FF_FULL);
740 EFX_EV_QSTAT_INCR(eep, EV_TX_UNEXPECTED);
744 static __checkReturn boolean_t
745 falconsiena_ev_global(
747 __in efx_qword_t *eqp,
748 __in const efx_ev_callbacks_t *eecp,
751 _NOTE(ARGUNUSED(eqp, eecp, arg))
753 EFX_EV_QSTAT_INCR(eep, EV_GLOBAL);
758 static __checkReturn boolean_t
759 falconsiena_ev_driver(
761 __in efx_qword_t *eqp,
762 __in const efx_ev_callbacks_t *eecp,
765 boolean_t should_abort;
767 EFX_EV_QSTAT_INCR(eep, EV_DRIVER);
768 should_abort = B_FALSE;
770 switch (EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBCODE)) {
771 case FSE_AZ_TX_DESCQ_FLS_DONE_EV: {
774 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE);
776 txq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
778 EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index);
780 EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL);
781 should_abort = eecp->eec_txq_flush_done(arg, txq_index);
785 case FSE_AZ_RX_DESCQ_FLS_DONE_EV: {
789 rxq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
790 failed = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
792 EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL);
793 EFSYS_ASSERT(eecp->eec_rxq_flush_failed != NULL);
796 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_FAILED);
798 EFSYS_PROBE1(rx_descq_fls_failed, uint32_t, rxq_index);
800 should_abort = eecp->eec_rxq_flush_failed(arg,
803 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE);
805 EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index);
807 should_abort = eecp->eec_rxq_flush_done(arg, rxq_index);
812 case FSE_AZ_EVQ_INIT_DONE_EV:
813 EFSYS_ASSERT(eecp->eec_initialized != NULL);
814 should_abort = eecp->eec_initialized(arg);
818 case FSE_AZ_EVQ_NOT_EN_EV:
819 EFSYS_PROBE(evq_not_en);
822 case FSE_AZ_SRM_UPD_DONE_EV: {
825 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_SRM_UPD_DONE);
827 code = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
829 EFSYS_ASSERT(eecp->eec_sram != NULL);
830 should_abort = eecp->eec_sram(arg, code);
834 case FSE_AZ_WAKE_UP_EV: {
837 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
839 EFSYS_ASSERT(eecp->eec_wake_up != NULL);
840 should_abort = eecp->eec_wake_up(arg, id);
844 case FSE_AZ_TX_PKT_NON_TCP_UDP:
845 EFSYS_PROBE(tx_pkt_non_tcp_udp);
848 case FSE_AZ_TIMER_EV: {
851 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
853 EFSYS_ASSERT(eecp->eec_timer != NULL);
854 should_abort = eecp->eec_timer(arg, id);
858 case FSE_AZ_RX_DSC_ERROR_EV:
859 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DSC_ERROR);
861 EFSYS_PROBE(rx_dsc_error);
863 EFSYS_ASSERT(eecp->eec_exception != NULL);
864 should_abort = eecp->eec_exception(arg,
865 EFX_EXCEPTION_RX_DSC_ERROR, 0);
869 case FSE_AZ_TX_DSC_ERROR_EV:
870 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DSC_ERROR);
872 EFSYS_PROBE(tx_dsc_error);
874 EFSYS_ASSERT(eecp->eec_exception != NULL);
875 should_abort = eecp->eec_exception(arg,
876 EFX_EXCEPTION_TX_DSC_ERROR, 0);
884 return (should_abort);
887 static __checkReturn boolean_t
888 falconsiena_ev_drv_gen(
890 __in efx_qword_t *eqp,
891 __in const efx_ev_callbacks_t *eecp,
895 boolean_t should_abort;
897 EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN);
899 data = EFX_QWORD_FIELD(*eqp, FSF_AZ_EV_DATA_DW0);
900 if (data >= ((uint32_t)1 << 16)) {
901 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
902 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
903 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
907 EFSYS_ASSERT(eecp->eec_software != NULL);
908 should_abort = eecp->eec_software(arg, (uint16_t)data);
910 return (should_abort);
915 static __checkReturn boolean_t
918 __in efx_qword_t *eqp,
919 __in const efx_ev_callbacks_t *eecp,
922 efx_nic_t *enp = eep->ee_enp;
924 boolean_t should_abort = B_FALSE;
926 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
928 if (enp->en_family != EFX_FAMILY_SIENA)
931 EFSYS_ASSERT(eecp->eec_link_change != NULL);
932 EFSYS_ASSERT(eecp->eec_exception != NULL);
933 #if EFSYS_OPT_MON_STATS
934 EFSYS_ASSERT(eecp->eec_monitor != NULL);
937 EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE);
939 code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE);
941 case MCDI_EVENT_CODE_BADSSERT:
942 efx_mcdi_ev_death(enp, EINTR);
945 case MCDI_EVENT_CODE_CMDDONE:
947 MCDI_EV_FIELD(eqp, CMDDONE_SEQ),
948 MCDI_EV_FIELD(eqp, CMDDONE_DATALEN),
949 MCDI_EV_FIELD(eqp, CMDDONE_ERRNO));
952 case MCDI_EVENT_CODE_LINKCHANGE: {
953 efx_link_mode_t link_mode;
955 siena_phy_link_ev(enp, eqp, &link_mode);
956 should_abort = eecp->eec_link_change(arg, link_mode);
959 case MCDI_EVENT_CODE_SENSOREVT: {
960 #if EFSYS_OPT_MON_STATS
962 efx_mon_stat_value_t value;
965 if ((rc = mcdi_mon_ev(enp, eqp, &id, &value)) == 0)
966 should_abort = eecp->eec_monitor(arg, id, value);
967 else if (rc == ENOTSUP) {
968 should_abort = eecp->eec_exception(arg,
969 EFX_EXCEPTION_UNKNOWN_SENSOREVT,
970 MCDI_EV_FIELD(eqp, DATA));
972 EFSYS_ASSERT(rc == ENODEV); /* Wrong port */
974 should_abort = B_FALSE;
978 case MCDI_EVENT_CODE_SCHEDERR:
979 /* Informational only */
982 case MCDI_EVENT_CODE_REBOOT:
983 efx_mcdi_ev_death(enp, EIO);
986 case MCDI_EVENT_CODE_MAC_STATS_DMA:
987 #if EFSYS_OPT_MAC_STATS
988 if (eecp->eec_mac_stats != NULL) {
989 eecp->eec_mac_stats(arg,
990 MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION));
995 case MCDI_EVENT_CODE_FWALERT: {
996 uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON);
998 if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS)
999 should_abort = eecp->eec_exception(arg,
1000 EFX_EXCEPTION_FWALERT_SRAM,
1001 MCDI_EV_FIELD(eqp, FWALERT_DATA));
1003 should_abort = eecp->eec_exception(arg,
1004 EFX_EXCEPTION_UNKNOWN_FWALERT,
1005 MCDI_EV_FIELD(eqp, DATA));
1010 EFSYS_PROBE1(mc_pcol_error, int, code);
1015 return (should_abort);
1018 #endif /* EFSYS_OPT_MCDI */
1020 static __checkReturn efx_rc_t
1021 falconsiena_ev_qprime(
1022 __in efx_evq_t *eep,
1023 __in unsigned int count)
1025 efx_nic_t *enp = eep->ee_enp;
1029 rptr = count & eep->ee_mask;
1031 EFX_POPULATE_DWORD_1(dword, FRF_AZ_EVQ_RPTR, rptr);
1033 EFX_BAR_TBL_WRITED(enp, FR_AZ_EVQ_RPTR_REG, eep->ee_index,
1039 #define EFX_EV_BATCH 8
1042 falconsiena_ev_qpoll(
1043 __in efx_evq_t *eep,
1044 __inout unsigned int *countp,
1045 __in const efx_ev_callbacks_t *eecp,
1048 efx_qword_t ev[EFX_EV_BATCH];
1055 EFSYS_ASSERT(countp != NULL);
1056 EFSYS_ASSERT(eecp != NULL);
1060 /* Read up until the end of the batch period */
1061 batch = EFX_EV_BATCH - (count & (EFX_EV_BATCH - 1));
1062 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
1063 for (total = 0; total < batch; ++total) {
1064 EFSYS_MEM_READQ(eep->ee_esmp, offset, &(ev[total]));
1066 if (!EFX_EV_PRESENT(ev[total]))
1069 EFSYS_PROBE3(event, unsigned int, eep->ee_index,
1070 uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_1),
1071 uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_0));
1073 offset += sizeof (efx_qword_t);
1076 #if EFSYS_OPT_EV_PREFETCH && (EFSYS_OPT_EV_PREFETCH_PERIOD > 1)
1078 * Prefetch the next batch when we get within PREFETCH_PERIOD
1079 * of a completed batch. If the batch is smaller, then prefetch
1082 if (total == batch && total < EFSYS_OPT_EV_PREFETCH_PERIOD)
1083 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
1084 #endif /* EFSYS_OPT_EV_PREFETCH */
1086 /* Process the batch of events */
1087 for (index = 0; index < total; ++index) {
1088 boolean_t should_abort;
1091 #if EFSYS_OPT_EV_PREFETCH
1092 /* Prefetch if we've now reached the batch period */
1093 if (total == batch &&
1094 index + EFSYS_OPT_EV_PREFETCH_PERIOD == total) {
1095 offset = (count + batch) & eep->ee_mask;
1096 offset *= sizeof (efx_qword_t);
1098 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
1100 #endif /* EFSYS_OPT_EV_PREFETCH */
1102 EFX_EV_QSTAT_INCR(eep, EV_ALL);
1104 code = EFX_QWORD_FIELD(ev[index], FSF_AZ_EV_CODE);
1106 case FSE_AZ_EV_CODE_RX_EV:
1107 should_abort = eep->ee_rx(eep,
1108 &(ev[index]), eecp, arg);
1110 case FSE_AZ_EV_CODE_TX_EV:
1111 should_abort = eep->ee_tx(eep,
1112 &(ev[index]), eecp, arg);
1114 case FSE_AZ_EV_CODE_DRIVER_EV:
1115 should_abort = eep->ee_driver(eep,
1116 &(ev[index]), eecp, arg);
1118 case FSE_AZ_EV_CODE_DRV_GEN_EV:
1119 should_abort = eep->ee_drv_gen(eep,
1120 &(ev[index]), eecp, arg);
1123 case FSE_AZ_EV_CODE_MCDI_EVRESPONSE:
1124 should_abort = eep->ee_mcdi(eep,
1125 &(ev[index]), eecp, arg);
1128 case FSE_AZ_EV_CODE_GLOBAL_EV:
1129 if (eep->ee_global) {
1130 should_abort = eep->ee_global(eep,
1131 &(ev[index]), eecp, arg);
1134 /* else fallthrough */
1136 EFSYS_PROBE3(bad_event,
1137 unsigned int, eep->ee_index,
1139 EFX_QWORD_FIELD(ev[index], EFX_DWORD_1),
1141 EFX_QWORD_FIELD(ev[index], EFX_DWORD_0));
1143 EFSYS_ASSERT(eecp->eec_exception != NULL);
1144 (void) eecp->eec_exception(arg,
1145 EFX_EXCEPTION_EV_ERROR, code);
1146 should_abort = B_TRUE;
1149 /* Ignore subsequent events */
1156 * Now that the hardware has most likely moved onto dma'ing
1157 * into the next cache line, clear the processed events. Take
1158 * care to only clear out events that we've processed
1160 EFX_SET_QWORD(ev[0]);
1161 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
1162 for (index = 0; index < total; ++index) {
1163 EFSYS_MEM_WRITEQ(eep->ee_esmp, offset, &(ev[0]));
1164 offset += sizeof (efx_qword_t);
1169 } while (total == batch);
1175 falconsiena_ev_qpost(
1176 __in efx_evq_t *eep,
1179 efx_nic_t *enp = eep->ee_enp;
1183 EFX_POPULATE_QWORD_2(ev, FSF_AZ_EV_CODE, FSE_AZ_EV_CODE_DRV_GEN_EV,
1184 FSF_AZ_EV_DATA_DW0, (uint32_t)data);
1186 EFX_POPULATE_OWORD_3(oword, FRF_AZ_DRV_EV_QID, eep->ee_index,
1187 EFX_DWORD_0, EFX_QWORD_FIELD(ev, EFX_DWORD_0),
1188 EFX_DWORD_1, EFX_QWORD_FIELD(ev, EFX_DWORD_1));
1190 EFX_BAR_WRITEO(enp, FR_AZ_DRV_EV_REG, &oword);
1193 static __checkReturn efx_rc_t
1194 falconsiena_ev_qmoderate(
1195 __in efx_evq_t *eep,
1196 __in unsigned int us)
1198 efx_nic_t *enp = eep->ee_enp;
1199 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1200 unsigned int locked;
1204 if (us > encp->enc_evq_timer_max_us) {
1209 /* If the value is zero then disable the timer */
1211 EFX_POPULATE_DWORD_2(dword,
1212 FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS,
1213 FRF_CZ_TC_TIMER_VAL, 0);
1217 /* Calculate the timer value in quanta */
1218 timer_val = us * 1000 / encp->enc_evq_timer_quantum_ns;
1220 /* Moderation value is base 0 so we need to deduct 1 */
1224 EFX_POPULATE_DWORD_2(dword,
1225 FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_INT_HLDOFF,
1226 FRF_CZ_TC_TIMER_VAL, timer_val);
1229 locked = (eep->ee_index == 0) ? 1 : 0;
1231 EFX_BAR_TBL_WRITED(enp, FR_BZ_TIMER_COMMAND_REGP0,
1232 eep->ee_index, &dword, locked);
1237 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1242 static __checkReturn efx_rc_t
1243 falconsiena_ev_qcreate(
1244 __in efx_nic_t *enp,
1245 __in unsigned int index,
1246 __in efsys_mem_t *esmp,
1249 __in efx_evq_t *eep)
1251 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1256 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MAXNEVS));
1257 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MINNEVS));
1259 if (!ISP2(n) || (n < EFX_EVQ_MINNEVS) || (n > EFX_EVQ_MAXNEVS)) {
1263 if (index >= encp->enc_evq_limit) {
1267 #if EFSYS_OPT_RX_SCALE
1268 if (enp->en_intr.ei_type == EFX_INTR_LINE &&
1269 index >= EFX_MAXRSS_LEGACY) {
1274 for (size = 0; (1 << size) <= (EFX_EVQ_MAXNEVS / EFX_EVQ_MINNEVS);
1276 if ((1 << size) == (int)(n / EFX_EVQ_MINNEVS))
1278 if (id + (1 << size) >= encp->enc_buftbl_limit) {
1283 /* Set up the handler table */
1284 eep->ee_rx = falconsiena_ev_rx;
1285 eep->ee_tx = falconsiena_ev_tx;
1286 eep->ee_driver = falconsiena_ev_driver;
1287 eep->ee_global = falconsiena_ev_global;
1288 eep->ee_drv_gen = falconsiena_ev_drv_gen;
1290 eep->ee_mcdi = falconsiena_ev_mcdi;
1291 #endif /* EFSYS_OPT_MCDI */
1293 /* Set up the new event queue */
1294 EFX_POPULATE_OWORD_1(oword, FRF_CZ_TIMER_Q_EN, 1);
1295 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, index, &oword, B_TRUE);
1297 EFX_POPULATE_OWORD_3(oword, FRF_AZ_EVQ_EN, 1, FRF_AZ_EVQ_SIZE, size,
1298 FRF_AZ_EVQ_BUF_BASE_ID, id);
1300 EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, index, &oword, B_TRUE);
1306 #if EFSYS_OPT_RX_SCALE
1313 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1318 #endif /* EFSYS_OPT_SIENA */
1320 #if EFSYS_OPT_QSTATS
1322 /* START MKCONFIG GENERATED EfxEventQueueStatNamesBlock b693ddf85aee1bfd */
1323 static const char *__efx_ev_qstat_name[] = {
1330 "rx_buf_owner_id_err",
1331 "rx_ipv4_hdr_chksum_err",
1332 "rx_tcp_udp_chksum_err",
1336 "rx_mcast_hash_match",
1353 "driver_srm_upd_done",
1354 "driver_tx_descq_fls_done",
1355 "driver_rx_descq_fls_done",
1356 "driver_rx_descq_fls_failed",
1357 "driver_rx_dsc_error",
1358 "driver_tx_dsc_error",
1362 /* END MKCONFIG GENERATED EfxEventQueueStatNamesBlock */
1366 __in efx_nic_t *enp,
1367 __in unsigned int id)
1369 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
1370 EFSYS_ASSERT3U(id, <, EV_NQSTATS);
1372 return (__efx_ev_qstat_name[id]);
1374 #endif /* EFSYS_OPT_NAMES */
1375 #endif /* EFSYS_OPT_QSTATS */
1379 #if EFSYS_OPT_QSTATS
1381 falconsiena_ev_qstats_update(
1382 __in efx_evq_t *eep,
1383 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat)
1387 for (id = 0; id < EV_NQSTATS; id++) {
1388 efsys_stat_t *essp = &stat[id];
1390 EFSYS_STAT_INCR(essp, eep->ee_stat[id]);
1391 eep->ee_stat[id] = 0;
1394 #endif /* EFSYS_OPT_QSTATS */
1397 falconsiena_ev_qdestroy(
1398 __in efx_evq_t *eep)
1400 efx_nic_t *enp = eep->ee_enp;
1403 /* Purge event queue */
1404 EFX_ZERO_OWORD(oword);
1406 EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL,
1407 eep->ee_index, &oword, B_TRUE);
1409 EFX_ZERO_OWORD(oword);
1410 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, eep->ee_index, &oword, B_TRUE);
1414 falconsiena_ev_fini(
1415 __in efx_nic_t *enp)
1417 _NOTE(ARGUNUSED(enp))
1420 #endif /* EFSYS_OPT_SIENA */