2 * Copyright (c) 2007-2015 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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33 #ifndef _SYS_EFX_IMPL_H
34 #define _SYS_EFX_IMPL_H
39 #include "efx_regs_ef10.h"
41 /* FIXME: Add definition for driver generated software events */
42 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
43 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
46 #include "efx_check.h"
50 #include "falcon_impl.h"
51 #endif /* EFSYS_OPT_FALCON */
54 #include "siena_impl.h"
55 #endif /* EFSYS_OPT_SIENA */
57 #if EFSYS_OPT_HUNTINGTON
58 #include "hunt_impl.h"
59 #endif /* EFSYS_OPT_HUNTINGTON */
62 #include "medford_impl.h"
63 #endif /* EFSYS_OPT_MEDFORD */
65 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
66 #include "ef10_impl.h"
67 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
73 #define EFX_MOD_MCDI 0x00000001
74 #define EFX_MOD_PROBE 0x00000002
75 #define EFX_MOD_NVRAM 0x00000004
76 #define EFX_MOD_VPD 0x00000008
77 #define EFX_MOD_NIC 0x00000010
78 #define EFX_MOD_INTR 0x00000020
79 #define EFX_MOD_EV 0x00000040
80 #define EFX_MOD_RX 0x00000080
81 #define EFX_MOD_TX 0x00000100
82 #define EFX_MOD_PORT 0x00000200
83 #define EFX_MOD_MON 0x00000400
84 #define EFX_MOD_WOL 0x00000800
85 #define EFX_MOD_FILTER 0x00001000
86 #define EFX_MOD_PKTFILTER 0x00002000
88 #define EFX_RESET_MAC 0x00000001
89 #define EFX_RESET_PHY 0x00000002
90 #define EFX_RESET_RXQ_ERR 0x00000004
91 #define EFX_RESET_TXQ_ERR 0x00000008
93 typedef enum efx_mac_type_e {
102 typedef struct efx_ev_ops_s {
103 efx_rc_t (*eevo_init)(efx_nic_t *);
104 void (*eevo_fini)(efx_nic_t *);
105 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int,
106 efsys_mem_t *, size_t, uint32_t,
108 void (*eevo_qdestroy)(efx_evq_t *);
109 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int);
110 void (*eevo_qpost)(efx_evq_t *, uint16_t);
111 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int);
113 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
117 typedef struct efx_tx_ops_s {
118 efx_rc_t (*etxo_init)(efx_nic_t *);
119 void (*etxo_fini)(efx_nic_t *);
120 efx_rc_t (*etxo_qcreate)(efx_nic_t *,
121 unsigned int, unsigned int,
122 efsys_mem_t *, size_t,
124 efx_evq_t *, efx_txq_t *,
126 void (*etxo_qdestroy)(efx_txq_t *);
127 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
128 unsigned int, unsigned int,
130 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
131 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int);
132 efx_rc_t (*etxo_qflush)(efx_txq_t *);
133 void (*etxo_qenable)(efx_txq_t *);
134 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *);
135 void (*etxo_qpio_disable)(efx_txq_t *);
136 efx_rc_t (*etxo_qpio_write)(efx_txq_t *,uint8_t *, size_t,
138 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
140 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
141 unsigned int, unsigned int,
143 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
146 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
149 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
152 void (*etxo_qstats_update)(efx_txq_t *,
157 typedef struct efx_rx_ops_s {
158 efx_rc_t (*erxo_init)(efx_nic_t *);
159 void (*erxo_fini)(efx_nic_t *);
160 #if EFSYS_OPT_RX_HDR_SPLIT
161 efx_rc_t (*erxo_hdr_split_enable)(efx_nic_t *, unsigned int,
164 #if EFSYS_OPT_RX_SCATTER
165 efx_rc_t (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
167 #if EFSYS_OPT_RX_SCALE
168 efx_rc_t (*erxo_scale_mode_set)(efx_nic_t *, efx_rx_hash_alg_t,
169 efx_rx_hash_type_t, boolean_t);
170 efx_rc_t (*erxo_scale_key_set)(efx_nic_t *, uint8_t *, size_t);
171 efx_rc_t (*erxo_scale_tbl_set)(efx_nic_t *, unsigned int *,
174 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
175 unsigned int, unsigned int,
177 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
178 efx_rc_t (*erxo_qflush)(efx_rxq_t *);
179 void (*erxo_qenable)(efx_rxq_t *);
180 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
181 unsigned int, efx_rxq_type_t,
182 efsys_mem_t *, size_t, uint32_t,
183 efx_evq_t *, efx_rxq_t *);
184 void (*erxo_qdestroy)(efx_rxq_t *);
187 typedef struct efx_mac_ops_s {
188 efx_rc_t (*emo_reset)(efx_nic_t *); /* optional */
189 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
190 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *);
191 efx_rc_t (*emo_addr_set)(efx_nic_t *);
192 efx_rc_t (*emo_reconfigure)(efx_nic_t *);
193 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *);
194 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *,
195 efx_rxq_t *, boolean_t);
196 void (*emo_filter_default_rxq_clear)(efx_nic_t *);
197 #if EFSYS_OPT_LOOPBACK
198 efx_rc_t (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
199 efx_loopback_type_t);
200 #endif /* EFSYS_OPT_LOOPBACK */
201 #if EFSYS_OPT_MAC_STATS
202 efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
203 efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
204 uint16_t, boolean_t);
205 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
206 efsys_stat_t *, uint32_t *);
207 #endif /* EFSYS_OPT_MAC_STATS */
210 typedef struct efx_phy_ops_s {
211 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */
212 efx_rc_t (*epo_reset)(efx_nic_t *);
213 efx_rc_t (*epo_reconfigure)(efx_nic_t *);
214 efx_rc_t (*epo_verify)(efx_nic_t *);
215 efx_rc_t (*epo_uplink_check)(efx_nic_t *,
216 boolean_t *); /* optional */
217 efx_rc_t (*epo_downlink_check)(efx_nic_t *, efx_link_mode_t *,
218 unsigned int *, uint32_t *);
219 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *);
220 #if EFSYS_OPT_PHY_STATS
221 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
223 #endif /* EFSYS_OPT_PHY_STATS */
224 #if EFSYS_OPT_PHY_PROPS
226 const char *(*epo_prop_name)(efx_nic_t *, unsigned int);
227 #endif /* EFSYS_OPT_PHY_PROPS */
228 efx_rc_t (*epo_prop_get)(efx_nic_t *, unsigned int, uint32_t,
230 efx_rc_t (*epo_prop_set)(efx_nic_t *, unsigned int, uint32_t);
231 #endif /* EFSYS_OPT_PHY_PROPS */
233 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *);
234 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
235 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
236 efx_bist_result_t *, uint32_t *,
237 unsigned long *, size_t);
238 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
239 #endif /* EFSYS_OPT_BIST */
243 typedef struct efx_filter_ops_s {
244 efx_rc_t (*efo_init)(efx_nic_t *);
245 void (*efo_fini)(efx_nic_t *);
246 efx_rc_t (*efo_restore)(efx_nic_t *);
247 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
248 boolean_t may_replace);
249 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
250 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *);
251 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
252 boolean_t, boolean_t, boolean_t,
253 uint8_t const *, int);
256 extern __checkReturn efx_rc_t
257 efx_filter_reconfigure(
259 __in_ecount(6) uint8_t const *mac_addr,
260 __in boolean_t all_unicst,
261 __in boolean_t mulcst,
262 __in boolean_t all_mulcst,
263 __in boolean_t brdcst,
264 __in_ecount(6*count) uint8_t const *addrs,
267 #endif /* EFSYS_OPT_FILTER */
269 typedef struct efx_pktfilter_ops_s {
270 efx_rc_t (*epfo_set)(efx_nic_t *,
273 #if EFSYS_OPT_MCAST_FILTER_LIST
274 efx_rc_t (*epfo_mcast_list_set)(efx_nic_t *,
275 uint8_t const *addrs, int count);
276 #endif /* EFSYS_OPT_MCAST_FILTER_LIST */
277 efx_rc_t (*epfo_mcast_all)(efx_nic_t *);
278 } efx_pktfilter_ops_t;
280 typedef struct efx_port_s {
281 efx_mac_type_t ep_mac_type;
282 uint32_t ep_phy_type;
285 uint8_t ep_mac_addr[6];
286 efx_link_mode_t ep_link_mode;
287 boolean_t ep_all_unicst;
289 boolean_t ep_all_mulcst;
291 unsigned int ep_fcntl;
292 boolean_t ep_fcntl_autoneg;
293 efx_oword_t ep_multicst_hash[2];
294 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
295 EFX_MAC_MULTICAST_LIST_MAX];
296 uint32_t ep_mulcst_addr_count;
297 #if EFSYS_OPT_LOOPBACK
298 efx_loopback_type_t ep_loopback_type;
299 efx_link_mode_t ep_loopback_link_mode;
300 #endif /* EFSYS_OPT_LOOPBACK */
301 #if EFSYS_OPT_PHY_FLAGS
302 uint32_t ep_phy_flags;
303 #endif /* EFSYS_OPT_PHY_FLAGS */
304 #if EFSYS_OPT_PHY_LED_CONTROL
305 efx_phy_led_mode_t ep_phy_led_mode;
306 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
307 efx_phy_media_type_t ep_fixed_port_type;
308 efx_phy_media_type_t ep_module_type;
309 uint32_t ep_adv_cap_mask;
310 uint32_t ep_lp_cap_mask;
311 uint32_t ep_default_adv_cap_mask;
312 uint32_t ep_phy_cap_mask;
313 #if EFSYS_OPT_PHY_TXC43128 || EFSYS_OPT_PHY_QT2025C
316 unsigned int bug10934_count;
319 unsigned int bug17190_count;
323 boolean_t ep_mac_poll_needed; /* falcon only */
324 boolean_t ep_mac_up; /* falcon only */
325 uint32_t ep_fwver; /* falcon only */
326 boolean_t ep_mac_drain;
327 boolean_t ep_mac_stats_pending;
329 efx_bist_type_t ep_current_bist;
331 efx_mac_ops_t *ep_emop;
332 efx_phy_ops_t *ep_epop;
335 typedef struct efx_mon_ops_s {
336 efx_rc_t (*emo_reset)(efx_nic_t *);
337 efx_rc_t (*emo_reconfigure)(efx_nic_t *);
338 #if EFSYS_OPT_MON_STATS
339 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
340 efx_mon_stat_value_t *);
341 #endif /* EFSYS_OPT_MON_STATS */
344 typedef struct efx_mon_s {
345 efx_mon_type_t em_type;
346 efx_mon_ops_t *em_emop;
349 typedef struct efx_intr_ops_s {
350 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
351 void (*eio_enable)(efx_nic_t *);
352 void (*eio_disable)(efx_nic_t *);
353 void (*eio_disable_unlocked)(efx_nic_t *);
354 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int);
355 void (*eio_fini)(efx_nic_t *);
358 typedef struct efx_intr_s {
359 efx_intr_ops_t *ei_eiop;
360 efsys_mem_t *ei_esmp;
361 efx_intr_type_t ei_type;
362 unsigned int ei_level;
365 typedef struct efx_nic_ops_s {
366 efx_rc_t (*eno_probe)(efx_nic_t *);
367 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
368 efx_rc_t (*eno_reset)(efx_nic_t *);
369 efx_rc_t (*eno_init)(efx_nic_t *);
370 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
371 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
372 uint32_t *, size_t *);
374 efx_rc_t (*eno_sram_test)(efx_nic_t *, efx_sram_pattern_fn_t);
375 efx_rc_t (*eno_register_test)(efx_nic_t *);
376 #endif /* EFSYS_OPT_DIAG */
377 void (*eno_fini)(efx_nic_t *);
378 void (*eno_unprobe)(efx_nic_t *);
381 #ifndef EFX_TXQ_LIMIT_TARGET
382 #define EFX_TXQ_LIMIT_TARGET 259
384 #ifndef EFX_RXQ_LIMIT_TARGET
385 #define EFX_RXQ_LIMIT_TARGET 512
387 #ifndef EFX_TXQ_DC_SIZE
388 #define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
390 #ifndef EFX_RXQ_DC_SIZE
391 #define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
396 typedef struct falconsiena_filter_spec_s {
399 uint32_t fsfs_dmaq_id;
400 uint32_t fsfs_dword[3];
401 } falconsiena_filter_spec_t;
403 typedef enum falconsiena_filter_type_e {
404 EFX_FS_FILTER_RX_TCP_FULL, /* TCP/IPv4 4-tuple {dIP,dTCP,sIP,sTCP} */
405 EFX_FS_FILTER_RX_TCP_WILD, /* TCP/IPv4 dest {dIP,dTCP, -, -} */
406 EFX_FS_FILTER_RX_UDP_FULL, /* UDP/IPv4 4-tuple {dIP,dUDP,sIP,sUDP} */
407 EFX_FS_FILTER_RX_UDP_WILD, /* UDP/IPv4 dest {dIP,dUDP, -, -} */
410 EFX_FS_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */
411 EFX_FS_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */
413 EFX_FS_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
414 EFX_FS_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */
415 EFX_FS_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
416 EFX_FS_FILTER_TX_UDP_WILD, /* UDP/IPv4 source (host, port) */
418 EFX_FS_FILTER_TX_MAC_FULL, /* Ethernet source (MAC address, VLAN ID) */
419 EFX_FS_FILTER_TX_MAC_WILD, /* Ethernet source (MAC address) */
420 #endif /* EFSYS_OPT_SIENA */
423 } falconsiena_filter_type_t;
425 typedef enum falconsiena_filter_tbl_id_e {
426 EFX_FS_FILTER_TBL_RX_IP = 0,
427 EFX_FS_FILTER_TBL_RX_MAC,
428 EFX_FS_FILTER_TBL_TX_IP,
429 EFX_FS_FILTER_TBL_TX_MAC,
431 } falconsiena_filter_tbl_id_t;
433 typedef struct falconsiena_filter_tbl_s {
434 int fsft_size; /* number of entries */
435 int fsft_used; /* active count */
436 uint32_t *fsft_bitmap; /* active bitmap */
437 falconsiena_filter_spec_t *fsft_spec; /* array of saved specs */
438 } falconsiena_filter_tbl_t;
440 typedef struct falconsiena_filter_s {
441 falconsiena_filter_tbl_t fsf_tbl[EFX_FS_FILTER_NTBLS];
442 unsigned int fsf_depth[EFX_FS_FILTER_NTYPES];
443 } falconsiena_filter_t;
445 typedef struct efx_filter_s {
446 #if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA
447 falconsiena_filter_t *ef_falconsiena_filter;
448 #endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */
449 #if EFSYS_OPT_HUNTINGTON
450 hunt_filter_table_t *ef_hunt_filter_table;
451 #endif /* EFSYS_OPT_HUNTINGTON */
455 falconsiena_filter_tbl_clear(
457 __in falconsiena_filter_tbl_id_t tbl);
459 #endif /* EFSYS_OPT_FILTER */
463 typedef struct efx_mcdi_ops_s {
464 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
465 void (*emco_request_copyin)(efx_nic_t *, efx_mcdi_req_t *,
466 unsigned int, boolean_t, boolean_t);
467 void (*emco_request_copyout)(efx_nic_t *, efx_mcdi_req_t *);
468 efx_rc_t (*emco_poll_reboot)(efx_nic_t *);
469 boolean_t (*emco_poll_response)(efx_nic_t *);
470 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
471 void (*emco_fini)(efx_nic_t *);
472 efx_rc_t (*emco_feature_supported)(efx_nic_t *, efx_mcdi_feature_id_t, boolean_t *);
475 typedef struct efx_mcdi_s {
476 efx_mcdi_ops_t *em_emcop;
477 const efx_mcdi_transport_t *em_emtp;
478 efx_mcdi_iface_t em_emip;
481 #endif /* EFSYS_OPT_MCDI */
484 typedef struct efx_nvram_ops_s {
486 efx_rc_t (*envo_test)(efx_nic_t *);
487 #endif /* EFSYS_OPT_DIAG */
488 efx_rc_t (*envo_size)(efx_nic_t *, efx_nvram_type_t, size_t *);
489 efx_rc_t (*envo_get_version)(efx_nic_t *, efx_nvram_type_t,
490 uint32_t *, uint16_t *);
491 efx_rc_t (*envo_rw_start)(efx_nic_t *, efx_nvram_type_t, size_t *);
492 efx_rc_t (*envo_read_chunk)(efx_nic_t *, efx_nvram_type_t,
493 unsigned int, caddr_t, size_t);
494 efx_rc_t (*envo_erase)(efx_nic_t *, efx_nvram_type_t);
495 efx_rc_t (*envo_write_chunk)(efx_nic_t *, efx_nvram_type_t,
496 unsigned int, caddr_t, size_t);
497 void (*envo_rw_finish)(efx_nic_t *, efx_nvram_type_t);
498 efx_rc_t (*envo_set_version)(efx_nic_t *, efx_nvram_type_t,
502 #endif /* EFSYS_OPT_NVRAM */
505 typedef struct efx_vpd_ops_s {
506 efx_rc_t (*evpdo_init)(efx_nic_t *);
507 efx_rc_t (*evpdo_size)(efx_nic_t *, size_t *);
508 efx_rc_t (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
509 efx_rc_t (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
510 efx_rc_t (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
511 efx_rc_t (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
513 efx_rc_t (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
515 efx_rc_t (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
516 efx_vpd_value_t *, unsigned int *);
517 efx_rc_t (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
518 void (*evpdo_fini)(efx_nic_t *);
520 #endif /* EFSYS_OPT_VPD */
522 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
524 __checkReturn efx_rc_t
525 efx_mcdi_nvram_partitions(
527 __out_bcount(size) caddr_t data,
529 __out unsigned int *npartnp);
531 __checkReturn efx_rc_t
532 efx_mcdi_nvram_metadata(
535 __out uint32_t *subtypep,
536 __out_ecount(4) uint16_t version[4],
537 __out_bcount_opt(size) char *descp,
540 __checkReturn efx_rc_t
544 __out_opt size_t *sizep,
545 __out_opt uint32_t *addressp,
546 __out_opt uint32_t *erase_sizep,
547 __out_opt uint32_t *write_sizep);
549 __checkReturn efx_rc_t
550 efx_mcdi_nvram_update_start(
552 __in uint32_t partn);
554 __checkReturn efx_rc_t
558 __in uint32_t offset,
559 __out_bcount(size) caddr_t data,
562 __checkReturn efx_rc_t
563 efx_mcdi_nvram_erase(
566 __in uint32_t offset,
569 __checkReturn efx_rc_t
570 efx_mcdi_nvram_write(
573 __in uint32_t offset,
574 __out_bcount(size) caddr_t data,
577 __checkReturn efx_rc_t
578 efx_mcdi_nvram_update_finish(
581 __in boolean_t reboot);
585 __checkReturn efx_rc_t
588 __in uint32_t partn);
590 #endif /* EFSYS_OPT_DIAG */
592 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
594 typedef struct efx_drv_cfg_s {
595 uint32_t edc_min_vi_count;
596 uint32_t edc_max_vi_count;
598 uint32_t edc_max_piobuf_count;
599 uint32_t edc_pio_alloc_size;
604 efx_family_t en_family;
605 uint32_t en_features;
606 efsys_identifier_t *en_esip;
607 efsys_lock_t *en_eslp;
608 efsys_bar_t *en_esbp;
609 unsigned int en_mod_flags;
610 unsigned int en_reset_flags;
611 efx_nic_cfg_t en_nic_cfg;
612 efx_drv_cfg_t en_drv_cfg;
616 uint32_t en_ev_qcount;
617 uint32_t en_rx_qcount;
618 uint32_t en_tx_qcount;
619 efx_nic_ops_t *en_enop;
620 efx_ev_ops_t *en_eevop;
621 efx_tx_ops_t *en_etxop;
622 efx_rx_ops_t *en_erxop;
624 efx_filter_t en_filter;
625 efx_filter_ops_t *en_efop;
626 #endif /* EFSYS_OPT_FILTER */
627 efx_pktfilter_ops_t *en_epfop;
630 #endif /* EFSYS_OPT_MCDI */
632 efx_nvram_type_t en_nvram_locked;
633 efx_nvram_ops_t *en_envop;
634 #endif /* EFSYS_OPT_NVRAM */
636 efx_vpd_ops_t *en_evpdop;
637 #endif /* EFSYS_OPT_VPD */
638 #if EFSYS_OPT_RX_SCALE
639 efx_rx_hash_support_t en_hash_support;
640 efx_rx_scale_support_t en_rss_support;
641 uint32_t en_rss_context;
642 #endif /* EFSYS_OPT_RX_SCALE */
643 uint32_t en_vport_id;
647 falcon_spi_dev_t enu_fsd[FALCON_SPI_NTYPES];
648 falcon_i2c_t enu_fip;
649 boolean_t enu_i2c_locked;
650 #if EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE
651 const uint8_t *enu_forced_cfg;
652 #endif /* EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE */
653 uint8_t enu_mon_devid;
654 #if EFSYS_OPT_PCIE_TUNE
655 unsigned int enu_nlanes;
656 #endif /* EFSYS_OPT_PCIE_TUNE */
657 uint16_t enu_board_rev;
658 boolean_t enu_internal_sram;
659 uint8_t enu_sram_num_bank;
660 uint8_t enu_sram_bank_size;
662 #endif /* EFSYS_OPT_FALCON */
665 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
666 unsigned int enu_partn_mask;
667 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
670 size_t enu_svpd_length;
671 #endif /* EFSYS_OPT_VPD */
674 #endif /* EFSYS_OPT_SIENA */
675 #if EFSYS_OPT_HUNTINGTON
681 size_t enu_svpd_length;
682 #endif /* EFSYS_OPT_VPD */
683 efx_piobuf_handle_t enu_piobuf_handle[HUNT_PIOBUF_NBUFS];
684 uint32_t enu_piobuf_count;
685 uint32_t enu_pio_alloc_map[HUNT_PIOBUF_NBUFS];
686 uint32_t enu_pio_write_vi_base;
687 /* Memory BAR mapping regions */
688 uint32_t enu_uc_mem_map_offset;
689 size_t enu_uc_mem_map_size;
690 uint32_t enu_wc_mem_map_offset;
691 size_t enu_wc_mem_map_size;
693 #endif /* EFSYS_OPT_HUNTINGTON */
698 #define EFX_NIC_MAGIC 0x02121996
700 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
701 const efx_ev_callbacks_t *, void *);
703 typedef struct efx_evq_rxq_state_s {
704 unsigned int eers_rx_read_ptr;
705 unsigned int eers_rx_mask;
706 } efx_evq_rxq_state_t;
711 unsigned int ee_index;
712 unsigned int ee_mask;
713 efsys_mem_t *ee_esmp;
715 uint32_t ee_stat[EV_NQSTATS];
716 #endif /* EFSYS_OPT_QSTATS */
718 efx_ev_handler_t ee_rx;
719 efx_ev_handler_t ee_tx;
720 efx_ev_handler_t ee_driver;
721 efx_ev_handler_t ee_global;
722 efx_ev_handler_t ee_drv_gen;
724 efx_ev_handler_t ee_mcdi;
725 #endif /* EFSYS_OPT_MCDI */
727 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS];
730 #define EFX_EVQ_MAGIC 0x08081997
732 #define EFX_EVQ_FALCON_TIMER_QUANTUM_NS 4968 /* 621 cycles */
733 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */
739 unsigned int er_index;
740 unsigned int er_label;
741 unsigned int er_mask;
742 efsys_mem_t *er_esmp;
745 #define EFX_RXQ_MAGIC 0x15022005
750 unsigned int et_index;
751 unsigned int et_mask;
752 efsys_mem_t *et_esmp;
753 #if EFSYS_OPT_HUNTINGTON
754 uint32_t et_pio_bufnum;
755 uint32_t et_pio_blknum;
756 uint32_t et_pio_write_offset;
757 uint32_t et_pio_offset;
761 uint32_t et_stat[TX_NQSTATS];
762 #endif /* EFSYS_OPT_QSTATS */
765 #define EFX_TXQ_MAGIC 0x05092005
767 #define EFX_MAC_ADDR_COPY(_dst, _src) \
769 (_dst)[0] = (_src)[0]; \
770 (_dst)[1] = (_src)[1]; \
771 (_dst)[2] = (_src)[2]; \
772 (_dst)[3] = (_src)[3]; \
773 (_dst)[4] = (_src)[4]; \
774 (_dst)[5] = (_src)[5]; \
775 _NOTE(CONSTANTCONDITION) \
778 #define EFX_MAC_BROADCAST_ADDR_SET(_dst) \
780 uint16_t *_d = (uint16_t *)(_dst); \
784 _NOTE(CONSTANTCONDITION) \
787 #if EFSYS_OPT_CHECK_REG
788 #define EFX_CHECK_REG(_enp, _reg) \
790 const char *name = #_reg; \
791 char min = name[4]; \
792 char max = name[5]; \
795 switch ((_enp)->en_family) { \
796 case EFX_FAMILY_FALCON: \
800 case EFX_FAMILY_SIENA: \
804 case EFX_FAMILY_HUNTINGTON: \
808 case EFX_FAMILY_MEDFORD: \
817 EFSYS_ASSERT3S(rev, >=, min); \
818 EFSYS_ASSERT3S(rev, <=, max); \
820 _NOTE(CONSTANTCONDITION) \
823 #define EFX_CHECK_REG(_enp, _reg) do { \
824 _NOTE(CONSTANTCONDITION) \
828 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \
830 EFX_CHECK_REG((_enp), (_reg)); \
831 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \
833 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \
834 uint32_t, _reg ## _OFST, \
835 uint32_t, (_edp)->ed_u32[0]); \
836 _NOTE(CONSTANTCONDITION) \
839 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \
841 EFX_CHECK_REG((_enp), (_reg)); \
842 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \
843 uint32_t, _reg ## _OFST, \
844 uint32_t, (_edp)->ed_u32[0]); \
845 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \
847 _NOTE(CONSTANTCONDITION) \
850 #define EFX_BAR_READQ(_enp, _reg, _eqp) \
852 EFX_CHECK_REG((_enp), (_reg)); \
853 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \
855 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \
856 uint32_t, _reg ## _OFST, \
857 uint32_t, (_eqp)->eq_u32[1], \
858 uint32_t, (_eqp)->eq_u32[0]); \
859 _NOTE(CONSTANTCONDITION) \
862 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \
864 EFX_CHECK_REG((_enp), (_reg)); \
865 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \
866 uint32_t, _reg ## _OFST, \
867 uint32_t, (_eqp)->eq_u32[1], \
868 uint32_t, (_eqp)->eq_u32[0]); \
869 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \
871 _NOTE(CONSTANTCONDITION) \
874 #define EFX_BAR_READO(_enp, _reg, _eop) \
876 EFX_CHECK_REG((_enp), (_reg)); \
877 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \
879 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \
880 uint32_t, _reg ## _OFST, \
881 uint32_t, (_eop)->eo_u32[3], \
882 uint32_t, (_eop)->eo_u32[2], \
883 uint32_t, (_eop)->eo_u32[1], \
884 uint32_t, (_eop)->eo_u32[0]); \
885 _NOTE(CONSTANTCONDITION) \
888 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \
890 EFX_CHECK_REG((_enp), (_reg)); \
891 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \
892 uint32_t, _reg ## _OFST, \
893 uint32_t, (_eop)->eo_u32[3], \
894 uint32_t, (_eop)->eo_u32[2], \
895 uint32_t, (_eop)->eo_u32[1], \
896 uint32_t, (_eop)->eo_u32[0]); \
897 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \
899 _NOTE(CONSTANTCONDITION) \
902 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \
904 EFX_CHECK_REG((_enp), (_reg)); \
905 EFSYS_BAR_READD((_enp)->en_esbp, \
906 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
908 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \
909 uint32_t, (_index), \
910 uint32_t, _reg ## _OFST, \
911 uint32_t, (_edp)->ed_u32[0]); \
912 _NOTE(CONSTANTCONDITION) \
915 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \
917 EFX_CHECK_REG((_enp), (_reg)); \
918 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
919 uint32_t, (_index), \
920 uint32_t, _reg ## _OFST, \
921 uint32_t, (_edp)->ed_u32[0]); \
922 EFSYS_BAR_WRITED((_enp)->en_esbp, \
923 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
925 _NOTE(CONSTANTCONDITION) \
928 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock) \
930 EFX_CHECK_REG((_enp), (_reg)); \
931 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
932 uint32_t, (_index), \
933 uint32_t, _reg ## _OFST, \
934 uint32_t, (_edp)->ed_u32[0]); \
935 EFSYS_BAR_WRITED((_enp)->en_esbp, \
937 (2 * sizeof (efx_dword_t)) + \
938 ((_index) * _reg ## _STEP)), \
940 _NOTE(CONSTANTCONDITION) \
943 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \
945 EFX_CHECK_REG((_enp), (_reg)); \
946 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
947 uint32_t, (_index), \
948 uint32_t, _reg ## _OFST, \
949 uint32_t, (_edp)->ed_u32[0]); \
950 EFSYS_BAR_WRITED((_enp)->en_esbp, \
952 (3 * sizeof (efx_dword_t)) + \
953 ((_index) * _reg ## _STEP)), \
955 _NOTE(CONSTANTCONDITION) \
958 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \
960 EFX_CHECK_REG((_enp), (_reg)); \
961 EFSYS_BAR_READQ((_enp)->en_esbp, \
962 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
964 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \
965 uint32_t, (_index), \
966 uint32_t, _reg ## _OFST, \
967 uint32_t, (_eqp)->eq_u32[1], \
968 uint32_t, (_eqp)->eq_u32[0]); \
969 _NOTE(CONSTANTCONDITION) \
972 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \
974 EFX_CHECK_REG((_enp), (_reg)); \
975 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \
976 uint32_t, (_index), \
977 uint32_t, _reg ## _OFST, \
978 uint32_t, (_eqp)->eq_u32[1], \
979 uint32_t, (_eqp)->eq_u32[0]); \
980 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \
981 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
983 _NOTE(CONSTANTCONDITION) \
986 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \
988 EFX_CHECK_REG((_enp), (_reg)); \
989 EFSYS_BAR_READO((_enp)->en_esbp, \
990 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
992 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \
993 uint32_t, (_index), \
994 uint32_t, _reg ## _OFST, \
995 uint32_t, (_eop)->eo_u32[3], \
996 uint32_t, (_eop)->eo_u32[2], \
997 uint32_t, (_eop)->eo_u32[1], \
998 uint32_t, (_eop)->eo_u32[0]); \
999 _NOTE(CONSTANTCONDITION) \
1002 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \
1004 EFX_CHECK_REG((_enp), (_reg)); \
1005 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \
1006 uint32_t, (_index), \
1007 uint32_t, _reg ## _OFST, \
1008 uint32_t, (_eop)->eo_u32[3], \
1009 uint32_t, (_eop)->eo_u32[2], \
1010 uint32_t, (_eop)->eo_u32[1], \
1011 uint32_t, (_eop)->eo_u32[0]); \
1012 EFSYS_BAR_WRITEO((_enp)->en_esbp, \
1013 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1015 _NOTE(CONSTANTCONDITION) \
1019 * Allow drivers to perform optimised 128-bit doorbell writes.
1020 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1021 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1022 * the need for locking in the host, and are the only ones known to be safe to
1023 * use 128-bites write with.
1025 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \
1027 EFX_CHECK_REG((_enp), (_reg)); \
1028 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo, \
1031 uint32_t, (_index), \
1032 uint32_t, _reg ## _OFST, \
1033 uint32_t, (_eop)->eo_u32[3], \
1034 uint32_t, (_eop)->eo_u32[2], \
1035 uint32_t, (_eop)->eo_u32[1], \
1036 uint32_t, (_eop)->eo_u32[0]); \
1037 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \
1038 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
1040 _NOTE(CONSTANTCONDITION) \
1043 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \
1045 unsigned int _new = (_wptr); \
1046 unsigned int _old = (_owptr); \
1048 if ((_new) >= (_old)) \
1049 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1050 (_old) * sizeof (efx_desc_t), \
1051 ((_new) - (_old)) * sizeof (efx_desc_t)); \
1054 * It is cheaper to sync entire map than sync \
1055 * two parts especially when offset/size are \
1056 * ignored and entire map is synced in any case.\
1058 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
1060 (_entries) * sizeof (efx_desc_t)); \
1061 _NOTE(CONSTANTCONDITION) \
1064 extern __checkReturn efx_rc_t
1066 __in efx_nic_t *enp);
1068 extern __checkReturn efx_rc_t
1070 __in efx_nic_t *enp);
1073 efx_mac_multicast_hash_compute(
1074 __in_ecount(6*count) uint8_t const *addrs,
1076 __out efx_oword_t *hash_low,
1077 __out efx_oword_t *hash_high);
1079 extern __checkReturn efx_rc_t
1081 __in efx_nic_t *enp);
1085 __in efx_nic_t *enp);
1089 /* VPD utility functions */
1091 extern __checkReturn efx_rc_t
1092 efx_vpd_hunk_length(
1093 __in_bcount(size) caddr_t data,
1095 __out size_t *lengthp);
1097 extern __checkReturn efx_rc_t
1098 efx_vpd_hunk_verify(
1099 __in_bcount(size) caddr_t data,
1101 __out_opt boolean_t *cksummedp);
1103 extern __checkReturn efx_rc_t
1104 efx_vpd_hunk_reinit(
1105 __in_bcount(size) caddr_t data,
1107 __in boolean_t wantpid);
1109 extern __checkReturn efx_rc_t
1111 __in_bcount(size) caddr_t data,
1113 __in efx_vpd_tag_t tag,
1114 __in efx_vpd_keyword_t keyword,
1115 __out unsigned int *payloadp,
1116 __out uint8_t *paylenp);
1118 extern __checkReturn efx_rc_t
1120 __in_bcount(size) caddr_t data,
1122 __out efx_vpd_tag_t *tagp,
1123 __out efx_vpd_keyword_t *keyword,
1124 __out_bcount_opt(*paylenp) unsigned int *payloadp,
1125 __out_opt uint8_t *paylenp,
1126 __inout unsigned int *contp);
1128 extern __checkReturn efx_rc_t
1130 __in_bcount(size) caddr_t data,
1132 __in efx_vpd_value_t *evvp);
1134 #endif /* EFSYS_OPT_VPD */
1138 extern efx_sram_pattern_fn_t __efx_sram_pattern_fns[];
1140 typedef struct efx_register_set_s {
1141 unsigned int address;
1145 } efx_register_set_t;
1147 extern __checkReturn efx_rc_t
1148 efx_nic_test_registers(
1149 __in efx_nic_t *enp,
1150 __in efx_register_set_t *rsp,
1153 extern __checkReturn efx_rc_t
1154 efx_nic_test_tables(
1155 __in efx_nic_t *enp,
1156 __in efx_register_set_t *rsp,
1157 __in efx_pattern_type_t pattern,
1160 #endif /* EFSYS_OPT_DIAG */
1164 extern __checkReturn efx_rc_t
1165 efx_mcdi_set_workaround(
1166 __in efx_nic_t *enp,
1168 __in boolean_t enabled,
1169 __out_opt uint32_t *flagsp);
1171 extern __checkReturn efx_rc_t
1172 efx_mcdi_get_workarounds(
1173 __in efx_nic_t *enp,
1174 __out_opt uint32_t *implementedp,
1175 __out_opt uint32_t *enabledp);
1177 #endif /* EFSYS_OPT_MCDI */
1183 #endif /* _SYS_EFX_IMPL_H */