sys/dev/sfxge/common/efx_impl.h

   1 /*-
   2  * Copyright (c) 2007-2015 Solarflare Communications Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  * 1. Redistributions of source code must retain the above copyright notice,
   9  *    this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright notice,
  11  *    this list of conditions and the following disclaimer in the documentation
  12  *    and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  15  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  16  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  18  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  19  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  20  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  21  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  22  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  23  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  24  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  * The views and conclusions contained in the software and documentation are
  27  * those of the authors and should not be interpreted as representing official
  28  * policies, either expressed or implied, of the FreeBSD Project.
  29  *
  30  * $FreeBSD$
  31  */
  32
  33 #ifndef _SYS_EFX_IMPL_H
  34 #define _SYS_EFX_IMPL_H
  35
  36 #include "efx.h"
  37 #include "efx_regs.h"
  38 #include "efx_regs_ef10.h"
  39
  40 /* FIXME: Add definition for driver generated software events */
  41 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
  42 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
  43 #endif
  44
  45
  46 #if EFSYS_OPT_SIENA
  47 #include "siena_impl.h"
  48 #endif  /* EFSYS_OPT_SIENA */
  49
  50 #if EFSYS_OPT_HUNTINGTON
  51 #include "hunt_impl.h"
  52 #endif  /* EFSYS_OPT_HUNTINGTON */
  53
  54 #if EFSYS_OPT_MEDFORD
  55 #include "medford_impl.h"
  56 #endif  /* EFSYS_OPT_MEDFORD */
  57
  58 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
  59 #include "ef10_impl.h"
  60 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
  61
  62 #ifdef  __cplusplus
  63 extern "C" {
  64 #endif
  65
  66 #define EFX_MOD_MCDI            0x00000001
  67 #define EFX_MOD_PROBE           0x00000002
  68 #define EFX_MOD_NVRAM           0x00000004
  69 #define EFX_MOD_VPD             0x00000008
  70 #define EFX_MOD_NIC             0x00000010
  71 #define EFX_MOD_INTR            0x00000020
  72 #define EFX_MOD_EV              0x00000040
  73 #define EFX_MOD_RX              0x00000080
  74 #define EFX_MOD_TX              0x00000100
  75 #define EFX_MOD_PORT            0x00000200
  76 #define EFX_MOD_MON             0x00000400
  77 #define EFX_MOD_WOL             0x00000800
  78 #define EFX_MOD_FILTER          0x00001000
  79 #define EFX_MOD_LIC             0x00002000
  80
  81 #define EFX_RESET_MAC           0x00000001
  82 #define EFX_RESET_PHY           0x00000002
  83 #define EFX_RESET_RXQ_ERR       0x00000004
  84 #define EFX_RESET_TXQ_ERR       0x00000008
  85
  86 typedef enum efx_mac_type_e {
  87         EFX_MAC_INVALID = 0,
  88         EFX_MAC_SIENA,
  89         EFX_MAC_HUNTINGTON,
  90         EFX_MAC_MEDFORD,
  91         EFX_MAC_NTYPES
  92 } efx_mac_type_t;
  93
  94 typedef struct efx_ev_ops_s {
  95         efx_rc_t        (*eevo_init)(efx_nic_t *);
  96         void            (*eevo_fini)(efx_nic_t *);
  97         efx_rc_t        (*eevo_qcreate)(efx_nic_t *, unsigned int,
  98                                           efsys_mem_t *, size_t, uint32_t,
  99                                           efx_evq_t *);
 100         void            (*eevo_qdestroy)(efx_evq_t *);
 101         efx_rc_t        (*eevo_qprime)(efx_evq_t *, unsigned int);
 102         void            (*eevo_qpost)(efx_evq_t *, uint16_t);
 103         efx_rc_t        (*eevo_qmoderate)(efx_evq_t *, unsigned int);
 104 #if EFSYS_OPT_QSTATS
 105         void            (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
 106 #endif
 107 } efx_ev_ops_t;
 108
 109 typedef struct efx_tx_ops_s {
 110         efx_rc_t        (*etxo_init)(efx_nic_t *);
 111         void            (*etxo_fini)(efx_nic_t *);
 112         efx_rc_t        (*etxo_qcreate)(efx_nic_t *,
 113                                         unsigned int, unsigned int,
 114                                         efsys_mem_t *, size_t,
 115                                         uint32_t, uint16_t,
 116                                         efx_evq_t *, efx_txq_t *,
 117                                         unsigned int *);
 118         void            (*etxo_qdestroy)(efx_txq_t *);
 119         efx_rc_t        (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
 120                                       unsigned int, unsigned int,
 121                                       unsigned int *);
 122         void            (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
 123         efx_rc_t        (*etxo_qpace)(efx_txq_t *, unsigned int);
 124         efx_rc_t        (*etxo_qflush)(efx_txq_t *);
 125         void            (*etxo_qenable)(efx_txq_t *);
 126         efx_rc_t        (*etxo_qpio_enable)(efx_txq_t *);
 127         void            (*etxo_qpio_disable)(efx_txq_t *);
 128         efx_rc_t        (*etxo_qpio_write)(efx_txq_t *,uint8_t *, size_t,
 129                                            size_t);
 130         efx_rc_t        (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
 131                                            unsigned int *);
 132         efx_rc_t        (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
 133                                       unsigned int, unsigned int,
 134                                       unsigned int *);
 135         void            (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
 136                                                 size_t, boolean_t,
 137                                                 efx_desc_t *);
 138         void            (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
 139                                                 uint32_t, uint8_t,
 140                                                 efx_desc_t *);
 141         void            (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
 142                                                 uint32_t, uint16_t,
 143                                                 efx_desc_t *, int);
 144         void            (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
 145                                                 efx_desc_t *);
 146 #if EFSYS_OPT_QSTATS
 147         void            (*etxo_qstats_update)(efx_txq_t *,
 148                                               efsys_stat_t *);
 149 #endif
 150 } efx_tx_ops_t;
 151
 152 typedef struct efx_rx_ops_s {
 153         efx_rc_t        (*erxo_init)(efx_nic_t *);
 154         void            (*erxo_fini)(efx_nic_t *);
 155 #if EFSYS_OPT_RX_SCATTER
 156         efx_rc_t        (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
 157 #endif
 158 #if EFSYS_OPT_RX_SCALE
 159         efx_rc_t        (*erxo_scale_mode_set)(efx_nic_t *, efx_rx_hash_alg_t,
 160                                                efx_rx_hash_type_t, boolean_t);
 161         efx_rc_t        (*erxo_scale_key_set)(efx_nic_t *, uint8_t *, size_t);
 162         efx_rc_t        (*erxo_scale_tbl_set)(efx_nic_t *, unsigned int *,
 163                                               size_t);
 164         uint32_t        (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
 165                                             uint8_t *);
 166 #endif /* EFSYS_OPT_RX_SCALE */
 167         efx_rc_t        (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
 168                                               uint16_t *);
 169         void            (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
 170                                       unsigned int, unsigned int,
 171                                       unsigned int);
 172         void            (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
 173         efx_rc_t        (*erxo_qflush)(efx_rxq_t *);
 174         void            (*erxo_qenable)(efx_rxq_t *);
 175         efx_rc_t        (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
 176                                         unsigned int, efx_rxq_type_t,
 177                                         efsys_mem_t *, size_t, uint32_t,
 178                                         efx_evq_t *, efx_rxq_t *);
 179         void            (*erxo_qdestroy)(efx_rxq_t *);
 180 } efx_rx_ops_t;
 181
 182 typedef struct efx_mac_ops_s {
 183         efx_rc_t        (*emo_reset)(efx_nic_t *); /* optional */
 184         efx_rc_t        (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
 185         efx_rc_t        (*emo_up)(efx_nic_t *, boolean_t *);
 186         efx_rc_t        (*emo_addr_set)(efx_nic_t *);
 187         efx_rc_t        (*emo_pdu_set)(efx_nic_t *);
 188         efx_rc_t        (*emo_reconfigure)(efx_nic_t *);
 189         efx_rc_t        (*emo_multicast_list_set)(efx_nic_t *);
 190         efx_rc_t        (*emo_filter_default_rxq_set)(efx_nic_t *,
 191                                                       efx_rxq_t *, boolean_t);
 192         void            (*emo_filter_default_rxq_clear)(efx_nic_t *);
 193 #if EFSYS_OPT_LOOPBACK
 194         efx_rc_t        (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
 195                                             efx_loopback_type_t);
 196 #endif  /* EFSYS_OPT_LOOPBACK */
 197 #if EFSYS_OPT_MAC_STATS
 198         efx_rc_t        (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
 199         efx_rc_t        (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
 200                                               uint16_t, boolean_t);
 201         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 202                                             efsys_stat_t *, uint32_t *);
 203 #endif  /* EFSYS_OPT_MAC_STATS */
 204 } efx_mac_ops_t;
 205
 206 typedef struct efx_phy_ops_s {
 207         efx_rc_t        (*epo_power)(efx_nic_t *, boolean_t); /* optional */
 208         efx_rc_t        (*epo_reset)(efx_nic_t *);
 209         efx_rc_t        (*epo_reconfigure)(efx_nic_t *);
 210         efx_rc_t        (*epo_verify)(efx_nic_t *);
 211         efx_rc_t        (*epo_uplink_check)(efx_nic_t *,
 212                                             boolean_t *); /* optional */
 213         efx_rc_t        (*epo_downlink_check)(efx_nic_t *, efx_link_mode_t *,
 214                                               unsigned int *, uint32_t *);
 215         efx_rc_t        (*epo_oui_get)(efx_nic_t *, uint32_t *);
 216 #if EFSYS_OPT_PHY_STATS
 217         efx_rc_t        (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
 218                                             uint32_t *);
 219 #endif  /* EFSYS_OPT_PHY_STATS */
 220 #if EFSYS_OPT_PHY_PROPS
 221 #if EFSYS_OPT_NAMES
 222         const char      *(*epo_prop_name)(efx_nic_t *, unsigned int);
 223 #endif  /* EFSYS_OPT_PHY_PROPS */
 224         efx_rc_t        (*epo_prop_get)(efx_nic_t *, unsigned int, uint32_t,
 225                                         uint32_t *);
 226         efx_rc_t        (*epo_prop_set)(efx_nic_t *, unsigned int, uint32_t);
 227 #endif  /* EFSYS_OPT_PHY_PROPS */
 228 #if EFSYS_OPT_BIST
 229         efx_rc_t        (*epo_bist_enable_offline)(efx_nic_t *);
 230         efx_rc_t        (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
 231         efx_rc_t        (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
 232                                          efx_bist_result_t *, uint32_t *,
 233                                          unsigned long *, size_t);
 234         void            (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
 235 #endif  /* EFSYS_OPT_BIST */
 236 } efx_phy_ops_t;
 237
 238 #if EFSYS_OPT_FILTER
 239 typedef struct efx_filter_ops_s {
 240         efx_rc_t        (*efo_init)(efx_nic_t *);
 241         void            (*efo_fini)(efx_nic_t *);
 242         efx_rc_t        (*efo_restore)(efx_nic_t *);
 243         efx_rc_t        (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
 244                                    boolean_t may_replace);
 245         efx_rc_t        (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
 246         efx_rc_t        (*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *);
 247         efx_rc_t        (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
 248                                    boolean_t, boolean_t, boolean_t,
 249                                    uint8_t const *, int);
 250 } efx_filter_ops_t;
 251
 252 extern  __checkReturn   efx_rc_t
 253 efx_filter_reconfigure(
 254         __in                            efx_nic_t *enp,
 255         __in_ecount(6)                  uint8_t const *mac_addr,
 256         __in                            boolean_t all_unicst,
 257         __in                            boolean_t mulcst,
 258         __in                            boolean_t all_mulcst,
 259         __in                            boolean_t brdcst,
 260         __in_ecount(6*count)            uint8_t const *addrs,
 261         __in                            int count);
 262
 263 #endif /* EFSYS_OPT_FILTER */
 264
 265
 266 typedef struct efx_port_s {
 267         efx_mac_type_t          ep_mac_type;
 268         uint32_t                ep_phy_type;
 269         uint8_t                 ep_port;
 270         uint32_t                ep_mac_pdu;
 271         uint8_t                 ep_mac_addr[6];
 272         efx_link_mode_t         ep_link_mode;
 273         boolean_t               ep_all_unicst;
 274         boolean_t               ep_mulcst;
 275         boolean_t               ep_all_mulcst;
 276         boolean_t               ep_brdcst;
 277         unsigned int            ep_fcntl;
 278         boolean_t               ep_fcntl_autoneg;
 279         efx_oword_t             ep_multicst_hash[2];
 280         uint8_t                 ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
 281                                                     EFX_MAC_MULTICAST_LIST_MAX];
 282         uint32_t                ep_mulcst_addr_count;
 283 #if EFSYS_OPT_LOOPBACK
 284         efx_loopback_type_t     ep_loopback_type;
 285         efx_link_mode_t         ep_loopback_link_mode;
 286 #endif  /* EFSYS_OPT_LOOPBACK */
 287 #if EFSYS_OPT_PHY_FLAGS
 288         uint32_t                ep_phy_flags;
 289 #endif  /* EFSYS_OPT_PHY_FLAGS */
 290 #if EFSYS_OPT_PHY_LED_CONTROL
 291         efx_phy_led_mode_t      ep_phy_led_mode;
 292 #endif  /* EFSYS_OPT_PHY_LED_CONTROL */
 293         efx_phy_media_type_t    ep_fixed_port_type;
 294         efx_phy_media_type_t    ep_module_type;
 295         uint32_t                ep_adv_cap_mask;
 296         uint32_t                ep_lp_cap_mask;
 297         uint32_t                ep_default_adv_cap_mask;
 298         uint32_t                ep_phy_cap_mask;
 299         boolean_t               ep_mac_drain;
 300         boolean_t               ep_mac_stats_pending;
 301 #if EFSYS_OPT_BIST
 302         efx_bist_type_t         ep_current_bist;
 303 #endif
 304         efx_mac_ops_t           *ep_emop;
 305         efx_phy_ops_t           *ep_epop;
 306 } efx_port_t;
 307
 308 typedef struct efx_mon_ops_s {
 309         efx_rc_t        (*emo_reset)(efx_nic_t *);
 310         efx_rc_t        (*emo_reconfigure)(efx_nic_t *);
 311 #if EFSYS_OPT_MON_STATS
 312         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 313                                             efx_mon_stat_value_t *);
 314 #endif  /* EFSYS_OPT_MON_STATS */
 315 } efx_mon_ops_t;
 316
 317 typedef struct efx_mon_s {
 318         efx_mon_type_t  em_type;
 319         efx_mon_ops_t   *em_emop;
 320 } efx_mon_t;
 321
 322 typedef struct efx_intr_ops_s {
 323         efx_rc_t        (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
 324         void            (*eio_enable)(efx_nic_t *);
 325         void            (*eio_disable)(efx_nic_t *);
 326         void            (*eio_disable_unlocked)(efx_nic_t *);
 327         efx_rc_t        (*eio_trigger)(efx_nic_t *, unsigned int);
 328         void            (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
 329         void            (*eio_status_message)(efx_nic_t *, unsigned int,
 330                                  boolean_t *);
 331         void            (*eio_fatal)(efx_nic_t *);
 332         void            (*eio_fini)(efx_nic_t *);
 333 } efx_intr_ops_t;
 334
 335 typedef struct efx_intr_s {
 336         efx_intr_ops_t  *ei_eiop;
 337         efsys_mem_t     *ei_esmp;
 338         efx_intr_type_t ei_type;
 339         unsigned int    ei_level;
 340 } efx_intr_t;
 341
 342 typedef struct efx_nic_ops_s {
 343         efx_rc_t        (*eno_probe)(efx_nic_t *);
 344         efx_rc_t        (*eno_board_cfg)(efx_nic_t *);
 345         efx_rc_t        (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
 346         efx_rc_t        (*eno_reset)(efx_nic_t *);
 347         efx_rc_t        (*eno_init)(efx_nic_t *);
 348         efx_rc_t        (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
 349         efx_rc_t        (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
 350                                         uint32_t *, size_t *);
 351 #if EFSYS_OPT_DIAG
 352         efx_rc_t        (*eno_register_test)(efx_nic_t *);
 353 #endif  /* EFSYS_OPT_DIAG */
 354         void            (*eno_fini)(efx_nic_t *);
 355         void            (*eno_unprobe)(efx_nic_t *);
 356 } efx_nic_ops_t;
 357
 358 #ifndef EFX_TXQ_LIMIT_TARGET
 359 #define EFX_TXQ_LIMIT_TARGET 259
 360 #endif
 361 #ifndef EFX_RXQ_LIMIT_TARGET
 362 #define EFX_RXQ_LIMIT_TARGET 512
 363 #endif
 364 #ifndef EFX_TXQ_DC_SIZE
 365 #define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
 366 #endif
 367 #ifndef EFX_RXQ_DC_SIZE
 368 #define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
 369 #endif
 370
 371 #if EFSYS_OPT_FILTER
 372
 373 typedef struct falconsiena_filter_spec_s {
 374         uint8_t         fsfs_type;
 375         uint32_t        fsfs_flags;
 376         uint32_t        fsfs_dmaq_id;
 377         uint32_t        fsfs_dword[3];
 378 } falconsiena_filter_spec_t;
 379
 380 typedef enum falconsiena_filter_type_e {
 381         EFX_FS_FILTER_RX_TCP_FULL,      /* TCP/IPv4 4-tuple {dIP,dTCP,sIP,sTCP} */
 382         EFX_FS_FILTER_RX_TCP_WILD,      /* TCP/IPv4 dest    {dIP,dTCP,  -,   -} */
 383         EFX_FS_FILTER_RX_UDP_FULL,      /* UDP/IPv4 4-tuple {dIP,dUDP,sIP,sUDP} */
 384         EFX_FS_FILTER_RX_UDP_WILD,      /* UDP/IPv4 dest    {dIP,dUDP,  -,   -} */
 385
 386 #if EFSYS_OPT_SIENA
 387         EFX_FS_FILTER_RX_MAC_FULL,      /* Ethernet {dMAC,VLAN} */
 388         EFX_FS_FILTER_RX_MAC_WILD,      /* Ethernet {dMAC,   -} */
 389
 390         EFX_FS_FILTER_TX_TCP_FULL,              /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 391         EFX_FS_FILTER_TX_TCP_WILD,              /* TCP/IPv4 {  -,   -,sIP,sTCP} */
 392         EFX_FS_FILTER_TX_UDP_FULL,              /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
 393         EFX_FS_FILTER_TX_UDP_WILD,              /* UDP/IPv4 source (host, port) */
 394
 395         EFX_FS_FILTER_TX_MAC_FULL,              /* Ethernet source (MAC address, VLAN ID) */
 396         EFX_FS_FILTER_TX_MAC_WILD,              /* Ethernet source (MAC address) */
 397 #endif /* EFSYS_OPT_SIENA */
 398
 399         EFX_FS_FILTER_NTYPES
 400 } falconsiena_filter_type_t;
 401
 402 typedef enum falconsiena_filter_tbl_id_e {
 403         EFX_FS_FILTER_TBL_RX_IP = 0,
 404         EFX_FS_FILTER_TBL_RX_MAC,
 405         EFX_FS_FILTER_TBL_TX_IP,
 406         EFX_FS_FILTER_TBL_TX_MAC,
 407         EFX_FS_FILTER_NTBLS
 408 } falconsiena_filter_tbl_id_t;
 409
 410 typedef struct falconsiena_filter_tbl_s {
 411         int                             fsft_size;      /* number of entries */
 412         int                             fsft_used;      /* active count */
 413         uint32_t                        *fsft_bitmap;   /* active bitmap */
 414         falconsiena_filter_spec_t       *fsft_spec;     /* array of saved specs */
 415 } falconsiena_filter_tbl_t;
 416
 417 typedef struct falconsiena_filter_s {
 418         falconsiena_filter_tbl_t        fsf_tbl[EFX_FS_FILTER_NTBLS];
 419         unsigned int                    fsf_depth[EFX_FS_FILTER_NTYPES];
 420 } falconsiena_filter_t;
 421
 422 typedef struct efx_filter_s {
 423 #if EFSYS_OPT_SIENA
 424         falconsiena_filter_t    *ef_falconsiena_filter;
 425 #endif /* EFSYS_OPT_SIENA */
 426 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
 427         ef10_filter_table_t     *ef_ef10_filter_table;
 428 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
 429 } efx_filter_t;
 430
 431 extern                  void
 432 falconsiena_filter_tbl_clear(
 433         __in            efx_nic_t *enp,
 434         __in            falconsiena_filter_tbl_id_t tbl);
 435
 436 #endif  /* EFSYS_OPT_FILTER */
 437
 438 #if EFSYS_OPT_MCDI
 439
 440 typedef struct efx_mcdi_ops_s {
 441         efx_rc_t        (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
 442         void            (*emco_send_request)(efx_nic_t *, void *, size_t,
 443                                         void *, size_t);
 444         efx_rc_t        (*emco_poll_reboot)(efx_nic_t *);
 445         boolean_t       (*emco_poll_response)(efx_nic_t *);
 446         void            (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
 447         void            (*emco_fini)(efx_nic_t *);
 448         efx_rc_t        (*emco_feature_supported)(efx_nic_t *, efx_mcdi_feature_id_t, boolean_t *);
 449 } efx_mcdi_ops_t;
 450
 451 typedef struct efx_mcdi_s {
 452         efx_mcdi_ops_t                  *em_emcop;
 453         const efx_mcdi_transport_t      *em_emtp;
 454         efx_mcdi_iface_t                em_emip;
 455 } efx_mcdi_t;
 456
 457 #endif /* EFSYS_OPT_MCDI */
 458
 459 #if EFSYS_OPT_NVRAM
 460 typedef struct efx_nvram_ops_s {
 461 #if EFSYS_OPT_DIAG
 462         efx_rc_t        (*envo_test)(efx_nic_t *);
 463 #endif  /* EFSYS_OPT_DIAG */
 464         efx_rc_t        (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
 465                                             uint32_t *);
 466         efx_rc_t        (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *);
 467         efx_rc_t        (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
 468         efx_rc_t        (*envo_partn_read)(efx_nic_t *, uint32_t,
 469                                             unsigned int, caddr_t, size_t);
 470         efx_rc_t        (*envo_partn_erase)(efx_nic_t *, uint32_t,
 471                                             unsigned int, size_t);
 472         efx_rc_t        (*envo_partn_write)(efx_nic_t *, uint32_t,
 473                                             unsigned int, caddr_t, size_t);
 474         void            (*envo_partn_rw_finish)(efx_nic_t *, uint32_t);
 475         efx_rc_t        (*envo_partn_get_version)(efx_nic_t *, uint32_t,
 476                                             uint32_t *, uint16_t *);
 477         efx_rc_t        (*envo_partn_set_version)(efx_nic_t *, uint32_t,
 478                                             uint16_t *);
 479         efx_rc_t        (*envo_buffer_validate)(efx_nic_t *, uint32_t,
 480                                             caddr_t, size_t);
 481 } efx_nvram_ops_t;
 482 #endif /* EFSYS_OPT_NVRAM */
 483
 484 extern  __checkReturn           efx_rc_t
 485 efx_nvram_tlv_validate(
 486         __in                    efx_nic_t *enp,
 487         __in                    uint32_t partn,
 488         __in_bcount(partn_size) caddr_t partn_data,
 489         __in                    size_t partn_size);
 490
 491
 492 #if EFSYS_OPT_VPD
 493 typedef struct efx_vpd_ops_s {
 494         efx_rc_t        (*evpdo_init)(efx_nic_t *);
 495         efx_rc_t        (*evpdo_size)(efx_nic_t *, size_t *);
 496         efx_rc_t        (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
 497         efx_rc_t        (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
 498         efx_rc_t        (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
 499         efx_rc_t        (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
 500                                         efx_vpd_value_t *);
 501         efx_rc_t        (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
 502                                         efx_vpd_value_t *);
 503         efx_rc_t        (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
 504                                         efx_vpd_value_t *, unsigned int *);
 505         efx_rc_t        (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
 506         void            (*evpdo_fini)(efx_nic_t *);
 507 } efx_vpd_ops_t;
 508 #endif  /* EFSYS_OPT_VPD */
 509
 510 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
 511
 512         __checkReturn           efx_rc_t
 513 efx_mcdi_nvram_partitions(
 514         __in                    efx_nic_t *enp,
 515         __out_bcount(size)      caddr_t data,
 516         __in                    size_t size,
 517         __out                   unsigned int *npartnp);
 518
 519         __checkReturn           efx_rc_t
 520 efx_mcdi_nvram_metadata(
 521         __in                    efx_nic_t *enp,
 522         __in                    uint32_t partn,
 523         __out                   uint32_t *subtypep,
 524         __out_ecount(4)         uint16_t version[4],
 525         __out_bcount_opt(size)  char *descp,
 526         __in                    size_t size);
 527
 528         __checkReturn           efx_rc_t
 529 efx_mcdi_nvram_info(
 530         __in                    efx_nic_t *enp,
 531         __in                    uint32_t partn,
 532         __out_opt               size_t *sizep,
 533         __out_opt               uint32_t *addressp,
 534         __out_opt               uint32_t *erase_sizep,
 535         __out_opt               uint32_t *write_sizep);
 536
 537         __checkReturn           efx_rc_t
 538 efx_mcdi_nvram_update_start(
 539         __in                    efx_nic_t *enp,
 540         __in                    uint32_t partn);
 541
 542         __checkReturn           efx_rc_t
 543 efx_mcdi_nvram_read(
 544         __in                    efx_nic_t *enp,
 545         __in                    uint32_t partn,
 546         __in                    uint32_t offset,
 547         __out_bcount(size)      caddr_t data,
 548         __in                    size_t size,
 549         __in                    uint32_t mode);
 550
 551         __checkReturn           efx_rc_t
 552 efx_mcdi_nvram_erase(
 553         __in                    efx_nic_t *enp,
 554         __in                    uint32_t partn,
 555         __in                    uint32_t offset,
 556         __in                    size_t size);
 557
 558         __checkReturn           efx_rc_t
 559 efx_mcdi_nvram_write(
 560         __in                    efx_nic_t *enp,
 561         __in                    uint32_t partn,
 562         __in                    uint32_t offset,
 563         __out_bcount(size)      caddr_t data,
 564         __in                    size_t size);
 565
 566         __checkReturn           efx_rc_t
 567 efx_mcdi_nvram_update_finish(
 568         __in                    efx_nic_t *enp,
 569         __in                    uint32_t partn,
 570         __in                    boolean_t reboot);
 571
 572 #if EFSYS_OPT_DIAG
 573
 574         __checkReturn           efx_rc_t
 575 efx_mcdi_nvram_test(
 576         __in                    efx_nic_t *enp,
 577         __in                    uint32_t partn);
 578
 579 #endif  /* EFSYS_OPT_DIAG */
 580
 581 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
 582
 583 #if EFSYS_OPT_LICENSING
 584
 585 typedef struct efx_lic_ops_s {
 586         efx_rc_t        (*elo_update_licenses)(efx_nic_t *);
 587         efx_rc_t        (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
 588         efx_rc_t        (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
 589         efx_rc_t        (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
 590                                       size_t *, uint8_t *);
 591 } efx_lic_ops_t;
 592
 593 #endif
 594
 595 typedef struct efx_drv_cfg_s {
 596         uint32_t                edc_min_vi_count;
 597         uint32_t                edc_max_vi_count;
 598
 599         uint32_t                edc_max_piobuf_count;
 600         uint32_t                edc_pio_alloc_size;
 601 } efx_drv_cfg_t;
 602
 603 struct efx_nic_s {
 604         uint32_t                en_magic;
 605         efx_family_t            en_family;
 606         uint32_t                en_features;
 607         efsys_identifier_t      *en_esip;
 608         efsys_lock_t            *en_eslp;
 609         efsys_bar_t             *en_esbp;
 610         unsigned int            en_mod_flags;
 611         unsigned int            en_reset_flags;
 612         efx_nic_cfg_t           en_nic_cfg;
 613         efx_drv_cfg_t           en_drv_cfg;
 614         efx_port_t              en_port;
 615         efx_mon_t               en_mon;
 616         efx_intr_t              en_intr;
 617         uint32_t                en_ev_qcount;
 618         uint32_t                en_rx_qcount;
 619         uint32_t                en_tx_qcount;
 620         efx_nic_ops_t           *en_enop;
 621         efx_ev_ops_t            *en_eevop;
 622         efx_tx_ops_t            *en_etxop;
 623         efx_rx_ops_t            *en_erxop;
 624 #if EFSYS_OPT_FILTER
 625         efx_filter_t            en_filter;
 626         efx_filter_ops_t        *en_efop;
 627 #endif  /* EFSYS_OPT_FILTER */
 628 #if EFSYS_OPT_MCDI
 629         efx_mcdi_t              en_mcdi;
 630 #endif  /* EFSYS_OPT_MCDI */
 631 #if EFSYS_OPT_NVRAM
 632         efx_nvram_type_t        en_nvram_locked;
 633         efx_nvram_ops_t         *en_envop;
 634 #endif  /* EFSYS_OPT_NVRAM */
 635 #if EFSYS_OPT_VPD
 636         efx_vpd_ops_t           *en_evpdop;
 637 #endif  /* EFSYS_OPT_VPD */
 638 #if EFSYS_OPT_RX_SCALE
 639         efx_rx_hash_support_t   en_hash_support;
 640         efx_rx_scale_support_t  en_rss_support;
 641         uint32_t                en_rss_context;
 642 #endif  /* EFSYS_OPT_RX_SCALE */
 643         uint32_t                en_vport_id;
 644 #if EFSYS_OPT_LICENSING
 645         efx_lic_ops_t           *en_elop;
 646 #endif
 647         union {
 648 #if EFSYS_OPT_SIENA
 649                 struct {
 650 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
 651                         unsigned int            enu_partn_mask;
 652 #endif  /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
 653 #if EFSYS_OPT_VPD
 654                         caddr_t                 enu_svpd;
 655                         size_t                  enu_svpd_length;
 656 #endif  /* EFSYS_OPT_VPD */
 657                         int                     enu_unused;
 658                 } siena;
 659 #endif  /* EFSYS_OPT_SIENA */
 660                 int     enu_unused;
 661         } en_u;
 662 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
 663         union en_arch {
 664                 struct {
 665                         int                     ena_vi_base;
 666                         int                     ena_vi_count;
 667                         int                     ena_vi_shift;
 668 #if EFSYS_OPT_VPD
 669                         caddr_t                 ena_svpd;
 670                         size_t                  ena_svpd_length;
 671 #endif  /* EFSYS_OPT_VPD */
 672                         efx_piobuf_handle_t     ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
 673                         uint32_t                ena_piobuf_count;
 674                         uint32_t                ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
 675                         uint32_t                ena_pio_write_vi_base;
 676                         /* Memory BAR mapping regions */
 677                         uint32_t                ena_uc_mem_map_offset;
 678                         size_t                  ena_uc_mem_map_size;
 679                         uint32_t                ena_wc_mem_map_offset;
 680                         size_t                  ena_wc_mem_map_size;
 681                 } ef10;
 682         } en_arch;
 683 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
 684 };
 685
 686
 687 #define EFX_NIC_MAGIC   0x02121996
 688
 689 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
 690     const efx_ev_callbacks_t *, void *);
 691
 692 typedef struct efx_evq_rxq_state_s {
 693         unsigned int                    eers_rx_read_ptr;
 694         unsigned int                    eers_rx_mask;
 695 } efx_evq_rxq_state_t;
 696
 697 struct efx_evq_s {
 698         uint32_t                        ee_magic;
 699         efx_nic_t                       *ee_enp;
 700         unsigned int                    ee_index;
 701         unsigned int                    ee_mask;
 702         efsys_mem_t                     *ee_esmp;
 703 #if EFSYS_OPT_QSTATS
 704         uint32_t                        ee_stat[EV_NQSTATS];
 705 #endif  /* EFSYS_OPT_QSTATS */
 706
 707         efx_ev_handler_t                ee_rx;
 708         efx_ev_handler_t                ee_tx;
 709         efx_ev_handler_t                ee_driver;
 710         efx_ev_handler_t                ee_global;
 711         efx_ev_handler_t                ee_drv_gen;
 712 #if EFSYS_OPT_MCDI
 713         efx_ev_handler_t                ee_mcdi;
 714 #endif  /* EFSYS_OPT_MCDI */
 715
 716         efx_evq_rxq_state_t             ee_rxq_state[EFX_EV_RX_NLABELS];
 717 };
 718
 719 #define EFX_EVQ_MAGIC   0x08081997
 720
 721 #define EFX_EVQ_FALCON_TIMER_QUANTUM_NS 4968 /* 621 cycles */
 722 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS  6144 /* 768 cycles */
 723
 724 struct efx_rxq_s {
 725         uint32_t                        er_magic;
 726         efx_nic_t                       *er_enp;
 727         efx_evq_t                       *er_eep;
 728         unsigned int                    er_index;
 729         unsigned int                    er_label;
 730         unsigned int                    er_mask;
 731         efsys_mem_t                     *er_esmp;
 732 };
 733
 734 #define EFX_RXQ_MAGIC   0x15022005
 735
 736 struct efx_txq_s {
 737         uint32_t                        et_magic;
 738         efx_nic_t                       *et_enp;
 739         unsigned int                    et_index;
 740         unsigned int                    et_mask;
 741         efsys_mem_t                     *et_esmp;
 742 #if EFSYS_OPT_HUNTINGTON
 743         uint32_t                        et_pio_bufnum;
 744         uint32_t                        et_pio_blknum;
 745         uint32_t                        et_pio_write_offset;
 746         uint32_t                        et_pio_offset;
 747         size_t                          et_pio_size;
 748 #endif
 749 #if EFSYS_OPT_QSTATS
 750         uint32_t                        et_stat[TX_NQSTATS];
 751 #endif  /* EFSYS_OPT_QSTATS */
 752 };
 753
 754 #define EFX_TXQ_MAGIC   0x05092005
 755
 756 #define EFX_MAC_ADDR_COPY(_dst, _src)                                   \
 757         do {                                                            \
 758                 (_dst)[0] = (_src)[0];                                  \
 759                 (_dst)[1] = (_src)[1];                                  \
 760                 (_dst)[2] = (_src)[2];                                  \
 761                 (_dst)[3] = (_src)[3];                                  \
 762                 (_dst)[4] = (_src)[4];                                  \
 763                 (_dst)[5] = (_src)[5];                                  \
 764         _NOTE(CONSTANTCONDITION)                                        \
 765         } while (B_FALSE)
 766
 767 #define EFX_MAC_BROADCAST_ADDR_SET(_dst)                                \
 768         do {                                                            \
 769                 uint16_t *_d = (uint16_t *)(_dst);                      \
 770                 _d[0] = 0xffff;                                         \
 771                 _d[1] = 0xffff;                                         \
 772                 _d[2] = 0xffff;                                         \
 773         _NOTE(CONSTANTCONDITION)                                        \
 774         } while (B_FALSE)
 775
 776 #if EFSYS_OPT_CHECK_REG
 777 #define EFX_CHECK_REG(_enp, _reg)                                       \
 778         do {                                                            \
 779                 const char *name = #_reg;                               \
 780                 char min = name[4];                                     \
 781                 char max = name[5];                                     \
 782                 char rev;                                               \
 783                                                                         \
 784                 switch ((_enp)->en_family) {                            \
 785                 case EFX_FAMILY_SIENA:                                  \
 786                         rev = 'C';                                      \
 787                         break;                                          \
 788                                                                         \
 789                 case EFX_FAMILY_HUNTINGTON:                             \
 790                         rev = 'D';                                      \
 791                         break;                                          \
 792                                                                         \
 793                 case EFX_FAMILY_MEDFORD:                                \
 794                         rev = 'E';                                      \
 795                         break;                                          \
 796                                                                         \
 797                 default:                                                \
 798                         rev = '?';                                      \
 799                         break;                                          \
 800                 }                                                       \
 801                                                                         \
 802                 EFSYS_ASSERT3S(rev, >=, min);                           \
 803                 EFSYS_ASSERT3S(rev, <=, max);                           \
 804                                                                         \
 805         _NOTE(CONSTANTCONDITION)                                        \
 806         } while (B_FALSE)
 807 #else
 808 #define EFX_CHECK_REG(_enp, _reg) do {                                  \
 809         _NOTE(CONSTANTCONDITION)                                        \
 810         } while(B_FALSE)
 811 #endif
 812
 813 #define EFX_BAR_READD(_enp, _reg, _edp, _lock)                          \
 814         do {                                                            \
 815                 EFX_CHECK_REG((_enp), (_reg));                          \
 816                 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST,         \
 817                     (_edp), (_lock));                                   \
 818                 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg,        \
 819                     uint32_t, _reg ## _OFST,                            \
 820                     uint32_t, (_edp)->ed_u32[0]);                       \
 821         _NOTE(CONSTANTCONDITION)                                        \
 822         } while (B_FALSE)
 823
 824 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock)                         \
 825         do {                                                            \
 826                 EFX_CHECK_REG((_enp), (_reg));                          \
 827                 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg,       \
 828                     uint32_t, _reg ## _OFST,                            \
 829                     uint32_t, (_edp)->ed_u32[0]);                       \
 830                 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST,        \
 831                     (_edp), (_lock));                                   \
 832         _NOTE(CONSTANTCONDITION)                                        \
 833         } while (B_FALSE)
 834
 835 #define EFX_BAR_READQ(_enp, _reg, _eqp)                                 \
 836         do {                                                            \
 837                 EFX_CHECK_REG((_enp), (_reg));                          \
 838                 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST,         \
 839                     (_eqp));                                            \
 840                 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg,        \
 841                     uint32_t, _reg ## _OFST,                            \
 842                     uint32_t, (_eqp)->eq_u32[1],                        \
 843                     uint32_t, (_eqp)->eq_u32[0]);                       \
 844         _NOTE(CONSTANTCONDITION)                                        \
 845         } while (B_FALSE)
 846
 847 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp)                                \
 848         do {                                                            \
 849                 EFX_CHECK_REG((_enp), (_reg));                          \
 850                 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg,       \
 851                     uint32_t, _reg ## _OFST,                            \
 852                     uint32_t, (_eqp)->eq_u32[1],                        \
 853                     uint32_t, (_eqp)->eq_u32[0]);                       \
 854                 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST,        \
 855                     (_eqp));                                            \
 856         _NOTE(CONSTANTCONDITION)                                        \
 857         } while (B_FALSE)
 858
 859 #define EFX_BAR_READO(_enp, _reg, _eop)                                 \
 860         do {                                                            \
 861                 EFX_CHECK_REG((_enp), (_reg));                          \
 862                 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST,         \
 863                     (_eop), B_TRUE);                                    \
 864                 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg,        \
 865                     uint32_t, _reg ## _OFST,                            \
 866                     uint32_t, (_eop)->eo_u32[3],                        \
 867                     uint32_t, (_eop)->eo_u32[2],                        \
 868                     uint32_t, (_eop)->eo_u32[1],                        \
 869                     uint32_t, (_eop)->eo_u32[0]);                       \
 870         _NOTE(CONSTANTCONDITION)                                        \
 871         } while (B_FALSE)
 872
 873 #define EFX_BAR_WRITEO(_enp, _reg, _eop)                                \
 874         do {                                                            \
 875                 EFX_CHECK_REG((_enp), (_reg));                          \
 876                 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg,       \
 877                     uint32_t, _reg ## _OFST,                            \
 878                     uint32_t, (_eop)->eo_u32[3],                        \
 879                     uint32_t, (_eop)->eo_u32[2],                        \
 880                     uint32_t, (_eop)->eo_u32[1],                        \
 881                     uint32_t, (_eop)->eo_u32[0]);                       \
 882                 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST,        \
 883                     (_eop), B_TRUE);                                    \
 884         _NOTE(CONSTANTCONDITION)                                        \
 885         } while (B_FALSE)
 886
 887 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock)              \
 888         do {                                                            \
 889                 EFX_CHECK_REG((_enp), (_reg));                          \
 890                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
 891                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 892                     (_edp), (_lock));                                   \
 893                 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg,    \
 894                     uint32_t, (_index),                                 \
 895                     uint32_t, _reg ## _OFST,                            \
 896                     uint32_t, (_edp)->ed_u32[0]);                       \
 897         _NOTE(CONSTANTCONDITION)                                        \
 898         } while (B_FALSE)
 899
 900 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock)             \
 901         do {                                                            \
 902                 EFX_CHECK_REG((_enp), (_reg));                          \
 903                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 904                     uint32_t, (_index),                                 \
 905                     uint32_t, _reg ## _OFST,                            \
 906                     uint32_t, (_edp)->ed_u32[0]);                       \
 907                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 908                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 909                     (_edp), (_lock));                                   \
 910         _NOTE(CONSTANTCONDITION)                                        \
 911         } while (B_FALSE)
 912
 913 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock)            \
 914         do {                                                            \
 915                 EFX_CHECK_REG((_enp), (_reg));                          \
 916                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 917                     uint32_t, (_index),                                 \
 918                     uint32_t, _reg ## _OFST,                            \
 919                     uint32_t, (_edp)->ed_u32[0]);                       \
 920                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 921                     (_reg ## _OFST +                                    \
 922                     (2 * sizeof (efx_dword_t)) +                        \
 923                     ((_index) * _reg ## _STEP)),                        \
 924                     (_edp), (_lock));                                   \
 925         _NOTE(CONSTANTCONDITION)                                        \
 926         } while (B_FALSE)
 927
 928 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock)            \
 929         do {                                                            \
 930                 EFX_CHECK_REG((_enp), (_reg));                          \
 931                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 932                     uint32_t, (_index),                                 \
 933                     uint32_t, _reg ## _OFST,                            \
 934                     uint32_t, (_edp)->ed_u32[0]);                       \
 935                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 936                     (_reg ## _OFST +                                    \
 937                     (3 * sizeof (efx_dword_t)) +                        \
 938                     ((_index) * _reg ## _STEP)),                        \
 939                     (_edp), (_lock));                                   \
 940         _NOTE(CONSTANTCONDITION)                                        \
 941         } while (B_FALSE)
 942
 943 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp)                     \
 944         do {                                                            \
 945                 EFX_CHECK_REG((_enp), (_reg));                          \
 946                 EFSYS_BAR_READQ((_enp)->en_esbp,                        \
 947                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 948                     (_eqp));                                            \
 949                 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg,    \
 950                     uint32_t, (_index),                                 \
 951                     uint32_t, _reg ## _OFST,                            \
 952                     uint32_t, (_eqp)->eq_u32[1],                        \
 953                     uint32_t, (_eqp)->eq_u32[0]);                       \
 954         _NOTE(CONSTANTCONDITION)                                        \
 955         } while (B_FALSE)
 956
 957 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp)                    \
 958         do {                                                            \
 959                 EFX_CHECK_REG((_enp), (_reg));                          \
 960                 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg,   \
 961                     uint32_t, (_index),                                 \
 962                     uint32_t, _reg ## _OFST,                            \
 963                     uint32_t, (_eqp)->eq_u32[1],                        \
 964                     uint32_t, (_eqp)->eq_u32[0]);                       \
 965                 EFSYS_BAR_WRITEQ((_enp)->en_esbp,                       \
 966                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 967                     (_eqp));                                            \
 968         _NOTE(CONSTANTCONDITION)                                        \
 969         } while (B_FALSE)
 970
 971 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock)              \
 972         do {                                                            \
 973                 EFX_CHECK_REG((_enp), (_reg));                          \
 974                 EFSYS_BAR_READO((_enp)->en_esbp,                        \
 975                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 976                     (_eop), (_lock));                                   \
 977                 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg,    \
 978                     uint32_t, (_index),                                 \
 979                     uint32_t, _reg ## _OFST,                            \
 980                     uint32_t, (_eop)->eo_u32[3],                        \
 981                     uint32_t, (_eop)->eo_u32[2],                        \
 982                     uint32_t, (_eop)->eo_u32[1],                        \
 983                     uint32_t, (_eop)->eo_u32[0]);                       \
 984         _NOTE(CONSTANTCONDITION)                                        \
 985         } while (B_FALSE)
 986
 987 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock)             \
 988         do {                                                            \
 989                 EFX_CHECK_REG((_enp), (_reg));                          \
 990                 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg,   \
 991                     uint32_t, (_index),                                 \
 992                     uint32_t, _reg ## _OFST,                            \
 993                     uint32_t, (_eop)->eo_u32[3],                        \
 994                     uint32_t, (_eop)->eo_u32[2],                        \
 995                     uint32_t, (_eop)->eo_u32[1],                        \
 996                     uint32_t, (_eop)->eo_u32[0]);                       \
 997                 EFSYS_BAR_WRITEO((_enp)->en_esbp,                       \
 998                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 999                     (_eop), (_lock));                                   \
1000         _NOTE(CONSTANTCONDITION)                                        \
1001         } while (B_FALSE)
1002
1003 /*
1004  * Allow drivers to perform optimised 128-bit doorbell writes.
1005  * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1006  * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1007  * the need for locking in the host, and are the only ones known to be safe to
1008  * use 128-bites write with.
1009  */
1010 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop)           \
1011         do {                                                            \
1012                 EFX_CHECK_REG((_enp), (_reg));                          \
1013                 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo,               \
1014                     const char *,                                       \
1015                     #_reg,                                              \
1016                     uint32_t, (_index),                                 \
1017                     uint32_t, _reg ## _OFST,                            \
1018                     uint32_t, (_eop)->eo_u32[3],                        \
1019                     uint32_t, (_eop)->eo_u32[2],                        \
1020                     uint32_t, (_eop)->eo_u32[1],                        \
1021                     uint32_t, (_eop)->eo_u32[0]);                       \
1022                 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp,              \
1023                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1024                     (_eop));                                            \
1025         _NOTE(CONSTANTCONDITION)                                        \
1026         } while (B_FALSE)
1027
1028 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr)   \
1029         do {                                                            \
1030                 unsigned int _new = (_wptr);                            \
1031                 unsigned int _old = (_owptr);                           \
1032                                                                         \
1033                 if ((_new) >= (_old))                                   \
1034                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1035                             (_old) * sizeof (efx_desc_t),               \
1036                             ((_new) - (_old)) * sizeof (efx_desc_t));   \
1037                 else                                                    \
1038                         /*                                              \
1039                          * It is cheaper to sync entire map than sync   \
1040                          * two parts especially when offset/size are    \
1041                          * ignored and entire map is synced in any case.\
1042                          */                                             \
1043                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1044                             0,                                          \
1045                             (_entries) * sizeof (efx_desc_t));          \
1046         _NOTE(CONSTANTCONDITION)                                        \
1047         } while (B_FALSE)
1048
1049 extern  __checkReturn   efx_rc_t
1050 efx_nic_biu_test(
1051         __in            efx_nic_t *enp);
1052
1053 extern  __checkReturn   efx_rc_t
1054 efx_mac_select(
1055         __in            efx_nic_t *enp);
1056
1057 extern  void
1058 efx_mac_multicast_hash_compute(
1059         __in_ecount(6*count)            uint8_t const *addrs,
1060         __in                            int count,
1061         __out                           efx_oword_t *hash_low,
1062         __out                           efx_oword_t *hash_high);
1063
1064 extern  __checkReturn   efx_rc_t
1065 efx_phy_probe(
1066         __in            efx_nic_t *enp);
1067
1068 extern                  void
1069 efx_phy_unprobe(
1070         __in            efx_nic_t *enp);
1071
1072 #if EFSYS_OPT_VPD
1073
1074 /* VPD utility functions */
1075
1076 extern  __checkReturn           efx_rc_t
1077 efx_vpd_hunk_length(
1078         __in_bcount(size)       caddr_t data,
1079         __in                    size_t size,
1080         __out                   size_t *lengthp);
1081
1082 extern  __checkReturn           efx_rc_t
1083 efx_vpd_hunk_verify(
1084         __in_bcount(size)       caddr_t data,
1085         __in                    size_t size,
1086         __out_opt               boolean_t *cksummedp);
1087
1088 extern  __checkReturn           efx_rc_t
1089 efx_vpd_hunk_reinit(
1090         __in_bcount(size)       caddr_t data,
1091         __in                    size_t size,
1092         __in                    boolean_t wantpid);
1093
1094 extern  __checkReturn           efx_rc_t
1095 efx_vpd_hunk_get(
1096         __in_bcount(size)       caddr_t data,
1097         __in                    size_t size,
1098         __in                    efx_vpd_tag_t tag,
1099         __in                    efx_vpd_keyword_t keyword,
1100         __out                   unsigned int *payloadp,
1101         __out                   uint8_t *paylenp);
1102
1103 extern  __checkReturn                   efx_rc_t
1104 efx_vpd_hunk_next(
1105         __in_bcount(size)               caddr_t data,
1106         __in                            size_t size,
1107         __out                           efx_vpd_tag_t *tagp,
1108         __out                           efx_vpd_keyword_t *keyword,
1109         __out_opt                       unsigned int *payloadp,
1110         __out_opt                       uint8_t *paylenp,
1111         __inout                         unsigned int *contp);
1112
1113 extern  __checkReturn           efx_rc_t
1114 efx_vpd_hunk_set(
1115         __in_bcount(size)       caddr_t data,
1116         __in                    size_t size,
1117         __in                    efx_vpd_value_t *evvp);
1118
1119 #endif  /* EFSYS_OPT_VPD */
1120
1121 #if EFSYS_OPT_DIAG
1122
1123 extern  efx_sram_pattern_fn_t   __efx_sram_pattern_fns[];
1124
1125 typedef struct efx_register_set_s {
1126         unsigned int            address;
1127         unsigned int            step;
1128         unsigned int            rows;
1129         efx_oword_t             mask;
1130 } efx_register_set_t;
1131
1132 extern  __checkReturn   efx_rc_t
1133 efx_nic_test_registers(
1134         __in            efx_nic_t *enp,
1135         __in            efx_register_set_t *rsp,
1136         __in            size_t count);
1137
1138 extern  __checkReturn   efx_rc_t
1139 efx_nic_test_tables(
1140         __in            efx_nic_t *enp,
1141         __in            efx_register_set_t *rsp,
1142         __in            efx_pattern_type_t pattern,
1143         __in            size_t count);
1144
1145 #endif  /* EFSYS_OPT_DIAG */
1146
1147 #if EFSYS_OPT_MCDI
1148
1149 extern  __checkReturn           efx_rc_t
1150 efx_mcdi_set_workaround(
1151         __in                    efx_nic_t *enp,
1152         __in                    uint32_t type,
1153         __in                    boolean_t enabled,
1154         __out_opt               uint32_t *flagsp);
1155
1156 extern  __checkReturn           efx_rc_t
1157 efx_mcdi_get_workarounds(
1158         __in                    efx_nic_t *enp,
1159         __out_opt               uint32_t *implementedp,
1160         __out_opt               uint32_t *enabledp);
1161
1162 #endif /* EFSYS_OPT_MCDI */
1163
1164 #ifdef  __cplusplus
1165 }
1166 #endif
1167
1168 #endif  /* _SYS_EFX_IMPL_H */