sys/dev/sfxge/common/efx_impl.h

   1 /*-
   2  * Copyright (c) 2007-2015 Solarflare Communications Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  * 1. Redistributions of source code must retain the above copyright notice,
   9  *    this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright notice,
  11  *    this list of conditions and the following disclaimer in the documentation
  12  *    and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  15  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  16  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  18  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  19  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  20  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  21  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  22  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  23  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  24  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  * The views and conclusions contained in the software and documentation are
  27  * those of the authors and should not be interpreted as representing official
  28  * policies, either expressed or implied, of the FreeBSD Project.
  29  *
  30  * $FreeBSD$
  31  */
  32
  33 #ifndef _SYS_EFX_IMPL_H
  34 #define _SYS_EFX_IMPL_H
  35
  36 #include "efsys.h"
  37 #include "efx.h"
  38 #include "efx_regs.h"
  39 #include "efx_regs_ef10.h"
  40
  41 /* FIXME: Add definition for driver generated software events */
  42 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
  43 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
  44 #endif
  45
  46 #include "efx_check.h"
  47
  48
  49 #if EFSYS_OPT_FALCON
  50 #include "falcon_impl.h"
  51 #endif  /* EFSYS_OPT_FALCON */
  52
  53 #if EFSYS_OPT_SIENA
  54 #include "siena_impl.h"
  55 #endif  /* EFSYS_OPT_SIENA */
  56
  57 #if EFSYS_OPT_HUNTINGTON
  58 #include "hunt_impl.h"
  59 #endif  /* EFSYS_OPT_HUNTINGTON */
  60
  61 #if EFSYS_OPT_MEDFORD
  62 #include "medford_impl.h"
  63 #endif  /* EFSYS_OPT_MEDFORD */
  64
  65 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
  66 #include "ef10_impl.h"
  67 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
  68
  69 #ifdef  __cplusplus
  70 extern "C" {
  71 #endif
  72
  73 #define EFX_MOD_MCDI            0x00000001
  74 #define EFX_MOD_PROBE           0x00000002
  75 #define EFX_MOD_NVRAM           0x00000004
  76 #define EFX_MOD_VPD             0x00000008
  77 #define EFX_MOD_NIC             0x00000010
  78 #define EFX_MOD_INTR            0x00000020
  79 #define EFX_MOD_EV              0x00000040
  80 #define EFX_MOD_RX              0x00000080
  81 #define EFX_MOD_TX              0x00000100
  82 #define EFX_MOD_PORT            0x00000200
  83 #define EFX_MOD_MON             0x00000400
  84 #define EFX_MOD_WOL             0x00000800
  85 #define EFX_MOD_FILTER          0x00001000
  86 #define EFX_MOD_PKTFILTER       0x00002000
  87
  88 #define EFX_RESET_MAC           0x00000001
  89 #define EFX_RESET_PHY           0x00000002
  90 #define EFX_RESET_RXQ_ERR       0x00000004
  91 #define EFX_RESET_TXQ_ERR       0x00000008
  92
  93 typedef enum efx_mac_type_e {
  94         EFX_MAC_INVALID = 0,
  95         EFX_MAC_FALCON_GMAC,
  96         EFX_MAC_FALCON_XMAC,
  97         EFX_MAC_SIENA,
  98         EFX_MAC_HUNTINGTON,
  99         EFX_MAC_NTYPES
 100 } efx_mac_type_t;
 101
 102 typedef struct efx_ev_ops_s {
 103         efx_rc_t        (*eevo_init)(efx_nic_t *);
 104         void            (*eevo_fini)(efx_nic_t *);
 105         efx_rc_t        (*eevo_qcreate)(efx_nic_t *, unsigned int,
 106                                           efsys_mem_t *, size_t, uint32_t,
 107                                           efx_evq_t *);
 108         void            (*eevo_qdestroy)(efx_evq_t *);
 109         efx_rc_t        (*eevo_qprime)(efx_evq_t *, unsigned int);
 110         void            (*eevo_qpost)(efx_evq_t *, uint16_t);
 111         efx_rc_t        (*eevo_qmoderate)(efx_evq_t *, unsigned int);
 112 #if EFSYS_OPT_QSTATS
 113         void            (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
 114 #endif
 115 } efx_ev_ops_t;
 116
 117 typedef struct efx_tx_ops_s {
 118         efx_rc_t        (*etxo_init)(efx_nic_t *);
 119         void            (*etxo_fini)(efx_nic_t *);
 120         efx_rc_t        (*etxo_qcreate)(efx_nic_t *,
 121                                         unsigned int, unsigned int,
 122                                         efsys_mem_t *, size_t,
 123                                         uint32_t, uint16_t,
 124                                         efx_evq_t *, efx_txq_t *,
 125                                         unsigned int *);
 126         void            (*etxo_qdestroy)(efx_txq_t *);
 127         efx_rc_t        (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
 128                                       unsigned int, unsigned int,
 129                                       unsigned int *);
 130         void            (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
 131         efx_rc_t        (*etxo_qpace)(efx_txq_t *, unsigned int);
 132         efx_rc_t        (*etxo_qflush)(efx_txq_t *);
 133         void            (*etxo_qenable)(efx_txq_t *);
 134         efx_rc_t        (*etxo_qpio_enable)(efx_txq_t *);
 135         void            (*etxo_qpio_disable)(efx_txq_t *);
 136         efx_rc_t        (*etxo_qpio_write)(efx_txq_t *,uint8_t *, size_t,
 137                                            size_t);
 138         efx_rc_t        (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
 139                                            unsigned int *);
 140         efx_rc_t        (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
 141                                       unsigned int, unsigned int,
 142                                       unsigned int *);
 143         void            (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
 144                                                 size_t, boolean_t,
 145                                                 efx_desc_t *);
 146         void            (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
 147                                                 uint32_t, uint8_t,
 148                                                 efx_desc_t *);
 149         void            (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
 150                                                 efx_desc_t *);
 151 #if EFSYS_OPT_QSTATS
 152         void            (*etxo_qstats_update)(efx_txq_t *,
 153                                               efsys_stat_t *);
 154 #endif
 155 } efx_tx_ops_t;
 156
 157 typedef struct efx_rx_ops_s {
 158         efx_rc_t        (*erxo_init)(efx_nic_t *);
 159         void            (*erxo_fini)(efx_nic_t *);
 160 #if EFSYS_OPT_RX_HDR_SPLIT
 161         efx_rc_t        (*erxo_hdr_split_enable)(efx_nic_t *, unsigned int,
 162                                                  unsigned int);
 163 #endif
 164 #if EFSYS_OPT_RX_SCATTER
 165         efx_rc_t        (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
 166 #endif
 167 #if EFSYS_OPT_RX_SCALE
 168         efx_rc_t        (*erxo_scale_mode_set)(efx_nic_t *, efx_rx_hash_alg_t,
 169                                                efx_rx_hash_type_t, boolean_t);
 170         efx_rc_t        (*erxo_scale_key_set)(efx_nic_t *, uint8_t *, size_t);
 171         efx_rc_t        (*erxo_scale_tbl_set)(efx_nic_t *, unsigned int *,
 172                                               size_t);
 173 #endif
 174         void            (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
 175                                       unsigned int, unsigned int,
 176                                       unsigned int);
 177         void            (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
 178         efx_rc_t        (*erxo_qflush)(efx_rxq_t *);
 179         void            (*erxo_qenable)(efx_rxq_t *);
 180         efx_rc_t        (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
 181                                         unsigned int, efx_rxq_type_t,
 182                                         efsys_mem_t *, size_t, uint32_t,
 183                                         efx_evq_t *, efx_rxq_t *);
 184         void            (*erxo_qdestroy)(efx_rxq_t *);
 185 } efx_rx_ops_t;
 186
 187 typedef struct efx_mac_ops_s {
 188         efx_rc_t        (*emo_reset)(efx_nic_t *); /* optional */
 189         efx_rc_t        (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
 190         efx_rc_t        (*emo_up)(efx_nic_t *, boolean_t *);
 191         efx_rc_t        (*emo_addr_set)(efx_nic_t *);
 192         efx_rc_t        (*emo_reconfigure)(efx_nic_t *);
 193         efx_rc_t        (*emo_multicast_list_set)(efx_nic_t *);
 194         efx_rc_t        (*emo_filter_default_rxq_set)(efx_nic_t *,
 195                                                       efx_rxq_t *, boolean_t);
 196         void            (*emo_filter_default_rxq_clear)(efx_nic_t *);
 197 #if EFSYS_OPT_LOOPBACK
 198         efx_rc_t        (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
 199                                             efx_loopback_type_t);
 200 #endif  /* EFSYS_OPT_LOOPBACK */
 201 #if EFSYS_OPT_MAC_STATS
 202         efx_rc_t        (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
 203         efx_rc_t        (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
 204                                               uint16_t, boolean_t);
 205         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 206                                             efsys_stat_t *, uint32_t *);
 207 #endif  /* EFSYS_OPT_MAC_STATS */
 208 } efx_mac_ops_t;
 209
 210 typedef struct efx_phy_ops_s {
 211         efx_rc_t        (*epo_power)(efx_nic_t *, boolean_t); /* optional */
 212         efx_rc_t        (*epo_reset)(efx_nic_t *);
 213         efx_rc_t        (*epo_reconfigure)(efx_nic_t *);
 214         efx_rc_t        (*epo_verify)(efx_nic_t *);
 215         efx_rc_t        (*epo_uplink_check)(efx_nic_t *,
 216                                             boolean_t *); /* optional */
 217         efx_rc_t        (*epo_downlink_check)(efx_nic_t *, efx_link_mode_t *,
 218                                               unsigned int *, uint32_t *);
 219         efx_rc_t        (*epo_oui_get)(efx_nic_t *, uint32_t *);
 220 #if EFSYS_OPT_PHY_STATS
 221         efx_rc_t        (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
 222                                             uint32_t *);
 223 #endif  /* EFSYS_OPT_PHY_STATS */
 224 #if EFSYS_OPT_PHY_PROPS
 225 #if EFSYS_OPT_NAMES
 226         const char      *(*epo_prop_name)(efx_nic_t *, unsigned int);
 227 #endif  /* EFSYS_OPT_PHY_PROPS */
 228         efx_rc_t        (*epo_prop_get)(efx_nic_t *, unsigned int, uint32_t,
 229                                         uint32_t *);
 230         efx_rc_t        (*epo_prop_set)(efx_nic_t *, unsigned int, uint32_t);
 231 #endif  /* EFSYS_OPT_PHY_PROPS */
 232 #if EFSYS_OPT_BIST
 233         efx_rc_t        (*epo_bist_enable_offline)(efx_nic_t *);
 234         efx_rc_t        (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
 235         efx_rc_t        (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
 236                                          efx_bist_result_t *, uint32_t *,
 237                                          unsigned long *, size_t);
 238         void            (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
 239 #endif  /* EFSYS_OPT_BIST */
 240 } efx_phy_ops_t;
 241
 242 #if EFSYS_OPT_FILTER
 243 typedef struct efx_filter_ops_s {
 244         efx_rc_t        (*efo_init)(efx_nic_t *);
 245         void            (*efo_fini)(efx_nic_t *);
 246         efx_rc_t        (*efo_restore)(efx_nic_t *);
 247         efx_rc_t        (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
 248                                    boolean_t may_replace);
 249         efx_rc_t        (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
 250         efx_rc_t        (*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *);
 251         efx_rc_t        (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
 252                                    boolean_t, boolean_t, boolean_t,
 253                                    uint8_t const *, int);
 254 } efx_filter_ops_t;
 255
 256 extern  __checkReturn   efx_rc_t
 257 efx_filter_reconfigure(
 258         __in                            efx_nic_t *enp,
 259         __in_ecount(6)                  uint8_t const *mac_addr,
 260         __in                            boolean_t all_unicst,
 261         __in                            boolean_t mulcst,
 262         __in                            boolean_t all_mulcst,
 263         __in                            boolean_t brdcst,
 264         __in_ecount(6*count)            uint8_t const *addrs,
 265         __in                            int count);
 266
 267 #endif /* EFSYS_OPT_FILTER */
 268
 269
 270 typedef struct efx_port_s {
 271         efx_mac_type_t          ep_mac_type;
 272         uint32_t                ep_phy_type;
 273         uint8_t                 ep_port;
 274         uint32_t                ep_mac_pdu;
 275         uint8_t                 ep_mac_addr[6];
 276         efx_link_mode_t         ep_link_mode;
 277         boolean_t               ep_all_unicst;
 278         boolean_t               ep_mulcst;
 279         boolean_t               ep_all_mulcst;
 280         boolean_t               ep_brdcst;
 281         unsigned int            ep_fcntl;
 282         boolean_t               ep_fcntl_autoneg;
 283         efx_oword_t             ep_multicst_hash[2];
 284         uint8_t                 ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
 285                                                     EFX_MAC_MULTICAST_LIST_MAX];
 286         uint32_t                ep_mulcst_addr_count;
 287 #if EFSYS_OPT_LOOPBACK
 288         efx_loopback_type_t     ep_loopback_type;
 289         efx_link_mode_t         ep_loopback_link_mode;
 290 #endif  /* EFSYS_OPT_LOOPBACK */
 291 #if EFSYS_OPT_PHY_FLAGS
 292         uint32_t                ep_phy_flags;
 293 #endif  /* EFSYS_OPT_PHY_FLAGS */
 294 #if EFSYS_OPT_PHY_LED_CONTROL
 295         efx_phy_led_mode_t      ep_phy_led_mode;
 296 #endif  /* EFSYS_OPT_PHY_LED_CONTROL */
 297         efx_phy_media_type_t    ep_fixed_port_type;
 298         efx_phy_media_type_t    ep_module_type;
 299         uint32_t                ep_adv_cap_mask;
 300         uint32_t                ep_lp_cap_mask;
 301         uint32_t                ep_default_adv_cap_mask;
 302         uint32_t                ep_phy_cap_mask;
 303 #if EFSYS_OPT_PHY_TXC43128 || EFSYS_OPT_PHY_QT2025C
 304         union {
 305                 struct {
 306                         unsigned int    bug10934_count;
 307                 } ep_txc43128;
 308                 struct {
 309                         unsigned int    bug17190_count;
 310                 } ep_qt2025c;
 311         };
 312 #endif
 313         boolean_t               ep_mac_poll_needed; /* falcon only */
 314         boolean_t               ep_mac_up; /* falcon only */
 315         uint32_t                ep_fwver; /* falcon only */
 316         boolean_t               ep_mac_drain;
 317         boolean_t               ep_mac_stats_pending;
 318 #if EFSYS_OPT_BIST
 319         efx_bist_type_t         ep_current_bist;
 320 #endif
 321         efx_mac_ops_t           *ep_emop;
 322         efx_phy_ops_t           *ep_epop;
 323 } efx_port_t;
 324
 325 typedef struct efx_mon_ops_s {
 326         efx_rc_t        (*emo_reset)(efx_nic_t *);
 327         efx_rc_t        (*emo_reconfigure)(efx_nic_t *);
 328 #if EFSYS_OPT_MON_STATS
 329         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 330                                             efx_mon_stat_value_t *);
 331 #endif  /* EFSYS_OPT_MON_STATS */
 332 } efx_mon_ops_t;
 333
 334 typedef struct efx_mon_s {
 335         efx_mon_type_t  em_type;
 336         efx_mon_ops_t   *em_emop;
 337 } efx_mon_t;
 338
 339 typedef struct efx_intr_ops_s {
 340         efx_rc_t        (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
 341         void            (*eio_enable)(efx_nic_t *);
 342         void            (*eio_disable)(efx_nic_t *);
 343         void            (*eio_disable_unlocked)(efx_nic_t *);
 344         efx_rc_t        (*eio_trigger)(efx_nic_t *, unsigned int);
 345         void            (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
 346         void            (*eio_status_message)(efx_nic_t *, unsigned int,
 347                                  boolean_t *);
 348         void            (*eio_fatal)(efx_nic_t *);
 349         void            (*eio_fini)(efx_nic_t *);
 350 } efx_intr_ops_t;
 351
 352 typedef struct efx_intr_s {
 353         efx_intr_ops_t  *ei_eiop;
 354         efsys_mem_t     *ei_esmp;
 355         efx_intr_type_t ei_type;
 356         unsigned int    ei_level;
 357 } efx_intr_t;
 358
 359 typedef struct efx_nic_ops_s {
 360         efx_rc_t        (*eno_probe)(efx_nic_t *);
 361         efx_rc_t        (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
 362         efx_rc_t        (*eno_reset)(efx_nic_t *);
 363         efx_rc_t        (*eno_init)(efx_nic_t *);
 364         efx_rc_t        (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
 365         efx_rc_t        (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
 366                                         uint32_t *, size_t *);
 367 #if EFSYS_OPT_DIAG
 368         efx_rc_t        (*eno_sram_test)(efx_nic_t *, efx_sram_pattern_fn_t);
 369         efx_rc_t        (*eno_register_test)(efx_nic_t *);
 370 #endif  /* EFSYS_OPT_DIAG */
 371         void            (*eno_fini)(efx_nic_t *);
 372         void            (*eno_unprobe)(efx_nic_t *);
 373 } efx_nic_ops_t;
 374
 375 #ifndef EFX_TXQ_LIMIT_TARGET
 376 #define EFX_TXQ_LIMIT_TARGET 259
 377 #endif
 378 #ifndef EFX_RXQ_LIMIT_TARGET
 379 #define EFX_RXQ_LIMIT_TARGET 512
 380 #endif
 381 #ifndef EFX_TXQ_DC_SIZE
 382 #define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
 383 #endif
 384 #ifndef EFX_RXQ_DC_SIZE
 385 #define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
 386 #endif
 387
 388 #if EFSYS_OPT_FILTER
 389
 390 typedef struct falconsiena_filter_spec_s {
 391         uint8_t         fsfs_type;
 392         uint32_t        fsfs_flags;
 393         uint32_t        fsfs_dmaq_id;
 394         uint32_t        fsfs_dword[3];
 395 } falconsiena_filter_spec_t;
 396
 397 typedef enum falconsiena_filter_type_e {
 398         EFX_FS_FILTER_RX_TCP_FULL,      /* TCP/IPv4 4-tuple {dIP,dTCP,sIP,sTCP} */
 399         EFX_FS_FILTER_RX_TCP_WILD,      /* TCP/IPv4 dest    {dIP,dTCP,  -,   -} */
 400         EFX_FS_FILTER_RX_UDP_FULL,      /* UDP/IPv4 4-tuple {dIP,dUDP,sIP,sUDP} */
 401         EFX_FS_FILTER_RX_UDP_WILD,      /* UDP/IPv4 dest    {dIP,dUDP,  -,   -} */
 402
 403 #if EFSYS_OPT_SIENA
 404         EFX_FS_FILTER_RX_MAC_FULL,      /* Ethernet {dMAC,VLAN} */
 405         EFX_FS_FILTER_RX_MAC_WILD,      /* Ethernet {dMAC,   -} */
 406
 407         EFX_FS_FILTER_TX_TCP_FULL,              /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 408         EFX_FS_FILTER_TX_TCP_WILD,              /* TCP/IPv4 {  -,   -,sIP,sTCP} */
 409         EFX_FS_FILTER_TX_UDP_FULL,              /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
 410         EFX_FS_FILTER_TX_UDP_WILD,              /* UDP/IPv4 source (host, port) */
 411
 412         EFX_FS_FILTER_TX_MAC_FULL,              /* Ethernet source (MAC address, VLAN ID) */
 413         EFX_FS_FILTER_TX_MAC_WILD,              /* Ethernet source (MAC address) */
 414 #endif /* EFSYS_OPT_SIENA */
 415
 416         EFX_FS_FILTER_NTYPES
 417 } falconsiena_filter_type_t;
 418
 419 typedef enum falconsiena_filter_tbl_id_e {
 420         EFX_FS_FILTER_TBL_RX_IP = 0,
 421         EFX_FS_FILTER_TBL_RX_MAC,
 422         EFX_FS_FILTER_TBL_TX_IP,
 423         EFX_FS_FILTER_TBL_TX_MAC,
 424         EFX_FS_FILTER_NTBLS
 425 } falconsiena_filter_tbl_id_t;
 426
 427 typedef struct falconsiena_filter_tbl_s {
 428         int                             fsft_size;      /* number of entries */
 429         int                             fsft_used;      /* active count */
 430         uint32_t                        *fsft_bitmap;   /* active bitmap */
 431         falconsiena_filter_spec_t       *fsft_spec;     /* array of saved specs */
 432 } falconsiena_filter_tbl_t;
 433
 434 typedef struct falconsiena_filter_s {
 435         falconsiena_filter_tbl_t        fsf_tbl[EFX_FS_FILTER_NTBLS];
 436         unsigned int                    fsf_depth[EFX_FS_FILTER_NTYPES];
 437 } falconsiena_filter_t;
 438
 439 typedef struct efx_filter_s {
 440 #if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA
 441         falconsiena_filter_t    *ef_falconsiena_filter;
 442 #endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */
 443 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
 444         ef10_filter_table_t     *ef_ef10_filter_table;
 445 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
 446 } efx_filter_t;
 447
 448 extern                  void
 449 falconsiena_filter_tbl_clear(
 450         __in            efx_nic_t *enp,
 451         __in            falconsiena_filter_tbl_id_t tbl);
 452
 453 #endif  /* EFSYS_OPT_FILTER */
 454
 455 #if EFSYS_OPT_MCDI
 456
 457 typedef struct efx_mcdi_ops_s {
 458         efx_rc_t        (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
 459         void            (*emco_request_copyin)(efx_nic_t *, efx_mcdi_req_t *,
 460                                         unsigned int, boolean_t, boolean_t);
 461         void            (*emco_request_copyout)(efx_nic_t *, efx_mcdi_req_t *);
 462         efx_rc_t        (*emco_poll_reboot)(efx_nic_t *);
 463         boolean_t       (*emco_poll_response)(efx_nic_t *);
 464         void            (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
 465         void            (*emco_fini)(efx_nic_t *);
 466         efx_rc_t        (*emco_feature_supported)(efx_nic_t *, efx_mcdi_feature_id_t, boolean_t *);
 467 } efx_mcdi_ops_t;
 468
 469 typedef struct efx_mcdi_s {
 470         efx_mcdi_ops_t                  *em_emcop;
 471         const efx_mcdi_transport_t      *em_emtp;
 472         efx_mcdi_iface_t                em_emip;
 473 } efx_mcdi_t;
 474
 475 #endif /* EFSYS_OPT_MCDI */
 476
 477 #if EFSYS_OPT_NVRAM
 478 typedef struct efx_nvram_ops_s {
 479 #if EFSYS_OPT_DIAG
 480         efx_rc_t        (*envo_test)(efx_nic_t *);
 481 #endif  /* EFSYS_OPT_DIAG */
 482         efx_rc_t        (*envo_size)(efx_nic_t *, efx_nvram_type_t, size_t *);
 483         efx_rc_t        (*envo_get_version)(efx_nic_t *, efx_nvram_type_t,
 484                                             uint32_t *, uint16_t *);
 485         efx_rc_t        (*envo_rw_start)(efx_nic_t *, efx_nvram_type_t, size_t *);
 486         efx_rc_t        (*envo_read_chunk)(efx_nic_t *, efx_nvram_type_t,
 487                                             unsigned int, caddr_t, size_t);
 488         efx_rc_t        (*envo_erase)(efx_nic_t *, efx_nvram_type_t);
 489         efx_rc_t        (*envo_write_chunk)(efx_nic_t *, efx_nvram_type_t,
 490                                             unsigned int, caddr_t, size_t);
 491         void            (*envo_rw_finish)(efx_nic_t *, efx_nvram_type_t);
 492         efx_rc_t        (*envo_set_version)(efx_nic_t *, efx_nvram_type_t,
 493                                             uint16_t *);
 494
 495 } efx_nvram_ops_t;
 496 #endif /* EFSYS_OPT_NVRAM */
 497
 498 #if EFSYS_OPT_VPD
 499 typedef struct efx_vpd_ops_s {
 500         efx_rc_t        (*evpdo_init)(efx_nic_t *);
 501         efx_rc_t        (*evpdo_size)(efx_nic_t *, size_t *);
 502         efx_rc_t        (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
 503         efx_rc_t        (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
 504         efx_rc_t        (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
 505         efx_rc_t        (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
 506                                         efx_vpd_value_t *);
 507         efx_rc_t        (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
 508                                         efx_vpd_value_t *);
 509         efx_rc_t        (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
 510                                         efx_vpd_value_t *, unsigned int *);
 511         efx_rc_t        (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
 512         void            (*evpdo_fini)(efx_nic_t *);
 513 } efx_vpd_ops_t;
 514 #endif  /* EFSYS_OPT_VPD */
 515
 516 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
 517
 518         __checkReturn           efx_rc_t
 519 efx_mcdi_nvram_partitions(
 520         __in                    efx_nic_t *enp,
 521         __out_bcount(size)      caddr_t data,
 522         __in                    size_t size,
 523         __out                   unsigned int *npartnp);
 524
 525         __checkReturn           efx_rc_t
 526 efx_mcdi_nvram_metadata(
 527         __in                    efx_nic_t *enp,
 528         __in                    uint32_t partn,
 529         __out                   uint32_t *subtypep,
 530         __out_ecount(4)         uint16_t version[4],
 531         __out_bcount_opt(size)  char *descp,
 532         __in                    size_t size);
 533
 534         __checkReturn           efx_rc_t
 535 efx_mcdi_nvram_info(
 536         __in                    efx_nic_t *enp,
 537         __in                    uint32_t partn,
 538         __out_opt               size_t *sizep,
 539         __out_opt               uint32_t *addressp,
 540         __out_opt               uint32_t *erase_sizep,
 541         __out_opt               uint32_t *write_sizep);
 542
 543         __checkReturn           efx_rc_t
 544 efx_mcdi_nvram_update_start(
 545         __in                    efx_nic_t *enp,
 546         __in                    uint32_t partn);
 547
 548         __checkReturn           efx_rc_t
 549 efx_mcdi_nvram_read(
 550         __in                    efx_nic_t *enp,
 551         __in                    uint32_t partn,
 552         __in                    uint32_t offset,
 553         __out_bcount(size)      caddr_t data,
 554         __in                    size_t size);
 555
 556         __checkReturn           efx_rc_t
 557 efx_mcdi_nvram_erase(
 558         __in                    efx_nic_t *enp,
 559         __in                    uint32_t partn,
 560         __in                    uint32_t offset,
 561         __in                    size_t size);
 562
 563         __checkReturn           efx_rc_t
 564 efx_mcdi_nvram_write(
 565         __in                    efx_nic_t *enp,
 566         __in                    uint32_t partn,
 567         __in                    uint32_t offset,
 568         __out_bcount(size)      caddr_t data,
 569         __in                    size_t size);
 570
 571         __checkReturn           efx_rc_t
 572 efx_mcdi_nvram_update_finish(
 573         __in                    efx_nic_t *enp,
 574         __in                    uint32_t partn,
 575         __in                    boolean_t reboot);
 576
 577 #if EFSYS_OPT_DIAG
 578
 579         __checkReturn           efx_rc_t
 580 efx_mcdi_nvram_test(
 581         __in                    efx_nic_t *enp,
 582         __in                    uint32_t partn);
 583
 584 #endif  /* EFSYS_OPT_DIAG */
 585
 586 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
 587
 588 typedef struct efx_drv_cfg_s {
 589         uint32_t                edc_min_vi_count;
 590         uint32_t                edc_max_vi_count;
 591
 592         uint32_t                edc_max_piobuf_count;
 593         uint32_t                edc_pio_alloc_size;
 594 } efx_drv_cfg_t;
 595
 596 struct efx_nic_s {
 597         uint32_t                en_magic;
 598         efx_family_t            en_family;
 599         uint32_t                en_features;
 600         efsys_identifier_t      *en_esip;
 601         efsys_lock_t            *en_eslp;
 602         efsys_bar_t             *en_esbp;
 603         unsigned int            en_mod_flags;
 604         unsigned int            en_reset_flags;
 605         efx_nic_cfg_t           en_nic_cfg;
 606         efx_drv_cfg_t           en_drv_cfg;
 607         efx_port_t              en_port;
 608         efx_mon_t               en_mon;
 609         efx_intr_t              en_intr;
 610         uint32_t                en_ev_qcount;
 611         uint32_t                en_rx_qcount;
 612         uint32_t                en_tx_qcount;
 613         efx_nic_ops_t           *en_enop;
 614         efx_ev_ops_t            *en_eevop;
 615         efx_tx_ops_t            *en_etxop;
 616         efx_rx_ops_t            *en_erxop;
 617 #if EFSYS_OPT_FILTER
 618         efx_filter_t            en_filter;
 619         efx_filter_ops_t        *en_efop;
 620 #endif  /* EFSYS_OPT_FILTER */
 621 #if EFSYS_OPT_MCDI
 622         efx_mcdi_t              en_mcdi;
 623 #endif  /* EFSYS_OPT_MCDI */
 624 #if EFSYS_OPT_NVRAM
 625         efx_nvram_type_t        en_nvram_locked;
 626         efx_nvram_ops_t         *en_envop;
 627 #endif  /* EFSYS_OPT_NVRAM */
 628 #if EFSYS_OPT_VPD
 629         efx_vpd_ops_t           *en_evpdop;
 630 #endif  /* EFSYS_OPT_VPD */
 631 #if EFSYS_OPT_RX_SCALE
 632         efx_rx_hash_support_t   en_hash_support;
 633         efx_rx_scale_support_t  en_rss_support;
 634         uint32_t                en_rss_context;
 635 #endif  /* EFSYS_OPT_RX_SCALE */
 636         uint32_t                en_vport_id;
 637         union {
 638 #if EFSYS_OPT_FALCON
 639                 struct {
 640                         falcon_spi_dev_t        enu_fsd[FALCON_SPI_NTYPES];
 641                         falcon_i2c_t            enu_fip;
 642                         boolean_t               enu_i2c_locked;
 643 #if EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE
 644                         const uint8_t           *enu_forced_cfg;
 645 #endif  /* EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE */
 646                         uint8_t                 enu_mon_devid;
 647 #if EFSYS_OPT_PCIE_TUNE
 648                         unsigned int            enu_nlanes;
 649 #endif  /* EFSYS_OPT_PCIE_TUNE */
 650                         uint16_t                enu_board_rev;
 651                         boolean_t               enu_internal_sram;
 652                         uint8_t                 enu_sram_num_bank;
 653                         uint8_t                 enu_sram_bank_size;
 654                 } falcon;
 655 #endif  /* EFSYS_OPT_FALCON */
 656 #if EFSYS_OPT_SIENA
 657                 struct {
 658 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
 659                         unsigned int            enu_partn_mask;
 660 #endif  /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
 661 #if EFSYS_OPT_VPD
 662                         caddr_t                 enu_svpd;
 663                         size_t                  enu_svpd_length;
 664 #endif  /* EFSYS_OPT_VPD */
 665                         int                     enu_unused;
 666                 } siena;
 667 #endif  /* EFSYS_OPT_SIENA */
 668                 int     enu_unused;
 669         } en_u;
 670 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
 671         union en_arch {
 672                 struct {
 673                         int                     ena_vi_base;
 674                         int                     ena_vi_count;
 675 #if EFSYS_OPT_VPD
 676                         caddr_t                 ena_svpd;
 677                         size_t                  ena_svpd_length;
 678 #endif  /* EFSYS_OPT_VPD */
 679                         efx_piobuf_handle_t     ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
 680                         uint32_t                ena_piobuf_count;
 681                         uint32_t                ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
 682                         uint32_t                ena_pio_write_vi_base;
 683                         /* Memory BAR mapping regions */
 684                         uint32_t                ena_uc_mem_map_offset;
 685                         size_t                  ena_uc_mem_map_size;
 686                         uint32_t                ena_wc_mem_map_offset;
 687                         size_t                  ena_wc_mem_map_size;
 688                 } ef10;
 689         } en_arch;
 690 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
 691 };
 692
 693
 694 #define EFX_NIC_MAGIC   0x02121996
 695
 696 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
 697     const efx_ev_callbacks_t *, void *);
 698
 699 typedef struct efx_evq_rxq_state_s {
 700         unsigned int                    eers_rx_read_ptr;
 701         unsigned int                    eers_rx_mask;
 702 } efx_evq_rxq_state_t;
 703
 704 struct efx_evq_s {
 705         uint32_t                        ee_magic;
 706         efx_nic_t                       *ee_enp;
 707         unsigned int                    ee_index;
 708         unsigned int                    ee_mask;
 709         efsys_mem_t                     *ee_esmp;
 710 #if EFSYS_OPT_QSTATS
 711         uint32_t                        ee_stat[EV_NQSTATS];
 712 #endif  /* EFSYS_OPT_QSTATS */
 713
 714         efx_ev_handler_t                ee_rx;
 715         efx_ev_handler_t                ee_tx;
 716         efx_ev_handler_t                ee_driver;
 717         efx_ev_handler_t                ee_global;
 718         efx_ev_handler_t                ee_drv_gen;
 719 #if EFSYS_OPT_MCDI
 720         efx_ev_handler_t                ee_mcdi;
 721 #endif  /* EFSYS_OPT_MCDI */
 722
 723         efx_evq_rxq_state_t             ee_rxq_state[EFX_EV_RX_NLABELS];
 724 };
 725
 726 #define EFX_EVQ_MAGIC   0x08081997
 727
 728 #define EFX_EVQ_FALCON_TIMER_QUANTUM_NS 4968 /* 621 cycles */
 729 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS  6144 /* 768 cycles */
 730
 731 struct efx_rxq_s {
 732         uint32_t                        er_magic;
 733         efx_nic_t                       *er_enp;
 734         efx_evq_t                       *er_eep;
 735         unsigned int                    er_index;
 736         unsigned int                    er_label;
 737         unsigned int                    er_mask;
 738         efsys_mem_t                     *er_esmp;
 739 };
 740
 741 #define EFX_RXQ_MAGIC   0x15022005
 742
 743 struct efx_txq_s {
 744         uint32_t                        et_magic;
 745         efx_nic_t                       *et_enp;
 746         unsigned int                    et_index;
 747         unsigned int                    et_mask;
 748         efsys_mem_t                     *et_esmp;
 749 #if EFSYS_OPT_HUNTINGTON
 750         uint32_t                        et_pio_bufnum;
 751         uint32_t                        et_pio_blknum;
 752         uint32_t                        et_pio_write_offset;
 753         uint32_t                        et_pio_offset;
 754         size_t                          et_pio_size;
 755 #endif
 756 #if EFSYS_OPT_QSTATS
 757         uint32_t                        et_stat[TX_NQSTATS];
 758 #endif  /* EFSYS_OPT_QSTATS */
 759 };
 760
 761 #define EFX_TXQ_MAGIC   0x05092005
 762
 763 #define EFX_MAC_ADDR_COPY(_dst, _src)                                   \
 764         do {                                                            \
 765                 (_dst)[0] = (_src)[0];                                  \
 766                 (_dst)[1] = (_src)[1];                                  \
 767                 (_dst)[2] = (_src)[2];                                  \
 768                 (_dst)[3] = (_src)[3];                                  \
 769                 (_dst)[4] = (_src)[4];                                  \
 770                 (_dst)[5] = (_src)[5];                                  \
 771         _NOTE(CONSTANTCONDITION)                                        \
 772         } while (B_FALSE)
 773
 774 #define EFX_MAC_BROADCAST_ADDR_SET(_dst)                                \
 775         do {                                                            \
 776                 uint16_t *_d = (uint16_t *)(_dst);                      \
 777                 _d[0] = 0xffff;                                         \
 778                 _d[1] = 0xffff;                                         \
 779                 _d[2] = 0xffff;                                         \
 780         _NOTE(CONSTANTCONDITION)                                        \
 781         } while (B_FALSE)
 782
 783 #if EFSYS_OPT_CHECK_REG
 784 #define EFX_CHECK_REG(_enp, _reg)                                       \
 785         do {                                                            \
 786                 const char *name = #_reg;                               \
 787                 char min = name[4];                                     \
 788                 char max = name[5];                                     \
 789                 char rev;                                               \
 790                                                                         \
 791                 switch ((_enp)->en_family) {                            \
 792                 case EFX_FAMILY_FALCON:                                 \
 793                         rev = 'B';                                      \
 794                         break;                                          \
 795                                                                         \
 796                 case EFX_FAMILY_SIENA:                                  \
 797                         rev = 'C';                                      \
 798                         break;                                          \
 799                                                                         \
 800                 case EFX_FAMILY_HUNTINGTON:                             \
 801                         rev = 'D';                                      \
 802                         break;                                          \
 803                                                                         \
 804                 case EFX_FAMILY_MEDFORD:                                \
 805                         rev = 'E';                                      \
 806                         break;                                          \
 807                                                                         \
 808                 default:                                                \
 809                         rev = '?';                                      \
 810                         break;                                          \
 811                 }                                                       \
 812                                                                         \
 813                 EFSYS_ASSERT3S(rev, >=, min);                           \
 814                 EFSYS_ASSERT3S(rev, <=, max);                           \
 815                                                                         \
 816         _NOTE(CONSTANTCONDITION)                                        \
 817         } while (B_FALSE)
 818 #else
 819 #define EFX_CHECK_REG(_enp, _reg) do {                                  \
 820         _NOTE(CONSTANTCONDITION)                                        \
 821         } while(B_FALSE)
 822 #endif
 823
 824 #define EFX_BAR_READD(_enp, _reg, _edp, _lock)                          \
 825         do {                                                            \
 826                 EFX_CHECK_REG((_enp), (_reg));                          \
 827                 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST,         \
 828                     (_edp), (_lock));                                   \
 829                 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg,        \
 830                     uint32_t, _reg ## _OFST,                            \
 831                     uint32_t, (_edp)->ed_u32[0]);                       \
 832         _NOTE(CONSTANTCONDITION)                                        \
 833         } while (B_FALSE)
 834
 835 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock)                         \
 836         do {                                                            \
 837                 EFX_CHECK_REG((_enp), (_reg));                          \
 838                 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg,       \
 839                     uint32_t, _reg ## _OFST,                            \
 840                     uint32_t, (_edp)->ed_u32[0]);                       \
 841                 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST,        \
 842                     (_edp), (_lock));                                   \
 843         _NOTE(CONSTANTCONDITION)                                        \
 844         } while (B_FALSE)
 845
 846 #define EFX_BAR_READQ(_enp, _reg, _eqp)                                 \
 847         do {                                                            \
 848                 EFX_CHECK_REG((_enp), (_reg));                          \
 849                 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST,         \
 850                     (_eqp));                                            \
 851                 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg,        \
 852                     uint32_t, _reg ## _OFST,                            \
 853                     uint32_t, (_eqp)->eq_u32[1],                        \
 854                     uint32_t, (_eqp)->eq_u32[0]);                       \
 855         _NOTE(CONSTANTCONDITION)                                        \
 856         } while (B_FALSE)
 857
 858 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp)                                \
 859         do {                                                            \
 860                 EFX_CHECK_REG((_enp), (_reg));                          \
 861                 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg,       \
 862                     uint32_t, _reg ## _OFST,                            \
 863                     uint32_t, (_eqp)->eq_u32[1],                        \
 864                     uint32_t, (_eqp)->eq_u32[0]);                       \
 865                 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST,        \
 866                     (_eqp));                                            \
 867         _NOTE(CONSTANTCONDITION)                                        \
 868         } while (B_FALSE)
 869
 870 #define EFX_BAR_READO(_enp, _reg, _eop)                                 \
 871         do {                                                            \
 872                 EFX_CHECK_REG((_enp), (_reg));                          \
 873                 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST,         \
 874                     (_eop), B_TRUE);                                    \
 875                 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg,        \
 876                     uint32_t, _reg ## _OFST,                            \
 877                     uint32_t, (_eop)->eo_u32[3],                        \
 878                     uint32_t, (_eop)->eo_u32[2],                        \
 879                     uint32_t, (_eop)->eo_u32[1],                        \
 880                     uint32_t, (_eop)->eo_u32[0]);                       \
 881         _NOTE(CONSTANTCONDITION)                                        \
 882         } while (B_FALSE)
 883
 884 #define EFX_BAR_WRITEO(_enp, _reg, _eop)                                \
 885         do {                                                            \
 886                 EFX_CHECK_REG((_enp), (_reg));                          \
 887                 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg,       \
 888                     uint32_t, _reg ## _OFST,                            \
 889                     uint32_t, (_eop)->eo_u32[3],                        \
 890                     uint32_t, (_eop)->eo_u32[2],                        \
 891                     uint32_t, (_eop)->eo_u32[1],                        \
 892                     uint32_t, (_eop)->eo_u32[0]);                       \
 893                 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST,        \
 894                     (_eop), B_TRUE);                                    \
 895         _NOTE(CONSTANTCONDITION)                                        \
 896         } while (B_FALSE)
 897
 898 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock)              \
 899         do {                                                            \
 900                 EFX_CHECK_REG((_enp), (_reg));                          \
 901                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
 902                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 903                     (_edp), (_lock));                                   \
 904                 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg,    \
 905                     uint32_t, (_index),                                 \
 906                     uint32_t, _reg ## _OFST,                            \
 907                     uint32_t, (_edp)->ed_u32[0]);                       \
 908         _NOTE(CONSTANTCONDITION)                                        \
 909         } while (B_FALSE)
 910
 911 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock)             \
 912         do {                                                            \
 913                 EFX_CHECK_REG((_enp), (_reg));                          \
 914                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 915                     uint32_t, (_index),                                 \
 916                     uint32_t, _reg ## _OFST,                            \
 917                     uint32_t, (_edp)->ed_u32[0]);                       \
 918                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 919                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 920                     (_edp), (_lock));                                   \
 921         _NOTE(CONSTANTCONDITION)                                        \
 922         } while (B_FALSE)
 923
 924 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock)            \
 925         do {                                                            \
 926                 EFX_CHECK_REG((_enp), (_reg));                          \
 927                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 928                     uint32_t, (_index),                                 \
 929                     uint32_t, _reg ## _OFST,                            \
 930                     uint32_t, (_edp)->ed_u32[0]);                       \
 931                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 932                     (_reg ## _OFST +                                    \
 933                     (2 * sizeof (efx_dword_t)) +                        \
 934                     ((_index) * _reg ## _STEP)),                        \
 935                     (_edp), (_lock));                                   \
 936         _NOTE(CONSTANTCONDITION)                                        \
 937         } while (B_FALSE)
 938
 939 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock)            \
 940         do {                                                            \
 941                 EFX_CHECK_REG((_enp), (_reg));                          \
 942                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 943                     uint32_t, (_index),                                 \
 944                     uint32_t, _reg ## _OFST,                            \
 945                     uint32_t, (_edp)->ed_u32[0]);                       \
 946                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 947                     (_reg ## _OFST +                                    \
 948                     (3 * sizeof (efx_dword_t)) +                        \
 949                     ((_index) * _reg ## _STEP)),                        \
 950                     (_edp), (_lock));                                   \
 951         _NOTE(CONSTANTCONDITION)                                        \
 952         } while (B_FALSE)
 953
 954 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp)                     \
 955         do {                                                            \
 956                 EFX_CHECK_REG((_enp), (_reg));                          \
 957                 EFSYS_BAR_READQ((_enp)->en_esbp,                        \
 958                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 959                     (_eqp));                                            \
 960                 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg,    \
 961                     uint32_t, (_index),                                 \
 962                     uint32_t, _reg ## _OFST,                            \
 963                     uint32_t, (_eqp)->eq_u32[1],                        \
 964                     uint32_t, (_eqp)->eq_u32[0]);                       \
 965         _NOTE(CONSTANTCONDITION)                                        \
 966         } while (B_FALSE)
 967
 968 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp)                    \
 969         do {                                                            \
 970                 EFX_CHECK_REG((_enp), (_reg));                          \
 971                 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg,   \
 972                     uint32_t, (_index),                                 \
 973                     uint32_t, _reg ## _OFST,                            \
 974                     uint32_t, (_eqp)->eq_u32[1],                        \
 975                     uint32_t, (_eqp)->eq_u32[0]);                       \
 976                 EFSYS_BAR_WRITEQ((_enp)->en_esbp,                       \
 977                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 978                     (_eqp));                                            \
 979         _NOTE(CONSTANTCONDITION)                                        \
 980         } while (B_FALSE)
 981
 982 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock)              \
 983         do {                                                            \
 984                 EFX_CHECK_REG((_enp), (_reg));                          \
 985                 EFSYS_BAR_READO((_enp)->en_esbp,                        \
 986                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 987                     (_eop), (_lock));                                   \
 988                 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg,    \
 989                     uint32_t, (_index),                                 \
 990                     uint32_t, _reg ## _OFST,                            \
 991                     uint32_t, (_eop)->eo_u32[3],                        \
 992                     uint32_t, (_eop)->eo_u32[2],                        \
 993                     uint32_t, (_eop)->eo_u32[1],                        \
 994                     uint32_t, (_eop)->eo_u32[0]);                       \
 995         _NOTE(CONSTANTCONDITION)                                        \
 996         } while (B_FALSE)
 997
 998 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock)             \
 999         do {                                                            \
1000                 EFX_CHECK_REG((_enp), (_reg));                          \
1001                 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg,   \
1002                     uint32_t, (_index),                                 \
1003                     uint32_t, _reg ## _OFST,                            \
1004                     uint32_t, (_eop)->eo_u32[3],                        \
1005                     uint32_t, (_eop)->eo_u32[2],                        \
1006                     uint32_t, (_eop)->eo_u32[1],                        \
1007                     uint32_t, (_eop)->eo_u32[0]);                       \
1008                 EFSYS_BAR_WRITEO((_enp)->en_esbp,                       \
1009                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1010                     (_eop), (_lock));                                   \
1011         _NOTE(CONSTANTCONDITION)                                        \
1012         } while (B_FALSE)
1013
1014 /*
1015  * Allow drivers to perform optimised 128-bit doorbell writes.
1016  * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1017  * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1018  * the need for locking in the host, and are the only ones known to be safe to
1019  * use 128-bites write with.
1020  */
1021 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop)           \
1022         do {                                                            \
1023                 EFX_CHECK_REG((_enp), (_reg));                          \
1024                 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo,               \
1025                     const char *,                                       \
1026                     #_reg,                                              \
1027                     uint32_t, (_index),                                 \
1028                     uint32_t, _reg ## _OFST,                            \
1029                     uint32_t, (_eop)->eo_u32[3],                        \
1030                     uint32_t, (_eop)->eo_u32[2],                        \
1031                     uint32_t, (_eop)->eo_u32[1],                        \
1032                     uint32_t, (_eop)->eo_u32[0]);                       \
1033                 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp,              \
1034                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1035                     (_eop));                                            \
1036         _NOTE(CONSTANTCONDITION)                                        \
1037         } while (B_FALSE)
1038
1039 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr)   \
1040         do {                                                            \
1041                 unsigned int _new = (_wptr);                            \
1042                 unsigned int _old = (_owptr);                           \
1043                                                                         \
1044                 if ((_new) >= (_old))                                   \
1045                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1046                             (_old) * sizeof (efx_desc_t),               \
1047                             ((_new) - (_old)) * sizeof (efx_desc_t));   \
1048                 else                                                    \
1049                         /*                                              \
1050                          * It is cheaper to sync entire map than sync   \
1051                          * two parts especially when offset/size are    \
1052                          * ignored and entire map is synced in any case.\
1053                          */                                             \
1054                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1055                             0,                                          \
1056                             (_entries) * sizeof (efx_desc_t));          \
1057         _NOTE(CONSTANTCONDITION)                                        \
1058         } while (B_FALSE)
1059
1060 extern  __checkReturn   efx_rc_t
1061 efx_nic_biu_test(
1062         __in            efx_nic_t *enp);
1063
1064 extern  __checkReturn   efx_rc_t
1065 efx_mac_select(
1066         __in            efx_nic_t *enp);
1067
1068 extern  void
1069 efx_mac_multicast_hash_compute(
1070         __in_ecount(6*count)            uint8_t const *addrs,
1071         __in                            int count,
1072         __out                           efx_oword_t *hash_low,
1073         __out                           efx_oword_t *hash_high);
1074
1075 extern  __checkReturn   efx_rc_t
1076 efx_phy_probe(
1077         __in            efx_nic_t *enp);
1078
1079 extern                  void
1080 efx_phy_unprobe(
1081         __in            efx_nic_t *enp);
1082
1083 #if EFSYS_OPT_VPD
1084
1085 /* VPD utility functions */
1086
1087 extern  __checkReturn           efx_rc_t
1088 efx_vpd_hunk_length(
1089         __in_bcount(size)       caddr_t data,
1090         __in                    size_t size,
1091         __out                   size_t *lengthp);
1092
1093 extern  __checkReturn           efx_rc_t
1094 efx_vpd_hunk_verify(
1095         __in_bcount(size)       caddr_t data,
1096         __in                    size_t size,
1097         __out_opt               boolean_t *cksummedp);
1098
1099 extern  __checkReturn           efx_rc_t
1100 efx_vpd_hunk_reinit(
1101         __in_bcount(size)       caddr_t data,
1102         __in                    size_t size,
1103         __in                    boolean_t wantpid);
1104
1105 extern  __checkReturn           efx_rc_t
1106 efx_vpd_hunk_get(
1107         __in_bcount(size)       caddr_t data,
1108         __in                    size_t size,
1109         __in                    efx_vpd_tag_t tag,
1110         __in                    efx_vpd_keyword_t keyword,
1111         __out                   unsigned int *payloadp,
1112         __out                   uint8_t *paylenp);
1113
1114 extern  __checkReturn                   efx_rc_t
1115 efx_vpd_hunk_next(
1116         __in_bcount(size)               caddr_t data,
1117         __in                            size_t size,
1118         __out                           efx_vpd_tag_t *tagp,
1119         __out                           efx_vpd_keyword_t *keyword,
1120         __out_bcount_opt(*paylenp)      unsigned int *payloadp,
1121         __out_opt                       uint8_t *paylenp,
1122         __inout                         unsigned int *contp);
1123
1124 extern  __checkReturn           efx_rc_t
1125 efx_vpd_hunk_set(
1126         __in_bcount(size)       caddr_t data,
1127         __in                    size_t size,
1128         __in                    efx_vpd_value_t *evvp);
1129
1130 #endif  /* EFSYS_OPT_VPD */
1131
1132 #if EFSYS_OPT_DIAG
1133
1134 extern  efx_sram_pattern_fn_t   __efx_sram_pattern_fns[];
1135
1136 typedef struct efx_register_set_s {
1137         unsigned int            address;
1138         unsigned int            step;
1139         unsigned int            rows;
1140         efx_oword_t             mask;
1141 } efx_register_set_t;
1142
1143 extern  __checkReturn   efx_rc_t
1144 efx_nic_test_registers(
1145         __in            efx_nic_t *enp,
1146         __in            efx_register_set_t *rsp,
1147         __in            size_t count);
1148
1149 extern  __checkReturn   efx_rc_t
1150 efx_nic_test_tables(
1151         __in            efx_nic_t *enp,
1152         __in            efx_register_set_t *rsp,
1153         __in            efx_pattern_type_t pattern,
1154         __in            size_t count);
1155
1156 #endif  /* EFSYS_OPT_DIAG */
1157
1158 #if EFSYS_OPT_MCDI
1159
1160 extern  __checkReturn           efx_rc_t
1161 efx_mcdi_set_workaround(
1162         __in                    efx_nic_t *enp,
1163         __in                    uint32_t type,
1164         __in                    boolean_t enabled,
1165         __out_opt               uint32_t *flagsp);
1166
1167 extern  __checkReturn           efx_rc_t
1168 efx_mcdi_get_workarounds(
1169         __in                    efx_nic_t *enp,
1170         __out_opt               uint32_t *implementedp,
1171         __out_opt               uint32_t *enabledp);
1172
1173 #endif /* EFSYS_OPT_MCDI */
1174
1175 #ifdef  __cplusplus
1176 }
1177 #endif
1178
1179 #endif  /* _SYS_EFX_IMPL_H */