sys/dev/sfxge/common/efx_impl.h

   1 /*-
   2  * Copyright (c) 2007-2015 Solarflare Communications Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  * 1. Redistributions of source code must retain the above copyright notice,
   9  *    this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright notice,
  11  *    this list of conditions and the following disclaimer in the documentation
  12  *    and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  15  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  16  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  18  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  19  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  20  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  21  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  22  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  23  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  24  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  * The views and conclusions contained in the software and documentation are
  27  * those of the authors and should not be interpreted as representing official
  28  * policies, either expressed or implied, of the FreeBSD Project.
  29  *
  30  * $FreeBSD$
  31  */
  32
  33 #ifndef _SYS_EFX_IMPL_H
  34 #define _SYS_EFX_IMPL_H
  35
  36 #include "efx.h"
  37 #include "efx_regs.h"
  38 #include "efx_regs_ef10.h"
  39
  40 /* FIXME: Add definition for driver generated software events */
  41 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
  42 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
  43 #endif
  44
  45
  46 #if EFSYS_OPT_SIENA
  47 #include "siena_impl.h"
  48 #endif  /* EFSYS_OPT_SIENA */
  49
  50 #if EFSYS_OPT_HUNTINGTON
  51 #include "hunt_impl.h"
  52 #endif  /* EFSYS_OPT_HUNTINGTON */
  53
  54 #if EFSYS_OPT_MEDFORD
  55 #include "medford_impl.h"
  56 #endif  /* EFSYS_OPT_MEDFORD */
  57
  58 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
  59 #include "ef10_impl.h"
  60 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
  61
  62 #ifdef  __cplusplus
  63 extern "C" {
  64 #endif
  65
  66 #define EFX_MOD_MCDI            0x00000001
  67 #define EFX_MOD_PROBE           0x00000002
  68 #define EFX_MOD_NVRAM           0x00000004
  69 #define EFX_MOD_VPD             0x00000008
  70 #define EFX_MOD_NIC             0x00000010
  71 #define EFX_MOD_INTR            0x00000020
  72 #define EFX_MOD_EV              0x00000040
  73 #define EFX_MOD_RX              0x00000080
  74 #define EFX_MOD_TX              0x00000100
  75 #define EFX_MOD_PORT            0x00000200
  76 #define EFX_MOD_MON             0x00000400
  77 #define EFX_MOD_WOL             0x00000800
  78 #define EFX_MOD_FILTER          0x00001000
  79 #define EFX_MOD_LIC             0x00002000
  80
  81 #define EFX_RESET_MAC           0x00000001
  82 #define EFX_RESET_PHY           0x00000002
  83 #define EFX_RESET_RXQ_ERR       0x00000004
  84 #define EFX_RESET_TXQ_ERR       0x00000008
  85
  86 typedef enum efx_mac_type_e {
  87         EFX_MAC_INVALID = 0,
  88         EFX_MAC_FALCON_GMAC,
  89         EFX_MAC_FALCON_XMAC,
  90         EFX_MAC_SIENA,
  91         EFX_MAC_HUNTINGTON,
  92         EFX_MAC_MEDFORD,
  93         EFX_MAC_NTYPES
  94 } efx_mac_type_t;
  95
  96 typedef struct efx_ev_ops_s {
  97         efx_rc_t        (*eevo_init)(efx_nic_t *);
  98         void            (*eevo_fini)(efx_nic_t *);
  99         efx_rc_t        (*eevo_qcreate)(efx_nic_t *, unsigned int,
 100                                           efsys_mem_t *, size_t, uint32_t,
 101                                           efx_evq_t *);
 102         void            (*eevo_qdestroy)(efx_evq_t *);
 103         efx_rc_t        (*eevo_qprime)(efx_evq_t *, unsigned int);
 104         void            (*eevo_qpost)(efx_evq_t *, uint16_t);
 105         efx_rc_t        (*eevo_qmoderate)(efx_evq_t *, unsigned int);
 106 #if EFSYS_OPT_QSTATS
 107         void            (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
 108 #endif
 109 } efx_ev_ops_t;
 110
 111 typedef struct efx_tx_ops_s {
 112         efx_rc_t        (*etxo_init)(efx_nic_t *);
 113         void            (*etxo_fini)(efx_nic_t *);
 114         efx_rc_t        (*etxo_qcreate)(efx_nic_t *,
 115                                         unsigned int, unsigned int,
 116                                         efsys_mem_t *, size_t,
 117                                         uint32_t, uint16_t,
 118                                         efx_evq_t *, efx_txq_t *,
 119                                         unsigned int *);
 120         void            (*etxo_qdestroy)(efx_txq_t *);
 121         efx_rc_t        (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
 122                                       unsigned int, unsigned int,
 123                                       unsigned int *);
 124         void            (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
 125         efx_rc_t        (*etxo_qpace)(efx_txq_t *, unsigned int);
 126         efx_rc_t        (*etxo_qflush)(efx_txq_t *);
 127         void            (*etxo_qenable)(efx_txq_t *);
 128         efx_rc_t        (*etxo_qpio_enable)(efx_txq_t *);
 129         void            (*etxo_qpio_disable)(efx_txq_t *);
 130         efx_rc_t        (*etxo_qpio_write)(efx_txq_t *,uint8_t *, size_t,
 131                                            size_t);
 132         efx_rc_t        (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
 133                                            unsigned int *);
 134         efx_rc_t        (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
 135                                       unsigned int, unsigned int,
 136                                       unsigned int *);
 137         void            (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
 138                                                 size_t, boolean_t,
 139                                                 efx_desc_t *);
 140         void            (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
 141                                                 uint32_t, uint8_t,
 142                                                 efx_desc_t *);
 143         void            (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
 144                                                 uint32_t, uint16_t,
 145                                                 efx_desc_t *, int);
 146         void            (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
 147                                                 efx_desc_t *);
 148 #if EFSYS_OPT_QSTATS
 149         void            (*etxo_qstats_update)(efx_txq_t *,
 150                                               efsys_stat_t *);
 151 #endif
 152 } efx_tx_ops_t;
 153
 154 typedef struct efx_rx_ops_s {
 155         efx_rc_t        (*erxo_init)(efx_nic_t *);
 156         void            (*erxo_fini)(efx_nic_t *);
 157 #if EFSYS_OPT_RX_SCATTER
 158         efx_rc_t        (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
 159 #endif
 160 #if EFSYS_OPT_RX_SCALE
 161         efx_rc_t        (*erxo_scale_mode_set)(efx_nic_t *, efx_rx_hash_alg_t,
 162                                                efx_rx_hash_type_t, boolean_t);
 163         efx_rc_t        (*erxo_scale_key_set)(efx_nic_t *, uint8_t *, size_t);
 164         efx_rc_t        (*erxo_scale_tbl_set)(efx_nic_t *, unsigned int *,
 165                                               size_t);
 166         uint32_t        (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
 167                                             uint8_t *);
 168 #endif /* EFSYS_OPT_RX_SCALE */
 169         efx_rc_t        (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
 170                                               uint16_t *);
 171         void            (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
 172                                       unsigned int, unsigned int,
 173                                       unsigned int);
 174         void            (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
 175         efx_rc_t        (*erxo_qflush)(efx_rxq_t *);
 176         void            (*erxo_qenable)(efx_rxq_t *);
 177         efx_rc_t        (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
 178                                         unsigned int, efx_rxq_type_t,
 179                                         efsys_mem_t *, size_t, uint32_t,
 180                                         efx_evq_t *, efx_rxq_t *);
 181         void            (*erxo_qdestroy)(efx_rxq_t *);
 182 } efx_rx_ops_t;
 183
 184 typedef struct efx_mac_ops_s {
 185         efx_rc_t        (*emo_reset)(efx_nic_t *); /* optional */
 186         efx_rc_t        (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
 187         efx_rc_t        (*emo_up)(efx_nic_t *, boolean_t *);
 188         efx_rc_t        (*emo_addr_set)(efx_nic_t *);
 189         efx_rc_t        (*emo_pdu_set)(efx_nic_t *);
 190         efx_rc_t        (*emo_reconfigure)(efx_nic_t *);
 191         efx_rc_t        (*emo_multicast_list_set)(efx_nic_t *);
 192         efx_rc_t        (*emo_filter_default_rxq_set)(efx_nic_t *,
 193                                                       efx_rxq_t *, boolean_t);
 194         void            (*emo_filter_default_rxq_clear)(efx_nic_t *);
 195 #if EFSYS_OPT_LOOPBACK
 196         efx_rc_t        (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
 197                                             efx_loopback_type_t);
 198 #endif  /* EFSYS_OPT_LOOPBACK */
 199 #if EFSYS_OPT_MAC_STATS
 200         efx_rc_t        (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
 201         efx_rc_t        (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
 202                                               uint16_t, boolean_t);
 203         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 204                                             efsys_stat_t *, uint32_t *);
 205 #endif  /* EFSYS_OPT_MAC_STATS */
 206 } efx_mac_ops_t;
 207
 208 typedef struct efx_phy_ops_s {
 209         efx_rc_t        (*epo_power)(efx_nic_t *, boolean_t); /* optional */
 210         efx_rc_t        (*epo_reset)(efx_nic_t *);
 211         efx_rc_t        (*epo_reconfigure)(efx_nic_t *);
 212         efx_rc_t        (*epo_verify)(efx_nic_t *);
 213         efx_rc_t        (*epo_uplink_check)(efx_nic_t *,
 214                                             boolean_t *); /* optional */
 215         efx_rc_t        (*epo_downlink_check)(efx_nic_t *, efx_link_mode_t *,
 216                                               unsigned int *, uint32_t *);
 217         efx_rc_t        (*epo_oui_get)(efx_nic_t *, uint32_t *);
 218 #if EFSYS_OPT_PHY_STATS
 219         efx_rc_t        (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
 220                                             uint32_t *);
 221 #endif  /* EFSYS_OPT_PHY_STATS */
 222 #if EFSYS_OPT_PHY_PROPS
 223 #if EFSYS_OPT_NAMES
 224         const char      *(*epo_prop_name)(efx_nic_t *, unsigned int);
 225 #endif  /* EFSYS_OPT_PHY_PROPS */
 226         efx_rc_t        (*epo_prop_get)(efx_nic_t *, unsigned int, uint32_t,
 227                                         uint32_t *);
 228         efx_rc_t        (*epo_prop_set)(efx_nic_t *, unsigned int, uint32_t);
 229 #endif  /* EFSYS_OPT_PHY_PROPS */
 230 #if EFSYS_OPT_BIST
 231         efx_rc_t        (*epo_bist_enable_offline)(efx_nic_t *);
 232         efx_rc_t        (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
 233         efx_rc_t        (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
 234                                          efx_bist_result_t *, uint32_t *,
 235                                          unsigned long *, size_t);
 236         void            (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
 237 #endif  /* EFSYS_OPT_BIST */
 238 } efx_phy_ops_t;
 239
 240 #if EFSYS_OPT_FILTER
 241 typedef struct efx_filter_ops_s {
 242         efx_rc_t        (*efo_init)(efx_nic_t *);
 243         void            (*efo_fini)(efx_nic_t *);
 244         efx_rc_t        (*efo_restore)(efx_nic_t *);
 245         efx_rc_t        (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
 246                                    boolean_t may_replace);
 247         efx_rc_t        (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
 248         efx_rc_t        (*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *);
 249         efx_rc_t        (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
 250                                    boolean_t, boolean_t, boolean_t,
 251                                    uint8_t const *, int);
 252 } efx_filter_ops_t;
 253
 254 extern  __checkReturn   efx_rc_t
 255 efx_filter_reconfigure(
 256         __in                            efx_nic_t *enp,
 257         __in_ecount(6)                  uint8_t const *mac_addr,
 258         __in                            boolean_t all_unicst,
 259         __in                            boolean_t mulcst,
 260         __in                            boolean_t all_mulcst,
 261         __in                            boolean_t brdcst,
 262         __in_ecount(6*count)            uint8_t const *addrs,
 263         __in                            int count);
 264
 265 #endif /* EFSYS_OPT_FILTER */
 266
 267
 268 typedef struct efx_port_s {
 269         efx_mac_type_t          ep_mac_type;
 270         uint32_t                ep_phy_type;
 271         uint8_t                 ep_port;
 272         uint32_t                ep_mac_pdu;
 273         uint8_t                 ep_mac_addr[6];
 274         efx_link_mode_t         ep_link_mode;
 275         boolean_t               ep_all_unicst;
 276         boolean_t               ep_mulcst;
 277         boolean_t               ep_all_mulcst;
 278         boolean_t               ep_brdcst;
 279         unsigned int            ep_fcntl;
 280         boolean_t               ep_fcntl_autoneg;
 281         efx_oword_t             ep_multicst_hash[2];
 282         uint8_t                 ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
 283                                                     EFX_MAC_MULTICAST_LIST_MAX];
 284         uint32_t                ep_mulcst_addr_count;
 285 #if EFSYS_OPT_LOOPBACK
 286         efx_loopback_type_t     ep_loopback_type;
 287         efx_link_mode_t         ep_loopback_link_mode;
 288 #endif  /* EFSYS_OPT_LOOPBACK */
 289 #if EFSYS_OPT_PHY_FLAGS
 290         uint32_t                ep_phy_flags;
 291 #endif  /* EFSYS_OPT_PHY_FLAGS */
 292 #if EFSYS_OPT_PHY_LED_CONTROL
 293         efx_phy_led_mode_t      ep_phy_led_mode;
 294 #endif  /* EFSYS_OPT_PHY_LED_CONTROL */
 295         efx_phy_media_type_t    ep_fixed_port_type;
 296         efx_phy_media_type_t    ep_module_type;
 297         uint32_t                ep_adv_cap_mask;
 298         uint32_t                ep_lp_cap_mask;
 299         uint32_t                ep_default_adv_cap_mask;
 300         uint32_t                ep_phy_cap_mask;
 301         boolean_t               ep_mac_poll_needed; /* falcon only */
 302         boolean_t               ep_mac_up; /* falcon only */
 303         uint32_t                ep_fwver; /* falcon only */
 304         boolean_t               ep_mac_drain;
 305         boolean_t               ep_mac_stats_pending;
 306 #if EFSYS_OPT_BIST
 307         efx_bist_type_t         ep_current_bist;
 308 #endif
 309         efx_mac_ops_t           *ep_emop;
 310         efx_phy_ops_t           *ep_epop;
 311 } efx_port_t;
 312
 313 typedef struct efx_mon_ops_s {
 314         efx_rc_t        (*emo_reset)(efx_nic_t *);
 315         efx_rc_t        (*emo_reconfigure)(efx_nic_t *);
 316 #if EFSYS_OPT_MON_STATS
 317         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 318                                             efx_mon_stat_value_t *);
 319 #endif  /* EFSYS_OPT_MON_STATS */
 320 } efx_mon_ops_t;
 321
 322 typedef struct efx_mon_s {
 323         efx_mon_type_t  em_type;
 324         efx_mon_ops_t   *em_emop;
 325 } efx_mon_t;
 326
 327 typedef struct efx_intr_ops_s {
 328         efx_rc_t        (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
 329         void            (*eio_enable)(efx_nic_t *);
 330         void            (*eio_disable)(efx_nic_t *);
 331         void            (*eio_disable_unlocked)(efx_nic_t *);
 332         efx_rc_t        (*eio_trigger)(efx_nic_t *, unsigned int);
 333         void            (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
 334         void            (*eio_status_message)(efx_nic_t *, unsigned int,
 335                                  boolean_t *);
 336         void            (*eio_fatal)(efx_nic_t *);
 337         void            (*eio_fini)(efx_nic_t *);
 338 } efx_intr_ops_t;
 339
 340 typedef struct efx_intr_s {
 341         efx_intr_ops_t  *ei_eiop;
 342         efsys_mem_t     *ei_esmp;
 343         efx_intr_type_t ei_type;
 344         unsigned int    ei_level;
 345 } efx_intr_t;
 346
 347 typedef struct efx_nic_ops_s {
 348         efx_rc_t        (*eno_probe)(efx_nic_t *);
 349         efx_rc_t        (*eno_board_cfg)(efx_nic_t *);
 350         efx_rc_t        (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
 351         efx_rc_t        (*eno_reset)(efx_nic_t *);
 352         efx_rc_t        (*eno_init)(efx_nic_t *);
 353         efx_rc_t        (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
 354         efx_rc_t        (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
 355                                         uint32_t *, size_t *);
 356 #if EFSYS_OPT_DIAG
 357         efx_rc_t        (*eno_sram_test)(efx_nic_t *, efx_sram_pattern_fn_t);
 358         efx_rc_t        (*eno_register_test)(efx_nic_t *);
 359 #endif  /* EFSYS_OPT_DIAG */
 360         void            (*eno_fini)(efx_nic_t *);
 361         void            (*eno_unprobe)(efx_nic_t *);
 362 } efx_nic_ops_t;
 363
 364 #ifndef EFX_TXQ_LIMIT_TARGET
 365 #define EFX_TXQ_LIMIT_TARGET 259
 366 #endif
 367 #ifndef EFX_RXQ_LIMIT_TARGET
 368 #define EFX_RXQ_LIMIT_TARGET 512
 369 #endif
 370 #ifndef EFX_TXQ_DC_SIZE
 371 #define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
 372 #endif
 373 #ifndef EFX_RXQ_DC_SIZE
 374 #define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
 375 #endif
 376
 377 #if EFSYS_OPT_FILTER
 378
 379 typedef struct falconsiena_filter_spec_s {
 380         uint8_t         fsfs_type;
 381         uint32_t        fsfs_flags;
 382         uint32_t        fsfs_dmaq_id;
 383         uint32_t        fsfs_dword[3];
 384 } falconsiena_filter_spec_t;
 385
 386 typedef enum falconsiena_filter_type_e {
 387         EFX_FS_FILTER_RX_TCP_FULL,      /* TCP/IPv4 4-tuple {dIP,dTCP,sIP,sTCP} */
 388         EFX_FS_FILTER_RX_TCP_WILD,      /* TCP/IPv4 dest    {dIP,dTCP,  -,   -} */
 389         EFX_FS_FILTER_RX_UDP_FULL,      /* UDP/IPv4 4-tuple {dIP,dUDP,sIP,sUDP} */
 390         EFX_FS_FILTER_RX_UDP_WILD,      /* UDP/IPv4 dest    {dIP,dUDP,  -,   -} */
 391
 392 #if EFSYS_OPT_SIENA
 393         EFX_FS_FILTER_RX_MAC_FULL,      /* Ethernet {dMAC,VLAN} */
 394         EFX_FS_FILTER_RX_MAC_WILD,      /* Ethernet {dMAC,   -} */
 395
 396         EFX_FS_FILTER_TX_TCP_FULL,              /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 397         EFX_FS_FILTER_TX_TCP_WILD,              /* TCP/IPv4 {  -,   -,sIP,sTCP} */
 398         EFX_FS_FILTER_TX_UDP_FULL,              /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
 399         EFX_FS_FILTER_TX_UDP_WILD,              /* UDP/IPv4 source (host, port) */
 400
 401         EFX_FS_FILTER_TX_MAC_FULL,              /* Ethernet source (MAC address, VLAN ID) */
 402         EFX_FS_FILTER_TX_MAC_WILD,              /* Ethernet source (MAC address) */
 403 #endif /* EFSYS_OPT_SIENA */
 404
 405         EFX_FS_FILTER_NTYPES
 406 } falconsiena_filter_type_t;
 407
 408 typedef enum falconsiena_filter_tbl_id_e {
 409         EFX_FS_FILTER_TBL_RX_IP = 0,
 410         EFX_FS_FILTER_TBL_RX_MAC,
 411         EFX_FS_FILTER_TBL_TX_IP,
 412         EFX_FS_FILTER_TBL_TX_MAC,
 413         EFX_FS_FILTER_NTBLS
 414 } falconsiena_filter_tbl_id_t;
 415
 416 typedef struct falconsiena_filter_tbl_s {
 417         int                             fsft_size;      /* number of entries */
 418         int                             fsft_used;      /* active count */
 419         uint32_t                        *fsft_bitmap;   /* active bitmap */
 420         falconsiena_filter_spec_t       *fsft_spec;     /* array of saved specs */
 421 } falconsiena_filter_tbl_t;
 422
 423 typedef struct falconsiena_filter_s {
 424         falconsiena_filter_tbl_t        fsf_tbl[EFX_FS_FILTER_NTBLS];
 425         unsigned int                    fsf_depth[EFX_FS_FILTER_NTYPES];
 426 } falconsiena_filter_t;
 427
 428 typedef struct efx_filter_s {
 429 #if EFSYS_OPT_SIENA
 430         falconsiena_filter_t    *ef_falconsiena_filter;
 431 #endif /* EFSYS_OPT_SIENA */
 432 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
 433         ef10_filter_table_t     *ef_ef10_filter_table;
 434 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
 435 } efx_filter_t;
 436
 437 extern                  void
 438 falconsiena_filter_tbl_clear(
 439         __in            efx_nic_t *enp,
 440         __in            falconsiena_filter_tbl_id_t tbl);
 441
 442 #endif  /* EFSYS_OPT_FILTER */
 443
 444 #if EFSYS_OPT_MCDI
 445
 446 typedef struct efx_mcdi_ops_s {
 447         efx_rc_t        (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
 448         void            (*emco_send_request)(efx_nic_t *, void *, size_t,
 449                                         void *, size_t);
 450         efx_rc_t        (*emco_poll_reboot)(efx_nic_t *);
 451         boolean_t       (*emco_poll_response)(efx_nic_t *);
 452         void            (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
 453         void            (*emco_fini)(efx_nic_t *);
 454         efx_rc_t        (*emco_feature_supported)(efx_nic_t *, efx_mcdi_feature_id_t, boolean_t *);
 455 } efx_mcdi_ops_t;
 456
 457 typedef struct efx_mcdi_s {
 458         efx_mcdi_ops_t                  *em_emcop;
 459         const efx_mcdi_transport_t      *em_emtp;
 460         efx_mcdi_iface_t                em_emip;
 461 } efx_mcdi_t;
 462
 463 #endif /* EFSYS_OPT_MCDI */
 464
 465 #if EFSYS_OPT_NVRAM
 466 typedef struct efx_nvram_ops_s {
 467 #if EFSYS_OPT_DIAG
 468         efx_rc_t        (*envo_test)(efx_nic_t *);
 469 #endif  /* EFSYS_OPT_DIAG */
 470         efx_rc_t        (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
 471                                             uint32_t *);
 472         efx_rc_t        (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *);
 473         efx_rc_t        (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
 474         efx_rc_t        (*envo_partn_read)(efx_nic_t *, uint32_t,
 475                                             unsigned int, caddr_t, size_t);
 476         efx_rc_t        (*envo_partn_erase)(efx_nic_t *, uint32_t,
 477                                             unsigned int, size_t);
 478         efx_rc_t        (*envo_partn_write)(efx_nic_t *, uint32_t,
 479                                             unsigned int, caddr_t, size_t);
 480         void            (*envo_partn_rw_finish)(efx_nic_t *, uint32_t);
 481         efx_rc_t        (*envo_partn_get_version)(efx_nic_t *, uint32_t,
 482                                             uint32_t *, uint16_t *);
 483         efx_rc_t        (*envo_partn_set_version)(efx_nic_t *, uint32_t,
 484                                             uint16_t *);
 485         efx_rc_t        (*envo_buffer_validate)(efx_nic_t *, uint32_t,
 486                                             caddr_t, size_t);
 487 } efx_nvram_ops_t;
 488 #endif /* EFSYS_OPT_NVRAM */
 489
 490 extern  __checkReturn           efx_rc_t
 491 efx_nvram_tlv_validate(
 492         __in                    efx_nic_t *enp,
 493         __in                    uint32_t partn,
 494         __in_bcount(partn_size) caddr_t partn_data,
 495         __in                    size_t partn_size);
 496
 497
 498 #if EFSYS_OPT_VPD
 499 typedef struct efx_vpd_ops_s {
 500         efx_rc_t        (*evpdo_init)(efx_nic_t *);
 501         efx_rc_t        (*evpdo_size)(efx_nic_t *, size_t *);
 502         efx_rc_t        (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
 503         efx_rc_t        (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
 504         efx_rc_t        (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
 505         efx_rc_t        (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
 506                                         efx_vpd_value_t *);
 507         efx_rc_t        (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
 508                                         efx_vpd_value_t *);
 509         efx_rc_t        (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
 510                                         efx_vpd_value_t *, unsigned int *);
 511         efx_rc_t        (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
 512         void            (*evpdo_fini)(efx_nic_t *);
 513 } efx_vpd_ops_t;
 514 #endif  /* EFSYS_OPT_VPD */
 515
 516 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
 517
 518         __checkReturn           efx_rc_t
 519 efx_mcdi_nvram_partitions(
 520         __in                    efx_nic_t *enp,
 521         __out_bcount(size)      caddr_t data,
 522         __in                    size_t size,
 523         __out                   unsigned int *npartnp);
 524
 525         __checkReturn           efx_rc_t
 526 efx_mcdi_nvram_metadata(
 527         __in                    efx_nic_t *enp,
 528         __in                    uint32_t partn,
 529         __out                   uint32_t *subtypep,
 530         __out_ecount(4)         uint16_t version[4],
 531         __out_bcount_opt(size)  char *descp,
 532         __in                    size_t size);
 533
 534         __checkReturn           efx_rc_t
 535 efx_mcdi_nvram_info(
 536         __in                    efx_nic_t *enp,
 537         __in                    uint32_t partn,
 538         __out_opt               size_t *sizep,
 539         __out_opt               uint32_t *addressp,
 540         __out_opt               uint32_t *erase_sizep,
 541         __out_opt               uint32_t *write_sizep);
 542
 543         __checkReturn           efx_rc_t
 544 efx_mcdi_nvram_update_start(
 545         __in                    efx_nic_t *enp,
 546         __in                    uint32_t partn);
 547
 548         __checkReturn           efx_rc_t
 549 efx_mcdi_nvram_read(
 550         __in                    efx_nic_t *enp,
 551         __in                    uint32_t partn,
 552         __in                    uint32_t offset,
 553         __out_bcount(size)      caddr_t data,
 554         __in                    size_t size,
 555         __in                    uint32_t mode);
 556
 557         __checkReturn           efx_rc_t
 558 efx_mcdi_nvram_erase(
 559         __in                    efx_nic_t *enp,
 560         __in                    uint32_t partn,
 561         __in                    uint32_t offset,
 562         __in                    size_t size);
 563
 564         __checkReturn           efx_rc_t
 565 efx_mcdi_nvram_write(
 566         __in                    efx_nic_t *enp,
 567         __in                    uint32_t partn,
 568         __in                    uint32_t offset,
 569         __out_bcount(size)      caddr_t data,
 570         __in                    size_t size);
 571
 572         __checkReturn           efx_rc_t
 573 efx_mcdi_nvram_update_finish(
 574         __in                    efx_nic_t *enp,
 575         __in                    uint32_t partn,
 576         __in                    boolean_t reboot);
 577
 578 #if EFSYS_OPT_DIAG
 579
 580         __checkReturn           efx_rc_t
 581 efx_mcdi_nvram_test(
 582         __in                    efx_nic_t *enp,
 583         __in                    uint32_t partn);
 584
 585 #endif  /* EFSYS_OPT_DIAG */
 586
 587 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
 588
 589 #if EFSYS_OPT_LICENSING
 590
 591 typedef struct efx_lic_ops_s {
 592         efx_rc_t        (*elo_update_licenses)(efx_nic_t *);
 593         efx_rc_t        (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
 594         efx_rc_t        (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
 595         efx_rc_t        (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
 596                                       size_t *, uint8_t *);
 597 } efx_lic_ops_t;
 598
 599 #endif
 600
 601 typedef struct efx_drv_cfg_s {
 602         uint32_t                edc_min_vi_count;
 603         uint32_t                edc_max_vi_count;
 604
 605         uint32_t                edc_max_piobuf_count;
 606         uint32_t                edc_pio_alloc_size;
 607 } efx_drv_cfg_t;
 608
 609 struct efx_nic_s {
 610         uint32_t                en_magic;
 611         efx_family_t            en_family;
 612         uint32_t                en_features;
 613         efsys_identifier_t      *en_esip;
 614         efsys_lock_t            *en_eslp;
 615         efsys_bar_t             *en_esbp;
 616         unsigned int            en_mod_flags;
 617         unsigned int            en_reset_flags;
 618         efx_nic_cfg_t           en_nic_cfg;
 619         efx_drv_cfg_t           en_drv_cfg;
 620         efx_port_t              en_port;
 621         efx_mon_t               en_mon;
 622         efx_intr_t              en_intr;
 623         uint32_t                en_ev_qcount;
 624         uint32_t                en_rx_qcount;
 625         uint32_t                en_tx_qcount;
 626         efx_nic_ops_t           *en_enop;
 627         efx_ev_ops_t            *en_eevop;
 628         efx_tx_ops_t            *en_etxop;
 629         efx_rx_ops_t            *en_erxop;
 630 #if EFSYS_OPT_FILTER
 631         efx_filter_t            en_filter;
 632         efx_filter_ops_t        *en_efop;
 633 #endif  /* EFSYS_OPT_FILTER */
 634 #if EFSYS_OPT_MCDI
 635         efx_mcdi_t              en_mcdi;
 636 #endif  /* EFSYS_OPT_MCDI */
 637 #if EFSYS_OPT_NVRAM
 638         efx_nvram_type_t        en_nvram_locked;
 639         efx_nvram_ops_t         *en_envop;
 640 #endif  /* EFSYS_OPT_NVRAM */
 641 #if EFSYS_OPT_VPD
 642         efx_vpd_ops_t           *en_evpdop;
 643 #endif  /* EFSYS_OPT_VPD */
 644 #if EFSYS_OPT_RX_SCALE
 645         efx_rx_hash_support_t   en_hash_support;
 646         efx_rx_scale_support_t  en_rss_support;
 647         uint32_t                en_rss_context;
 648 #endif  /* EFSYS_OPT_RX_SCALE */
 649         uint32_t                en_vport_id;
 650 #if EFSYS_OPT_LICENSING
 651         efx_lic_ops_t           *en_elop;
 652 #endif
 653         union {
 654 #if EFSYS_OPT_SIENA
 655                 struct {
 656 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
 657                         unsigned int            enu_partn_mask;
 658 #endif  /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
 659 #if EFSYS_OPT_VPD
 660                         caddr_t                 enu_svpd;
 661                         size_t                  enu_svpd_length;
 662 #endif  /* EFSYS_OPT_VPD */
 663                         int                     enu_unused;
 664                 } siena;
 665 #endif  /* EFSYS_OPT_SIENA */
 666                 int     enu_unused;
 667         } en_u;
 668 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
 669         union en_arch {
 670                 struct {
 671                         int                     ena_vi_base;
 672                         int                     ena_vi_count;
 673                         int                     ena_vi_shift;
 674 #if EFSYS_OPT_VPD
 675                         caddr_t                 ena_svpd;
 676                         size_t                  ena_svpd_length;
 677 #endif  /* EFSYS_OPT_VPD */
 678                         efx_piobuf_handle_t     ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
 679                         uint32_t                ena_piobuf_count;
 680                         uint32_t                ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
 681                         uint32_t                ena_pio_write_vi_base;
 682                         /* Memory BAR mapping regions */
 683                         uint32_t                ena_uc_mem_map_offset;
 684                         size_t                  ena_uc_mem_map_size;
 685                         uint32_t                ena_wc_mem_map_offset;
 686                         size_t                  ena_wc_mem_map_size;
 687                 } ef10;
 688         } en_arch;
 689 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
 690 };
 691
 692
 693 #define EFX_NIC_MAGIC   0x02121996
 694
 695 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
 696     const efx_ev_callbacks_t *, void *);
 697
 698 typedef struct efx_evq_rxq_state_s {
 699         unsigned int                    eers_rx_read_ptr;
 700         unsigned int                    eers_rx_mask;
 701 } efx_evq_rxq_state_t;
 702
 703 struct efx_evq_s {
 704         uint32_t                        ee_magic;
 705         efx_nic_t                       *ee_enp;
 706         unsigned int                    ee_index;
 707         unsigned int                    ee_mask;
 708         efsys_mem_t                     *ee_esmp;
 709 #if EFSYS_OPT_QSTATS
 710         uint32_t                        ee_stat[EV_NQSTATS];
 711 #endif  /* EFSYS_OPT_QSTATS */
 712
 713         efx_ev_handler_t                ee_rx;
 714         efx_ev_handler_t                ee_tx;
 715         efx_ev_handler_t                ee_driver;
 716         efx_ev_handler_t                ee_global;
 717         efx_ev_handler_t                ee_drv_gen;
 718 #if EFSYS_OPT_MCDI
 719         efx_ev_handler_t                ee_mcdi;
 720 #endif  /* EFSYS_OPT_MCDI */
 721
 722         efx_evq_rxq_state_t             ee_rxq_state[EFX_EV_RX_NLABELS];
 723 };
 724
 725 #define EFX_EVQ_MAGIC   0x08081997
 726
 727 #define EFX_EVQ_FALCON_TIMER_QUANTUM_NS 4968 /* 621 cycles */
 728 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS  6144 /* 768 cycles */
 729
 730 struct efx_rxq_s {
 731         uint32_t                        er_magic;
 732         efx_nic_t                       *er_enp;
 733         efx_evq_t                       *er_eep;
 734         unsigned int                    er_index;
 735         unsigned int                    er_label;
 736         unsigned int                    er_mask;
 737         efsys_mem_t                     *er_esmp;
 738 };
 739
 740 #define EFX_RXQ_MAGIC   0x15022005
 741
 742 struct efx_txq_s {
 743         uint32_t                        et_magic;
 744         efx_nic_t                       *et_enp;
 745         unsigned int                    et_index;
 746         unsigned int                    et_mask;
 747         efsys_mem_t                     *et_esmp;
 748 #if EFSYS_OPT_HUNTINGTON
 749         uint32_t                        et_pio_bufnum;
 750         uint32_t                        et_pio_blknum;
 751         uint32_t                        et_pio_write_offset;
 752         uint32_t                        et_pio_offset;
 753         size_t                          et_pio_size;
 754 #endif
 755 #if EFSYS_OPT_QSTATS
 756         uint32_t                        et_stat[TX_NQSTATS];
 757 #endif  /* EFSYS_OPT_QSTATS */
 758 };
 759
 760 #define EFX_TXQ_MAGIC   0x05092005
 761
 762 #define EFX_MAC_ADDR_COPY(_dst, _src)                                   \
 763         do {                                                            \
 764                 (_dst)[0] = (_src)[0];                                  \
 765                 (_dst)[1] = (_src)[1];                                  \
 766                 (_dst)[2] = (_src)[2];                                  \
 767                 (_dst)[3] = (_src)[3];                                  \
 768                 (_dst)[4] = (_src)[4];                                  \
 769                 (_dst)[5] = (_src)[5];                                  \
 770         _NOTE(CONSTANTCONDITION)                                        \
 771         } while (B_FALSE)
 772
 773 #define EFX_MAC_BROADCAST_ADDR_SET(_dst)                                \
 774         do {                                                            \
 775                 uint16_t *_d = (uint16_t *)(_dst);                      \
 776                 _d[0] = 0xffff;                                         \
 777                 _d[1] = 0xffff;                                         \
 778                 _d[2] = 0xffff;                                         \
 779         _NOTE(CONSTANTCONDITION)                                        \
 780         } while (B_FALSE)
 781
 782 #if EFSYS_OPT_CHECK_REG
 783 #define EFX_CHECK_REG(_enp, _reg)                                       \
 784         do {                                                            \
 785                 const char *name = #_reg;                               \
 786                 char min = name[4];                                     \
 787                 char max = name[5];                                     \
 788                 char rev;                                               \
 789                                                                         \
 790                 switch ((_enp)->en_family) {                            \
 791                 case EFX_FAMILY_FALCON:                                 \
 792                         rev = 'B';                                      \
 793                         break;                                          \
 794                                                                         \
 795                 case EFX_FAMILY_SIENA:                                  \
 796                         rev = 'C';                                      \
 797                         break;                                          \
 798                                                                         \
 799                 case EFX_FAMILY_HUNTINGTON:                             \
 800                         rev = 'D';                                      \
 801                         break;                                          \
 802                                                                         \
 803                 case EFX_FAMILY_MEDFORD:                                \
 804                         rev = 'E';                                      \
 805                         break;                                          \
 806                                                                         \
 807                 default:                                                \
 808                         rev = '?';                                      \
 809                         break;                                          \
 810                 }                                                       \
 811                                                                         \
 812                 EFSYS_ASSERT3S(rev, >=, min);                           \
 813                 EFSYS_ASSERT3S(rev, <=, max);                           \
 814                                                                         \
 815         _NOTE(CONSTANTCONDITION)                                        \
 816         } while (B_FALSE)
 817 #else
 818 #define EFX_CHECK_REG(_enp, _reg) do {                                  \
 819         _NOTE(CONSTANTCONDITION)                                        \
 820         } while(B_FALSE)
 821 #endif
 822
 823 #define EFX_BAR_READD(_enp, _reg, _edp, _lock)                          \
 824         do {                                                            \
 825                 EFX_CHECK_REG((_enp), (_reg));                          \
 826                 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST,         \
 827                     (_edp), (_lock));                                   \
 828                 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg,        \
 829                     uint32_t, _reg ## _OFST,                            \
 830                     uint32_t, (_edp)->ed_u32[0]);                       \
 831         _NOTE(CONSTANTCONDITION)                                        \
 832         } while (B_FALSE)
 833
 834 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock)                         \
 835         do {                                                            \
 836                 EFX_CHECK_REG((_enp), (_reg));                          \
 837                 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg,       \
 838                     uint32_t, _reg ## _OFST,                            \
 839                     uint32_t, (_edp)->ed_u32[0]);                       \
 840                 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST,        \
 841                     (_edp), (_lock));                                   \
 842         _NOTE(CONSTANTCONDITION)                                        \
 843         } while (B_FALSE)
 844
 845 #define EFX_BAR_READQ(_enp, _reg, _eqp)                                 \
 846         do {                                                            \
 847                 EFX_CHECK_REG((_enp), (_reg));                          \
 848                 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST,         \
 849                     (_eqp));                                            \
 850                 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg,        \
 851                     uint32_t, _reg ## _OFST,                            \
 852                     uint32_t, (_eqp)->eq_u32[1],                        \
 853                     uint32_t, (_eqp)->eq_u32[0]);                       \
 854         _NOTE(CONSTANTCONDITION)                                        \
 855         } while (B_FALSE)
 856
 857 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp)                                \
 858         do {                                                            \
 859                 EFX_CHECK_REG((_enp), (_reg));                          \
 860                 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg,       \
 861                     uint32_t, _reg ## _OFST,                            \
 862                     uint32_t, (_eqp)->eq_u32[1],                        \
 863                     uint32_t, (_eqp)->eq_u32[0]);                       \
 864                 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST,        \
 865                     (_eqp));                                            \
 866         _NOTE(CONSTANTCONDITION)                                        \
 867         } while (B_FALSE)
 868
 869 #define EFX_BAR_READO(_enp, _reg, _eop)                                 \
 870         do {                                                            \
 871                 EFX_CHECK_REG((_enp), (_reg));                          \
 872                 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST,         \
 873                     (_eop), B_TRUE);                                    \
 874                 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg,        \
 875                     uint32_t, _reg ## _OFST,                            \
 876                     uint32_t, (_eop)->eo_u32[3],                        \
 877                     uint32_t, (_eop)->eo_u32[2],                        \
 878                     uint32_t, (_eop)->eo_u32[1],                        \
 879                     uint32_t, (_eop)->eo_u32[0]);                       \
 880         _NOTE(CONSTANTCONDITION)                                        \
 881         } while (B_FALSE)
 882
 883 #define EFX_BAR_WRITEO(_enp, _reg, _eop)                                \
 884         do {                                                            \
 885                 EFX_CHECK_REG((_enp), (_reg));                          \
 886                 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg,       \
 887                     uint32_t, _reg ## _OFST,                            \
 888                     uint32_t, (_eop)->eo_u32[3],                        \
 889                     uint32_t, (_eop)->eo_u32[2],                        \
 890                     uint32_t, (_eop)->eo_u32[1],                        \
 891                     uint32_t, (_eop)->eo_u32[0]);                       \
 892                 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST,        \
 893                     (_eop), B_TRUE);                                    \
 894         _NOTE(CONSTANTCONDITION)                                        \
 895         } while (B_FALSE)
 896
 897 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock)              \
 898         do {                                                            \
 899                 EFX_CHECK_REG((_enp), (_reg));                          \
 900                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
 901                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 902                     (_edp), (_lock));                                   \
 903                 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg,    \
 904                     uint32_t, (_index),                                 \
 905                     uint32_t, _reg ## _OFST,                            \
 906                     uint32_t, (_edp)->ed_u32[0]);                       \
 907         _NOTE(CONSTANTCONDITION)                                        \
 908         } while (B_FALSE)
 909
 910 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock)             \
 911         do {                                                            \
 912                 EFX_CHECK_REG((_enp), (_reg));                          \
 913                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 914                     uint32_t, (_index),                                 \
 915                     uint32_t, _reg ## _OFST,                            \
 916                     uint32_t, (_edp)->ed_u32[0]);                       \
 917                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 918                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 919                     (_edp), (_lock));                                   \
 920         _NOTE(CONSTANTCONDITION)                                        \
 921         } while (B_FALSE)
 922
 923 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock)            \
 924         do {                                                            \
 925                 EFX_CHECK_REG((_enp), (_reg));                          \
 926                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 927                     uint32_t, (_index),                                 \
 928                     uint32_t, _reg ## _OFST,                            \
 929                     uint32_t, (_edp)->ed_u32[0]);                       \
 930                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 931                     (_reg ## _OFST +                                    \
 932                     (2 * sizeof (efx_dword_t)) +                        \
 933                     ((_index) * _reg ## _STEP)),                        \
 934                     (_edp), (_lock));                                   \
 935         _NOTE(CONSTANTCONDITION)                                        \
 936         } while (B_FALSE)
 937
 938 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock)            \
 939         do {                                                            \
 940                 EFX_CHECK_REG((_enp), (_reg));                          \
 941                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 942                     uint32_t, (_index),                                 \
 943                     uint32_t, _reg ## _OFST,                            \
 944                     uint32_t, (_edp)->ed_u32[0]);                       \
 945                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 946                     (_reg ## _OFST +                                    \
 947                     (3 * sizeof (efx_dword_t)) +                        \
 948                     ((_index) * _reg ## _STEP)),                        \
 949                     (_edp), (_lock));                                   \
 950         _NOTE(CONSTANTCONDITION)                                        \
 951         } while (B_FALSE)
 952
 953 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp)                     \
 954         do {                                                            \
 955                 EFX_CHECK_REG((_enp), (_reg));                          \
 956                 EFSYS_BAR_READQ((_enp)->en_esbp,                        \
 957                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 958                     (_eqp));                                            \
 959                 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg,    \
 960                     uint32_t, (_index),                                 \
 961                     uint32_t, _reg ## _OFST,                            \
 962                     uint32_t, (_eqp)->eq_u32[1],                        \
 963                     uint32_t, (_eqp)->eq_u32[0]);                       \
 964         _NOTE(CONSTANTCONDITION)                                        \
 965         } while (B_FALSE)
 966
 967 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp)                    \
 968         do {                                                            \
 969                 EFX_CHECK_REG((_enp), (_reg));                          \
 970                 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg,   \
 971                     uint32_t, (_index),                                 \
 972                     uint32_t, _reg ## _OFST,                            \
 973                     uint32_t, (_eqp)->eq_u32[1],                        \
 974                     uint32_t, (_eqp)->eq_u32[0]);                       \
 975                 EFSYS_BAR_WRITEQ((_enp)->en_esbp,                       \
 976                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 977                     (_eqp));                                            \
 978         _NOTE(CONSTANTCONDITION)                                        \
 979         } while (B_FALSE)
 980
 981 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock)              \
 982         do {                                                            \
 983                 EFX_CHECK_REG((_enp), (_reg));                          \
 984                 EFSYS_BAR_READO((_enp)->en_esbp,                        \
 985                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 986                     (_eop), (_lock));                                   \
 987                 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg,    \
 988                     uint32_t, (_index),                                 \
 989                     uint32_t, _reg ## _OFST,                            \
 990                     uint32_t, (_eop)->eo_u32[3],                        \
 991                     uint32_t, (_eop)->eo_u32[2],                        \
 992                     uint32_t, (_eop)->eo_u32[1],                        \
 993                     uint32_t, (_eop)->eo_u32[0]);                       \
 994         _NOTE(CONSTANTCONDITION)                                        \
 995         } while (B_FALSE)
 996
 997 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock)             \
 998         do {                                                            \
 999                 EFX_CHECK_REG((_enp), (_reg));                          \
1000                 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg,   \
1001                     uint32_t, (_index),                                 \
1002                     uint32_t, _reg ## _OFST,                            \
1003                     uint32_t, (_eop)->eo_u32[3],                        \
1004                     uint32_t, (_eop)->eo_u32[2],                        \
1005                     uint32_t, (_eop)->eo_u32[1],                        \
1006                     uint32_t, (_eop)->eo_u32[0]);                       \
1007                 EFSYS_BAR_WRITEO((_enp)->en_esbp,                       \
1008                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1009                     (_eop), (_lock));                                   \
1010         _NOTE(CONSTANTCONDITION)                                        \
1011         } while (B_FALSE)
1012
1013 /*
1014  * Allow drivers to perform optimised 128-bit doorbell writes.
1015  * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1016  * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1017  * the need for locking in the host, and are the only ones known to be safe to
1018  * use 128-bites write with.
1019  */
1020 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop)           \
1021         do {                                                            \
1022                 EFX_CHECK_REG((_enp), (_reg));                          \
1023                 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo,               \
1024                     const char *,                                       \
1025                     #_reg,                                              \
1026                     uint32_t, (_index),                                 \
1027                     uint32_t, _reg ## _OFST,                            \
1028                     uint32_t, (_eop)->eo_u32[3],                        \
1029                     uint32_t, (_eop)->eo_u32[2],                        \
1030                     uint32_t, (_eop)->eo_u32[1],                        \
1031                     uint32_t, (_eop)->eo_u32[0]);                       \
1032                 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp,              \
1033                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1034                     (_eop));                                            \
1035         _NOTE(CONSTANTCONDITION)                                        \
1036         } while (B_FALSE)
1037
1038 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr)   \
1039         do {                                                            \
1040                 unsigned int _new = (_wptr);                            \
1041                 unsigned int _old = (_owptr);                           \
1042                                                                         \
1043                 if ((_new) >= (_old))                                   \
1044                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1045                             (_old) * sizeof (efx_desc_t),               \
1046                             ((_new) - (_old)) * sizeof (efx_desc_t));   \
1047                 else                                                    \
1048                         /*                                              \
1049                          * It is cheaper to sync entire map than sync   \
1050                          * two parts especially when offset/size are    \
1051                          * ignored and entire map is synced in any case.\
1052                          */                                             \
1053                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1054                             0,                                          \
1055                             (_entries) * sizeof (efx_desc_t));          \
1056         _NOTE(CONSTANTCONDITION)                                        \
1057         } while (B_FALSE)
1058
1059 extern  __checkReturn   efx_rc_t
1060 efx_nic_biu_test(
1061         __in            efx_nic_t *enp);
1062
1063 extern  __checkReturn   efx_rc_t
1064 efx_mac_select(
1065         __in            efx_nic_t *enp);
1066
1067 extern  void
1068 efx_mac_multicast_hash_compute(
1069         __in_ecount(6*count)            uint8_t const *addrs,
1070         __in                            int count,
1071         __out                           efx_oword_t *hash_low,
1072         __out                           efx_oword_t *hash_high);
1073
1074 extern  __checkReturn   efx_rc_t
1075 efx_phy_probe(
1076         __in            efx_nic_t *enp);
1077
1078 extern                  void
1079 efx_phy_unprobe(
1080         __in            efx_nic_t *enp);
1081
1082 #if EFSYS_OPT_VPD
1083
1084 /* VPD utility functions */
1085
1086 extern  __checkReturn           efx_rc_t
1087 efx_vpd_hunk_length(
1088         __in_bcount(size)       caddr_t data,
1089         __in                    size_t size,
1090         __out                   size_t *lengthp);
1091
1092 extern  __checkReturn           efx_rc_t
1093 efx_vpd_hunk_verify(
1094         __in_bcount(size)       caddr_t data,
1095         __in                    size_t size,
1096         __out_opt               boolean_t *cksummedp);
1097
1098 extern  __checkReturn           efx_rc_t
1099 efx_vpd_hunk_reinit(
1100         __in_bcount(size)       caddr_t data,
1101         __in                    size_t size,
1102         __in                    boolean_t wantpid);
1103
1104 extern  __checkReturn           efx_rc_t
1105 efx_vpd_hunk_get(
1106         __in_bcount(size)       caddr_t data,
1107         __in                    size_t size,
1108         __in                    efx_vpd_tag_t tag,
1109         __in                    efx_vpd_keyword_t keyword,
1110         __out                   unsigned int *payloadp,
1111         __out                   uint8_t *paylenp);
1112
1113 extern  __checkReturn                   efx_rc_t
1114 efx_vpd_hunk_next(
1115         __in_bcount(size)               caddr_t data,
1116         __in                            size_t size,
1117         __out                           efx_vpd_tag_t *tagp,
1118         __out                           efx_vpd_keyword_t *keyword,
1119         __out_opt                       unsigned int *payloadp,
1120         __out_opt                       uint8_t *paylenp,
1121         __inout                         unsigned int *contp);
1122
1123 extern  __checkReturn           efx_rc_t
1124 efx_vpd_hunk_set(
1125         __in_bcount(size)       caddr_t data,
1126         __in                    size_t size,
1127         __in                    efx_vpd_value_t *evvp);
1128
1129 #endif  /* EFSYS_OPT_VPD */
1130
1131 #if EFSYS_OPT_DIAG
1132
1133 extern  efx_sram_pattern_fn_t   __efx_sram_pattern_fns[];
1134
1135 typedef struct efx_register_set_s {
1136         unsigned int            address;
1137         unsigned int            step;
1138         unsigned int            rows;
1139         efx_oword_t             mask;
1140 } efx_register_set_t;
1141
1142 extern  __checkReturn   efx_rc_t
1143 efx_nic_test_registers(
1144         __in            efx_nic_t *enp,
1145         __in            efx_register_set_t *rsp,
1146         __in            size_t count);
1147
1148 extern  __checkReturn   efx_rc_t
1149 efx_nic_test_tables(
1150         __in            efx_nic_t *enp,
1151         __in            efx_register_set_t *rsp,
1152         __in            efx_pattern_type_t pattern,
1153         __in            size_t count);
1154
1155 #endif  /* EFSYS_OPT_DIAG */
1156
1157 #if EFSYS_OPT_MCDI
1158
1159 extern  __checkReturn           efx_rc_t
1160 efx_mcdi_set_workaround(
1161         __in                    efx_nic_t *enp,
1162         __in                    uint32_t type,
1163         __in                    boolean_t enabled,
1164         __out_opt               uint32_t *flagsp);
1165
1166 extern  __checkReturn           efx_rc_t
1167 efx_mcdi_get_workarounds(
1168         __in                    efx_nic_t *enp,
1169         __out_opt               uint32_t *implementedp,
1170         __out_opt               uint32_t *enabledp);
1171
1172 #endif /* EFSYS_OPT_MCDI */
1173
1174 #ifdef  __cplusplus
1175 }
1176 #endif
1177
1178 #endif  /* _SYS_EFX_IMPL_H */