2 * Copyright 2007-2009 Solarflare Communications Inc. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD$");
31 #include "efx_types.h"
39 __out efx_family_t *efp)
42 if (venid == EFX_PCI_VENID_SFC && devid == EFX_PCI_DEVID_FALCON) {
43 *efp = EFX_FAMILY_FALCON;
48 if (venid == EFX_PCI_VENID_SFC && devid == EFX_PCI_DEVID_BETHPAGE) {
49 *efp = EFX_FAMILY_SIENA;
52 if (venid == EFX_PCI_VENID_SFC && devid == EFX_PCI_DEVID_SIENA) {
53 *efp = EFX_FAMILY_SIENA;
56 if (venid == EFX_PCI_VENID_SFC &&
57 devid == EFX_PCI_DEVID_SIENA_F1_UNINIT) {
58 *efp = EFX_FAMILY_SIENA;
66 * To support clients which aren't provided with any PCI context infer
67 * the hardware family by inspecting the hardware. Obviously the caller
68 * must be damn sure they're really talking to a supported device.
72 __in efsys_bar_t *esbp,
73 __out efx_family_t *efp)
80 EFSYS_BAR_READO(esbp, FR_AZ_CS_DEBUG_REG_OFST, &oword, B_TRUE);
81 portnum = EFX_OWORD_FIELD(oword, FRF_CZ_CS_PORT_NUM);
85 family = EFX_FAMILY_FALCON;
91 family = EFX_FAMILY_SIENA;
104 EFSYS_PROBE1(fail1, int, rc);
110 * The built-in default value device id for port 1 of Siena is 0x0810.
111 * manftest needs to be able to cope with that.
114 #define EFX_BIU_MAGIC0 0x01234567
115 #define EFX_BIU_MAGIC1 0xfedcba98
117 static __checkReturn int
125 * Write magic values to scratch registers 0 and 1, then
126 * verify that the values were written correctly. Interleave
127 * the accesses to ensure that the BIU is not just reading
128 * back the cached value that was last written.
130 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC0);
131 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword);
133 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC1);
134 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 1, &oword);
136 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword);
137 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC0) {
142 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 1, &oword);
143 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC1) {
149 * Perform the same test, with the values swapped. This
150 * ensures that subsequent tests don't start with the correct
151 * values already written into the scratch registers.
153 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC1);
154 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword);
156 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, EFX_BIU_MAGIC0);
157 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 1, &oword);
159 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword);
160 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC1) {
165 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 1, &oword);
166 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != EFX_BIU_MAGIC0) {
180 EFSYS_PROBE1(fail1, int, rc);
187 static efx_nic_ops_t __cs __efx_nic_falcon_ops = {
188 falcon_nic_probe, /* eno_probe */
189 falcon_nic_reset, /* eno_reset */
190 falcon_nic_init, /* eno_init */
192 falcon_sram_test, /* eno_sram_test */
193 falcon_nic_register_test, /* eno_register_test */
194 #endif /* EFSYS_OPT_DIAG */
195 falcon_nic_fini, /* eno_fini */
196 falcon_nic_unprobe, /* eno_unprobe */
199 #endif /* EFSYS_OPT_FALCON */
203 static efx_nic_ops_t __cs __efx_nic_siena_ops = {
204 siena_nic_probe, /* eno_probe */
205 siena_nic_reset, /* eno_reset */
206 siena_nic_init, /* eno_init */
208 siena_sram_test, /* eno_sram_test */
209 siena_nic_register_test, /* eno_register_test */
210 #endif /* EFSYS_OPT_DIAG */
211 siena_nic_fini, /* eno_fini */
212 siena_nic_unprobe, /* eno_unprobe */
215 #endif /* EFSYS_OPT_SIENA */
219 __in efx_family_t family,
220 __in efsys_identifier_t *esip,
221 __in efsys_bar_t *esbp,
222 __in efsys_lock_t *eslp,
223 __deref_out efx_nic_t **enpp)
228 EFSYS_ASSERT3U(family, >, EFX_FAMILY_INVALID);
229 EFSYS_ASSERT3U(family, <, EFX_FAMILY_NTYPES);
231 /* Allocate a NIC object */
232 EFSYS_KMEM_ALLOC(esip, sizeof (efx_nic_t), enp);
239 enp->en_magic = EFX_NIC_MAGIC;
243 case EFX_FAMILY_FALCON:
244 enp->en_enop = (efx_nic_ops_t *)&__efx_nic_falcon_ops;
245 enp->en_features = 0;
247 #endif /* EFSYS_OPT_FALCON */
250 case EFX_FAMILY_SIENA:
251 enp->en_enop = (efx_nic_ops_t *)&__efx_nic_siena_ops;
252 enp->en_features = EFX_FEATURE_IPV6 |
253 EFX_FEATURE_LFSR_HASH_INSERT |
254 EFX_FEATURE_LINK_EVENTS | EFX_FEATURE_PERIODIC_MAC_STATS |
255 EFX_FEATURE_WOL | EFX_FEATURE_MCDI |
256 EFX_FEATURE_LOOKAHEAD_SPLIT |
257 EFX_FEATURE_MAC_HEADER_FILTERS;
259 #endif /* EFSYS_OPT_SIENA */
266 enp->en_family = family;
280 /* Free the NIC object */
281 EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
284 EFSYS_PROBE1(fail1, int, rc);
297 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
299 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
300 #endif /* EFSYS_OPT_MCDI */
301 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_PROBE));
304 if ((rc = efx_nic_biu_test(enp)) != 0)
307 /* Clear the region register */
308 EFX_POPULATE_OWORD_4(oword,
309 FRF_AZ_ADR_REGION0, 0,
310 FRF_AZ_ADR_REGION1, (1 << 16),
311 FRF_AZ_ADR_REGION2, (2 << 16),
312 FRF_AZ_ADR_REGION3, (3 << 16));
313 EFX_BAR_WRITEO(enp, FR_AZ_ADR_REGION_REG, &oword);
316 if ((rc = enop->eno_probe(enp)) != 0)
319 if ((rc = efx_phy_probe(enp)) != 0)
322 enp->en_mod_flags |= EFX_MOD_PROBE;
329 enop->eno_unprobe(enp);
334 EFSYS_PROBE1(fail1, int, rc);
339 #if EFSYS_OPT_PCIE_TUNE
346 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
347 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
348 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
351 if (enp->en_family == EFX_FAMILY_FALCON)
352 return (falcon_nic_pcie_tune(enp, nlanes));
358 efx_nic_pcie_extended_sync(
361 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
362 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
363 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
366 if (enp->en_family == EFX_FAMILY_SIENA)
367 return (siena_nic_pcie_extended_sync(enp));
373 #endif /* EFSYS_OPT_PCIE_TUNE */
379 efx_nic_ops_t *enop = enp->en_enop;
382 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
383 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
385 if (enp->en_mod_flags & EFX_MOD_NIC) {
390 if ((rc = enop->eno_init(enp)) != 0)
393 enp->en_mod_flags |= EFX_MOD_NIC;
400 EFSYS_PROBE1(fail1, int, rc);
409 efx_nic_ops_t *enop = enp->en_enop;
411 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
412 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
413 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_NIC);
414 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
415 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
416 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
417 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
421 enp->en_mod_flags &= ~EFX_MOD_NIC;
428 efx_nic_ops_t *enop = enp->en_enop;
430 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
432 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
433 #endif /* EFSYS_OPT_MCDI */
434 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
435 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
436 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
437 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
438 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
439 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
441 efx_phy_unprobe(enp);
443 enop->eno_unprobe(enp);
445 enp->en_mod_flags &= ~EFX_MOD_PROBE;
452 efsys_identifier_t *esip = enp->en_esip;
454 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
455 EFSYS_ASSERT3U(enp->en_mod_flags, ==, 0);
466 /* Free the NIC object */
467 EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
474 efx_nic_ops_t *enop = enp->en_enop;
475 unsigned int mod_flags;
478 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
479 EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
481 * All modules except the MCDI, PROBE, NVRAM, VPD, MON (which we
482 * do not reset here) must have been shut down or never initialized.
484 * A rule of thumb here is: If the controller or MC reboots, is *any*
485 * state lost. If it's lost and needs reapplying, then the module
486 * *must* not be initialised during the reset.
488 mod_flags = enp->en_mod_flags;
489 mod_flags &= ~(EFX_MOD_MCDI | EFX_MOD_PROBE | EFX_MOD_NVRAM |
490 EFX_MOD_VPD | EFX_MOD_MON);
491 EFSYS_ASSERT3U(mod_flags, ==, 0);
492 if (mod_flags != 0) {
497 if ((rc = enop->eno_reset(enp)) != 0)
500 enp->en_reset_flags |= EFX_RESET_MAC;
507 EFSYS_PROBE1(fail1, int, rc);
512 const efx_nic_cfg_t *
516 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
518 return (&(enp->en_nic_cfg));
524 efx_nic_register_test(
527 efx_nic_ops_t *enop = enp->en_enop;
530 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
531 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
532 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
534 if ((rc = enop->eno_register_test(enp)) != 0)
540 EFSYS_PROBE1(fail1, int, rc);
546 efx_nic_test_registers(
548 __in efx_register_set_t *rsp,
552 efx_oword_t original;
558 /* This function is only suitable for registers */
559 EFSYS_ASSERT(rsp->rows == 1);
561 /* bit sweep on and off */
562 EFSYS_BAR_READO(enp->en_esbp, rsp->address, &original,
564 for (bit = 0; bit < 128; bit++) {
565 /* Is this bit in the mask? */
566 if (~(rsp->mask.eo_u32[bit >> 5]) & (1 << bit))
569 /* Test this bit can be set in isolation */
571 EFX_AND_OWORD(reg, rsp->mask);
572 EFX_SET_OWORD_BIT(reg, bit);
574 EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, ®,
576 EFSYS_BAR_READO(enp->en_esbp, rsp->address, &buf,
579 EFX_AND_OWORD(buf, rsp->mask);
580 if (memcmp(®, &buf, sizeof (reg))) {
585 /* Test this bit can be cleared in isolation */
586 EFX_OR_OWORD(reg, rsp->mask);
587 EFX_CLEAR_OWORD_BIT(reg, bit);
589 EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, ®,
591 EFSYS_BAR_READO(enp->en_esbp, rsp->address, &buf,
594 EFX_AND_OWORD(buf, rsp->mask);
595 if (memcmp(®, &buf, sizeof (reg))) {
601 /* Restore the old value */
602 EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, &original,
614 EFSYS_PROBE1(fail1, int, rc);
616 /* Restore the old value */
617 EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, &original, B_TRUE);
625 __in efx_register_set_t *rsp,
626 __in efx_pattern_type_t pattern,
629 efx_sram_pattern_fn_t func;
631 unsigned int address;
636 EFSYS_ASSERT(pattern < EFX_PATTERN_NTYPES);
637 func = __efx_sram_pattern_fns[pattern];
641 address = rsp->address;
642 for (index = 0; index < rsp->rows; ++index) {
643 func(2 * index + 0, B_FALSE, ®.eo_qword[0]);
644 func(2 * index + 1, B_FALSE, ®.eo_qword[1]);
645 EFX_AND_OWORD(reg, rsp->mask);
646 EFSYS_BAR_WRITEO(enp->en_esbp, address, ®, B_TRUE);
648 address += rsp->step;
652 address = rsp->address;
653 for (index = 0; index < rsp->rows; ++index) {
654 func(2 * index + 0, B_FALSE, ®.eo_qword[0]);
655 func(2 * index + 1, B_FALSE, ®.eo_qword[1]);
656 EFX_AND_OWORD(reg, rsp->mask);
657 EFSYS_BAR_READO(enp->en_esbp, address, &buf, B_TRUE);
658 if (memcmp(®, &buf, sizeof (reg))) {
663 address += rsp->step;
673 EFSYS_PROBE1(fail1, int, rc);
678 #endif /* EFSYS_OPT_DIAG */