2 * Copyright (c) 2007-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
39 static const efx_phy_ops_t __efx_phy_siena_ops = {
40 siena_phy_power, /* epo_power */
42 siena_phy_reconfigure, /* epo_reconfigure */
43 siena_phy_verify, /* epo_verify */
44 siena_phy_oui_get, /* epo_oui_get */
45 #if EFSYS_OPT_PHY_STATS
46 siena_phy_stats_update, /* epo_stats_update */
47 #endif /* EFSYS_OPT_PHY_STATS */
49 NULL, /* epo_bist_enable_offline */
50 siena_phy_bist_start, /* epo_bist_start */
51 siena_phy_bist_poll, /* epo_bist_poll */
52 siena_phy_bist_stop, /* epo_bist_stop */
53 #endif /* EFSYS_OPT_BIST */
55 #endif /* EFSYS_OPT_SIENA */
57 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
58 static const efx_phy_ops_t __efx_phy_ef10_ops = {
59 ef10_phy_power, /* epo_power */
61 ef10_phy_reconfigure, /* epo_reconfigure */
62 ef10_phy_verify, /* epo_verify */
63 ef10_phy_oui_get, /* epo_oui_get */
64 #if EFSYS_OPT_PHY_STATS
65 ef10_phy_stats_update, /* epo_stats_update */
66 #endif /* EFSYS_OPT_PHY_STATS */
68 /* FIXME: Are these BIST methods appropriate for Medford? */
69 hunt_bist_enable_offline, /* epo_bist_enable_offline */
70 hunt_bist_start, /* epo_bist_start */
71 hunt_bist_poll, /* epo_bist_poll */
72 hunt_bist_stop, /* epo_bist_stop */
73 #endif /* EFSYS_OPT_BIST */
75 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
77 __checkReturn efx_rc_t
81 efx_port_t *epp = &(enp->en_port);
82 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
83 const efx_phy_ops_t *epop;
86 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
88 epp->ep_port = encp->enc_port;
89 epp->ep_phy_type = encp->enc_phy_type;
91 /* Hook in operations structure */
92 switch (enp->en_family) {
94 case EFX_FAMILY_SIENA:
95 epop = &__efx_phy_siena_ops;
97 #endif /* EFSYS_OPT_SIENA */
98 #if EFSYS_OPT_HUNTINGTON
99 case EFX_FAMILY_HUNTINGTON:
100 epop = &__efx_phy_ef10_ops;
102 #endif /* EFSYS_OPT_HUNTINGTON */
103 #if EFSYS_OPT_MEDFORD
104 case EFX_FAMILY_MEDFORD:
105 epop = &__efx_phy_ef10_ops;
107 #endif /* EFSYS_OPT_MEDFORD */
118 EFSYS_PROBE1(fail1, efx_rc_t, rc);
121 epp->ep_phy_type = 0;
126 __checkReturn efx_rc_t
130 efx_port_t *epp = &(enp->en_port);
131 const efx_phy_ops_t *epop = epp->ep_epop;
133 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
134 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
136 return (epop->epo_verify(enp));
139 #if EFSYS_OPT_PHY_LED_CONTROL
141 __checkReturn efx_rc_t
144 __in efx_phy_led_mode_t mode)
146 efx_nic_cfg_t *encp = (&enp->en_nic_cfg);
147 efx_port_t *epp = &(enp->en_port);
148 const efx_phy_ops_t *epop = epp->ep_epop;
152 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
153 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
155 if (epp->ep_phy_led_mode == mode)
158 mask = (1 << EFX_PHY_LED_DEFAULT);
159 mask |= encp->enc_led_mask;
161 if (!((1 << mode) & mask)) {
166 EFSYS_ASSERT3U(mode, <, EFX_PHY_LED_NMODES);
167 epp->ep_phy_led_mode = mode;
169 if ((rc = epop->epo_reconfigure(enp)) != 0)
178 EFSYS_PROBE1(fail1, efx_rc_t, rc);
182 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
188 __out uint32_t *maskp)
190 efx_port_t *epp = &(enp->en_port);
192 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
193 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
196 case EFX_PHY_CAP_CURRENT:
197 *maskp = epp->ep_adv_cap_mask;
199 case EFX_PHY_CAP_DEFAULT:
200 *maskp = epp->ep_default_adv_cap_mask;
202 case EFX_PHY_CAP_PERM:
203 *maskp = epp->ep_phy_cap_mask;
206 EFSYS_ASSERT(B_FALSE);
211 __checkReturn efx_rc_t
216 efx_port_t *epp = &(enp->en_port);
217 const efx_phy_ops_t *epop = epp->ep_epop;
221 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
222 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
224 if ((mask & ~epp->ep_phy_cap_mask) != 0) {
229 if (epp->ep_adv_cap_mask == mask)
232 old_mask = epp->ep_adv_cap_mask;
233 epp->ep_adv_cap_mask = mask;
235 if ((rc = epop->epo_reconfigure(enp)) != 0)
244 epp->ep_adv_cap_mask = old_mask;
245 /* Reconfigure for robustness */
246 if (epop->epo_reconfigure(enp) != 0) {
248 * We may have an inconsistent view of our advertised speed
255 EFSYS_PROBE1(fail1, efx_rc_t, rc);
263 __out uint32_t *maskp)
265 efx_port_t *epp = &(enp->en_port);
267 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
268 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
270 *maskp = epp->ep_lp_cap_mask;
273 __checkReturn efx_rc_t
276 __out uint32_t *ouip)
278 efx_port_t *epp = &(enp->en_port);
279 const efx_phy_ops_t *epop = epp->ep_epop;
281 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
282 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
284 return (epop->epo_oui_get(enp, ouip));
288 efx_phy_media_type_get(
290 __out efx_phy_media_type_t *typep)
292 efx_port_t *epp = &(enp->en_port);
294 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
295 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
297 if (epp->ep_module_type != EFX_PHY_MEDIA_INVALID)
298 *typep = epp->ep_module_type;
300 *typep = epp->ep_fixed_port_type;
303 __checkReturn efx_rc_t
304 efx_phy_module_get_info(
306 __in uint8_t dev_addr,
309 __out_bcount(len) uint8_t *data)
313 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
314 EFSYS_ASSERT(data != NULL);
316 if ((uint32_t)offset + len > 0xff) {
321 if ((rc = efx_mcdi_phy_module_get_info(enp, dev_addr,
322 offset, len, data)) != 0)
330 EFSYS_PROBE1(fail1, efx_rc_t, rc);
335 #if EFSYS_OPT_PHY_STATS
339 /* START MKCONFIG GENERATED PhyStatNamesBlock d5f79b4bc2c050fe */
340 static const char *__efx_phy_stat_name[] = {
389 /* END MKCONFIG GENERATED PhyStatNamesBlock */
394 __in efx_phy_stat_t type)
396 _NOTE(ARGUNUSED(enp))
397 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
398 EFSYS_ASSERT3U(type, <, EFX_PHY_NSTATS);
400 return (__efx_phy_stat_name[type]);
403 #endif /* EFSYS_OPT_NAMES */
405 __checkReturn efx_rc_t
406 efx_phy_stats_update(
408 __in efsys_mem_t *esmp,
409 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat)
411 efx_port_t *epp = &(enp->en_port);
412 const efx_phy_ops_t *epop = epp->ep_epop;
414 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
415 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
417 return (epop->epo_stats_update(enp, esmp, stat));
420 #endif /* EFSYS_OPT_PHY_STATS */
425 __checkReturn efx_rc_t
426 efx_bist_enable_offline(
429 efx_port_t *epp = &(enp->en_port);
430 const efx_phy_ops_t *epop = epp->ep_epop;
433 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
435 if (epop->epo_bist_enable_offline == NULL) {
440 if ((rc = epop->epo_bist_enable_offline(enp)) != 0)
448 EFSYS_PROBE1(fail1, efx_rc_t, rc);
454 __checkReturn efx_rc_t
457 __in efx_bist_type_t type)
459 efx_port_t *epp = &(enp->en_port);
460 const efx_phy_ops_t *epop = epp->ep_epop;
463 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
465 EFSYS_ASSERT3U(type, !=, EFX_BIST_TYPE_UNKNOWN);
466 EFSYS_ASSERT3U(type, <, EFX_BIST_TYPE_NTYPES);
467 EFSYS_ASSERT3U(epp->ep_current_bist, ==, EFX_BIST_TYPE_UNKNOWN);
469 if (epop->epo_bist_start == NULL) {
474 if ((rc = epop->epo_bist_start(enp, type)) != 0)
477 epp->ep_current_bist = type;
484 EFSYS_PROBE1(fail1, efx_rc_t, rc);
489 __checkReturn efx_rc_t
492 __in efx_bist_type_t type,
493 __out efx_bist_result_t *resultp,
494 __out_opt uint32_t *value_maskp,
495 __out_ecount_opt(count) unsigned long *valuesp,
498 efx_port_t *epp = &(enp->en_port);
499 const efx_phy_ops_t *epop = epp->ep_epop;
502 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
504 EFSYS_ASSERT3U(type, !=, EFX_BIST_TYPE_UNKNOWN);
505 EFSYS_ASSERT3U(type, <, EFX_BIST_TYPE_NTYPES);
506 EFSYS_ASSERT3U(epp->ep_current_bist, ==, type);
508 EFSYS_ASSERT(epop->epo_bist_poll != NULL);
509 if (epop->epo_bist_poll == NULL) {
514 if ((rc = epop->epo_bist_poll(enp, type, resultp, value_maskp,
515 valuesp, count)) != 0)
523 EFSYS_PROBE1(fail1, efx_rc_t, rc);
531 __in efx_bist_type_t type)
533 efx_port_t *epp = &(enp->en_port);
534 const efx_phy_ops_t *epop = epp->ep_epop;
536 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
538 EFSYS_ASSERT3U(type, !=, EFX_BIST_TYPE_UNKNOWN);
539 EFSYS_ASSERT3U(type, <, EFX_BIST_TYPE_NTYPES);
540 EFSYS_ASSERT3U(epp->ep_current_bist, ==, type);
542 EFSYS_ASSERT(epop->epo_bist_stop != NULL);
544 if (epop->epo_bist_stop != NULL)
545 epop->epo_bist_stop(enp, type);
547 epp->ep_current_bist = EFX_BIST_TYPE_UNKNOWN;
550 #endif /* EFSYS_OPT_BIST */
555 efx_port_t *epp = &(enp->en_port);
557 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
561 epp->ep_adv_cap_mask = 0;
564 epp->ep_phy_type = 0;