2 * Copyright (c) 2012-2015 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
33 #ifndef _SYS_HUNT_IMPL_H
34 #define _SYS_HUNT_IMPL_H
38 #include "efx_regs_ef10.h"
46 * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could
47 * possibly be increased, or the write size reported by newer firmware used
50 #define EF10_NVRAM_CHUNK 0x80
52 /* Alignment requirement for value written to RX WPTR:
53 * the WPTR must be aligned to an 8 descriptor boundary
55 #define EF10_RX_WPTR_ALIGN 8
58 * Max byte offset into the packet the TCP header must start for the hardware
59 * to be able to parse the packet correctly.
60 * FIXME: Move to ef10_impl.h when it is included in all driver builds.
62 #define EF10_TCP_HEADER_OFFSET_LIMIT 208
64 /* Invalid RSS context handle */
65 #define EF10_RSS_CONTEXT_INVALID (0xffffffff)
70 __checkReturn efx_rc_t
78 __checkReturn efx_rc_t
81 __in unsigned int index,
82 __in efsys_mem_t *esmp,
91 __checkReturn efx_rc_t
94 __in unsigned int count);
101 __checkReturn efx_rc_t
104 __in unsigned int us);
108 ef10_ev_qstats_update(
110 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
111 #endif /* EFSYS_OPT_QSTATS */
114 ef10_ev_rxlabel_init(
117 __in unsigned int label);
120 ef10_ev_rxlabel_fini(
122 __in unsigned int label);
126 __checkReturn efx_rc_t
129 __in efx_intr_type_t type,
130 __in efsys_mem_t *esmp);
134 __in efx_nic_t *enp);
138 __in efx_nic_t *enp);
141 ef10_intr_disable_unlocked(
142 __in efx_nic_t *enp);
144 __checkReturn efx_rc_t
147 __in unsigned int level);
150 ef10_intr_status_line(
152 __out boolean_t *fatalp,
153 __out uint32_t *qmaskp);
156 ef10_intr_status_message(
158 __in unsigned int message,
159 __out boolean_t *fatalp);
163 __in efx_nic_t *enp);
166 __in efx_nic_t *enp);
170 extern __checkReturn efx_rc_t
172 __in efx_nic_t *enp);
174 extern __checkReturn efx_rc_t
176 __in efx_nic_t *enp);
178 extern __checkReturn efx_rc_t
179 ef10_nic_set_drv_limits(
180 __inout efx_nic_t *enp,
181 __in efx_drv_limits_t *edlp);
183 extern __checkReturn efx_rc_t
184 ef10_nic_get_vi_pool(
186 __out uint32_t *vi_countp);
188 extern __checkReturn efx_rc_t
189 ef10_nic_get_bar_region(
191 __in efx_nic_region_t region,
192 __out uint32_t *offsetp,
193 __out size_t *sizep);
195 extern __checkReturn efx_rc_t
197 __in efx_nic_t *enp);
199 extern __checkReturn efx_rc_t
201 __in efx_nic_t *enp);
205 extern __checkReturn efx_rc_t
206 ef10_nic_register_test(
207 __in efx_nic_t *enp);
209 #endif /* EFSYS_OPT_DIAG */
213 __in efx_nic_t *enp);
217 __in efx_nic_t *enp);
222 extern __checkReturn efx_rc_t
225 __out efx_link_mode_t *link_modep);
227 extern __checkReturn efx_rc_t
230 __out boolean_t *mac_upp);
232 extern __checkReturn efx_rc_t
234 __in efx_nic_t *enp);
236 extern __checkReturn efx_rc_t
238 __in efx_nic_t *enp);
240 extern __checkReturn efx_rc_t
241 ef10_mac_reconfigure(
242 __in efx_nic_t *enp);
244 extern __checkReturn efx_rc_t
245 ef10_mac_multicast_list_set(
246 __in efx_nic_t *enp);
248 extern __checkReturn efx_rc_t
249 ef10_mac_filter_default_rxq_set(
252 __in boolean_t using_rss);
255 ef10_mac_filter_default_rxq_clear(
256 __in efx_nic_t *enp);
258 #if EFSYS_OPT_LOOPBACK
260 extern __checkReturn efx_rc_t
261 ef10_mac_loopback_set(
263 __in efx_link_mode_t link_mode,
264 __in efx_loopback_type_t loopback_type);
266 #endif /* EFSYS_OPT_LOOPBACK */
268 #if EFSYS_OPT_MAC_STATS
270 extern __checkReturn efx_rc_t
271 ef10_mac_stats_update(
273 __in efsys_mem_t *esmp,
274 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
275 __inout_opt uint32_t *generationp);
277 #endif /* EFSYS_OPT_MAC_STATS */
284 extern __checkReturn efx_rc_t
287 __in const efx_mcdi_transport_t *mtp);
291 __in efx_nic_t *enp);
294 ef10_mcdi_send_request(
299 __in size_t sdu_len);
301 extern __checkReturn boolean_t
302 ef10_mcdi_poll_response(
303 __in efx_nic_t *enp);
306 ef10_mcdi_read_response(
308 __out_bcount(length) void *bufferp,
313 ef10_mcdi_poll_reboot(
314 __in efx_nic_t *enp);
316 extern __checkReturn efx_rc_t
317 ef10_mcdi_feature_supported(
319 __in efx_mcdi_feature_id_t id,
320 __out boolean_t *supportedp);
322 #endif /* EFSYS_OPT_MCDI */
326 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
328 extern __checkReturn efx_rc_t
329 ef10_nvram_buf_read_tlv(
331 __in_bcount(max_seg_size) caddr_t seg_data,
332 __in size_t max_seg_size,
334 __deref_out_bcount_opt(*sizep) caddr_t *datap,
335 __out size_t *sizep);
337 extern __checkReturn efx_rc_t
338 ef10_nvram_buf_write_tlv(
339 __inout_bcount(partn_size) caddr_t partn_data,
340 __in size_t partn_size,
342 __in_bcount(tag_size) caddr_t tag_data,
343 __in size_t tag_size,
344 __out size_t *total_lengthp);
346 extern __checkReturn efx_rc_t
347 ef10_nvram_partn_read_tlv(
351 __deref_out_bcount_opt(*sizep) caddr_t *datap,
352 __out size_t *sizep);
354 extern __checkReturn efx_rc_t
355 ef10_nvram_partn_write_tlv(
359 __in_bcount(size) caddr_t data,
362 extern __checkReturn efx_rc_t
363 ef10_nvram_partn_write_segment_tlv(
367 __in_bcount(size) caddr_t data,
369 __in boolean_t all_segments);
371 extern __checkReturn efx_rc_t
372 ef10_nvram_partn_lock(
374 __in uint32_t partn);
377 ef10_nvram_partn_unlock(
379 __in uint32_t partn);
381 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
387 extern __checkReturn efx_rc_t
389 __in efx_nic_t *enp);
391 #endif /* EFSYS_OPT_DIAG */
393 extern __checkReturn efx_rc_t
394 ef10_nvram_type_to_partn(
396 __in efx_nvram_type_t type,
397 __out uint32_t *partnp);
399 extern __checkReturn efx_rc_t
400 ef10_nvram_partn_size(
403 __out size_t *sizep);
405 extern __checkReturn efx_rc_t
406 ef10_nvram_partn_rw_start(
409 __out size_t *chunk_sizep);
411 extern __checkReturn efx_rc_t
412 ef10_nvram_partn_read_mode(
415 __in unsigned int offset,
416 __out_bcount(size) caddr_t data,
420 extern __checkReturn efx_rc_t
421 ef10_nvram_partn_read(
424 __in unsigned int offset,
425 __out_bcount(size) caddr_t data,
428 extern __checkReturn efx_rc_t
429 ef10_nvram_partn_erase(
432 __in unsigned int offset,
435 extern __checkReturn efx_rc_t
436 ef10_nvram_partn_write(
439 __in unsigned int offset,
440 __out_bcount(size) caddr_t data,
444 ef10_nvram_partn_rw_finish(
446 __in uint32_t partn);
448 extern __checkReturn efx_rc_t
449 ef10_nvram_partn_get_version(
452 __out uint32_t *subtypep,
453 __out_ecount(4) uint16_t version[4]);
455 extern __checkReturn efx_rc_t
456 ef10_nvram_partn_set_version(
459 __in_ecount(4) uint16_t version[4]);
461 extern __checkReturn efx_rc_t
462 ef10_nvram_buffer_validate(
465 __in_bcount(buffer_size)
467 __in size_t buffer_size);
469 #endif /* EFSYS_OPT_NVRAM */
474 typedef struct ef10_link_state_s {
475 uint32_t els_adv_cap_mask;
476 uint32_t els_lp_cap_mask;
477 unsigned int els_fcntl;
478 efx_link_mode_t els_link_mode;
479 #if EFSYS_OPT_LOOPBACK
480 efx_loopback_type_t els_loopback;
482 boolean_t els_mac_up;
488 __in efx_qword_t *eqp,
489 __out efx_link_mode_t *link_modep);
491 extern __checkReturn efx_rc_t
494 __out ef10_link_state_t *elsp);
496 extern __checkReturn efx_rc_t
501 extern __checkReturn efx_rc_t
502 ef10_phy_reconfigure(
503 __in efx_nic_t *enp);
505 extern __checkReturn efx_rc_t
507 __in efx_nic_t *enp);
509 extern __checkReturn efx_rc_t
512 __out uint32_t *ouip);
514 #if EFSYS_OPT_PHY_STATS
516 extern __checkReturn efx_rc_t
517 ef10_phy_stats_update(
519 __in efsys_mem_t *esmp,
520 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
522 #endif /* EFSYS_OPT_PHY_STATS */
524 #if EFSYS_OPT_PHY_PROPS
531 __in unsigned int id);
533 #endif /* EFSYS_OPT_NAMES */
535 extern __checkReturn efx_rc_t
538 __in unsigned int id,
540 __out uint32_t *valp);
542 extern __checkReturn efx_rc_t
545 __in unsigned int id,
548 #endif /* EFSYS_OPT_PHY_PROPS */
552 extern __checkReturn efx_rc_t
553 hunt_bist_enable_offline(
554 __in efx_nic_t *enp);
556 extern __checkReturn efx_rc_t
559 __in efx_bist_type_t type);
561 extern __checkReturn efx_rc_t
564 __in efx_bist_type_t type,
565 __out efx_bist_result_t *resultp,
566 __out_opt __drv_when(count > 0, __notnull)
567 uint32_t *value_maskp,
568 __out_ecount_opt(count) __drv_when(count > 0, __notnull)
569 unsigned long *valuesp,
575 __in efx_bist_type_t type);
577 #endif /* EFSYS_OPT_BIST */
584 extern __checkReturn efx_rc_t
587 __in efx_sram_pattern_fn_t func);
589 #endif /* EFSYS_OPT_DIAG */
594 extern __checkReturn efx_rc_t
596 __in efx_nic_t *enp);
600 __in efx_nic_t *enp);
602 extern __checkReturn efx_rc_t
605 __in unsigned int index,
606 __in unsigned int label,
607 __in efsys_mem_t *esmp,
613 __out unsigned int *addedp);
617 __in efx_txq_t *etp);
619 extern __checkReturn efx_rc_t
622 __in_ecount(n) efx_buffer_t *eb,
624 __in unsigned int completed,
625 __inout unsigned int *addedp);
630 __in unsigned int added,
631 __in unsigned int pushed);
633 extern __checkReturn efx_rc_t
636 __in unsigned int ns);
638 extern __checkReturn efx_rc_t
640 __in efx_txq_t *etp);
644 __in efx_txq_t *etp);
646 extern __checkReturn efx_rc_t
648 __in efx_txq_t *etp);
651 ef10_tx_qpio_disable(
652 __in efx_txq_t *etp);
654 extern __checkReturn efx_rc_t
657 __in_ecount(buf_length) uint8_t *buffer,
658 __in size_t buf_length,
659 __in size_t pio_buf_offset);
661 extern __checkReturn efx_rc_t
664 __in size_t pkt_length,
665 __in unsigned int completed,
666 __inout unsigned int *addedp);
668 extern __checkReturn efx_rc_t
671 __in_ecount(n) efx_desc_t *ed,
673 __in unsigned int completed,
674 __inout unsigned int *addedp);
677 ef10_tx_qdesc_dma_create(
679 __in efsys_dma_addr_t addr,
682 __out efx_desc_t *edp);
685 hunt_tx_qdesc_tso_create(
687 __in uint16_t ipv4_id,
688 __in uint32_t tcp_seq,
689 __in uint8_t tcp_flags,
690 __out efx_desc_t *edp);
693 ef10_tx_qdesc_tso2_create(
695 __in uint16_t ipv4_id,
696 __in uint32_t tcp_seq,
697 __in uint16_t tcp_mss,
698 __out_ecount(count) efx_desc_t *edp,
702 ef10_tx_qdesc_vlantci_create(
704 __in uint16_t vlan_tci,
705 __out efx_desc_t *edp);
711 ef10_tx_qstats_update(
713 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
715 #endif /* EFSYS_OPT_QSTATS */
719 /* Missing register definitions */
720 #ifndef ER_DZ_TX_PIOBUF_OFST
721 #define ER_DZ_TX_PIOBUF_OFST 0x00001000
723 #ifndef ER_DZ_TX_PIOBUF_STEP
724 #define ER_DZ_TX_PIOBUF_STEP 8192
726 #ifndef ER_DZ_TX_PIOBUF_ROWS
727 #define ER_DZ_TX_PIOBUF_ROWS 2048
730 #ifndef ER_DZ_TX_PIOBUF_SIZE
731 #define ER_DZ_TX_PIOBUF_SIZE 2048
734 #define HUNT_PIOBUF_NBUFS (16)
735 #define HUNT_PIOBUF_SIZE (ER_DZ_TX_PIOBUF_SIZE)
737 #define HUNT_MIN_PIO_ALLOC_SIZE (HUNT_PIOBUF_SIZE / 32)
739 #define EF10_LEGACY_PF_PRIVILEGE_MASK \
740 (MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN | \
741 MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK | \
742 MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD | \
743 MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP | \
744 MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS | \
745 MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING | \
746 MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST | \
747 MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST | \
748 MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST | \
749 MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST | \
750 MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS)
752 #define EF10_LEGACY_VF_PRIVILEGE_MASK 0
754 typedef uint32_t efx_piobuf_handle_t;
756 #define EFX_PIOBUF_HANDLE_INVALID ((efx_piobuf_handle_t) -1)
758 extern __checkReturn efx_rc_t
760 __inout efx_nic_t *enp,
761 __out uint32_t *bufnump,
762 __out efx_piobuf_handle_t *handlep,
763 __out uint32_t *blknump,
764 __out uint32_t *offsetp,
765 __out size_t *sizep);
767 extern __checkReturn efx_rc_t
769 __inout efx_nic_t *enp,
770 __in uint32_t bufnum,
771 __in uint32_t blknum);
773 extern __checkReturn efx_rc_t
775 __inout efx_nic_t *enp,
776 __in uint32_t vi_index,
777 __in efx_piobuf_handle_t handle);
779 extern __checkReturn efx_rc_t
781 __inout efx_nic_t *enp,
782 __in uint32_t vi_index);
789 extern __checkReturn efx_rc_t
791 __in efx_nic_t *enp);
793 extern __checkReturn efx_rc_t
796 __out size_t *sizep);
798 extern __checkReturn efx_rc_t
801 __out_bcount(size) caddr_t data,
804 extern __checkReturn efx_rc_t
807 __in_bcount(size) caddr_t data,
810 extern __checkReturn efx_rc_t
813 __in_bcount(size) caddr_t data,
816 extern __checkReturn efx_rc_t
819 __in_bcount(size) caddr_t data,
821 __inout efx_vpd_value_t *evvp);
823 extern __checkReturn efx_rc_t
826 __in_bcount(size) caddr_t data,
828 __in efx_vpd_value_t *evvp);
830 extern __checkReturn efx_rc_t
833 __in_bcount(size) caddr_t data,
835 __out efx_vpd_value_t *evvp,
836 __inout unsigned int *contp);
838 extern __checkReturn efx_rc_t
841 __in_bcount(size) caddr_t data,
846 __in efx_nic_t *enp);
848 #endif /* EFSYS_OPT_VPD */
853 extern __checkReturn efx_rc_t
855 __in efx_nic_t *enp);
857 #if EFSYS_OPT_RX_SCATTER
858 extern __checkReturn efx_rc_t
859 ef10_rx_scatter_enable(
861 __in unsigned int buf_size);
862 #endif /* EFSYS_OPT_RX_SCATTER */
865 #if EFSYS_OPT_RX_SCALE
867 extern __checkReturn efx_rc_t
868 ef10_rx_scale_mode_set(
870 __in efx_rx_hash_alg_t alg,
871 __in efx_rx_hash_type_t type,
872 __in boolean_t insert);
874 extern __checkReturn efx_rc_t
875 ef10_rx_scale_key_set(
877 __in_ecount(n) uint8_t *key,
880 extern __checkReturn efx_rc_t
881 ef10_rx_scale_tbl_set(
883 __in_ecount(n) unsigned int *table,
886 extern __checkReturn uint32_t
889 __in efx_rx_hash_alg_t func,
890 __in uint8_t *buffer);
892 #endif /* EFSYS_OPT_RX_SCALE */
894 extern __checkReturn efx_rc_t
895 ef10_rx_prefix_pktlen(
897 __in uint8_t *buffer,
898 __out uint16_t *lengthp);
903 __in_ecount(n) efsys_dma_addr_t *addrp,
906 __in unsigned int completed,
907 __in unsigned int added);
912 __in unsigned int added,
913 __inout unsigned int *pushedp);
915 extern __checkReturn efx_rc_t
917 __in efx_rxq_t *erp);
921 __in efx_rxq_t *erp);
923 extern __checkReturn efx_rc_t
926 __in unsigned int index,
927 __in unsigned int label,
928 __in efx_rxq_type_t type,
929 __in efsys_mem_t *esmp,
933 __in efx_rxq_t *erp);
937 __in efx_rxq_t *erp);
941 __in efx_nic_t *enp);
945 typedef struct ef10_filter_handle_s {
948 } ef10_filter_handle_t;
950 typedef struct ef10_filter_entry_s {
951 uintptr_t efe_spec; /* pointer to filter spec plus busy bit */
952 ef10_filter_handle_t efe_handle;
953 } ef10_filter_entry_t;
956 * BUSY flag indicates that an update is in progress.
957 * AUTO_OLD flag is used to mark and sweep MAC packet filters.
959 #define EFX_EF10_FILTER_FLAG_BUSY 1U
960 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2U
961 #define EFX_EF10_FILTER_FLAGS 3U
964 * Size of the hash table used by the driver. Doesn't need to be the
965 * same size as the hardware's table.
967 #define EFX_EF10_FILTER_TBL_ROWS 8192
969 /* Allow for the broadcast address to be added to the multicast list */
970 #define EFX_EF10_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1)
972 typedef struct ef10_filter_table_s {
973 ef10_filter_entry_t eft_entry[EFX_EF10_FILTER_TBL_ROWS];
974 efx_rxq_t * eft_default_rxq;
975 boolean_t eft_using_rss;
976 uint32_t eft_unicst_filter_index;
977 boolean_t eft_unicst_filter_set;
978 uint32_t eft_mulcst_filter_indexes[
979 EFX_EF10_FILTER_MULTICAST_FILTERS_MAX];
980 uint32_t eft_mulcst_filter_count;
981 } ef10_filter_table_t;
983 __checkReturn efx_rc_t
985 __in efx_nic_t *enp);
989 __in efx_nic_t *enp);
991 __checkReturn efx_rc_t
993 __in efx_nic_t *enp);
995 __checkReturn efx_rc_t
998 __inout efx_filter_spec_t *spec,
999 __in boolean_t may_replace);
1001 __checkReturn efx_rc_t
1003 __in efx_nic_t *enp,
1004 __inout efx_filter_spec_t *spec);
1006 extern __checkReturn efx_rc_t
1007 ef10_filter_supported_filters(
1008 __in efx_nic_t *enp,
1009 __out uint32_t *list,
1010 __out size_t *length);
1012 extern __checkReturn efx_rc_t
1013 ef10_filter_reconfigure(
1014 __in efx_nic_t *enp,
1015 __in_ecount(6) uint8_t const *mac_addr,
1016 __in boolean_t all_unicst,
1017 __in boolean_t mulcst,
1018 __in boolean_t all_mulcst,
1019 __in boolean_t brdcst,
1020 __in_ecount(6*count) uint8_t const *addrs,
1024 ef10_filter_get_default_rxq(
1025 __in efx_nic_t *enp,
1026 __out efx_rxq_t **erpp,
1027 __out boolean_t *using_rss);
1030 ef10_filter_default_rxq_set(
1031 __in efx_nic_t *enp,
1032 __in efx_rxq_t *erp,
1033 __in boolean_t using_rss);
1036 ef10_filter_default_rxq_clear(
1037 __in efx_nic_t *enp);
1040 #endif /* EFSYS_OPT_FILTER */
1042 extern __checkReturn efx_rc_t
1043 efx_mcdi_get_function_info(
1044 __in efx_nic_t *enp,
1045 __out uint32_t *pfp,
1046 __out_opt uint32_t *vfp);
1048 extern __checkReturn efx_rc_t
1049 efx_mcdi_privilege_mask(
1050 __in efx_nic_t *enp,
1053 __out uint32_t *maskp);
1059 #endif /* _SYS_HUNT_IMPL_H */