2 * Copyright (c) 2012-2015 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
39 #if EFSYS_OPT_HUNTINGTON
41 #include "ef10_tlv_layout.h"
43 static __checkReturn efx_rc_t
44 efx_mcdi_get_port_assignment(
46 __out uint32_t *portp)
49 uint8_t payload[MAX(MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN,
50 MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN)];
53 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
54 enp->en_family == EFX_FAMILY_MEDFORD);
56 (void) memset(payload, 0, sizeof (payload));
57 req.emr_cmd = MC_CMD_GET_PORT_ASSIGNMENT;
58 req.emr_in_buf = payload;
59 req.emr_in_length = MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN;
60 req.emr_out_buf = payload;
61 req.emr_out_length = MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN;
63 efx_mcdi_execute(enp, &req);
65 if (req.emr_rc != 0) {
70 if (req.emr_out_length_used < MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN) {
75 *portp = MCDI_OUT_DWORD(req, GET_PORT_ASSIGNMENT_OUT_PORT);
82 EFSYS_PROBE1(fail1, efx_rc_t, rc);
87 static __checkReturn efx_rc_t
88 efx_mcdi_get_port_modes(
90 __out uint32_t *modesp)
93 uint8_t payload[MAX(MC_CMD_GET_PORT_MODES_IN_LEN,
94 MC_CMD_GET_PORT_MODES_OUT_LEN)];
97 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
98 enp->en_family == EFX_FAMILY_MEDFORD);
100 (void) memset(payload, 0, sizeof (payload));
101 req.emr_cmd = MC_CMD_GET_PORT_MODES;
102 req.emr_in_buf = payload;
103 req.emr_in_length = MC_CMD_GET_PORT_MODES_IN_LEN;
104 req.emr_out_buf = payload;
105 req.emr_out_length = MC_CMD_GET_PORT_MODES_OUT_LEN;
107 efx_mcdi_execute(enp, &req);
109 if (req.emr_rc != 0) {
114 /* Accept pre-Medford size (8 bytes - no CurrentMode field) */
115 if (req.emr_out_length_used <
116 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST) {
121 *modesp = MCDI_OUT_DWORD(req, GET_PORT_MODES_OUT_MODES);
128 EFSYS_PROBE1(fail1, efx_rc_t, rc);
134 static __checkReturn efx_rc_t
135 efx_mcdi_vadaptor_alloc(
137 __in uint32_t port_id)
140 uint8_t payload[MAX(MC_CMD_VADAPTOR_ALLOC_IN_LEN,
141 MC_CMD_VADAPTOR_ALLOC_OUT_LEN)];
144 EFSYS_ASSERT3U(enp->en_vport_id, ==, EVB_PORT_ID_NULL);
146 (void) memset(payload, 0, sizeof (payload));
147 req.emr_cmd = MC_CMD_VADAPTOR_ALLOC;
148 req.emr_in_buf = payload;
149 req.emr_in_length = MC_CMD_VADAPTOR_ALLOC_IN_LEN;
150 req.emr_out_buf = payload;
151 req.emr_out_length = MC_CMD_VADAPTOR_ALLOC_OUT_LEN;
153 MCDI_IN_SET_DWORD(req, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
154 MCDI_IN_POPULATE_DWORD_1(req, VADAPTOR_ALLOC_IN_FLAGS,
155 VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED,
156 enp->en_nic_cfg.enc_allow_set_mac_with_installed_filters ? 1 : 0);
158 efx_mcdi_execute(enp, &req);
160 if (req.emr_rc != 0) {
168 EFSYS_PROBE1(fail1, efx_rc_t, rc);
173 static __checkReturn efx_rc_t
174 efx_mcdi_vadaptor_free(
176 __in uint32_t port_id)
179 uint8_t payload[MAX(MC_CMD_VADAPTOR_FREE_IN_LEN,
180 MC_CMD_VADAPTOR_FREE_OUT_LEN)];
183 (void) memset(payload, 0, sizeof (payload));
184 req.emr_cmd = MC_CMD_VADAPTOR_FREE;
185 req.emr_in_buf = payload;
186 req.emr_in_length = MC_CMD_VADAPTOR_FREE_IN_LEN;
187 req.emr_out_buf = payload;
188 req.emr_out_length = MC_CMD_VADAPTOR_FREE_OUT_LEN;
190 MCDI_IN_SET_DWORD(req, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
192 efx_mcdi_execute(enp, &req);
194 if (req.emr_rc != 0) {
202 EFSYS_PROBE1(fail1, efx_rc_t, rc);
207 static __checkReturn efx_rc_t
208 efx_mcdi_get_mac_address_pf(
210 __out_ecount_opt(6) uint8_t mac_addrp[6])
213 uint8_t payload[MAX(MC_CMD_GET_MAC_ADDRESSES_IN_LEN,
214 MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)];
217 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
218 enp->en_family == EFX_FAMILY_MEDFORD);
220 (void) memset(payload, 0, sizeof (payload));
221 req.emr_cmd = MC_CMD_GET_MAC_ADDRESSES;
222 req.emr_in_buf = payload;
223 req.emr_in_length = MC_CMD_GET_MAC_ADDRESSES_IN_LEN;
224 req.emr_out_buf = payload;
225 req.emr_out_length = MC_CMD_GET_MAC_ADDRESSES_OUT_LEN;
227 efx_mcdi_execute(enp, &req);
229 if (req.emr_rc != 0) {
234 if (req.emr_out_length_used < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) {
239 if (MCDI_OUT_DWORD(req, GET_MAC_ADDRESSES_OUT_MAC_COUNT) < 1) {
244 if (mac_addrp != NULL) {
247 addrp = MCDI_OUT2(req, uint8_t,
248 GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE);
250 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
260 EFSYS_PROBE1(fail1, efx_rc_t, rc);
265 static __checkReturn efx_rc_t
266 efx_mcdi_get_mac_address_vf(
268 __out_ecount_opt(6) uint8_t mac_addrp[6])
271 uint8_t payload[MAX(MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN,
272 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX)];
275 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
276 enp->en_family == EFX_FAMILY_MEDFORD);
278 (void) memset(payload, 0, sizeof (payload));
279 req.emr_cmd = MC_CMD_VPORT_GET_MAC_ADDRESSES;
280 req.emr_in_buf = payload;
281 req.emr_in_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN;
282 req.emr_out_buf = payload;
283 req.emr_out_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX;
285 MCDI_IN_SET_DWORD(req, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
286 EVB_PORT_ID_ASSIGNED);
288 efx_mcdi_execute(enp, &req);
290 if (req.emr_rc != 0) {
295 if (req.emr_out_length_used <
296 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN) {
301 if (MCDI_OUT_DWORD(req,
302 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT) < 1) {
307 if (mac_addrp != NULL) {
310 addrp = MCDI_OUT2(req, uint8_t,
311 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR);
313 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
323 EFSYS_PROBE1(fail1, efx_rc_t, rc);
328 static __checkReturn efx_rc_t
331 __out uint32_t *sys_freqp)
334 uint8_t payload[MAX(MC_CMD_GET_CLOCK_IN_LEN,
335 MC_CMD_GET_CLOCK_OUT_LEN)];
338 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
339 enp->en_family == EFX_FAMILY_MEDFORD);
341 (void) memset(payload, 0, sizeof (payload));
342 req.emr_cmd = MC_CMD_GET_CLOCK;
343 req.emr_in_buf = payload;
344 req.emr_in_length = MC_CMD_GET_CLOCK_IN_LEN;
345 req.emr_out_buf = payload;
346 req.emr_out_length = MC_CMD_GET_CLOCK_OUT_LEN;
348 efx_mcdi_execute(enp, &req);
350 if (req.emr_rc != 0) {
355 if (req.emr_out_length_used < MC_CMD_GET_CLOCK_OUT_LEN) {
360 *sys_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_SYS_FREQ);
361 if (*sys_freqp == 0) {
373 EFSYS_PROBE1(fail1, efx_rc_t, rc);
378 static __checkReturn efx_rc_t
379 efx_mcdi_get_vector_cfg(
381 __out_opt uint32_t *vec_basep,
382 __out_opt uint32_t *pf_nvecp,
383 __out_opt uint32_t *vf_nvecp)
386 uint8_t payload[MAX(MC_CMD_GET_VECTOR_CFG_IN_LEN,
387 MC_CMD_GET_VECTOR_CFG_OUT_LEN)];
390 (void) memset(payload, 0, sizeof (payload));
391 req.emr_cmd = MC_CMD_GET_VECTOR_CFG;
392 req.emr_in_buf = payload;
393 req.emr_in_length = MC_CMD_GET_VECTOR_CFG_IN_LEN;
394 req.emr_out_buf = payload;
395 req.emr_out_length = MC_CMD_GET_VECTOR_CFG_OUT_LEN;
397 efx_mcdi_execute(enp, &req);
399 if (req.emr_rc != 0) {
404 if (req.emr_out_length_used < MC_CMD_GET_VECTOR_CFG_OUT_LEN) {
409 if (vec_basep != NULL)
410 *vec_basep = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VEC_BASE);
411 if (pf_nvecp != NULL)
412 *pf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_PF);
413 if (vf_nvecp != NULL)
414 *vf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_VF);
421 EFSYS_PROBE1(fail1, efx_rc_t, rc);
426 static __checkReturn efx_rc_t
427 efx_mcdi_get_capabilities(
429 __out efx_dword_t *flagsp)
432 uint8_t payload[MAX(MC_CMD_GET_CAPABILITIES_IN_LEN,
433 MC_CMD_GET_CAPABILITIES_OUT_LEN)];
436 (void) memset(payload, 0, sizeof (payload));
437 req.emr_cmd = MC_CMD_GET_CAPABILITIES;
438 req.emr_in_buf = payload;
439 req.emr_in_length = MC_CMD_GET_CAPABILITIES_IN_LEN;
440 req.emr_out_buf = payload;
441 req.emr_out_length = MC_CMD_GET_CAPABILITIES_OUT_LEN;
443 efx_mcdi_execute(enp, &req);
445 if (req.emr_rc != 0) {
450 if (req.emr_out_length_used < MC_CMD_GET_CAPABILITIES_OUT_LEN) {
455 *flagsp = *MCDI_OUT2(req, efx_dword_t, GET_CAPABILITIES_OUT_FLAGS1);
462 EFSYS_PROBE1(fail1, efx_rc_t, rc);
468 static __checkReturn efx_rc_t
471 __in uint32_t min_vi_count,
472 __in uint32_t max_vi_count,
473 __out_opt uint32_t *vi_basep,
474 __out uint32_t *vi_countp)
478 uint8_t payload[MAX(MC_CMD_ALLOC_VIS_IN_LEN,
479 MC_CMD_ALLOC_VIS_OUT_LEN)];
482 if (vi_countp == NULL) {
487 (void) memset(payload, 0, sizeof (payload));
488 req.emr_cmd = MC_CMD_ALLOC_VIS;
489 req.emr_in_buf = payload;
490 req.emr_in_length = MC_CMD_ALLOC_VIS_IN_LEN;
491 req.emr_out_buf = payload;
492 req.emr_out_length = MC_CMD_ALLOC_VIS_OUT_LEN;
494 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MIN_VI_COUNT, min_vi_count);
495 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MAX_VI_COUNT, max_vi_count);
497 efx_mcdi_execute(enp, &req);
499 if (req.emr_rc != 0) {
504 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_OUT_LEN) {
509 if (vi_basep != NULL)
510 *vi_basep = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_BASE);
512 if (vi_countp != NULL)
513 *vi_countp = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_COUNT);
522 EFSYS_PROBE1(fail1, efx_rc_t, rc);
528 static __checkReturn efx_rc_t
535 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_IN_LEN == 0);
536 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_OUT_LEN == 0);
538 req.emr_cmd = MC_CMD_FREE_VIS;
539 req.emr_in_buf = NULL;
540 req.emr_in_length = 0;
541 req.emr_out_buf = NULL;
542 req.emr_out_length = 0;
544 efx_mcdi_execute_quiet(enp, &req);
546 /* Ignore ELREADY (no allocated VIs, so nothing to free) */
547 if ((req.emr_rc != 0) && (req.emr_rc != EALREADY)) {
555 EFSYS_PROBE1(fail1, efx_rc_t, rc);
561 static __checkReturn efx_rc_t
562 efx_mcdi_alloc_piobuf(
564 __out efx_piobuf_handle_t *handlep)
567 uint8_t payload[MAX(MC_CMD_ALLOC_PIOBUF_IN_LEN,
568 MC_CMD_ALLOC_PIOBUF_OUT_LEN)];
571 if (handlep == NULL) {
576 (void) memset(payload, 0, sizeof (payload));
577 req.emr_cmd = MC_CMD_ALLOC_PIOBUF;
578 req.emr_in_buf = payload;
579 req.emr_in_length = MC_CMD_ALLOC_PIOBUF_IN_LEN;
580 req.emr_out_buf = payload;
581 req.emr_out_length = MC_CMD_ALLOC_PIOBUF_OUT_LEN;
583 efx_mcdi_execute_quiet(enp, &req);
585 if (req.emr_rc != 0) {
590 if (req.emr_out_length_used < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
595 *handlep = MCDI_OUT_DWORD(req, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
604 EFSYS_PROBE1(fail1, efx_rc_t, rc);
609 static __checkReturn efx_rc_t
610 efx_mcdi_free_piobuf(
612 __in efx_piobuf_handle_t handle)
615 uint8_t payload[MAX(MC_CMD_FREE_PIOBUF_IN_LEN,
616 MC_CMD_FREE_PIOBUF_OUT_LEN)];
619 (void) memset(payload, 0, sizeof (payload));
620 req.emr_cmd = MC_CMD_FREE_PIOBUF;
621 req.emr_in_buf = payload;
622 req.emr_in_length = MC_CMD_FREE_PIOBUF_IN_LEN;
623 req.emr_out_buf = payload;
624 req.emr_out_length = MC_CMD_FREE_PIOBUF_OUT_LEN;
626 MCDI_IN_SET_DWORD(req, FREE_PIOBUF_IN_PIOBUF_HANDLE, handle);
628 efx_mcdi_execute_quiet(enp, &req);
630 if (req.emr_rc != 0) {
638 EFSYS_PROBE1(fail1, efx_rc_t, rc);
643 static __checkReturn efx_rc_t
644 efx_mcdi_link_piobuf(
646 __in uint32_t vi_index,
647 __in efx_piobuf_handle_t handle)
650 uint8_t payload[MAX(MC_CMD_LINK_PIOBUF_IN_LEN,
651 MC_CMD_LINK_PIOBUF_OUT_LEN)];
654 (void) memset(payload, 0, sizeof (payload));
655 req.emr_cmd = MC_CMD_LINK_PIOBUF;
656 req.emr_in_buf = payload;
657 req.emr_in_length = MC_CMD_LINK_PIOBUF_IN_LEN;
658 req.emr_out_buf = payload;
659 req.emr_out_length = MC_CMD_LINK_PIOBUF_OUT_LEN;
661 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_PIOBUF_HANDLE, handle);
662 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
664 efx_mcdi_execute(enp, &req);
666 if (req.emr_rc != 0) {
674 EFSYS_PROBE1(fail1, efx_rc_t, rc);
679 static __checkReturn efx_rc_t
680 efx_mcdi_unlink_piobuf(
682 __in uint32_t vi_index)
685 uint8_t payload[MAX(MC_CMD_UNLINK_PIOBUF_IN_LEN,
686 MC_CMD_UNLINK_PIOBUF_OUT_LEN)];
689 (void) memset(payload, 0, sizeof (payload));
690 req.emr_cmd = MC_CMD_UNLINK_PIOBUF;
691 req.emr_in_buf = payload;
692 req.emr_in_length = MC_CMD_UNLINK_PIOBUF_IN_LEN;
693 req.emr_out_buf = payload;
694 req.emr_out_length = MC_CMD_UNLINK_PIOBUF_OUT_LEN;
696 MCDI_IN_SET_DWORD(req, UNLINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
698 efx_mcdi_execute(enp, &req);
700 if (req.emr_rc != 0) {
708 EFSYS_PROBE1(fail1, efx_rc_t, rc);
714 ef10_nic_alloc_piobufs(
716 __in uint32_t max_piobuf_count)
718 efx_piobuf_handle_t *handlep;
722 EFSYS_ASSERT3U(max_piobuf_count, <=,
723 EFX_ARRAY_SIZE(enp->en_arch.ef10.ena_piobuf_handle));
725 enp->en_arch.ef10.ena_piobuf_count = 0;
727 for (i = 0; i < max_piobuf_count; i++) {
728 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
730 if ((rc = efx_mcdi_alloc_piobuf(enp, handlep)) != 0)
733 enp->en_arch.ef10.ena_pio_alloc_map[i] = 0;
734 enp->en_arch.ef10.ena_piobuf_count++;
740 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
741 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
743 efx_mcdi_free_piobuf(enp, *handlep);
744 *handlep = EFX_PIOBUF_HANDLE_INVALID;
746 enp->en_arch.ef10.ena_piobuf_count = 0;
751 ef10_nic_free_piobufs(
754 efx_piobuf_handle_t *handlep;
757 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
758 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
760 efx_mcdi_free_piobuf(enp, *handlep);
761 *handlep = EFX_PIOBUF_HANDLE_INVALID;
763 enp->en_arch.ef10.ena_piobuf_count = 0;
766 /* Sub-allocate a block from a piobuf */
767 __checkReturn efx_rc_t
769 __inout efx_nic_t *enp,
770 __out uint32_t *bufnump,
771 __out efx_piobuf_handle_t *handlep,
772 __out uint32_t *blknump,
773 __out uint32_t *offsetp,
776 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
777 efx_drv_cfg_t *edcp = &enp->en_drv_cfg;
778 uint32_t blk_per_buf;
782 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
783 enp->en_family == EFX_FAMILY_MEDFORD);
784 EFSYS_ASSERT(bufnump);
785 EFSYS_ASSERT(handlep);
786 EFSYS_ASSERT(blknump);
787 EFSYS_ASSERT(offsetp);
790 if ((edcp->edc_pio_alloc_size == 0) ||
791 (enp->en_arch.ef10.ena_piobuf_count == 0)) {
795 blk_per_buf = encp->enc_piobuf_size / edcp->edc_pio_alloc_size;
797 for (buf = 0; buf < enp->en_arch.ef10.ena_piobuf_count; buf++) {
798 uint32_t *map = &enp->en_arch.ef10.ena_pio_alloc_map[buf];
803 EFSYS_ASSERT3U(blk_per_buf, <=, (8 * sizeof (*map)));
804 for (blk = 0; blk < blk_per_buf; blk++) {
805 if ((*map & (1u << blk)) == 0) {
815 *handlep = enp->en_arch.ef10.ena_piobuf_handle[buf];
818 *sizep = edcp->edc_pio_alloc_size;
819 *offsetp = blk * (*sizep);
826 EFSYS_PROBE1(fail1, efx_rc_t, rc);
831 /* Free a piobuf sub-allocated block */
832 __checkReturn efx_rc_t
834 __inout efx_nic_t *enp,
835 __in uint32_t bufnum,
836 __in uint32_t blknum)
841 if ((bufnum >= enp->en_arch.ef10.ena_piobuf_count) ||
842 (blknum >= (8 * sizeof (*map)))) {
847 map = &enp->en_arch.ef10.ena_pio_alloc_map[bufnum];
848 if ((*map & (1u << blknum)) == 0) {
852 *map &= ~(1u << blknum);
859 EFSYS_PROBE1(fail1, efx_rc_t, rc);
864 __checkReturn efx_rc_t
866 __inout efx_nic_t *enp,
867 __in uint32_t vi_index,
868 __in efx_piobuf_handle_t handle)
870 return (efx_mcdi_link_piobuf(enp, vi_index, handle));
873 __checkReturn efx_rc_t
875 __inout efx_nic_t *enp,
876 __in uint32_t vi_index)
878 return (efx_mcdi_unlink_piobuf(enp, vi_index));
881 static __checkReturn efx_rc_t
882 ef10_get_datapath_caps(
885 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
886 efx_dword_t datapath_capabilities;
889 if ((rc = efx_mcdi_get_capabilities(enp, &datapath_capabilities)) != 0)
893 * Huntington RXDP firmware inserts a 0 or 14 byte prefix.
894 * We only support the 14 byte prefix here.
896 if (MCDI_CMD_DWORD_FIELD(&datapath_capabilities,
897 GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14) != 1) {
901 encp->enc_rx_prefix_size = 14;
903 /* Check if the firmware supports TSO */
904 if (MCDI_CMD_DWORD_FIELD(&datapath_capabilities,
905 GET_CAPABILITIES_OUT_TX_TSO) == 1)
906 encp->enc_fw_assisted_tso_enabled = B_TRUE;
908 encp->enc_fw_assisted_tso_enabled = B_FALSE;
910 /* Check if the firmware has vadapter/vport/vswitch support */
911 if (MCDI_CMD_DWORD_FIELD(&datapath_capabilities,
912 GET_CAPABILITIES_OUT_EVB) == 1)
913 encp->enc_datapath_cap_evb = B_TRUE;
915 encp->enc_datapath_cap_evb = B_FALSE;
917 /* Check if the firmware supports VLAN insertion */
918 if (MCDI_CMD_DWORD_FIELD(&datapath_capabilities,
919 GET_CAPABILITIES_OUT_TX_VLAN_INSERTION) == 1)
920 encp->enc_hw_tx_insert_vlan_enabled = B_TRUE;
922 encp->enc_hw_tx_insert_vlan_enabled = B_FALSE;
924 /* Check if the firmware supports RX event batching */
925 if (MCDI_CMD_DWORD_FIELD(&datapath_capabilities,
926 GET_CAPABILITIES_OUT_RX_BATCHING) == 1) {
927 encp->enc_rx_batching_enabled = B_TRUE;
928 encp->enc_rx_batch_max = 16;
930 encp->enc_rx_batching_enabled = B_FALSE;
933 /* Check if the firmware supports disabling scatter on RXQs */
934 if (MCDI_CMD_DWORD_FIELD(&datapath_capabilities,
935 GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER) == 1) {
936 encp->enc_rx_disable_scatter_supported = B_TRUE;
938 encp->enc_rx_disable_scatter_supported = B_FALSE;
941 /* Check if the firmware supports set mac with running filters */
942 if (MCDI_CMD_DWORD_FIELD(&datapath_capabilities,
943 GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED)
945 encp->enc_allow_set_mac_with_installed_filters = B_TRUE;
947 encp->enc_allow_set_mac_with_installed_filters = B_FALSE;
955 EFSYS_PROBE1(fail1, efx_rc_t, rc);
961 * The external port mapping is a one-based numbering of the external
962 * connectors on the board. It does not distinguish off-board separated
963 * outputs such as multi-headed cables.
964 * The number of ports that map to each external port connector
965 * on the board is determined by the chip family and the port modes to
966 * which the NIC can be configured. The mapping table lists modes with
967 * port numbering requirements in increasing order.
973 } __ef10_external_port_mappings[] = {
974 /* Supported modes requiring 1 output per port */
976 EFX_FAMILY_HUNTINGTON,
977 (1 << TLV_PORT_MODE_10G) |
978 (1 << TLV_PORT_MODE_10G_10G) |
979 (1 << TLV_PORT_MODE_10G_10G_10G_10G),
982 /* Supported modes requiring 2 outputs per port */
984 EFX_FAMILY_HUNTINGTON,
985 (1 << TLV_PORT_MODE_40G) |
986 (1 << TLV_PORT_MODE_40G_40G) |
987 (1 << TLV_PORT_MODE_40G_10G_10G) |
988 (1 << TLV_PORT_MODE_10G_10G_40G),
992 * NOTE: Medford modes will require 4 outputs per port:
993 * TLV_PORT_MODE_10G_10G_10G_10G_Q
994 * TLV_PORT_MODE_10G_10G_10G_10G_Q2
995 * The Q2 mode routes outputs to external port 2. Support for this
996 * will require a new field specifying the number to add after
997 * scaling by stride. This is fixed at 1 currently.
1001 static __checkReturn efx_rc_t
1002 ef10_external_port_mapping(
1003 __in efx_nic_t *enp,
1005 __out uint8_t *external_portp)
1009 uint32_t port_modes;
1011 uint32_t stride = 1; /* default 1-1 mapping */
1013 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes)) != 0) {
1014 /* No port mode information available - use default mapping */
1019 * Infer the internal port -> external port mapping from
1020 * the possible port modes for this NIC.
1022 for (i = 0; i < EFX_ARRAY_SIZE(__ef10_external_port_mappings); ++i) {
1023 if (__ef10_external_port_mappings[i].family !=
1026 matches = (__ef10_external_port_mappings[i].modes_mask &
1029 stride = __ef10_external_port_mappings[i].stride;
1030 port_modes &= ~matches;
1034 if (port_modes != 0) {
1035 /* Some advertised modes are not supported */
1042 * Scale as required by last matched mode and then convert to
1043 * one-based numbering
1045 *external_portp = (uint8_t)(port / stride) + 1;
1049 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1054 static __checkReturn efx_rc_t
1056 __in efx_nic_t *enp)
1058 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
1059 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1060 uint8_t mac_addr[6];
1061 uint32_t board_type = 0;
1062 hunt_link_state_t hls;
1063 efx_port_t *epp = &(enp->en_port);
1070 uint32_t base, nvec;
1073 if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
1077 * NOTE: The MCDI protocol numbers ports from zero.
1078 * The common code MCDI interface numbers ports from one.
1080 emip->emi_port = port + 1;
1082 if ((rc = ef10_external_port_mapping(enp, port,
1083 &encp->enc_external_port)) != 0)
1087 * Get PCIe function number from firmware (used for
1088 * per-function privilege and dynamic config info).
1089 * - PCIe PF: pf = PF number, vf = 0xffff.
1090 * - PCIe VF: pf = parent PF, vf = VF number.
1092 if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
1098 /* MAC address for this function */
1099 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
1100 rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
1101 if ((rc == 0) && (mac_addr[0] & 0x02)) {
1103 * If the static config does not include a global MAC
1104 * address pool then the board may return a locally
1105 * administered MAC address (this should only happen on
1106 * incorrectly programmed boards).
1111 rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
1116 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
1118 /* Board configuration */
1119 rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
1121 /* Unprivileged functions may not be able to read board cfg */
1128 encp->enc_board_type = board_type;
1129 encp->enc_clk_mult = 1; /* not used for Huntington */
1131 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
1132 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
1135 /* Obtain the default PHY advertised capabilities */
1136 if ((rc = hunt_phy_get_link(enp, &hls)) != 0)
1138 epp->ep_default_adv_cap_mask = hls.hls_adv_cap_mask;
1139 epp->ep_adv_cap_mask = hls.hls_adv_cap_mask;
1142 * Enable firmware workarounds for hardware errata.
1143 * Expected responses are:
1145 * Success: workaround enabled or disabled as requested.
1146 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
1147 * Firmware does not support the MC_CMD_WORKAROUND request.
1148 * (assume that the workaround is not supported).
1149 * - MC_CMD_ERR_ENOENT (reported as ENOENT):
1150 * Firmware does not support the requested workaround.
1151 * - MC_CMD_ERR_EPERM (reported as EACCES):
1152 * Unprivileged function cannot enable/disable workarounds.
1154 * See efx_mcdi_request_errcode() for MCDI error translations.
1158 * If the bug35388 workaround is enabled, then use an indirect access
1159 * method to avoid unsafe EVQ writes.
1161 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG35388, B_TRUE,
1163 if ((rc == 0) || (rc == EACCES))
1164 encp->enc_bug35388_workaround = B_TRUE;
1165 else if ((rc == ENOTSUP) || (rc == ENOENT))
1166 encp->enc_bug35388_workaround = B_FALSE;
1171 * If the bug41750 workaround is enabled, then do not test interrupts,
1172 * as the test will fail (seen with Greenport controllers).
1174 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG41750, B_TRUE,
1177 encp->enc_bug41750_workaround = B_TRUE;
1178 } else if (rc == EACCES) {
1179 /* Assume a controller with 40G ports needs the workaround. */
1180 if (epp->ep_default_adv_cap_mask & EFX_PHY_CAP_40000FDX)
1181 encp->enc_bug41750_workaround = B_TRUE;
1183 encp->enc_bug41750_workaround = B_FALSE;
1184 } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
1185 encp->enc_bug41750_workaround = B_FALSE;
1189 if (EFX_PCI_FUNCTION_IS_VF(encp)) {
1190 /* Interrupt testing does not work for VFs. See bug50084. */
1191 encp->enc_bug41750_workaround = B_TRUE;
1195 * If the bug26807 workaround is enabled, then firmware has enabled
1196 * support for chained multicast filters. Firmware will reset (FLR)
1197 * functions which have filters in the hardware filter table when the
1198 * workaround is enabled/disabled.
1200 * We must recheck if the workaround is enabled after inserting the
1201 * first hardware filter, in case it has been changed since this check.
1203 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG26807,
1206 encp->enc_bug26807_workaround = B_TRUE;
1207 if (flags & (1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN)) {
1209 * Other functions had installed filters before the
1210 * workaround was enabled, and they have been reset
1213 EFSYS_PROBE(bug26807_workaround_flr_done);
1214 /* FIXME: bump MC warm boot count ? */
1216 } else if (rc == EACCES) {
1218 * Unprivileged functions cannot enable the workaround in older
1221 encp->enc_bug26807_workaround = B_FALSE;
1222 } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
1223 encp->enc_bug26807_workaround = B_FALSE;
1228 /* Get sysclk frequency (in MHz). */
1229 if ((rc = efx_mcdi_get_clock(enp, &sysclk)) != 0)
1233 * The timer quantum is 1536 sysclk cycles, documented for the
1234 * EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
1236 encp->enc_evq_timer_quantum_ns = 1536000UL / sysclk; /* 1536 cycles */
1237 if (encp->enc_bug35388_workaround) {
1238 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
1239 ERF_DD_EVQ_IND_TIMER_VAL_WIDTH) / 1000;
1241 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
1242 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
1245 /* Check capabilities of running datapath firmware */
1246 if ((rc = ef10_get_datapath_caps(enp)) != 0)
1249 /* Alignment for receive packet DMA buffers */
1250 encp->enc_rx_buf_align_start = 1;
1251 encp->enc_rx_buf_align_end = 64; /* RX DMA end padding */
1253 /* Alignment for WPTR updates */
1254 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
1257 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
1258 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
1259 * resources (allocated to this PCIe function), which is zero until
1260 * after we have allocated VIs.
1262 encp->enc_evq_limit = 1024;
1263 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
1264 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
1266 encp->enc_buftbl_limit = 0xFFFFFFFF;
1268 encp->enc_piobuf_limit = HUNT_PIOBUF_NBUFS;
1269 encp->enc_piobuf_size = HUNT_PIOBUF_SIZE;
1270 encp->enc_piobuf_min_alloc_size = HUNT_MIN_PIO_ALLOC_SIZE;
1273 * Get the current privilege mask. Note that this may be modified
1274 * dynamically, so this value is informational only. DO NOT use
1275 * the privilege mask to check for sufficient privileges, as that
1276 * can result in time-of-check/time-of-use bugs.
1278 if ((rc = efx_mcdi_privilege_mask(enp, pf, vf, &mask)) != 0) {
1282 /* Fallback for old firmware without privilege mask support */
1283 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
1284 /* Assume PF has admin privilege */
1285 mask = HUNT_LEGACY_PF_PRIVILEGE_MASK;
1287 /* VF is always unprivileged by default */
1288 mask = HUNT_LEGACY_VF_PRIVILEGE_MASK;
1292 encp->enc_privilege_mask = mask;
1294 /* Get interrupt vector limits */
1295 if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
1296 if (EFX_PCI_FUNCTION_IS_PF(encp))
1299 /* Ignore error (cannot query vector limits from a VF). */
1303 encp->enc_intr_vec_base = base;
1304 encp->enc_intr_limit = nvec;
1307 * Maximum number of bytes into the frame the TCP header can start for
1308 * firmware assisted TSO to work.
1310 encp->enc_tx_tso_tcp_header_offset_limit = 208;
1315 EFSYS_PROBE(fail14);
1317 EFSYS_PROBE(fail13);
1319 EFSYS_PROBE(fail12);
1321 EFSYS_PROBE(fail11);
1323 EFSYS_PROBE(fail10);
1341 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1347 __checkReturn efx_rc_t
1349 __in efx_nic_t *enp)
1351 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1352 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1355 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1356 enp->en_family == EFX_FAMILY_MEDFORD);
1358 /* Read and clear any assertion state */
1359 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
1362 /* Exit the assertion handler */
1363 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
1367 if ((rc = efx_mcdi_drv_attach(enp, B_TRUE)) != 0)
1370 if ((rc = hunt_board_cfg(enp)) != 0)
1375 * Set default driver config limits (based on board config).
1377 * FIXME: For now allocate a fixed number of VIs which is likely to be
1378 * sufficient and small enough to allow multiple functions on the same
1381 edcp->edc_min_vi_count = edcp->edc_max_vi_count =
1382 MIN(128, MAX(encp->enc_rxq_limit, encp->enc_txq_limit));
1384 /* The client driver must configure and enable PIO buffer support */
1385 edcp->edc_max_piobuf_count = 0;
1386 edcp->edc_pio_alloc_size = 0;
1388 #if EFSYS_OPT_MAC_STATS
1389 /* Wipe the MAC statistics */
1390 if ((rc = efx_mcdi_mac_stats_clear(enp)) != 0)
1394 #if EFSYS_OPT_LOOPBACK
1395 if ((rc = efx_mcdi_get_loopback_modes(enp)) != 0)
1399 #if EFSYS_OPT_MON_STATS
1400 if ((rc = mcdi_mon_cfg_build(enp)) != 0) {
1401 /* Unprivileged functions do not have access to sensors */
1407 encp->enc_features = enp->en_features;
1411 #if EFSYS_OPT_MON_STATS
1415 #if EFSYS_OPT_LOOPBACK
1419 #if EFSYS_OPT_MAC_STATS
1430 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1435 __checkReturn efx_rc_t
1436 ef10_nic_set_drv_limits(
1437 __inout efx_nic_t *enp,
1438 __in efx_drv_limits_t *edlp)
1440 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1441 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1442 uint32_t min_evq_count, max_evq_count;
1443 uint32_t min_rxq_count, max_rxq_count;
1444 uint32_t min_txq_count, max_txq_count;
1452 /* Get minimum required and maximum usable VI limits */
1453 min_evq_count = MIN(edlp->edl_min_evq_count, encp->enc_evq_limit);
1454 min_rxq_count = MIN(edlp->edl_min_rxq_count, encp->enc_rxq_limit);
1455 min_txq_count = MIN(edlp->edl_min_txq_count, encp->enc_txq_limit);
1457 edcp->edc_min_vi_count =
1458 MAX(min_evq_count, MAX(min_rxq_count, min_txq_count));
1460 max_evq_count = MIN(edlp->edl_max_evq_count, encp->enc_evq_limit);
1461 max_rxq_count = MIN(edlp->edl_max_rxq_count, encp->enc_rxq_limit);
1462 max_txq_count = MIN(edlp->edl_max_txq_count, encp->enc_txq_limit);
1464 edcp->edc_max_vi_count =
1465 MAX(max_evq_count, MAX(max_rxq_count, max_txq_count));
1468 * Check limits for sub-allocated piobuf blocks.
1469 * PIO is optional, so don't fail if the limits are incorrect.
1471 if ((encp->enc_piobuf_size == 0) ||
1472 (encp->enc_piobuf_limit == 0) ||
1473 (edlp->edl_min_pio_alloc_size == 0) ||
1474 (edlp->edl_min_pio_alloc_size > encp->enc_piobuf_size)) {
1476 edcp->edc_max_piobuf_count = 0;
1477 edcp->edc_pio_alloc_size = 0;
1479 uint32_t blk_size, blk_count, blks_per_piobuf;
1482 MAX(edlp->edl_min_pio_alloc_size,
1483 encp->enc_piobuf_min_alloc_size);
1485 blks_per_piobuf = encp->enc_piobuf_size / blk_size;
1486 EFSYS_ASSERT3U(blks_per_piobuf, <=, 32);
1488 blk_count = (encp->enc_piobuf_limit * blks_per_piobuf);
1490 /* A zero max pio alloc count means unlimited */
1491 if ((edlp->edl_max_pio_alloc_count > 0) &&
1492 (edlp->edl_max_pio_alloc_count < blk_count)) {
1493 blk_count = edlp->edl_max_pio_alloc_count;
1496 edcp->edc_pio_alloc_size = blk_size;
1497 edcp->edc_max_piobuf_count =
1498 (blk_count + (blks_per_piobuf - 1)) / blks_per_piobuf;
1504 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1510 __checkReturn efx_rc_t
1512 __in efx_nic_t *enp)
1515 uint8_t payload[MAX(MC_CMD_ENTITY_RESET_IN_LEN,
1516 MC_CMD_ENTITY_RESET_OUT_LEN)];
1519 /* ef10_nic_reset() is called to recover from BADASSERT failures. */
1520 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
1522 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
1525 (void) memset(payload, 0, sizeof (payload));
1526 req.emr_cmd = MC_CMD_ENTITY_RESET;
1527 req.emr_in_buf = payload;
1528 req.emr_in_length = MC_CMD_ENTITY_RESET_IN_LEN;
1529 req.emr_out_buf = payload;
1530 req.emr_out_length = MC_CMD_ENTITY_RESET_OUT_LEN;
1532 MCDI_IN_POPULATE_DWORD_1(req, ENTITY_RESET_IN_FLAG,
1533 ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET, 1);
1535 efx_mcdi_execute(enp, &req);
1537 if (req.emr_rc != 0) {
1542 /* Clear RX/TX DMA queue errors */
1543 enp->en_reset_flags &= ~(EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR);
1552 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1557 __checkReturn efx_rc_t
1559 __in efx_nic_t *enp)
1561 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1562 uint32_t min_vi_count, max_vi_count;
1563 uint32_t vi_count, vi_base;
1569 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1570 enp->en_family == EFX_FAMILY_MEDFORD);
1572 /* Enable reporting of some events (e.g. link change) */
1573 if ((rc = efx_mcdi_log_ctrl(enp)) != 0)
1576 /* Allocate (optional) on-chip PIO buffers */
1577 ef10_nic_alloc_piobufs(enp, edcp->edc_max_piobuf_count);
1580 * For best performance, PIO writes should use a write-combined
1581 * (WC) memory mapping. Using a separate WC mapping for the PIO
1582 * aperture of each VI would be a burden to drivers (and not
1583 * possible if the host page size is >4Kbyte).
1585 * To avoid this we use a single uncached (UC) mapping for VI
1586 * register access, and a single WC mapping for extra VIs used
1589 * Each piobuf must be linked to a VI in the WC mapping, and to
1590 * each VI that is using a sub-allocated block from the piobuf.
1592 min_vi_count = edcp->edc_min_vi_count;
1594 edcp->edc_max_vi_count + enp->en_arch.ef10.ena_piobuf_count;
1596 /* Ensure that the previously attached driver's VIs are freed */
1597 if ((rc = efx_mcdi_free_vis(enp)) != 0)
1601 * Reserve VI resources (EVQ+RXQ+TXQ) for this PCIe function. If this
1602 * fails then retrying the request for fewer VI resources may succeed.
1605 if ((rc = efx_mcdi_alloc_vis(enp, min_vi_count, max_vi_count,
1606 &vi_base, &vi_count)) != 0)
1609 EFSYS_PROBE2(vi_alloc, uint32_t, vi_base, uint32_t, vi_count);
1611 if (vi_count < min_vi_count) {
1616 enp->en_arch.ef10.ena_vi_base = vi_base;
1617 enp->en_arch.ef10.ena_vi_count = vi_count;
1619 if (vi_count < min_vi_count + enp->en_arch.ef10.ena_piobuf_count) {
1620 /* Not enough extra VIs to map piobufs */
1621 ef10_nic_free_piobufs(enp);
1624 enp->en_arch.ef10.ena_pio_write_vi_base =
1625 vi_count - enp->en_arch.ef10.ena_piobuf_count;
1627 /* Save UC memory mapping details */
1628 enp->en_arch.ef10.ena_uc_mem_map_offset = 0;
1629 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
1630 enp->en_arch.ef10.ena_uc_mem_map_size =
1631 (ER_DZ_TX_PIOBUF_STEP *
1632 enp->en_arch.ef10.ena_pio_write_vi_base);
1634 enp->en_arch.ef10.ena_uc_mem_map_size =
1635 (ER_DZ_TX_PIOBUF_STEP *
1636 enp->en_arch.ef10.ena_vi_count);
1639 /* Save WC memory mapping details */
1640 enp->en_arch.ef10.ena_wc_mem_map_offset =
1641 enp->en_arch.ef10.ena_uc_mem_map_offset +
1642 enp->en_arch.ef10.ena_uc_mem_map_size;
1644 enp->en_arch.ef10.ena_wc_mem_map_size =
1645 (ER_DZ_TX_PIOBUF_STEP *
1646 enp->en_arch.ef10.ena_piobuf_count);
1648 /* Link piobufs to extra VIs in WC mapping */
1649 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
1650 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
1651 rc = efx_mcdi_link_piobuf(enp,
1652 enp->en_arch.ef10.ena_pio_write_vi_base + i,
1653 enp->en_arch.ef10.ena_piobuf_handle[i]);
1660 * Allocate a vAdaptor attached to our upstream vPort/pPort.
1662 * On a VF, this may fail with MC_CMD_ERR_NO_EVB_PORT (ENOENT) if the PF
1663 * driver has yet to bring up the EVB port. See bug 56147. In this case,
1664 * retry the request several times after waiting a while. The wait time
1665 * between retries starts small (10ms) and exponentially increases.
1666 * Total wait time is a little over two seconds. Retry logic in the
1667 * client driver may mean this whole loop is repeated if it continues to
1672 while ((rc = efx_mcdi_vadaptor_alloc(enp, EVB_PORT_ID_ASSIGNED)) != 0) {
1673 if (EFX_PCI_FUNCTION_IS_PF(&enp->en_nic_cfg) ||
1676 * Do not retry alloc for PF, or for other errors on
1682 /* VF startup before PF is ready. Retry allocation. */
1684 /* Too many attempts */
1688 EFSYS_PROBE1(mcdi_no_evb_port_retry, int, retry);
1689 EFSYS_SLEEP(delay_us);
1691 if (delay_us < 500000)
1695 enp->en_vport_id = EVB_PORT_ID_ASSIGNED;
1696 enp->en_nic_cfg.enc_mcdi_max_payload_length = MCDI_CTL_SDU_LEN_MAX_V2;
1711 ef10_nic_free_piobufs(enp);
1714 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1719 __checkReturn efx_rc_t
1720 ef10_nic_get_vi_pool(
1721 __in efx_nic_t *enp,
1722 __out uint32_t *vi_countp)
1724 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1725 enp->en_family == EFX_FAMILY_MEDFORD);
1728 * Report VIs that the client driver can use.
1729 * Do not include VIs used for PIO buffer writes.
1731 *vi_countp = enp->en_arch.ef10.ena_pio_write_vi_base;
1736 __checkReturn efx_rc_t
1737 ef10_nic_get_bar_region(
1738 __in efx_nic_t *enp,
1739 __in efx_nic_region_t region,
1740 __out uint32_t *offsetp,
1741 __out size_t *sizep)
1745 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1746 enp->en_family == EFX_FAMILY_MEDFORD);
1749 * TODO: Specify host memory mapping alignment and granularity
1750 * in efx_drv_limits_t so that they can be taken into account
1751 * when allocating extra VIs for PIO writes.
1755 /* UC mapped memory BAR region for VI registers */
1756 *offsetp = enp->en_arch.ef10.ena_uc_mem_map_offset;
1757 *sizep = enp->en_arch.ef10.ena_uc_mem_map_size;
1760 case EFX_REGION_PIO_WRITE_VI:
1761 /* WC mapped memory BAR region for piobuf writes */
1762 *offsetp = enp->en_arch.ef10.ena_wc_mem_map_offset;
1763 *sizep = enp->en_arch.ef10.ena_wc_mem_map_size;
1774 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1781 __in efx_nic_t *enp)
1786 (void) efx_mcdi_vadaptor_free(enp, enp->en_vport_id);
1787 enp->en_vport_id = 0;
1789 /* Unlink piobufs from extra VIs in WC mapping */
1790 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
1791 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
1792 rc = efx_mcdi_unlink_piobuf(enp,
1793 enp->en_arch.ef10.ena_pio_write_vi_base + i);
1799 ef10_nic_free_piobufs(enp);
1801 (void) efx_mcdi_free_vis(enp);
1802 enp->en_arch.ef10.ena_vi_count = 0;
1807 __in efx_nic_t *enp)
1809 #if EFSYS_OPT_MON_STATS
1810 mcdi_mon_cfg_free(enp);
1811 #endif /* EFSYS_OPT_MON_STATS */
1812 (void) efx_mcdi_drv_attach(enp, B_FALSE);
1817 __checkReturn efx_rc_t
1818 ef10_nic_register_test(
1819 __in efx_nic_t *enp)
1824 _NOTE(ARGUNUSED(enp))
1834 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1839 #endif /* EFSYS_OPT_DIAG */
1843 #endif /* EFSYS_OPT_HUNTINGTON */