2 * Copyright (c) 2012-2015 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
36 #if EFSYS_OPT_MON_MCDI
40 #if EFSYS_OPT_HUNTINGTON
42 #include "ef10_tlv_layout.h"
44 __checkReturn efx_rc_t
45 efx_mcdi_get_port_assignment(
47 __out uint32_t *portp)
50 uint8_t payload[MAX(MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN,
51 MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN)];
54 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
55 enp->en_family == EFX_FAMILY_MEDFORD);
57 (void) memset(payload, 0, sizeof (payload));
58 req.emr_cmd = MC_CMD_GET_PORT_ASSIGNMENT;
59 req.emr_in_buf = payload;
60 req.emr_in_length = MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN;
61 req.emr_out_buf = payload;
62 req.emr_out_length = MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN;
64 efx_mcdi_execute(enp, &req);
66 if (req.emr_rc != 0) {
71 if (req.emr_out_length_used < MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN) {
76 *portp = MCDI_OUT_DWORD(req, GET_PORT_ASSIGNMENT_OUT_PORT);
83 EFSYS_PROBE1(fail1, efx_rc_t, rc);
88 __checkReturn efx_rc_t
89 efx_mcdi_get_port_modes(
91 __out uint32_t *modesp)
94 uint8_t payload[MAX(MC_CMD_GET_PORT_MODES_IN_LEN,
95 MC_CMD_GET_PORT_MODES_OUT_LEN)];
98 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
99 enp->en_family == EFX_FAMILY_MEDFORD);
101 (void) memset(payload, 0, sizeof (payload));
102 req.emr_cmd = MC_CMD_GET_PORT_MODES;
103 req.emr_in_buf = payload;
104 req.emr_in_length = MC_CMD_GET_PORT_MODES_IN_LEN;
105 req.emr_out_buf = payload;
106 req.emr_out_length = MC_CMD_GET_PORT_MODES_OUT_LEN;
108 efx_mcdi_execute(enp, &req);
110 if (req.emr_rc != 0) {
116 * Require only Modes and DefaultMode fields.
117 * (CurrentMode field was added for Medford)
119 if (req.emr_out_length_used <
120 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST) {
125 *modesp = MCDI_OUT_DWORD(req, GET_PORT_MODES_OUT_MODES);
132 EFSYS_PROBE1(fail1, efx_rc_t, rc);
138 static __checkReturn efx_rc_t
139 efx_mcdi_vadaptor_alloc(
141 __in uint32_t port_id)
144 uint8_t payload[MAX(MC_CMD_VADAPTOR_ALLOC_IN_LEN,
145 MC_CMD_VADAPTOR_ALLOC_OUT_LEN)];
148 EFSYS_ASSERT3U(enp->en_vport_id, ==, EVB_PORT_ID_NULL);
150 (void) memset(payload, 0, sizeof (payload));
151 req.emr_cmd = MC_CMD_VADAPTOR_ALLOC;
152 req.emr_in_buf = payload;
153 req.emr_in_length = MC_CMD_VADAPTOR_ALLOC_IN_LEN;
154 req.emr_out_buf = payload;
155 req.emr_out_length = MC_CMD_VADAPTOR_ALLOC_OUT_LEN;
157 MCDI_IN_SET_DWORD(req, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
158 MCDI_IN_POPULATE_DWORD_1(req, VADAPTOR_ALLOC_IN_FLAGS,
159 VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED,
160 enp->en_nic_cfg.enc_allow_set_mac_with_installed_filters ? 1 : 0);
162 efx_mcdi_execute(enp, &req);
164 if (req.emr_rc != 0) {
172 EFSYS_PROBE1(fail1, efx_rc_t, rc);
177 static __checkReturn efx_rc_t
178 efx_mcdi_vadaptor_free(
180 __in uint32_t port_id)
183 uint8_t payload[MAX(MC_CMD_VADAPTOR_FREE_IN_LEN,
184 MC_CMD_VADAPTOR_FREE_OUT_LEN)];
187 (void) memset(payload, 0, sizeof (payload));
188 req.emr_cmd = MC_CMD_VADAPTOR_FREE;
189 req.emr_in_buf = payload;
190 req.emr_in_length = MC_CMD_VADAPTOR_FREE_IN_LEN;
191 req.emr_out_buf = payload;
192 req.emr_out_length = MC_CMD_VADAPTOR_FREE_OUT_LEN;
194 MCDI_IN_SET_DWORD(req, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
196 efx_mcdi_execute(enp, &req);
198 if (req.emr_rc != 0) {
206 EFSYS_PROBE1(fail1, efx_rc_t, rc);
211 __checkReturn efx_rc_t
212 efx_mcdi_get_mac_address_pf(
214 __out_ecount_opt(6) uint8_t mac_addrp[6])
217 uint8_t payload[MAX(MC_CMD_GET_MAC_ADDRESSES_IN_LEN,
218 MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)];
221 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
222 enp->en_family == EFX_FAMILY_MEDFORD);
224 (void) memset(payload, 0, sizeof (payload));
225 req.emr_cmd = MC_CMD_GET_MAC_ADDRESSES;
226 req.emr_in_buf = payload;
227 req.emr_in_length = MC_CMD_GET_MAC_ADDRESSES_IN_LEN;
228 req.emr_out_buf = payload;
229 req.emr_out_length = MC_CMD_GET_MAC_ADDRESSES_OUT_LEN;
231 efx_mcdi_execute(enp, &req);
233 if (req.emr_rc != 0) {
238 if (req.emr_out_length_used < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) {
243 if (MCDI_OUT_DWORD(req, GET_MAC_ADDRESSES_OUT_MAC_COUNT) < 1) {
248 if (mac_addrp != NULL) {
251 addrp = MCDI_OUT2(req, uint8_t,
252 GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE);
254 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
264 EFSYS_PROBE1(fail1, efx_rc_t, rc);
269 __checkReturn efx_rc_t
270 efx_mcdi_get_mac_address_vf(
272 __out_ecount_opt(6) uint8_t mac_addrp[6])
275 uint8_t payload[MAX(MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN,
276 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX)];
279 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
280 enp->en_family == EFX_FAMILY_MEDFORD);
282 (void) memset(payload, 0, sizeof (payload));
283 req.emr_cmd = MC_CMD_VPORT_GET_MAC_ADDRESSES;
284 req.emr_in_buf = payload;
285 req.emr_in_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN;
286 req.emr_out_buf = payload;
287 req.emr_out_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX;
289 MCDI_IN_SET_DWORD(req, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
290 EVB_PORT_ID_ASSIGNED);
292 efx_mcdi_execute(enp, &req);
294 if (req.emr_rc != 0) {
299 if (req.emr_out_length_used <
300 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN) {
305 if (MCDI_OUT_DWORD(req,
306 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT) < 1) {
311 if (mac_addrp != NULL) {
314 addrp = MCDI_OUT2(req, uint8_t,
315 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR);
317 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
327 EFSYS_PROBE1(fail1, efx_rc_t, rc);
332 __checkReturn efx_rc_t
335 __out uint32_t *sys_freqp)
338 uint8_t payload[MAX(MC_CMD_GET_CLOCK_IN_LEN,
339 MC_CMD_GET_CLOCK_OUT_LEN)];
342 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
343 enp->en_family == EFX_FAMILY_MEDFORD);
345 (void) memset(payload, 0, sizeof (payload));
346 req.emr_cmd = MC_CMD_GET_CLOCK;
347 req.emr_in_buf = payload;
348 req.emr_in_length = MC_CMD_GET_CLOCK_IN_LEN;
349 req.emr_out_buf = payload;
350 req.emr_out_length = MC_CMD_GET_CLOCK_OUT_LEN;
352 efx_mcdi_execute(enp, &req);
354 if (req.emr_rc != 0) {
359 if (req.emr_out_length_used < MC_CMD_GET_CLOCK_OUT_LEN) {
364 *sys_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_SYS_FREQ);
365 if (*sys_freqp == 0) {
377 EFSYS_PROBE1(fail1, efx_rc_t, rc);
382 __checkReturn efx_rc_t
383 efx_mcdi_get_vector_cfg(
385 __out_opt uint32_t *vec_basep,
386 __out_opt uint32_t *pf_nvecp,
387 __out_opt uint32_t *vf_nvecp)
390 uint8_t payload[MAX(MC_CMD_GET_VECTOR_CFG_IN_LEN,
391 MC_CMD_GET_VECTOR_CFG_OUT_LEN)];
394 (void) memset(payload, 0, sizeof (payload));
395 req.emr_cmd = MC_CMD_GET_VECTOR_CFG;
396 req.emr_in_buf = payload;
397 req.emr_in_length = MC_CMD_GET_VECTOR_CFG_IN_LEN;
398 req.emr_out_buf = payload;
399 req.emr_out_length = MC_CMD_GET_VECTOR_CFG_OUT_LEN;
401 efx_mcdi_execute(enp, &req);
403 if (req.emr_rc != 0) {
408 if (req.emr_out_length_used < MC_CMD_GET_VECTOR_CFG_OUT_LEN) {
413 if (vec_basep != NULL)
414 *vec_basep = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VEC_BASE);
415 if (pf_nvecp != NULL)
416 *pf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_PF);
417 if (vf_nvecp != NULL)
418 *vf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_VF);
425 EFSYS_PROBE1(fail1, efx_rc_t, rc);
430 static __checkReturn efx_rc_t
431 efx_mcdi_get_capabilities(
433 __out efx_dword_t *flagsp,
434 __out efx_dword_t *flags2p)
437 uint8_t payload[MAX(MC_CMD_GET_CAPABILITIES_IN_LEN,
438 MC_CMD_GET_CAPABILITIES_V2_OUT_LEN)];
441 (void) memset(payload, 0, sizeof (payload));
442 req.emr_cmd = MC_CMD_GET_CAPABILITIES;
443 req.emr_in_buf = payload;
444 req.emr_in_length = MC_CMD_GET_CAPABILITIES_IN_LEN;
445 req.emr_out_buf = payload;
446 req.emr_out_length = MC_CMD_GET_CAPABILITIES_V2_OUT_LEN;
448 efx_mcdi_execute(enp, &req);
450 if (req.emr_rc != 0) {
455 if (req.emr_out_length_used < MC_CMD_GET_CAPABILITIES_OUT_LEN) {
460 *flagsp = *MCDI_OUT2(req, efx_dword_t, GET_CAPABILITIES_OUT_FLAGS1);
462 if (req.emr_out_length_used < MC_CMD_GET_CAPABILITIES_V2_OUT_LEN)
463 EFX_ZERO_DWORD(*flags2p);
465 *flags2p = *MCDI_OUT2(req, efx_dword_t,
466 GET_CAPABILITIES_V2_OUT_FLAGS2);
473 EFSYS_PROBE1(fail1, efx_rc_t, rc);
479 static __checkReturn efx_rc_t
482 __in uint32_t min_vi_count,
483 __in uint32_t max_vi_count,
484 __out uint32_t *vi_basep,
485 __out uint32_t *vi_countp,
486 __out uint32_t *vi_shiftp)
489 uint8_t payload[MAX(MC_CMD_ALLOC_VIS_IN_LEN,
490 MC_CMD_ALLOC_VIS_OUT_LEN)];
493 if (vi_countp == NULL) {
498 (void) memset(payload, 0, sizeof (payload));
499 req.emr_cmd = MC_CMD_ALLOC_VIS;
500 req.emr_in_buf = payload;
501 req.emr_in_length = MC_CMD_ALLOC_VIS_IN_LEN;
502 req.emr_out_buf = payload;
503 req.emr_out_length = MC_CMD_ALLOC_VIS_OUT_LEN;
505 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MIN_VI_COUNT, min_vi_count);
506 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MAX_VI_COUNT, max_vi_count);
508 efx_mcdi_execute(enp, &req);
510 if (req.emr_rc != 0) {
515 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_OUT_LEN) {
520 *vi_basep = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_BASE);
521 *vi_countp = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_COUNT);
523 /* Report VI_SHIFT if available (always zero for Huntington) */
524 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_EXT_OUT_LEN)
527 *vi_shiftp = MCDI_OUT_DWORD(req, ALLOC_VIS_EXT_OUT_VI_SHIFT);
536 EFSYS_PROBE1(fail1, efx_rc_t, rc);
542 static __checkReturn efx_rc_t
549 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_IN_LEN == 0);
550 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_OUT_LEN == 0);
552 req.emr_cmd = MC_CMD_FREE_VIS;
553 req.emr_in_buf = NULL;
554 req.emr_in_length = 0;
555 req.emr_out_buf = NULL;
556 req.emr_out_length = 0;
558 efx_mcdi_execute_quiet(enp, &req);
560 /* Ignore ELREADY (no allocated VIs, so nothing to free) */
561 if ((req.emr_rc != 0) && (req.emr_rc != EALREADY)) {
569 EFSYS_PROBE1(fail1, efx_rc_t, rc);
575 static __checkReturn efx_rc_t
576 efx_mcdi_alloc_piobuf(
578 __out efx_piobuf_handle_t *handlep)
581 uint8_t payload[MAX(MC_CMD_ALLOC_PIOBUF_IN_LEN,
582 MC_CMD_ALLOC_PIOBUF_OUT_LEN)];
585 if (handlep == NULL) {
590 (void) memset(payload, 0, sizeof (payload));
591 req.emr_cmd = MC_CMD_ALLOC_PIOBUF;
592 req.emr_in_buf = payload;
593 req.emr_in_length = MC_CMD_ALLOC_PIOBUF_IN_LEN;
594 req.emr_out_buf = payload;
595 req.emr_out_length = MC_CMD_ALLOC_PIOBUF_OUT_LEN;
597 efx_mcdi_execute_quiet(enp, &req);
599 if (req.emr_rc != 0) {
604 if (req.emr_out_length_used < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
609 *handlep = MCDI_OUT_DWORD(req, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
618 EFSYS_PROBE1(fail1, efx_rc_t, rc);
623 static __checkReturn efx_rc_t
624 efx_mcdi_free_piobuf(
626 __in efx_piobuf_handle_t handle)
629 uint8_t payload[MAX(MC_CMD_FREE_PIOBUF_IN_LEN,
630 MC_CMD_FREE_PIOBUF_OUT_LEN)];
633 (void) memset(payload, 0, sizeof (payload));
634 req.emr_cmd = MC_CMD_FREE_PIOBUF;
635 req.emr_in_buf = payload;
636 req.emr_in_length = MC_CMD_FREE_PIOBUF_IN_LEN;
637 req.emr_out_buf = payload;
638 req.emr_out_length = MC_CMD_FREE_PIOBUF_OUT_LEN;
640 MCDI_IN_SET_DWORD(req, FREE_PIOBUF_IN_PIOBUF_HANDLE, handle);
642 efx_mcdi_execute_quiet(enp, &req);
644 if (req.emr_rc != 0) {
652 EFSYS_PROBE1(fail1, efx_rc_t, rc);
657 static __checkReturn efx_rc_t
658 efx_mcdi_link_piobuf(
660 __in uint32_t vi_index,
661 __in efx_piobuf_handle_t handle)
664 uint8_t payload[MAX(MC_CMD_LINK_PIOBUF_IN_LEN,
665 MC_CMD_LINK_PIOBUF_OUT_LEN)];
668 (void) memset(payload, 0, sizeof (payload));
669 req.emr_cmd = MC_CMD_LINK_PIOBUF;
670 req.emr_in_buf = payload;
671 req.emr_in_length = MC_CMD_LINK_PIOBUF_IN_LEN;
672 req.emr_out_buf = payload;
673 req.emr_out_length = MC_CMD_LINK_PIOBUF_OUT_LEN;
675 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_PIOBUF_HANDLE, handle);
676 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
678 efx_mcdi_execute(enp, &req);
680 if (req.emr_rc != 0) {
688 EFSYS_PROBE1(fail1, efx_rc_t, rc);
693 static __checkReturn efx_rc_t
694 efx_mcdi_unlink_piobuf(
696 __in uint32_t vi_index)
699 uint8_t payload[MAX(MC_CMD_UNLINK_PIOBUF_IN_LEN,
700 MC_CMD_UNLINK_PIOBUF_OUT_LEN)];
703 (void) memset(payload, 0, sizeof (payload));
704 req.emr_cmd = MC_CMD_UNLINK_PIOBUF;
705 req.emr_in_buf = payload;
706 req.emr_in_length = MC_CMD_UNLINK_PIOBUF_IN_LEN;
707 req.emr_out_buf = payload;
708 req.emr_out_length = MC_CMD_UNLINK_PIOBUF_OUT_LEN;
710 MCDI_IN_SET_DWORD(req, UNLINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
712 efx_mcdi_execute(enp, &req);
714 if (req.emr_rc != 0) {
722 EFSYS_PROBE1(fail1, efx_rc_t, rc);
728 ef10_nic_alloc_piobufs(
730 __in uint32_t max_piobuf_count)
732 efx_piobuf_handle_t *handlep;
736 EFSYS_ASSERT3U(max_piobuf_count, <=,
737 EFX_ARRAY_SIZE(enp->en_arch.ef10.ena_piobuf_handle));
739 enp->en_arch.ef10.ena_piobuf_count = 0;
741 for (i = 0; i < max_piobuf_count; i++) {
742 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
744 if ((rc = efx_mcdi_alloc_piobuf(enp, handlep)) != 0)
747 enp->en_arch.ef10.ena_pio_alloc_map[i] = 0;
748 enp->en_arch.ef10.ena_piobuf_count++;
754 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
755 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
757 efx_mcdi_free_piobuf(enp, *handlep);
758 *handlep = EFX_PIOBUF_HANDLE_INVALID;
760 enp->en_arch.ef10.ena_piobuf_count = 0;
765 ef10_nic_free_piobufs(
768 efx_piobuf_handle_t *handlep;
771 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
772 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
774 efx_mcdi_free_piobuf(enp, *handlep);
775 *handlep = EFX_PIOBUF_HANDLE_INVALID;
777 enp->en_arch.ef10.ena_piobuf_count = 0;
780 /* Sub-allocate a block from a piobuf */
781 __checkReturn efx_rc_t
783 __inout efx_nic_t *enp,
784 __out uint32_t *bufnump,
785 __out efx_piobuf_handle_t *handlep,
786 __out uint32_t *blknump,
787 __out uint32_t *offsetp,
790 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
791 efx_drv_cfg_t *edcp = &enp->en_drv_cfg;
792 uint32_t blk_per_buf;
796 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
797 enp->en_family == EFX_FAMILY_MEDFORD);
798 EFSYS_ASSERT(bufnump);
799 EFSYS_ASSERT(handlep);
800 EFSYS_ASSERT(blknump);
801 EFSYS_ASSERT(offsetp);
804 if ((edcp->edc_pio_alloc_size == 0) ||
805 (enp->en_arch.ef10.ena_piobuf_count == 0)) {
809 blk_per_buf = encp->enc_piobuf_size / edcp->edc_pio_alloc_size;
811 for (buf = 0; buf < enp->en_arch.ef10.ena_piobuf_count; buf++) {
812 uint32_t *map = &enp->en_arch.ef10.ena_pio_alloc_map[buf];
817 EFSYS_ASSERT3U(blk_per_buf, <=, (8 * sizeof (*map)));
818 for (blk = 0; blk < blk_per_buf; blk++) {
819 if ((*map & (1u << blk)) == 0) {
829 *handlep = enp->en_arch.ef10.ena_piobuf_handle[buf];
832 *sizep = edcp->edc_pio_alloc_size;
833 *offsetp = blk * (*sizep);
840 EFSYS_PROBE1(fail1, efx_rc_t, rc);
845 /* Free a piobuf sub-allocated block */
846 __checkReturn efx_rc_t
848 __inout efx_nic_t *enp,
849 __in uint32_t bufnum,
850 __in uint32_t blknum)
855 if ((bufnum >= enp->en_arch.ef10.ena_piobuf_count) ||
856 (blknum >= (8 * sizeof (*map)))) {
861 map = &enp->en_arch.ef10.ena_pio_alloc_map[bufnum];
862 if ((*map & (1u << blknum)) == 0) {
866 *map &= ~(1u << blknum);
873 EFSYS_PROBE1(fail1, efx_rc_t, rc);
878 __checkReturn efx_rc_t
880 __inout efx_nic_t *enp,
881 __in uint32_t vi_index,
882 __in efx_piobuf_handle_t handle)
884 return (efx_mcdi_link_piobuf(enp, vi_index, handle));
887 __checkReturn efx_rc_t
889 __inout efx_nic_t *enp,
890 __in uint32_t vi_index)
892 return (efx_mcdi_unlink_piobuf(enp, vi_index));
895 __checkReturn efx_rc_t
896 ef10_get_datapath_caps(
899 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
900 efx_dword_t datapath_capabilities;
901 efx_dword_t datapath_capabilities_v2;
904 if ((rc = efx_mcdi_get_capabilities(enp, &datapath_capabilities,
905 &datapath_capabilities_v2)) != 0)
909 * Huntington RXDP firmware inserts a 0 or 14 byte prefix.
910 * We only support the 14 byte prefix here.
912 if (MCDI_CMD_DWORD_FIELD(&datapath_capabilities,
913 GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14) != 1) {
917 encp->enc_rx_prefix_size = 14;
919 /* Check if the firmware supports TSO */
920 if (MCDI_CMD_DWORD_FIELD(&datapath_capabilities,
921 GET_CAPABILITIES_OUT_TX_TSO) == 1)
922 encp->enc_fw_assisted_tso_enabled = B_TRUE;
924 encp->enc_fw_assisted_tso_enabled = B_FALSE;
926 /* Check if the firmware supports FATSOv2 */
927 if (MCDI_CMD_DWORD_FIELD(&datapath_capabilities_v2,
928 GET_CAPABILITIES_V2_OUT_TX_TSO_V2) == 1)
929 encp->enc_fw_assisted_tso_v2_enabled = B_TRUE;
931 encp->enc_fw_assisted_tso_v2_enabled = B_FALSE;
933 /* Check if the firmware has vadapter/vport/vswitch support */
934 if (MCDI_CMD_DWORD_FIELD(&datapath_capabilities,
935 GET_CAPABILITIES_OUT_EVB) == 1)
936 encp->enc_datapath_cap_evb = B_TRUE;
938 encp->enc_datapath_cap_evb = B_FALSE;
940 /* Check if the firmware supports VLAN insertion */
941 if (MCDI_CMD_DWORD_FIELD(&datapath_capabilities,
942 GET_CAPABILITIES_OUT_TX_VLAN_INSERTION) == 1)
943 encp->enc_hw_tx_insert_vlan_enabled = B_TRUE;
945 encp->enc_hw_tx_insert_vlan_enabled = B_FALSE;
947 /* Check if the firmware supports RX event batching */
948 if (MCDI_CMD_DWORD_FIELD(&datapath_capabilities,
949 GET_CAPABILITIES_OUT_RX_BATCHING) == 1) {
950 encp->enc_rx_batching_enabled = B_TRUE;
951 encp->enc_rx_batch_max = 16;
953 encp->enc_rx_batching_enabled = B_FALSE;
956 /* Check if the firmware supports disabling scatter on RXQs */
957 if (MCDI_CMD_DWORD_FIELD(&datapath_capabilities,
958 GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER) == 1) {
959 encp->enc_rx_disable_scatter_supported = B_TRUE;
961 encp->enc_rx_disable_scatter_supported = B_FALSE;
964 /* Check if the firmware supports set mac with running filters */
965 if (MCDI_CMD_DWORD_FIELD(&datapath_capabilities,
966 GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED)
968 encp->enc_allow_set_mac_with_installed_filters = B_TRUE;
970 encp->enc_allow_set_mac_with_installed_filters = B_FALSE;
978 EFSYS_PROBE1(fail1, efx_rc_t, rc);
984 * The external port mapping is a one-based numbering of the external
985 * connectors on the board. It does not distinguish off-board separated
986 * outputs such as multi-headed cables.
987 * The number of ports that map to each external port connector
988 * on the board is determined by the chip family and the port modes to
989 * which the NIC can be configured. The mapping table lists modes with
990 * port numbering requirements in increasing order.
996 } __ef10_external_port_mappings[] = {
997 /* Supported modes requiring 1 output per port */
999 EFX_FAMILY_HUNTINGTON,
1000 (1 << TLV_PORT_MODE_10G) |
1001 (1 << TLV_PORT_MODE_10G_10G) |
1002 (1 << TLV_PORT_MODE_10G_10G_10G_10G),
1007 (1 << TLV_PORT_MODE_10G) |
1008 (1 << TLV_PORT_MODE_10G_10G) |
1009 (1 << TLV_PORT_MODE_10G_10G_10G_10G),
1012 /* Supported modes requiring 2 outputs per port */
1014 EFX_FAMILY_HUNTINGTON,
1015 (1 << TLV_PORT_MODE_40G) |
1016 (1 << TLV_PORT_MODE_40G_40G) |
1017 (1 << TLV_PORT_MODE_40G_10G_10G) |
1018 (1 << TLV_PORT_MODE_10G_10G_40G),
1023 (1 << TLV_PORT_MODE_40G) |
1024 (1 << TLV_PORT_MODE_40G_40G) |
1025 (1 << TLV_PORT_MODE_40G_10G_10G) |
1026 (1 << TLV_PORT_MODE_10G_10G_40G),
1029 /* Supported modes requiring 4 outputs per port */
1032 (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q) |
1033 (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q2),
1038 __checkReturn efx_rc_t
1039 ef10_external_port_mapping(
1040 __in efx_nic_t *enp,
1042 __out uint8_t *external_portp)
1046 uint32_t port_modes;
1048 uint32_t stride = 1; /* default 1-1 mapping */
1050 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes)) != 0) {
1051 /* No port mode information available - use default mapping */
1056 * Infer the internal port -> external port mapping from
1057 * the possible port modes for this NIC.
1059 for (i = 0; i < EFX_ARRAY_SIZE(__ef10_external_port_mappings); ++i) {
1060 if (__ef10_external_port_mappings[i].family !=
1063 matches = (__ef10_external_port_mappings[i].modes_mask &
1066 stride = __ef10_external_port_mappings[i].stride;
1067 port_modes &= ~matches;
1071 if (port_modes != 0) {
1072 /* Some advertised modes are not supported */
1079 * Scale as required by last matched mode and then convert to
1080 * one-based numbering
1082 *external_portp = (uint8_t)(port / stride) + 1;
1086 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1091 __checkReturn efx_rc_t
1093 __in efx_nic_t *enp)
1095 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
1096 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1097 uint8_t mac_addr[6];
1098 uint32_t board_type = 0;
1099 ef10_link_state_t els;
1100 efx_port_t *epp = &(enp->en_port);
1107 uint32_t base, nvec;
1110 if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
1114 * NOTE: The MCDI protocol numbers ports from zero.
1115 * The common code MCDI interface numbers ports from one.
1117 emip->emi_port = port + 1;
1119 if ((rc = ef10_external_port_mapping(enp, port,
1120 &encp->enc_external_port)) != 0)
1124 * Get PCIe function number from firmware (used for
1125 * per-function privilege and dynamic config info).
1126 * - PCIe PF: pf = PF number, vf = 0xffff.
1127 * - PCIe VF: pf = parent PF, vf = VF number.
1129 if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
1135 /* MAC address for this function */
1136 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
1137 rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
1138 if ((rc == 0) && (mac_addr[0] & 0x02)) {
1140 * If the static config does not include a global MAC
1141 * address pool then the board may return a locally
1142 * administered MAC address (this should only happen on
1143 * incorrectly programmed boards).
1148 rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
1153 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
1155 /* Board configuration */
1156 rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
1158 /* Unprivileged functions may not be able to read board cfg */
1165 encp->enc_board_type = board_type;
1166 encp->enc_clk_mult = 1; /* not used for Huntington */
1168 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
1169 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
1172 /* Obtain the default PHY advertised capabilities */
1173 if ((rc = hunt_phy_get_link(enp, &els)) != 0)
1175 epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
1176 epp->ep_adv_cap_mask = els.els_adv_cap_mask;
1179 * Enable firmware workarounds for hardware errata.
1180 * Expected responses are:
1182 * Success: workaround enabled or disabled as requested.
1183 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
1184 * Firmware does not support the MC_CMD_WORKAROUND request.
1185 * (assume that the workaround is not supported).
1186 * - MC_CMD_ERR_ENOENT (reported as ENOENT):
1187 * Firmware does not support the requested workaround.
1188 * - MC_CMD_ERR_EPERM (reported as EACCES):
1189 * Unprivileged function cannot enable/disable workarounds.
1191 * See efx_mcdi_request_errcode() for MCDI error translations.
1195 * If the bug35388 workaround is enabled, then use an indirect access
1196 * method to avoid unsafe EVQ writes.
1198 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG35388, B_TRUE,
1200 if ((rc == 0) || (rc == EACCES))
1201 encp->enc_bug35388_workaround = B_TRUE;
1202 else if ((rc == ENOTSUP) || (rc == ENOENT))
1203 encp->enc_bug35388_workaround = B_FALSE;
1208 * If the bug41750 workaround is enabled, then do not test interrupts,
1209 * as the test will fail (seen with Greenport controllers).
1211 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG41750, B_TRUE,
1214 encp->enc_bug41750_workaround = B_TRUE;
1215 } else if (rc == EACCES) {
1216 /* Assume a controller with 40G ports needs the workaround. */
1217 if (epp->ep_default_adv_cap_mask & EFX_PHY_CAP_40000FDX)
1218 encp->enc_bug41750_workaround = B_TRUE;
1220 encp->enc_bug41750_workaround = B_FALSE;
1221 } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
1222 encp->enc_bug41750_workaround = B_FALSE;
1226 if (EFX_PCI_FUNCTION_IS_VF(encp)) {
1227 /* Interrupt testing does not work for VFs. See bug50084. */
1228 encp->enc_bug41750_workaround = B_TRUE;
1232 * If the bug26807 workaround is enabled, then firmware has enabled
1233 * support for chained multicast filters. Firmware will reset (FLR)
1234 * functions which have filters in the hardware filter table when the
1235 * workaround is enabled/disabled.
1237 * We must recheck if the workaround is enabled after inserting the
1238 * first hardware filter, in case it has been changed since this check.
1240 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG26807,
1243 encp->enc_bug26807_workaround = B_TRUE;
1244 if (flags & (1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN)) {
1246 * Other functions had installed filters before the
1247 * workaround was enabled, and they have been reset
1250 EFSYS_PROBE(bug26807_workaround_flr_done);
1251 /* FIXME: bump MC warm boot count ? */
1253 } else if (rc == EACCES) {
1255 * Unprivileged functions cannot enable the workaround in older
1258 encp->enc_bug26807_workaround = B_FALSE;
1259 } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
1260 encp->enc_bug26807_workaround = B_FALSE;
1265 /* Get sysclk frequency (in MHz). */
1266 if ((rc = efx_mcdi_get_clock(enp, &sysclk)) != 0)
1270 * The timer quantum is 1536 sysclk cycles, documented for the
1271 * EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
1273 encp->enc_evq_timer_quantum_ns = 1536000UL / sysclk; /* 1536 cycles */
1274 if (encp->enc_bug35388_workaround) {
1275 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
1276 ERF_DD_EVQ_IND_TIMER_VAL_WIDTH) / 1000;
1278 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
1279 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
1282 /* Check capabilities of running datapath firmware */
1283 if ((rc = ef10_get_datapath_caps(enp)) != 0)
1286 /* Alignment for receive packet DMA buffers */
1287 encp->enc_rx_buf_align_start = 1;
1288 encp->enc_rx_buf_align_end = 64; /* RX DMA end padding */
1290 /* Alignment for WPTR updates */
1291 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
1294 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
1295 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
1296 * resources (allocated to this PCIe function), which is zero until
1297 * after we have allocated VIs.
1299 encp->enc_evq_limit = 1024;
1300 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
1301 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
1303 encp->enc_buftbl_limit = 0xFFFFFFFF;
1305 encp->enc_piobuf_limit = HUNT_PIOBUF_NBUFS;
1306 encp->enc_piobuf_size = HUNT_PIOBUF_SIZE;
1307 encp->enc_piobuf_min_alloc_size = HUNT_MIN_PIO_ALLOC_SIZE;
1310 * Get the current privilege mask. Note that this may be modified
1311 * dynamically, so this value is informational only. DO NOT use
1312 * the privilege mask to check for sufficient privileges, as that
1313 * can result in time-of-check/time-of-use bugs.
1315 if ((rc = efx_mcdi_privilege_mask(enp, pf, vf, &mask)) != 0) {
1319 /* Fallback for old firmware without privilege mask support */
1320 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
1321 /* Assume PF has admin privilege */
1322 mask = HUNT_LEGACY_PF_PRIVILEGE_MASK;
1324 /* VF is always unprivileged by default */
1325 mask = HUNT_LEGACY_VF_PRIVILEGE_MASK;
1329 encp->enc_privilege_mask = mask;
1331 /* Get interrupt vector limits */
1332 if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
1333 if (EFX_PCI_FUNCTION_IS_PF(encp))
1336 /* Ignore error (cannot query vector limits from a VF). */
1340 encp->enc_intr_vec_base = base;
1341 encp->enc_intr_limit = nvec;
1344 * Maximum number of bytes into the frame the TCP header can start for
1345 * firmware assisted TSO to work.
1347 encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
1352 EFSYS_PROBE(fail14);
1354 EFSYS_PROBE(fail13);
1356 EFSYS_PROBE(fail12);
1358 EFSYS_PROBE(fail11);
1360 EFSYS_PROBE(fail10);
1378 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1384 __checkReturn efx_rc_t
1386 __in efx_nic_t *enp)
1388 efx_nic_ops_t *enop = enp->en_enop;
1389 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1390 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1393 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1394 enp->en_family == EFX_FAMILY_MEDFORD);
1396 /* Read and clear any assertion state */
1397 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
1400 /* Exit the assertion handler */
1401 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
1405 if ((rc = efx_mcdi_drv_attach(enp, B_TRUE)) != 0)
1408 if ((rc = enop->eno_board_cfg(enp)) != 0)
1413 * Set default driver config limits (based on board config).
1415 * FIXME: For now allocate a fixed number of VIs which is likely to be
1416 * sufficient and small enough to allow multiple functions on the same
1419 edcp->edc_min_vi_count = edcp->edc_max_vi_count =
1420 MIN(128, MAX(encp->enc_rxq_limit, encp->enc_txq_limit));
1422 /* The client driver must configure and enable PIO buffer support */
1423 edcp->edc_max_piobuf_count = 0;
1424 edcp->edc_pio_alloc_size = 0;
1426 #if EFSYS_OPT_MAC_STATS
1427 /* Wipe the MAC statistics */
1428 if ((rc = efx_mcdi_mac_stats_clear(enp)) != 0)
1432 #if EFSYS_OPT_LOOPBACK
1433 if ((rc = efx_mcdi_get_loopback_modes(enp)) != 0)
1437 #if EFSYS_OPT_MON_STATS
1438 if ((rc = mcdi_mon_cfg_build(enp)) != 0) {
1439 /* Unprivileged functions do not have access to sensors */
1445 encp->enc_features = enp->en_features;
1449 #if EFSYS_OPT_MON_STATS
1453 #if EFSYS_OPT_LOOPBACK
1457 #if EFSYS_OPT_MAC_STATS
1468 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1473 __checkReturn efx_rc_t
1474 ef10_nic_set_drv_limits(
1475 __inout efx_nic_t *enp,
1476 __in efx_drv_limits_t *edlp)
1478 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1479 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1480 uint32_t min_evq_count, max_evq_count;
1481 uint32_t min_rxq_count, max_rxq_count;
1482 uint32_t min_txq_count, max_txq_count;
1490 /* Get minimum required and maximum usable VI limits */
1491 min_evq_count = MIN(edlp->edl_min_evq_count, encp->enc_evq_limit);
1492 min_rxq_count = MIN(edlp->edl_min_rxq_count, encp->enc_rxq_limit);
1493 min_txq_count = MIN(edlp->edl_min_txq_count, encp->enc_txq_limit);
1495 edcp->edc_min_vi_count =
1496 MAX(min_evq_count, MAX(min_rxq_count, min_txq_count));
1498 max_evq_count = MIN(edlp->edl_max_evq_count, encp->enc_evq_limit);
1499 max_rxq_count = MIN(edlp->edl_max_rxq_count, encp->enc_rxq_limit);
1500 max_txq_count = MIN(edlp->edl_max_txq_count, encp->enc_txq_limit);
1502 edcp->edc_max_vi_count =
1503 MAX(max_evq_count, MAX(max_rxq_count, max_txq_count));
1506 * Check limits for sub-allocated piobuf blocks.
1507 * PIO is optional, so don't fail if the limits are incorrect.
1509 if ((encp->enc_piobuf_size == 0) ||
1510 (encp->enc_piobuf_limit == 0) ||
1511 (edlp->edl_min_pio_alloc_size == 0) ||
1512 (edlp->edl_min_pio_alloc_size > encp->enc_piobuf_size)) {
1514 edcp->edc_max_piobuf_count = 0;
1515 edcp->edc_pio_alloc_size = 0;
1517 uint32_t blk_size, blk_count, blks_per_piobuf;
1520 MAX(edlp->edl_min_pio_alloc_size,
1521 encp->enc_piobuf_min_alloc_size);
1523 blks_per_piobuf = encp->enc_piobuf_size / blk_size;
1524 EFSYS_ASSERT3U(blks_per_piobuf, <=, 32);
1526 blk_count = (encp->enc_piobuf_limit * blks_per_piobuf);
1528 /* A zero max pio alloc count means unlimited */
1529 if ((edlp->edl_max_pio_alloc_count > 0) &&
1530 (edlp->edl_max_pio_alloc_count < blk_count)) {
1531 blk_count = edlp->edl_max_pio_alloc_count;
1534 edcp->edc_pio_alloc_size = blk_size;
1535 edcp->edc_max_piobuf_count =
1536 (blk_count + (blks_per_piobuf - 1)) / blks_per_piobuf;
1542 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1548 __checkReturn efx_rc_t
1550 __in efx_nic_t *enp)
1553 uint8_t payload[MAX(MC_CMD_ENTITY_RESET_IN_LEN,
1554 MC_CMD_ENTITY_RESET_OUT_LEN)];
1557 /* ef10_nic_reset() is called to recover from BADASSERT failures. */
1558 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
1560 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
1563 (void) memset(payload, 0, sizeof (payload));
1564 req.emr_cmd = MC_CMD_ENTITY_RESET;
1565 req.emr_in_buf = payload;
1566 req.emr_in_length = MC_CMD_ENTITY_RESET_IN_LEN;
1567 req.emr_out_buf = payload;
1568 req.emr_out_length = MC_CMD_ENTITY_RESET_OUT_LEN;
1570 MCDI_IN_POPULATE_DWORD_1(req, ENTITY_RESET_IN_FLAG,
1571 ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET, 1);
1573 efx_mcdi_execute(enp, &req);
1575 if (req.emr_rc != 0) {
1580 /* Clear RX/TX DMA queue errors */
1581 enp->en_reset_flags &= ~(EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR);
1590 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1595 __checkReturn efx_rc_t
1597 __in efx_nic_t *enp)
1599 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1600 uint32_t min_vi_count, max_vi_count;
1601 uint32_t vi_count, vi_base, vi_shift;
1607 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1608 enp->en_family == EFX_FAMILY_MEDFORD);
1610 /* Enable reporting of some events (e.g. link change) */
1611 if ((rc = efx_mcdi_log_ctrl(enp)) != 0)
1614 /* Allocate (optional) on-chip PIO buffers */
1615 ef10_nic_alloc_piobufs(enp, edcp->edc_max_piobuf_count);
1618 * For best performance, PIO writes should use a write-combined
1619 * (WC) memory mapping. Using a separate WC mapping for the PIO
1620 * aperture of each VI would be a burden to drivers (and not
1621 * possible if the host page size is >4Kbyte).
1623 * To avoid this we use a single uncached (UC) mapping for VI
1624 * register access, and a single WC mapping for extra VIs used
1627 * Each piobuf must be linked to a VI in the WC mapping, and to
1628 * each VI that is using a sub-allocated block from the piobuf.
1630 min_vi_count = edcp->edc_min_vi_count;
1632 edcp->edc_max_vi_count + enp->en_arch.ef10.ena_piobuf_count;
1634 /* Ensure that the previously attached driver's VIs are freed */
1635 if ((rc = efx_mcdi_free_vis(enp)) != 0)
1639 * Reserve VI resources (EVQ+RXQ+TXQ) for this PCIe function. If this
1640 * fails then retrying the request for fewer VI resources may succeed.
1643 if ((rc = efx_mcdi_alloc_vis(enp, min_vi_count, max_vi_count,
1644 &vi_base, &vi_count, &vi_shift)) != 0)
1647 EFSYS_PROBE2(vi_alloc, uint32_t, vi_base, uint32_t, vi_count);
1649 if (vi_count < min_vi_count) {
1654 enp->en_arch.ef10.ena_vi_base = vi_base;
1655 enp->en_arch.ef10.ena_vi_count = vi_count;
1656 enp->en_arch.ef10.ena_vi_shift = vi_shift;
1658 if (vi_count < min_vi_count + enp->en_arch.ef10.ena_piobuf_count) {
1659 /* Not enough extra VIs to map piobufs */
1660 ef10_nic_free_piobufs(enp);
1663 enp->en_arch.ef10.ena_pio_write_vi_base =
1664 vi_count - enp->en_arch.ef10.ena_piobuf_count;
1666 /* Save UC memory mapping details */
1667 enp->en_arch.ef10.ena_uc_mem_map_offset = 0;
1668 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
1669 enp->en_arch.ef10.ena_uc_mem_map_size =
1670 (ER_DZ_TX_PIOBUF_STEP *
1671 enp->en_arch.ef10.ena_pio_write_vi_base);
1673 enp->en_arch.ef10.ena_uc_mem_map_size =
1674 (ER_DZ_TX_PIOBUF_STEP *
1675 enp->en_arch.ef10.ena_vi_count);
1678 /* Save WC memory mapping details */
1679 enp->en_arch.ef10.ena_wc_mem_map_offset =
1680 enp->en_arch.ef10.ena_uc_mem_map_offset +
1681 enp->en_arch.ef10.ena_uc_mem_map_size;
1683 enp->en_arch.ef10.ena_wc_mem_map_size =
1684 (ER_DZ_TX_PIOBUF_STEP *
1685 enp->en_arch.ef10.ena_piobuf_count);
1687 /* Link piobufs to extra VIs in WC mapping */
1688 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
1689 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
1690 rc = efx_mcdi_link_piobuf(enp,
1691 enp->en_arch.ef10.ena_pio_write_vi_base + i,
1692 enp->en_arch.ef10.ena_piobuf_handle[i]);
1699 * Allocate a vAdaptor attached to our upstream vPort/pPort.
1701 * On a VF, this may fail with MC_CMD_ERR_NO_EVB_PORT (ENOENT) if the PF
1702 * driver has yet to bring up the EVB port. See bug 56147. In this case,
1703 * retry the request several times after waiting a while. The wait time
1704 * between retries starts small (10ms) and exponentially increases.
1705 * Total wait time is a little over two seconds. Retry logic in the
1706 * client driver may mean this whole loop is repeated if it continues to
1711 while ((rc = efx_mcdi_vadaptor_alloc(enp, EVB_PORT_ID_ASSIGNED)) != 0) {
1712 if (EFX_PCI_FUNCTION_IS_PF(&enp->en_nic_cfg) ||
1715 * Do not retry alloc for PF, or for other errors on
1721 /* VF startup before PF is ready. Retry allocation. */
1723 /* Too many attempts */
1727 EFSYS_PROBE1(mcdi_no_evb_port_retry, int, retry);
1728 EFSYS_SLEEP(delay_us);
1730 if (delay_us < 500000)
1734 enp->en_vport_id = EVB_PORT_ID_ASSIGNED;
1735 enp->en_nic_cfg.enc_mcdi_max_payload_length = MCDI_CTL_SDU_LEN_MAX_V2;
1750 ef10_nic_free_piobufs(enp);
1753 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1758 __checkReturn efx_rc_t
1759 ef10_nic_get_vi_pool(
1760 __in efx_nic_t *enp,
1761 __out uint32_t *vi_countp)
1763 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1764 enp->en_family == EFX_FAMILY_MEDFORD);
1767 * Report VIs that the client driver can use.
1768 * Do not include VIs used for PIO buffer writes.
1770 *vi_countp = enp->en_arch.ef10.ena_pio_write_vi_base;
1775 __checkReturn efx_rc_t
1776 ef10_nic_get_bar_region(
1777 __in efx_nic_t *enp,
1778 __in efx_nic_region_t region,
1779 __out uint32_t *offsetp,
1780 __out size_t *sizep)
1784 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1785 enp->en_family == EFX_FAMILY_MEDFORD);
1788 * TODO: Specify host memory mapping alignment and granularity
1789 * in efx_drv_limits_t so that they can be taken into account
1790 * when allocating extra VIs for PIO writes.
1794 /* UC mapped memory BAR region for VI registers */
1795 *offsetp = enp->en_arch.ef10.ena_uc_mem_map_offset;
1796 *sizep = enp->en_arch.ef10.ena_uc_mem_map_size;
1799 case EFX_REGION_PIO_WRITE_VI:
1800 /* WC mapped memory BAR region for piobuf writes */
1801 *offsetp = enp->en_arch.ef10.ena_wc_mem_map_offset;
1802 *sizep = enp->en_arch.ef10.ena_wc_mem_map_size;
1813 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1820 __in efx_nic_t *enp)
1825 (void) efx_mcdi_vadaptor_free(enp, enp->en_vport_id);
1826 enp->en_vport_id = 0;
1828 /* Unlink piobufs from extra VIs in WC mapping */
1829 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
1830 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
1831 rc = efx_mcdi_unlink_piobuf(enp,
1832 enp->en_arch.ef10.ena_pio_write_vi_base + i);
1838 ef10_nic_free_piobufs(enp);
1840 (void) efx_mcdi_free_vis(enp);
1841 enp->en_arch.ef10.ena_vi_count = 0;
1846 __in efx_nic_t *enp)
1848 #if EFSYS_OPT_MON_STATS
1849 mcdi_mon_cfg_free(enp);
1850 #endif /* EFSYS_OPT_MON_STATS */
1851 (void) efx_mcdi_drv_attach(enp, B_FALSE);
1856 __checkReturn efx_rc_t
1857 ef10_nic_register_test(
1858 __in efx_nic_t *enp)
1863 _NOTE(ARGUNUSED(enp))
1873 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1878 #endif /* EFSYS_OPT_DIAG */
1882 #endif /* EFSYS_OPT_HUNTINGTON */