2 * Copyright (c) 2012-2015 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
36 #if EFSYS_OPT_MON_MCDI
40 #if EFSYS_OPT_HUNTINGTON
42 #include "ef10_tlv_layout.h"
44 __checkReturn efx_rc_t
45 efx_mcdi_get_port_assignment(
47 __out uint32_t *portp)
50 uint8_t payload[MAX(MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN,
51 MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN)];
54 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
55 enp->en_family == EFX_FAMILY_MEDFORD);
57 (void) memset(payload, 0, sizeof (payload));
58 req.emr_cmd = MC_CMD_GET_PORT_ASSIGNMENT;
59 req.emr_in_buf = payload;
60 req.emr_in_length = MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN;
61 req.emr_out_buf = payload;
62 req.emr_out_length = MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN;
64 efx_mcdi_execute(enp, &req);
66 if (req.emr_rc != 0) {
71 if (req.emr_out_length_used < MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN) {
76 *portp = MCDI_OUT_DWORD(req, GET_PORT_ASSIGNMENT_OUT_PORT);
83 EFSYS_PROBE1(fail1, efx_rc_t, rc);
88 __checkReturn efx_rc_t
89 efx_mcdi_get_port_modes(
91 __out uint32_t *modesp)
94 uint8_t payload[MAX(MC_CMD_GET_PORT_MODES_IN_LEN,
95 MC_CMD_GET_PORT_MODES_OUT_LEN)];
98 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
99 enp->en_family == EFX_FAMILY_MEDFORD);
101 (void) memset(payload, 0, sizeof (payload));
102 req.emr_cmd = MC_CMD_GET_PORT_MODES;
103 req.emr_in_buf = payload;
104 req.emr_in_length = MC_CMD_GET_PORT_MODES_IN_LEN;
105 req.emr_out_buf = payload;
106 req.emr_out_length = MC_CMD_GET_PORT_MODES_OUT_LEN;
108 efx_mcdi_execute(enp, &req);
110 if (req.emr_rc != 0) {
115 /* Accept pre-Medford size (8 bytes - no CurrentMode field) */
116 if (req.emr_out_length_used <
117 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST) {
122 *modesp = MCDI_OUT_DWORD(req, GET_PORT_MODES_OUT_MODES);
129 EFSYS_PROBE1(fail1, efx_rc_t, rc);
135 static __checkReturn efx_rc_t
136 efx_mcdi_vadaptor_alloc(
138 __in uint32_t port_id)
141 uint8_t payload[MAX(MC_CMD_VADAPTOR_ALLOC_IN_LEN,
142 MC_CMD_VADAPTOR_ALLOC_OUT_LEN)];
145 EFSYS_ASSERT3U(enp->en_vport_id, ==, EVB_PORT_ID_NULL);
147 (void) memset(payload, 0, sizeof (payload));
148 req.emr_cmd = MC_CMD_VADAPTOR_ALLOC;
149 req.emr_in_buf = payload;
150 req.emr_in_length = MC_CMD_VADAPTOR_ALLOC_IN_LEN;
151 req.emr_out_buf = payload;
152 req.emr_out_length = MC_CMD_VADAPTOR_ALLOC_OUT_LEN;
154 MCDI_IN_SET_DWORD(req, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
155 MCDI_IN_POPULATE_DWORD_1(req, VADAPTOR_ALLOC_IN_FLAGS,
156 VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED,
157 enp->en_nic_cfg.enc_allow_set_mac_with_installed_filters ? 1 : 0);
159 efx_mcdi_execute(enp, &req);
161 if (req.emr_rc != 0) {
169 EFSYS_PROBE1(fail1, efx_rc_t, rc);
174 static __checkReturn efx_rc_t
175 efx_mcdi_vadaptor_free(
177 __in uint32_t port_id)
180 uint8_t payload[MAX(MC_CMD_VADAPTOR_FREE_IN_LEN,
181 MC_CMD_VADAPTOR_FREE_OUT_LEN)];
184 (void) memset(payload, 0, sizeof (payload));
185 req.emr_cmd = MC_CMD_VADAPTOR_FREE;
186 req.emr_in_buf = payload;
187 req.emr_in_length = MC_CMD_VADAPTOR_FREE_IN_LEN;
188 req.emr_out_buf = payload;
189 req.emr_out_length = MC_CMD_VADAPTOR_FREE_OUT_LEN;
191 MCDI_IN_SET_DWORD(req, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
193 efx_mcdi_execute(enp, &req);
195 if (req.emr_rc != 0) {
203 EFSYS_PROBE1(fail1, efx_rc_t, rc);
208 __checkReturn efx_rc_t
209 efx_mcdi_get_mac_address_pf(
211 __out_ecount_opt(6) uint8_t mac_addrp[6])
214 uint8_t payload[MAX(MC_CMD_GET_MAC_ADDRESSES_IN_LEN,
215 MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)];
218 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
219 enp->en_family == EFX_FAMILY_MEDFORD);
221 (void) memset(payload, 0, sizeof (payload));
222 req.emr_cmd = MC_CMD_GET_MAC_ADDRESSES;
223 req.emr_in_buf = payload;
224 req.emr_in_length = MC_CMD_GET_MAC_ADDRESSES_IN_LEN;
225 req.emr_out_buf = payload;
226 req.emr_out_length = MC_CMD_GET_MAC_ADDRESSES_OUT_LEN;
228 efx_mcdi_execute(enp, &req);
230 if (req.emr_rc != 0) {
235 if (req.emr_out_length_used < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) {
240 if (MCDI_OUT_DWORD(req, GET_MAC_ADDRESSES_OUT_MAC_COUNT) < 1) {
245 if (mac_addrp != NULL) {
248 addrp = MCDI_OUT2(req, uint8_t,
249 GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE);
251 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
261 EFSYS_PROBE1(fail1, efx_rc_t, rc);
266 __checkReturn efx_rc_t
267 efx_mcdi_get_mac_address_vf(
269 __out_ecount_opt(6) uint8_t mac_addrp[6])
272 uint8_t payload[MAX(MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN,
273 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX)];
276 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
277 enp->en_family == EFX_FAMILY_MEDFORD);
279 (void) memset(payload, 0, sizeof (payload));
280 req.emr_cmd = MC_CMD_VPORT_GET_MAC_ADDRESSES;
281 req.emr_in_buf = payload;
282 req.emr_in_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN;
283 req.emr_out_buf = payload;
284 req.emr_out_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX;
286 MCDI_IN_SET_DWORD(req, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
287 EVB_PORT_ID_ASSIGNED);
289 efx_mcdi_execute(enp, &req);
291 if (req.emr_rc != 0) {
296 if (req.emr_out_length_used <
297 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN) {
302 if (MCDI_OUT_DWORD(req,
303 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT) < 1) {
308 if (mac_addrp != NULL) {
311 addrp = MCDI_OUT2(req, uint8_t,
312 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR);
314 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
324 EFSYS_PROBE1(fail1, efx_rc_t, rc);
329 __checkReturn efx_rc_t
332 __out uint32_t *sys_freqp)
335 uint8_t payload[MAX(MC_CMD_GET_CLOCK_IN_LEN,
336 MC_CMD_GET_CLOCK_OUT_LEN)];
339 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
340 enp->en_family == EFX_FAMILY_MEDFORD);
342 (void) memset(payload, 0, sizeof (payload));
343 req.emr_cmd = MC_CMD_GET_CLOCK;
344 req.emr_in_buf = payload;
345 req.emr_in_length = MC_CMD_GET_CLOCK_IN_LEN;
346 req.emr_out_buf = payload;
347 req.emr_out_length = MC_CMD_GET_CLOCK_OUT_LEN;
349 efx_mcdi_execute(enp, &req);
351 if (req.emr_rc != 0) {
356 if (req.emr_out_length_used < MC_CMD_GET_CLOCK_OUT_LEN) {
361 *sys_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_SYS_FREQ);
362 if (*sys_freqp == 0) {
374 EFSYS_PROBE1(fail1, efx_rc_t, rc);
379 __checkReturn efx_rc_t
380 efx_mcdi_get_vector_cfg(
382 __out_opt uint32_t *vec_basep,
383 __out_opt uint32_t *pf_nvecp,
384 __out_opt uint32_t *vf_nvecp)
387 uint8_t payload[MAX(MC_CMD_GET_VECTOR_CFG_IN_LEN,
388 MC_CMD_GET_VECTOR_CFG_OUT_LEN)];
391 (void) memset(payload, 0, sizeof (payload));
392 req.emr_cmd = MC_CMD_GET_VECTOR_CFG;
393 req.emr_in_buf = payload;
394 req.emr_in_length = MC_CMD_GET_VECTOR_CFG_IN_LEN;
395 req.emr_out_buf = payload;
396 req.emr_out_length = MC_CMD_GET_VECTOR_CFG_OUT_LEN;
398 efx_mcdi_execute(enp, &req);
400 if (req.emr_rc != 0) {
405 if (req.emr_out_length_used < MC_CMD_GET_VECTOR_CFG_OUT_LEN) {
410 if (vec_basep != NULL)
411 *vec_basep = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VEC_BASE);
412 if (pf_nvecp != NULL)
413 *pf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_PF);
414 if (vf_nvecp != NULL)
415 *vf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_VF);
422 EFSYS_PROBE1(fail1, efx_rc_t, rc);
427 static __checkReturn efx_rc_t
428 efx_mcdi_get_capabilities(
430 __out efx_dword_t *flagsp,
431 __out efx_dword_t *flags2p)
434 uint8_t payload[MAX(MC_CMD_GET_CAPABILITIES_IN_LEN,
435 MC_CMD_GET_CAPABILITIES_V2_OUT_LEN)];
438 (void) memset(payload, 0, sizeof (payload));
439 req.emr_cmd = MC_CMD_GET_CAPABILITIES;
440 req.emr_in_buf = payload;
441 req.emr_in_length = MC_CMD_GET_CAPABILITIES_IN_LEN;
442 req.emr_out_buf = payload;
443 req.emr_out_length = MC_CMD_GET_CAPABILITIES_V2_OUT_LEN;
445 efx_mcdi_execute(enp, &req);
447 if (req.emr_rc != 0) {
452 if (req.emr_out_length_used < MC_CMD_GET_CAPABILITIES_OUT_LEN) {
457 *flagsp = *MCDI_OUT2(req, efx_dword_t, GET_CAPABILITIES_OUT_FLAGS1);
459 if (req.emr_out_length_used < MC_CMD_GET_CAPABILITIES_V2_OUT_LEN)
460 EFX_ZERO_DWORD(*flags2p);
462 *flags2p = *MCDI_OUT2(req, efx_dword_t,
463 GET_CAPABILITIES_V2_OUT_FLAGS2);
470 EFSYS_PROBE1(fail1, efx_rc_t, rc);
476 static __checkReturn efx_rc_t
479 __in uint32_t min_vi_count,
480 __in uint32_t max_vi_count,
481 __out uint32_t *vi_basep,
482 __out uint32_t *vi_countp,
483 __out uint32_t *vi_shiftp)
486 uint8_t payload[MAX(MC_CMD_ALLOC_VIS_IN_LEN,
487 MC_CMD_ALLOC_VIS_OUT_LEN)];
490 if (vi_countp == NULL) {
495 (void) memset(payload, 0, sizeof (payload));
496 req.emr_cmd = MC_CMD_ALLOC_VIS;
497 req.emr_in_buf = payload;
498 req.emr_in_length = MC_CMD_ALLOC_VIS_IN_LEN;
499 req.emr_out_buf = payload;
500 req.emr_out_length = MC_CMD_ALLOC_VIS_OUT_LEN;
502 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MIN_VI_COUNT, min_vi_count);
503 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MAX_VI_COUNT, max_vi_count);
505 efx_mcdi_execute(enp, &req);
507 if (req.emr_rc != 0) {
512 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_OUT_LEN) {
517 *vi_basep = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_BASE);
518 *vi_countp = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_COUNT);
520 /* Report VI_SHIFT if available (always zero for Huntington) */
521 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_EXT_OUT_LEN)
524 *vi_shiftp = MCDI_OUT_DWORD(req, ALLOC_VIS_EXT_OUT_VI_SHIFT);
533 EFSYS_PROBE1(fail1, efx_rc_t, rc);
539 static __checkReturn efx_rc_t
546 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_IN_LEN == 0);
547 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_OUT_LEN == 0);
549 req.emr_cmd = MC_CMD_FREE_VIS;
550 req.emr_in_buf = NULL;
551 req.emr_in_length = 0;
552 req.emr_out_buf = NULL;
553 req.emr_out_length = 0;
555 efx_mcdi_execute_quiet(enp, &req);
557 /* Ignore ELREADY (no allocated VIs, so nothing to free) */
558 if ((req.emr_rc != 0) && (req.emr_rc != EALREADY)) {
566 EFSYS_PROBE1(fail1, efx_rc_t, rc);
572 static __checkReturn efx_rc_t
573 efx_mcdi_alloc_piobuf(
575 __out efx_piobuf_handle_t *handlep)
578 uint8_t payload[MAX(MC_CMD_ALLOC_PIOBUF_IN_LEN,
579 MC_CMD_ALLOC_PIOBUF_OUT_LEN)];
582 if (handlep == NULL) {
587 (void) memset(payload, 0, sizeof (payload));
588 req.emr_cmd = MC_CMD_ALLOC_PIOBUF;
589 req.emr_in_buf = payload;
590 req.emr_in_length = MC_CMD_ALLOC_PIOBUF_IN_LEN;
591 req.emr_out_buf = payload;
592 req.emr_out_length = MC_CMD_ALLOC_PIOBUF_OUT_LEN;
594 efx_mcdi_execute_quiet(enp, &req);
596 if (req.emr_rc != 0) {
601 if (req.emr_out_length_used < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
606 *handlep = MCDI_OUT_DWORD(req, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
615 EFSYS_PROBE1(fail1, efx_rc_t, rc);
620 static __checkReturn efx_rc_t
621 efx_mcdi_free_piobuf(
623 __in efx_piobuf_handle_t handle)
626 uint8_t payload[MAX(MC_CMD_FREE_PIOBUF_IN_LEN,
627 MC_CMD_FREE_PIOBUF_OUT_LEN)];
630 (void) memset(payload, 0, sizeof (payload));
631 req.emr_cmd = MC_CMD_FREE_PIOBUF;
632 req.emr_in_buf = payload;
633 req.emr_in_length = MC_CMD_FREE_PIOBUF_IN_LEN;
634 req.emr_out_buf = payload;
635 req.emr_out_length = MC_CMD_FREE_PIOBUF_OUT_LEN;
637 MCDI_IN_SET_DWORD(req, FREE_PIOBUF_IN_PIOBUF_HANDLE, handle);
639 efx_mcdi_execute_quiet(enp, &req);
641 if (req.emr_rc != 0) {
649 EFSYS_PROBE1(fail1, efx_rc_t, rc);
654 static __checkReturn efx_rc_t
655 efx_mcdi_link_piobuf(
657 __in uint32_t vi_index,
658 __in efx_piobuf_handle_t handle)
661 uint8_t payload[MAX(MC_CMD_LINK_PIOBUF_IN_LEN,
662 MC_CMD_LINK_PIOBUF_OUT_LEN)];
665 (void) memset(payload, 0, sizeof (payload));
666 req.emr_cmd = MC_CMD_LINK_PIOBUF;
667 req.emr_in_buf = payload;
668 req.emr_in_length = MC_CMD_LINK_PIOBUF_IN_LEN;
669 req.emr_out_buf = payload;
670 req.emr_out_length = MC_CMD_LINK_PIOBUF_OUT_LEN;
672 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_PIOBUF_HANDLE, handle);
673 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
675 efx_mcdi_execute(enp, &req);
677 if (req.emr_rc != 0) {
685 EFSYS_PROBE1(fail1, efx_rc_t, rc);
690 static __checkReturn efx_rc_t
691 efx_mcdi_unlink_piobuf(
693 __in uint32_t vi_index)
696 uint8_t payload[MAX(MC_CMD_UNLINK_PIOBUF_IN_LEN,
697 MC_CMD_UNLINK_PIOBUF_OUT_LEN)];
700 (void) memset(payload, 0, sizeof (payload));
701 req.emr_cmd = MC_CMD_UNLINK_PIOBUF;
702 req.emr_in_buf = payload;
703 req.emr_in_length = MC_CMD_UNLINK_PIOBUF_IN_LEN;
704 req.emr_out_buf = payload;
705 req.emr_out_length = MC_CMD_UNLINK_PIOBUF_OUT_LEN;
707 MCDI_IN_SET_DWORD(req, UNLINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
709 efx_mcdi_execute(enp, &req);
711 if (req.emr_rc != 0) {
719 EFSYS_PROBE1(fail1, efx_rc_t, rc);
725 ef10_nic_alloc_piobufs(
727 __in uint32_t max_piobuf_count)
729 efx_piobuf_handle_t *handlep;
733 EFSYS_ASSERT3U(max_piobuf_count, <=,
734 EFX_ARRAY_SIZE(enp->en_arch.ef10.ena_piobuf_handle));
736 enp->en_arch.ef10.ena_piobuf_count = 0;
738 for (i = 0; i < max_piobuf_count; i++) {
739 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
741 if ((rc = efx_mcdi_alloc_piobuf(enp, handlep)) != 0)
744 enp->en_arch.ef10.ena_pio_alloc_map[i] = 0;
745 enp->en_arch.ef10.ena_piobuf_count++;
751 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
752 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
754 efx_mcdi_free_piobuf(enp, *handlep);
755 *handlep = EFX_PIOBUF_HANDLE_INVALID;
757 enp->en_arch.ef10.ena_piobuf_count = 0;
762 ef10_nic_free_piobufs(
765 efx_piobuf_handle_t *handlep;
768 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
769 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
771 efx_mcdi_free_piobuf(enp, *handlep);
772 *handlep = EFX_PIOBUF_HANDLE_INVALID;
774 enp->en_arch.ef10.ena_piobuf_count = 0;
777 /* Sub-allocate a block from a piobuf */
778 __checkReturn efx_rc_t
780 __inout efx_nic_t *enp,
781 __out uint32_t *bufnump,
782 __out efx_piobuf_handle_t *handlep,
783 __out uint32_t *blknump,
784 __out uint32_t *offsetp,
787 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
788 efx_drv_cfg_t *edcp = &enp->en_drv_cfg;
789 uint32_t blk_per_buf;
793 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
794 enp->en_family == EFX_FAMILY_MEDFORD);
795 EFSYS_ASSERT(bufnump);
796 EFSYS_ASSERT(handlep);
797 EFSYS_ASSERT(blknump);
798 EFSYS_ASSERT(offsetp);
801 if ((edcp->edc_pio_alloc_size == 0) ||
802 (enp->en_arch.ef10.ena_piobuf_count == 0)) {
806 blk_per_buf = encp->enc_piobuf_size / edcp->edc_pio_alloc_size;
808 for (buf = 0; buf < enp->en_arch.ef10.ena_piobuf_count; buf++) {
809 uint32_t *map = &enp->en_arch.ef10.ena_pio_alloc_map[buf];
814 EFSYS_ASSERT3U(blk_per_buf, <=, (8 * sizeof (*map)));
815 for (blk = 0; blk < blk_per_buf; blk++) {
816 if ((*map & (1u << blk)) == 0) {
826 *handlep = enp->en_arch.ef10.ena_piobuf_handle[buf];
829 *sizep = edcp->edc_pio_alloc_size;
830 *offsetp = blk * (*sizep);
837 EFSYS_PROBE1(fail1, efx_rc_t, rc);
842 /* Free a piobuf sub-allocated block */
843 __checkReturn efx_rc_t
845 __inout efx_nic_t *enp,
846 __in uint32_t bufnum,
847 __in uint32_t blknum)
852 if ((bufnum >= enp->en_arch.ef10.ena_piobuf_count) ||
853 (blknum >= (8 * sizeof (*map)))) {
858 map = &enp->en_arch.ef10.ena_pio_alloc_map[bufnum];
859 if ((*map & (1u << blknum)) == 0) {
863 *map &= ~(1u << blknum);
870 EFSYS_PROBE1(fail1, efx_rc_t, rc);
875 __checkReturn efx_rc_t
877 __inout efx_nic_t *enp,
878 __in uint32_t vi_index,
879 __in efx_piobuf_handle_t handle)
881 return (efx_mcdi_link_piobuf(enp, vi_index, handle));
884 __checkReturn efx_rc_t
886 __inout efx_nic_t *enp,
887 __in uint32_t vi_index)
889 return (efx_mcdi_unlink_piobuf(enp, vi_index));
892 __checkReturn efx_rc_t
893 ef10_get_datapath_caps(
896 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
897 efx_dword_t datapath_capabilities;
898 efx_dword_t datapath_capabilities_v2;
901 if ((rc = efx_mcdi_get_capabilities(enp, &datapath_capabilities,
902 &datapath_capabilities_v2)) != 0)
906 * Huntington RXDP firmware inserts a 0 or 14 byte prefix.
907 * We only support the 14 byte prefix here.
909 if (MCDI_CMD_DWORD_FIELD(&datapath_capabilities,
910 GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14) != 1) {
914 encp->enc_rx_prefix_size = 14;
916 /* Check if the firmware supports TSO */
917 if (MCDI_CMD_DWORD_FIELD(&datapath_capabilities,
918 GET_CAPABILITIES_OUT_TX_TSO) == 1)
919 encp->enc_fw_assisted_tso_enabled = B_TRUE;
921 encp->enc_fw_assisted_tso_enabled = B_FALSE;
923 /* Check if the firmware has vadapter/vport/vswitch support */
924 if (MCDI_CMD_DWORD_FIELD(&datapath_capabilities,
925 GET_CAPABILITIES_OUT_EVB) == 1)
926 encp->enc_datapath_cap_evb = B_TRUE;
928 encp->enc_datapath_cap_evb = B_FALSE;
930 /* Check if the firmware supports VLAN insertion */
931 if (MCDI_CMD_DWORD_FIELD(&datapath_capabilities,
932 GET_CAPABILITIES_OUT_TX_VLAN_INSERTION) == 1)
933 encp->enc_hw_tx_insert_vlan_enabled = B_TRUE;
935 encp->enc_hw_tx_insert_vlan_enabled = B_FALSE;
937 /* Check if the firmware supports RX event batching */
938 if (MCDI_CMD_DWORD_FIELD(&datapath_capabilities,
939 GET_CAPABILITIES_OUT_RX_BATCHING) == 1) {
940 encp->enc_rx_batching_enabled = B_TRUE;
941 encp->enc_rx_batch_max = 16;
943 encp->enc_rx_batching_enabled = B_FALSE;
946 /* Check if the firmware supports disabling scatter on RXQs */
947 if (MCDI_CMD_DWORD_FIELD(&datapath_capabilities,
948 GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER) == 1) {
949 encp->enc_rx_disable_scatter_supported = B_TRUE;
951 encp->enc_rx_disable_scatter_supported = B_FALSE;
954 /* Check if the firmware supports set mac with running filters */
955 if (MCDI_CMD_DWORD_FIELD(&datapath_capabilities,
956 GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED)
958 encp->enc_allow_set_mac_with_installed_filters = B_TRUE;
960 encp->enc_allow_set_mac_with_installed_filters = B_FALSE;
968 EFSYS_PROBE1(fail1, efx_rc_t, rc);
974 * The external port mapping is a one-based numbering of the external
975 * connectors on the board. It does not distinguish off-board separated
976 * outputs such as multi-headed cables.
977 * The number of ports that map to each external port connector
978 * on the board is determined by the chip family and the port modes to
979 * which the NIC can be configured. The mapping table lists modes with
980 * port numbering requirements in increasing order.
986 } __ef10_external_port_mappings[] = {
987 /* Supported modes requiring 1 output per port */
989 EFX_FAMILY_HUNTINGTON,
990 (1 << TLV_PORT_MODE_10G) |
991 (1 << TLV_PORT_MODE_10G_10G) |
992 (1 << TLV_PORT_MODE_10G_10G_10G_10G),
997 (1 << TLV_PORT_MODE_10G) |
998 (1 << TLV_PORT_MODE_10G_10G) |
999 (1 << TLV_PORT_MODE_10G_10G_10G_10G),
1002 /* Supported modes requiring 2 outputs per port */
1004 EFX_FAMILY_HUNTINGTON,
1005 (1 << TLV_PORT_MODE_40G) |
1006 (1 << TLV_PORT_MODE_40G_40G) |
1007 (1 << TLV_PORT_MODE_40G_10G_10G) |
1008 (1 << TLV_PORT_MODE_10G_10G_40G),
1013 (1 << TLV_PORT_MODE_40G) |
1014 (1 << TLV_PORT_MODE_40G_40G) |
1015 (1 << TLV_PORT_MODE_40G_10G_10G) |
1016 (1 << TLV_PORT_MODE_10G_10G_40G),
1019 /* Supported modes requiring 4 outputs per port */
1022 (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q) |
1023 (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q2),
1028 __checkReturn efx_rc_t
1029 ef10_external_port_mapping(
1030 __in efx_nic_t *enp,
1032 __out uint8_t *external_portp)
1036 uint32_t port_modes;
1038 uint32_t stride = 1; /* default 1-1 mapping */
1040 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes)) != 0) {
1041 /* No port mode information available - use default mapping */
1046 * Infer the internal port -> external port mapping from
1047 * the possible port modes for this NIC.
1049 for (i = 0; i < EFX_ARRAY_SIZE(__ef10_external_port_mappings); ++i) {
1050 if (__ef10_external_port_mappings[i].family !=
1053 matches = (__ef10_external_port_mappings[i].modes_mask &
1056 stride = __ef10_external_port_mappings[i].stride;
1057 port_modes &= ~matches;
1061 if (port_modes != 0) {
1062 /* Some advertised modes are not supported */
1069 * Scale as required by last matched mode and then convert to
1070 * one-based numbering
1072 *external_portp = (uint8_t)(port / stride) + 1;
1076 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1081 __checkReturn efx_rc_t
1083 __in efx_nic_t *enp)
1085 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
1086 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1087 uint8_t mac_addr[6];
1088 uint32_t board_type = 0;
1089 hunt_link_state_t hls;
1090 efx_port_t *epp = &(enp->en_port);
1097 uint32_t base, nvec;
1100 if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
1104 * NOTE: The MCDI protocol numbers ports from zero.
1105 * The common code MCDI interface numbers ports from one.
1107 emip->emi_port = port + 1;
1109 if ((rc = ef10_external_port_mapping(enp, port,
1110 &encp->enc_external_port)) != 0)
1114 * Get PCIe function number from firmware (used for
1115 * per-function privilege and dynamic config info).
1116 * - PCIe PF: pf = PF number, vf = 0xffff.
1117 * - PCIe VF: pf = parent PF, vf = VF number.
1119 if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
1125 /* MAC address for this function */
1126 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
1127 rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
1128 if ((rc == 0) && (mac_addr[0] & 0x02)) {
1130 * If the static config does not include a global MAC
1131 * address pool then the board may return a locally
1132 * administered MAC address (this should only happen on
1133 * incorrectly programmed boards).
1138 rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
1143 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
1145 /* Board configuration */
1146 rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
1148 /* Unprivileged functions may not be able to read board cfg */
1155 encp->enc_board_type = board_type;
1156 encp->enc_clk_mult = 1; /* not used for Huntington */
1158 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
1159 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
1162 /* Obtain the default PHY advertised capabilities */
1163 if ((rc = hunt_phy_get_link(enp, &hls)) != 0)
1165 epp->ep_default_adv_cap_mask = hls.hls_adv_cap_mask;
1166 epp->ep_adv_cap_mask = hls.hls_adv_cap_mask;
1169 * Enable firmware workarounds for hardware errata.
1170 * Expected responses are:
1172 * Success: workaround enabled or disabled as requested.
1173 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
1174 * Firmware does not support the MC_CMD_WORKAROUND request.
1175 * (assume that the workaround is not supported).
1176 * - MC_CMD_ERR_ENOENT (reported as ENOENT):
1177 * Firmware does not support the requested workaround.
1178 * - MC_CMD_ERR_EPERM (reported as EACCES):
1179 * Unprivileged function cannot enable/disable workarounds.
1181 * See efx_mcdi_request_errcode() for MCDI error translations.
1185 * If the bug35388 workaround is enabled, then use an indirect access
1186 * method to avoid unsafe EVQ writes.
1188 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG35388, B_TRUE,
1190 if ((rc == 0) || (rc == EACCES))
1191 encp->enc_bug35388_workaround = B_TRUE;
1192 else if ((rc == ENOTSUP) || (rc == ENOENT))
1193 encp->enc_bug35388_workaround = B_FALSE;
1198 * If the bug41750 workaround is enabled, then do not test interrupts,
1199 * as the test will fail (seen with Greenport controllers).
1201 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG41750, B_TRUE,
1204 encp->enc_bug41750_workaround = B_TRUE;
1205 } else if (rc == EACCES) {
1206 /* Assume a controller with 40G ports needs the workaround. */
1207 if (epp->ep_default_adv_cap_mask & EFX_PHY_CAP_40000FDX)
1208 encp->enc_bug41750_workaround = B_TRUE;
1210 encp->enc_bug41750_workaround = B_FALSE;
1211 } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
1212 encp->enc_bug41750_workaround = B_FALSE;
1216 if (EFX_PCI_FUNCTION_IS_VF(encp)) {
1217 /* Interrupt testing does not work for VFs. See bug50084. */
1218 encp->enc_bug41750_workaround = B_TRUE;
1222 * If the bug26807 workaround is enabled, then firmware has enabled
1223 * support for chained multicast filters. Firmware will reset (FLR)
1224 * functions which have filters in the hardware filter table when the
1225 * workaround is enabled/disabled.
1227 * We must recheck if the workaround is enabled after inserting the
1228 * first hardware filter, in case it has been changed since this check.
1230 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG26807,
1233 encp->enc_bug26807_workaround = B_TRUE;
1234 if (flags & (1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN)) {
1236 * Other functions had installed filters before the
1237 * workaround was enabled, and they have been reset
1240 EFSYS_PROBE(bug26807_workaround_flr_done);
1241 /* FIXME: bump MC warm boot count ? */
1243 } else if (rc == EACCES) {
1245 * Unprivileged functions cannot enable the workaround in older
1248 encp->enc_bug26807_workaround = B_FALSE;
1249 } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
1250 encp->enc_bug26807_workaround = B_FALSE;
1255 /* Get sysclk frequency (in MHz). */
1256 if ((rc = efx_mcdi_get_clock(enp, &sysclk)) != 0)
1260 * The timer quantum is 1536 sysclk cycles, documented for the
1261 * EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
1263 encp->enc_evq_timer_quantum_ns = 1536000UL / sysclk; /* 1536 cycles */
1264 if (encp->enc_bug35388_workaround) {
1265 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
1266 ERF_DD_EVQ_IND_TIMER_VAL_WIDTH) / 1000;
1268 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
1269 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
1272 /* Check capabilities of running datapath firmware */
1273 if ((rc = ef10_get_datapath_caps(enp)) != 0)
1276 /* Alignment for receive packet DMA buffers */
1277 encp->enc_rx_buf_align_start = 1;
1278 encp->enc_rx_buf_align_end = 64; /* RX DMA end padding */
1280 /* Alignment for WPTR updates */
1281 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
1284 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
1285 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
1286 * resources (allocated to this PCIe function), which is zero until
1287 * after we have allocated VIs.
1289 encp->enc_evq_limit = 1024;
1290 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
1291 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
1293 encp->enc_buftbl_limit = 0xFFFFFFFF;
1295 encp->enc_piobuf_limit = HUNT_PIOBUF_NBUFS;
1296 encp->enc_piobuf_size = HUNT_PIOBUF_SIZE;
1297 encp->enc_piobuf_min_alloc_size = HUNT_MIN_PIO_ALLOC_SIZE;
1300 * Get the current privilege mask. Note that this may be modified
1301 * dynamically, so this value is informational only. DO NOT use
1302 * the privilege mask to check for sufficient privileges, as that
1303 * can result in time-of-check/time-of-use bugs.
1305 if ((rc = efx_mcdi_privilege_mask(enp, pf, vf, &mask)) != 0) {
1309 /* Fallback for old firmware without privilege mask support */
1310 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
1311 /* Assume PF has admin privilege */
1312 mask = HUNT_LEGACY_PF_PRIVILEGE_MASK;
1314 /* VF is always unprivileged by default */
1315 mask = HUNT_LEGACY_VF_PRIVILEGE_MASK;
1319 encp->enc_privilege_mask = mask;
1321 /* Get interrupt vector limits */
1322 if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
1323 if (EFX_PCI_FUNCTION_IS_PF(encp))
1326 /* Ignore error (cannot query vector limits from a VF). */
1330 encp->enc_intr_vec_base = base;
1331 encp->enc_intr_limit = nvec;
1334 * Maximum number of bytes into the frame the TCP header can start for
1335 * firmware assisted TSO to work.
1337 encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
1342 EFSYS_PROBE(fail14);
1344 EFSYS_PROBE(fail13);
1346 EFSYS_PROBE(fail12);
1348 EFSYS_PROBE(fail11);
1350 EFSYS_PROBE(fail10);
1368 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1374 __checkReturn efx_rc_t
1376 __in efx_nic_t *enp)
1378 efx_nic_ops_t *enop = enp->en_enop;
1379 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1380 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1383 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1384 enp->en_family == EFX_FAMILY_MEDFORD);
1386 /* Read and clear any assertion state */
1387 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
1390 /* Exit the assertion handler */
1391 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
1395 if ((rc = efx_mcdi_drv_attach(enp, B_TRUE)) != 0)
1398 if ((rc = enop->eno_board_cfg(enp)) != 0)
1403 * Set default driver config limits (based on board config).
1405 * FIXME: For now allocate a fixed number of VIs which is likely to be
1406 * sufficient and small enough to allow multiple functions on the same
1409 edcp->edc_min_vi_count = edcp->edc_max_vi_count =
1410 MIN(128, MAX(encp->enc_rxq_limit, encp->enc_txq_limit));
1412 /* The client driver must configure and enable PIO buffer support */
1413 edcp->edc_max_piobuf_count = 0;
1414 edcp->edc_pio_alloc_size = 0;
1416 #if EFSYS_OPT_MAC_STATS
1417 /* Wipe the MAC statistics */
1418 if ((rc = efx_mcdi_mac_stats_clear(enp)) != 0)
1422 #if EFSYS_OPT_LOOPBACK
1423 if ((rc = efx_mcdi_get_loopback_modes(enp)) != 0)
1427 #if EFSYS_OPT_MON_STATS
1428 if ((rc = mcdi_mon_cfg_build(enp)) != 0) {
1429 /* Unprivileged functions do not have access to sensors */
1435 encp->enc_features = enp->en_features;
1439 #if EFSYS_OPT_MON_STATS
1443 #if EFSYS_OPT_LOOPBACK
1447 #if EFSYS_OPT_MAC_STATS
1458 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1463 __checkReturn efx_rc_t
1464 ef10_nic_set_drv_limits(
1465 __inout efx_nic_t *enp,
1466 __in efx_drv_limits_t *edlp)
1468 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1469 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1470 uint32_t min_evq_count, max_evq_count;
1471 uint32_t min_rxq_count, max_rxq_count;
1472 uint32_t min_txq_count, max_txq_count;
1480 /* Get minimum required and maximum usable VI limits */
1481 min_evq_count = MIN(edlp->edl_min_evq_count, encp->enc_evq_limit);
1482 min_rxq_count = MIN(edlp->edl_min_rxq_count, encp->enc_rxq_limit);
1483 min_txq_count = MIN(edlp->edl_min_txq_count, encp->enc_txq_limit);
1485 edcp->edc_min_vi_count =
1486 MAX(min_evq_count, MAX(min_rxq_count, min_txq_count));
1488 max_evq_count = MIN(edlp->edl_max_evq_count, encp->enc_evq_limit);
1489 max_rxq_count = MIN(edlp->edl_max_rxq_count, encp->enc_rxq_limit);
1490 max_txq_count = MIN(edlp->edl_max_txq_count, encp->enc_txq_limit);
1492 edcp->edc_max_vi_count =
1493 MAX(max_evq_count, MAX(max_rxq_count, max_txq_count));
1496 * Check limits for sub-allocated piobuf blocks.
1497 * PIO is optional, so don't fail if the limits are incorrect.
1499 if ((encp->enc_piobuf_size == 0) ||
1500 (encp->enc_piobuf_limit == 0) ||
1501 (edlp->edl_min_pio_alloc_size == 0) ||
1502 (edlp->edl_min_pio_alloc_size > encp->enc_piobuf_size)) {
1504 edcp->edc_max_piobuf_count = 0;
1505 edcp->edc_pio_alloc_size = 0;
1507 uint32_t blk_size, blk_count, blks_per_piobuf;
1510 MAX(edlp->edl_min_pio_alloc_size,
1511 encp->enc_piobuf_min_alloc_size);
1513 blks_per_piobuf = encp->enc_piobuf_size / blk_size;
1514 EFSYS_ASSERT3U(blks_per_piobuf, <=, 32);
1516 blk_count = (encp->enc_piobuf_limit * blks_per_piobuf);
1518 /* A zero max pio alloc count means unlimited */
1519 if ((edlp->edl_max_pio_alloc_count > 0) &&
1520 (edlp->edl_max_pio_alloc_count < blk_count)) {
1521 blk_count = edlp->edl_max_pio_alloc_count;
1524 edcp->edc_pio_alloc_size = blk_size;
1525 edcp->edc_max_piobuf_count =
1526 (blk_count + (blks_per_piobuf - 1)) / blks_per_piobuf;
1532 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1538 __checkReturn efx_rc_t
1540 __in efx_nic_t *enp)
1543 uint8_t payload[MAX(MC_CMD_ENTITY_RESET_IN_LEN,
1544 MC_CMD_ENTITY_RESET_OUT_LEN)];
1547 /* ef10_nic_reset() is called to recover from BADASSERT failures. */
1548 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
1550 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
1553 (void) memset(payload, 0, sizeof (payload));
1554 req.emr_cmd = MC_CMD_ENTITY_RESET;
1555 req.emr_in_buf = payload;
1556 req.emr_in_length = MC_CMD_ENTITY_RESET_IN_LEN;
1557 req.emr_out_buf = payload;
1558 req.emr_out_length = MC_CMD_ENTITY_RESET_OUT_LEN;
1560 MCDI_IN_POPULATE_DWORD_1(req, ENTITY_RESET_IN_FLAG,
1561 ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET, 1);
1563 efx_mcdi_execute(enp, &req);
1565 if (req.emr_rc != 0) {
1570 /* Clear RX/TX DMA queue errors */
1571 enp->en_reset_flags &= ~(EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR);
1580 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1585 __checkReturn efx_rc_t
1587 __in efx_nic_t *enp)
1589 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1590 uint32_t min_vi_count, max_vi_count;
1591 uint32_t vi_count, vi_base, vi_shift;
1597 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1598 enp->en_family == EFX_FAMILY_MEDFORD);
1600 /* Enable reporting of some events (e.g. link change) */
1601 if ((rc = efx_mcdi_log_ctrl(enp)) != 0)
1604 /* Allocate (optional) on-chip PIO buffers */
1605 ef10_nic_alloc_piobufs(enp, edcp->edc_max_piobuf_count);
1608 * For best performance, PIO writes should use a write-combined
1609 * (WC) memory mapping. Using a separate WC mapping for the PIO
1610 * aperture of each VI would be a burden to drivers (and not
1611 * possible if the host page size is >4Kbyte).
1613 * To avoid this we use a single uncached (UC) mapping for VI
1614 * register access, and a single WC mapping for extra VIs used
1617 * Each piobuf must be linked to a VI in the WC mapping, and to
1618 * each VI that is using a sub-allocated block from the piobuf.
1620 min_vi_count = edcp->edc_min_vi_count;
1622 edcp->edc_max_vi_count + enp->en_arch.ef10.ena_piobuf_count;
1624 /* Ensure that the previously attached driver's VIs are freed */
1625 if ((rc = efx_mcdi_free_vis(enp)) != 0)
1629 * Reserve VI resources (EVQ+RXQ+TXQ) for this PCIe function. If this
1630 * fails then retrying the request for fewer VI resources may succeed.
1633 if ((rc = efx_mcdi_alloc_vis(enp, min_vi_count, max_vi_count,
1634 &vi_base, &vi_count, &vi_shift)) != 0)
1637 EFSYS_PROBE2(vi_alloc, uint32_t, vi_base, uint32_t, vi_count);
1639 if (vi_count < min_vi_count) {
1644 enp->en_arch.ef10.ena_vi_base = vi_base;
1645 enp->en_arch.ef10.ena_vi_count = vi_count;
1646 enp->en_arch.ef10.ena_vi_shift = vi_shift;
1648 if (vi_count < min_vi_count + enp->en_arch.ef10.ena_piobuf_count) {
1649 /* Not enough extra VIs to map piobufs */
1650 ef10_nic_free_piobufs(enp);
1653 enp->en_arch.ef10.ena_pio_write_vi_base =
1654 vi_count - enp->en_arch.ef10.ena_piobuf_count;
1656 /* Save UC memory mapping details */
1657 enp->en_arch.ef10.ena_uc_mem_map_offset = 0;
1658 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
1659 enp->en_arch.ef10.ena_uc_mem_map_size =
1660 (ER_DZ_TX_PIOBUF_STEP *
1661 enp->en_arch.ef10.ena_pio_write_vi_base);
1663 enp->en_arch.ef10.ena_uc_mem_map_size =
1664 (ER_DZ_TX_PIOBUF_STEP *
1665 enp->en_arch.ef10.ena_vi_count);
1668 /* Save WC memory mapping details */
1669 enp->en_arch.ef10.ena_wc_mem_map_offset =
1670 enp->en_arch.ef10.ena_uc_mem_map_offset +
1671 enp->en_arch.ef10.ena_uc_mem_map_size;
1673 enp->en_arch.ef10.ena_wc_mem_map_size =
1674 (ER_DZ_TX_PIOBUF_STEP *
1675 enp->en_arch.ef10.ena_piobuf_count);
1677 /* Link piobufs to extra VIs in WC mapping */
1678 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
1679 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
1680 rc = efx_mcdi_link_piobuf(enp,
1681 enp->en_arch.ef10.ena_pio_write_vi_base + i,
1682 enp->en_arch.ef10.ena_piobuf_handle[i]);
1689 * Allocate a vAdaptor attached to our upstream vPort/pPort.
1691 * On a VF, this may fail with MC_CMD_ERR_NO_EVB_PORT (ENOENT) if the PF
1692 * driver has yet to bring up the EVB port. See bug 56147. In this case,
1693 * retry the request several times after waiting a while. The wait time
1694 * between retries starts small (10ms) and exponentially increases.
1695 * Total wait time is a little over two seconds. Retry logic in the
1696 * client driver may mean this whole loop is repeated if it continues to
1701 while ((rc = efx_mcdi_vadaptor_alloc(enp, EVB_PORT_ID_ASSIGNED)) != 0) {
1702 if (EFX_PCI_FUNCTION_IS_PF(&enp->en_nic_cfg) ||
1705 * Do not retry alloc for PF, or for other errors on
1711 /* VF startup before PF is ready. Retry allocation. */
1713 /* Too many attempts */
1717 EFSYS_PROBE1(mcdi_no_evb_port_retry, int, retry);
1718 EFSYS_SLEEP(delay_us);
1720 if (delay_us < 500000)
1724 enp->en_vport_id = EVB_PORT_ID_ASSIGNED;
1725 enp->en_nic_cfg.enc_mcdi_max_payload_length = MCDI_CTL_SDU_LEN_MAX_V2;
1740 ef10_nic_free_piobufs(enp);
1743 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1748 __checkReturn efx_rc_t
1749 ef10_nic_get_vi_pool(
1750 __in efx_nic_t *enp,
1751 __out uint32_t *vi_countp)
1753 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1754 enp->en_family == EFX_FAMILY_MEDFORD);
1757 * Report VIs that the client driver can use.
1758 * Do not include VIs used for PIO buffer writes.
1760 *vi_countp = enp->en_arch.ef10.ena_pio_write_vi_base;
1765 __checkReturn efx_rc_t
1766 ef10_nic_get_bar_region(
1767 __in efx_nic_t *enp,
1768 __in efx_nic_region_t region,
1769 __out uint32_t *offsetp,
1770 __out size_t *sizep)
1774 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1775 enp->en_family == EFX_FAMILY_MEDFORD);
1778 * TODO: Specify host memory mapping alignment and granularity
1779 * in efx_drv_limits_t so that they can be taken into account
1780 * when allocating extra VIs for PIO writes.
1784 /* UC mapped memory BAR region for VI registers */
1785 *offsetp = enp->en_arch.ef10.ena_uc_mem_map_offset;
1786 *sizep = enp->en_arch.ef10.ena_uc_mem_map_size;
1789 case EFX_REGION_PIO_WRITE_VI:
1790 /* WC mapped memory BAR region for piobuf writes */
1791 *offsetp = enp->en_arch.ef10.ena_wc_mem_map_offset;
1792 *sizep = enp->en_arch.ef10.ena_wc_mem_map_size;
1803 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1810 __in efx_nic_t *enp)
1815 (void) efx_mcdi_vadaptor_free(enp, enp->en_vport_id);
1816 enp->en_vport_id = 0;
1818 /* Unlink piobufs from extra VIs in WC mapping */
1819 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
1820 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
1821 rc = efx_mcdi_unlink_piobuf(enp,
1822 enp->en_arch.ef10.ena_pio_write_vi_base + i);
1828 ef10_nic_free_piobufs(enp);
1830 (void) efx_mcdi_free_vis(enp);
1831 enp->en_arch.ef10.ena_vi_count = 0;
1836 __in efx_nic_t *enp)
1838 #if EFSYS_OPT_MON_STATS
1839 mcdi_mon_cfg_free(enp);
1840 #endif /* EFSYS_OPT_MON_STATS */
1841 (void) efx_mcdi_drv_attach(enp, B_FALSE);
1846 __checkReturn efx_rc_t
1847 ef10_nic_register_test(
1848 __in efx_nic_t *enp)
1853 _NOTE(ARGUNUSED(enp))
1863 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1868 #endif /* EFSYS_OPT_DIAG */
1872 #endif /* EFSYS_OPT_HUNTINGTON */