2 * Copyright (c) 2012-2015 Solarflare Communications Inc.
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6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
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11 * this list of conditions and the following disclaimer in the documentation
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14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
36 #if EFSYS_OPT_MON_MCDI
40 #if EFSYS_OPT_HUNTINGTON
43 __checkReturn efx_rc_t
47 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
48 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
50 uint32_t board_type = 0;
51 ef10_link_state_t els;
52 efx_port_t *epp = &(enp->en_port);
62 if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
66 * NOTE: The MCDI protocol numbers ports from zero.
67 * The common code MCDI interface numbers ports from one.
69 emip->emi_port = port + 1;
71 if ((rc = ef10_external_port_mapping(enp, port,
72 &encp->enc_external_port)) != 0)
76 * Get PCIe function number from firmware (used for
77 * per-function privilege and dynamic config info).
78 * - PCIe PF: pf = PF number, vf = 0xffff.
79 * - PCIe VF: pf = parent PF, vf = VF number.
81 if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
87 /* MAC address for this function */
88 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
89 rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
90 if ((rc == 0) && (mac_addr[0] & 0x02)) {
92 * If the static config does not include a global MAC
93 * address pool then the board may return a locally
94 * administered MAC address (this should only happen on
95 * incorrectly programmed boards).
100 rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
105 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
107 /* Board configuration */
108 rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
110 /* Unprivileged functions may not be able to read board cfg */
117 encp->enc_board_type = board_type;
118 encp->enc_clk_mult = 1; /* not used for Huntington */
120 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
121 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
124 /* Obtain the default PHY advertised capabilities */
125 if ((rc = ef10_phy_get_link(enp, &els)) != 0)
127 epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
128 epp->ep_adv_cap_mask = els.els_adv_cap_mask;
131 * Enable firmware workarounds for hardware errata.
132 * Expected responses are:
134 * Success: workaround enabled or disabled as requested.
135 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
136 * Firmware does not support the MC_CMD_WORKAROUND request.
137 * (assume that the workaround is not supported).
138 * - MC_CMD_ERR_ENOENT (reported as ENOENT):
139 * Firmware does not support the requested workaround.
140 * - MC_CMD_ERR_EPERM (reported as EACCES):
141 * Unprivileged function cannot enable/disable workarounds.
143 * See efx_mcdi_request_errcode() for MCDI error translations.
147 * If the bug35388 workaround is enabled, then use an indirect access
148 * method to avoid unsafe EVQ writes.
150 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG35388, B_TRUE,
152 if ((rc == 0) || (rc == EACCES))
153 encp->enc_bug35388_workaround = B_TRUE;
154 else if ((rc == ENOTSUP) || (rc == ENOENT))
155 encp->enc_bug35388_workaround = B_FALSE;
160 * If the bug41750 workaround is enabled, then do not test interrupts,
161 * as the test will fail (seen with Greenport controllers).
163 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG41750, B_TRUE,
166 encp->enc_bug41750_workaround = B_TRUE;
167 } else if (rc == EACCES) {
168 /* Assume a controller with 40G ports needs the workaround. */
169 if (epp->ep_default_adv_cap_mask & EFX_PHY_CAP_40000FDX)
170 encp->enc_bug41750_workaround = B_TRUE;
172 encp->enc_bug41750_workaround = B_FALSE;
173 } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
174 encp->enc_bug41750_workaround = B_FALSE;
178 if (EFX_PCI_FUNCTION_IS_VF(encp)) {
179 /* Interrupt testing does not work for VFs. See bug50084. */
180 encp->enc_bug41750_workaround = B_TRUE;
184 * If the bug26807 workaround is enabled, then firmware has enabled
185 * support for chained multicast filters. Firmware will reset (FLR)
186 * functions which have filters in the hardware filter table when the
187 * workaround is enabled/disabled.
189 * We must recheck if the workaround is enabled after inserting the
190 * first hardware filter, in case it has been changed since this check.
192 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG26807,
195 encp->enc_bug26807_workaround = B_TRUE;
196 if (flags & (1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN)) {
198 * Other functions had installed filters before the
199 * workaround was enabled, and they have been reset
202 EFSYS_PROBE(bug26807_workaround_flr_done);
203 /* FIXME: bump MC warm boot count ? */
205 } else if (rc == EACCES) {
207 * Unprivileged functions cannot enable the workaround in older
210 encp->enc_bug26807_workaround = B_FALSE;
211 } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
212 encp->enc_bug26807_workaround = B_FALSE;
217 /* Get sysclk frequency (in MHz). */
218 if ((rc = efx_mcdi_get_clock(enp, &sysclk)) != 0)
222 * The timer quantum is 1536 sysclk cycles, documented for the
223 * EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
225 encp->enc_evq_timer_quantum_ns = 1536000UL / sysclk; /* 1536 cycles */
226 if (encp->enc_bug35388_workaround) {
227 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
228 ERF_DD_EVQ_IND_TIMER_VAL_WIDTH) / 1000;
230 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
231 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
234 /* Check capabilities of running datapath firmware */
235 if ((rc = ef10_get_datapath_caps(enp)) != 0)
238 /* Alignment for receive packet DMA buffers */
239 encp->enc_rx_buf_align_start = 1;
240 encp->enc_rx_buf_align_end = 64; /* RX DMA end padding */
242 /* Alignment for WPTR updates */
243 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
246 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
247 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
248 * resources (allocated to this PCIe function), which is zero until
249 * after we have allocated VIs.
251 encp->enc_evq_limit = 1024;
252 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
253 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
255 encp->enc_buftbl_limit = 0xFFFFFFFF;
257 encp->enc_piobuf_limit = HUNT_PIOBUF_NBUFS;
258 encp->enc_piobuf_size = HUNT_PIOBUF_SIZE;
259 encp->enc_piobuf_min_alloc_size = HUNT_MIN_PIO_ALLOC_SIZE;
262 * Get the current privilege mask. Note that this may be modified
263 * dynamically, so this value is informational only. DO NOT use
264 * the privilege mask to check for sufficient privileges, as that
265 * can result in time-of-check/time-of-use bugs.
267 if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
269 encp->enc_privilege_mask = mask;
271 /* Get interrupt vector limits */
272 if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
273 if (EFX_PCI_FUNCTION_IS_PF(encp))
276 /* Ignore error (cannot query vector limits from a VF). */
280 encp->enc_intr_vec_base = base;
281 encp->enc_intr_limit = nvec;
284 * Maximum number of bytes into the frame the TCP header can start for
285 * firmware assisted TSO to work.
287 encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
318 EFSYS_PROBE1(fail1, efx_rc_t, rc);
324 #endif /* EFSYS_OPT_HUNTINGTON */