2 * Copyright (c) 2012-2015 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
39 #if EFSYS_OPT_HUNTINGTON
41 #include "ef10_tlv_layout.h"
43 static __checkReturn efx_rc_t
44 efx_mcdi_get_port_assignment(
46 __out uint32_t *portp)
49 uint8_t payload[MAX(MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN,
50 MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN)];
53 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON);
55 (void) memset(payload, 0, sizeof (payload));
56 req.emr_cmd = MC_CMD_GET_PORT_ASSIGNMENT;
57 req.emr_in_buf = payload;
58 req.emr_in_length = MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN;
59 req.emr_out_buf = payload;
60 req.emr_out_length = MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN;
62 efx_mcdi_execute(enp, &req);
64 if (req.emr_rc != 0) {
69 if (req.emr_out_length_used < MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN) {
74 *portp = MCDI_OUT_DWORD(req, GET_PORT_ASSIGNMENT_OUT_PORT);
81 EFSYS_PROBE1(fail1, efx_rc_t, rc);
86 static __checkReturn efx_rc_t
87 efx_mcdi_get_port_modes(
89 __out uint32_t *modesp)
92 uint8_t payload[MAX(MC_CMD_GET_PORT_MODES_IN_LEN,
93 MC_CMD_GET_PORT_MODES_OUT_LEN)];
96 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON);
98 (void) memset(payload, 0, sizeof (payload));
99 req.emr_cmd = MC_CMD_GET_PORT_MODES;
100 req.emr_in_buf = payload;
101 req.emr_in_length = MC_CMD_GET_PORT_MODES_IN_LEN;
102 req.emr_out_buf = payload;
103 req.emr_out_length = MC_CMD_GET_PORT_MODES_OUT_LEN;
105 efx_mcdi_execute(enp, &req);
107 if (req.emr_rc != 0) {
112 /* Accept pre-Medford size (8 bytes - no CurrentMode field) */
113 if (req.emr_out_length_used <
114 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST) {
119 *modesp = MCDI_OUT_DWORD(req, GET_PORT_MODES_OUT_MODES);
126 EFSYS_PROBE1(fail1, efx_rc_t, rc);
132 static __checkReturn efx_rc_t
133 efx_mcdi_vadaptor_alloc(
135 __in uint32_t port_id)
138 uint8_t payload[MAX(MC_CMD_VADAPTOR_ALLOC_IN_LEN,
139 MC_CMD_VADAPTOR_ALLOC_OUT_LEN)];
142 EFSYS_ASSERT3U(enp->en_vport_id, ==, EVB_PORT_ID_NULL);
144 (void) memset(payload, 0, sizeof (payload));
145 req.emr_cmd = MC_CMD_VADAPTOR_ALLOC;
146 req.emr_in_buf = payload;
147 req.emr_in_length = MC_CMD_VADAPTOR_ALLOC_IN_LEN;
148 req.emr_out_buf = payload;
149 req.emr_out_length = MC_CMD_VADAPTOR_ALLOC_OUT_LEN;
151 MCDI_IN_SET_DWORD(req, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
153 efx_mcdi_execute(enp, &req);
155 if (req.emr_rc != 0) {
163 EFSYS_PROBE1(fail1, efx_rc_t, rc);
168 static __checkReturn efx_rc_t
169 efx_mcdi_vadaptor_free(
171 __in uint32_t port_id)
174 uint8_t payload[MAX(MC_CMD_VADAPTOR_FREE_IN_LEN,
175 MC_CMD_VADAPTOR_FREE_OUT_LEN)];
178 (void) memset(payload, 0, sizeof (payload));
179 req.emr_cmd = MC_CMD_VADAPTOR_FREE;
180 req.emr_in_buf = payload;
181 req.emr_in_length = MC_CMD_VADAPTOR_FREE_IN_LEN;
182 req.emr_out_buf = payload;
183 req.emr_out_length = MC_CMD_VADAPTOR_FREE_OUT_LEN;
185 MCDI_IN_SET_DWORD(req, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
187 efx_mcdi_execute(enp, &req);
189 if (req.emr_rc != 0) {
197 EFSYS_PROBE1(fail1, efx_rc_t, rc);
202 static __checkReturn efx_rc_t
203 efx_mcdi_get_mac_address_pf(
205 __out_ecount_opt(6) uint8_t mac_addrp[6])
208 uint8_t payload[MAX(MC_CMD_GET_MAC_ADDRESSES_IN_LEN,
209 MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)];
212 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON);
214 (void) memset(payload, 0, sizeof (payload));
215 req.emr_cmd = MC_CMD_GET_MAC_ADDRESSES;
216 req.emr_in_buf = payload;
217 req.emr_in_length = MC_CMD_GET_MAC_ADDRESSES_IN_LEN;
218 req.emr_out_buf = payload;
219 req.emr_out_length = MC_CMD_GET_MAC_ADDRESSES_OUT_LEN;
221 efx_mcdi_execute(enp, &req);
223 if (req.emr_rc != 0) {
228 if (req.emr_out_length_used < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) {
233 if (MCDI_OUT_DWORD(req, GET_MAC_ADDRESSES_OUT_MAC_COUNT) < 1) {
238 if (mac_addrp != NULL) {
241 addrp = MCDI_OUT2(req, uint8_t,
242 GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE);
244 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
254 EFSYS_PROBE1(fail1, efx_rc_t, rc);
259 static __checkReturn efx_rc_t
260 efx_mcdi_get_mac_address_vf(
262 __out_ecount_opt(6) uint8_t mac_addrp[6])
265 uint8_t payload[MAX(MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN,
266 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX)];
269 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON);
271 (void) memset(payload, 0, sizeof (payload));
272 req.emr_cmd = MC_CMD_VPORT_GET_MAC_ADDRESSES;
273 req.emr_in_buf = payload;
274 req.emr_in_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN;
275 req.emr_out_buf = payload;
276 req.emr_out_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX;
278 MCDI_IN_SET_DWORD(req, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
279 EVB_PORT_ID_ASSIGNED);
281 efx_mcdi_execute(enp, &req);
283 if (req.emr_rc != 0) {
288 if (req.emr_out_length_used <
289 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN) {
294 if (MCDI_OUT_DWORD(req,
295 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT) < 1) {
300 if (mac_addrp != NULL) {
303 addrp = MCDI_OUT2(req, uint8_t,
304 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR);
306 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
316 EFSYS_PROBE1(fail1, efx_rc_t, rc);
321 static __checkReturn efx_rc_t
324 __out uint32_t *sys_freqp)
327 uint8_t payload[MAX(MC_CMD_GET_CLOCK_IN_LEN,
328 MC_CMD_GET_CLOCK_OUT_LEN)];
331 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON);
333 (void) memset(payload, 0, sizeof (payload));
334 req.emr_cmd = MC_CMD_GET_CLOCK;
335 req.emr_in_buf = payload;
336 req.emr_in_length = MC_CMD_GET_CLOCK_IN_LEN;
337 req.emr_out_buf = payload;
338 req.emr_out_length = MC_CMD_GET_CLOCK_OUT_LEN;
340 efx_mcdi_execute(enp, &req);
342 if (req.emr_rc != 0) {
347 if (req.emr_out_length_used < MC_CMD_GET_CLOCK_OUT_LEN) {
352 *sys_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_SYS_FREQ);
353 if (*sys_freqp == 0) {
365 EFSYS_PROBE1(fail1, efx_rc_t, rc);
370 static __checkReturn efx_rc_t
371 efx_mcdi_get_vector_cfg(
373 __out_opt uint32_t *vec_basep,
374 __out_opt uint32_t *pf_nvecp,
375 __out_opt uint32_t *vf_nvecp)
378 uint8_t payload[MAX(MC_CMD_GET_VECTOR_CFG_IN_LEN,
379 MC_CMD_GET_VECTOR_CFG_OUT_LEN)];
382 (void) memset(payload, 0, sizeof (payload));
383 req.emr_cmd = MC_CMD_GET_VECTOR_CFG;
384 req.emr_in_buf = payload;
385 req.emr_in_length = MC_CMD_GET_VECTOR_CFG_IN_LEN;
386 req.emr_out_buf = payload;
387 req.emr_out_length = MC_CMD_GET_VECTOR_CFG_OUT_LEN;
389 efx_mcdi_execute(enp, &req);
391 if (req.emr_rc != 0) {
396 if (req.emr_out_length_used < MC_CMD_GET_VECTOR_CFG_OUT_LEN) {
401 if (vec_basep != NULL)
402 *vec_basep = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VEC_BASE);
403 if (pf_nvecp != NULL)
404 *pf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_PF);
405 if (vf_nvecp != NULL)
406 *vf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_VF);
413 EFSYS_PROBE1(fail1, efx_rc_t, rc);
418 static __checkReturn efx_rc_t
419 efx_mcdi_get_capabilities(
421 __out efx_dword_t *flagsp)
424 uint8_t payload[MAX(MC_CMD_GET_CAPABILITIES_IN_LEN,
425 MC_CMD_GET_CAPABILITIES_OUT_LEN)];
428 (void) memset(payload, 0, sizeof (payload));
429 req.emr_cmd = MC_CMD_GET_CAPABILITIES;
430 req.emr_in_buf = payload;
431 req.emr_in_length = MC_CMD_GET_CAPABILITIES_IN_LEN;
432 req.emr_out_buf = payload;
433 req.emr_out_length = MC_CMD_GET_CAPABILITIES_OUT_LEN;
435 efx_mcdi_execute(enp, &req);
437 if (req.emr_rc != 0) {
442 if (req.emr_out_length_used < MC_CMD_GET_CAPABILITIES_OUT_LEN) {
447 *flagsp = *MCDI_OUT2(req, efx_dword_t, GET_CAPABILITIES_OUT_FLAGS1);
454 EFSYS_PROBE1(fail1, efx_rc_t, rc);
460 static __checkReturn efx_rc_t
463 __in uint32_t min_vi_count,
464 __in uint32_t max_vi_count,
465 __out_opt uint32_t *vi_basep,
466 __out uint32_t *vi_countp)
470 uint8_t payload[MAX(MC_CMD_ALLOC_VIS_IN_LEN,
471 MC_CMD_ALLOC_VIS_OUT_LEN)];
474 if (vi_countp == NULL) {
479 (void) memset(payload, 0, sizeof (payload));
480 req.emr_cmd = MC_CMD_ALLOC_VIS;
481 req.emr_in_buf = payload;
482 req.emr_in_length = MC_CMD_ALLOC_VIS_IN_LEN;
483 req.emr_out_buf = payload;
484 req.emr_out_length = MC_CMD_ALLOC_VIS_OUT_LEN;
486 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MIN_VI_COUNT, min_vi_count);
487 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MAX_VI_COUNT, max_vi_count);
489 efx_mcdi_execute(enp, &req);
491 if (req.emr_rc != 0) {
496 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_OUT_LEN) {
501 if (vi_basep != NULL)
502 *vi_basep = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_BASE);
504 if (vi_countp != NULL)
505 *vi_countp = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_COUNT);
514 EFSYS_PROBE1(fail1, efx_rc_t, rc);
520 static __checkReturn efx_rc_t
527 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_IN_LEN == 0);
528 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_OUT_LEN == 0);
530 req.emr_cmd = MC_CMD_FREE_VIS;
531 req.emr_in_buf = NULL;
532 req.emr_in_length = 0;
533 req.emr_out_buf = NULL;
534 req.emr_out_length = 0;
536 efx_mcdi_execute_quiet(enp, &req);
538 /* Ignore ELREADY (no allocated VIs, so nothing to free) */
539 if ((req.emr_rc != 0) && (req.emr_rc != EALREADY)) {
547 EFSYS_PROBE1(fail1, efx_rc_t, rc);
553 static __checkReturn efx_rc_t
554 efx_mcdi_alloc_piobuf(
556 __out efx_piobuf_handle_t *handlep)
559 uint8_t payload[MAX(MC_CMD_ALLOC_PIOBUF_IN_LEN,
560 MC_CMD_ALLOC_PIOBUF_OUT_LEN)];
563 if (handlep == NULL) {
568 (void) memset(payload, 0, sizeof (payload));
569 req.emr_cmd = MC_CMD_ALLOC_PIOBUF;
570 req.emr_in_buf = payload;
571 req.emr_in_length = MC_CMD_ALLOC_PIOBUF_IN_LEN;
572 req.emr_out_buf = payload;
573 req.emr_out_length = MC_CMD_ALLOC_PIOBUF_OUT_LEN;
575 efx_mcdi_execute_quiet(enp, &req);
577 if (req.emr_rc != 0) {
582 if (req.emr_out_length_used < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
587 *handlep = MCDI_OUT_DWORD(req, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
596 EFSYS_PROBE1(fail1, efx_rc_t, rc);
601 static __checkReturn efx_rc_t
602 efx_mcdi_free_piobuf(
604 __in efx_piobuf_handle_t handle)
607 uint8_t payload[MAX(MC_CMD_FREE_PIOBUF_IN_LEN,
608 MC_CMD_FREE_PIOBUF_OUT_LEN)];
611 (void) memset(payload, 0, sizeof (payload));
612 req.emr_cmd = MC_CMD_FREE_PIOBUF;
613 req.emr_in_buf = payload;
614 req.emr_in_length = MC_CMD_FREE_PIOBUF_IN_LEN;
615 req.emr_out_buf = payload;
616 req.emr_out_length = MC_CMD_FREE_PIOBUF_OUT_LEN;
618 MCDI_IN_SET_DWORD(req, FREE_PIOBUF_IN_PIOBUF_HANDLE, handle);
620 efx_mcdi_execute_quiet(enp, &req);
622 if (req.emr_rc != 0) {
630 EFSYS_PROBE1(fail1, efx_rc_t, rc);
635 static __checkReturn efx_rc_t
636 efx_mcdi_link_piobuf(
638 __in uint32_t vi_index,
639 __in efx_piobuf_handle_t handle)
642 uint8_t payload[MAX(MC_CMD_LINK_PIOBUF_IN_LEN,
643 MC_CMD_LINK_PIOBUF_OUT_LEN)];
646 (void) memset(payload, 0, sizeof (payload));
647 req.emr_cmd = MC_CMD_LINK_PIOBUF;
648 req.emr_in_buf = payload;
649 req.emr_in_length = MC_CMD_LINK_PIOBUF_IN_LEN;
650 req.emr_out_buf = payload;
651 req.emr_out_length = MC_CMD_LINK_PIOBUF_OUT_LEN;
653 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_PIOBUF_HANDLE, handle);
654 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
656 efx_mcdi_execute(enp, &req);
658 if (req.emr_rc != 0) {
666 EFSYS_PROBE1(fail1, efx_rc_t, rc);
671 static __checkReturn efx_rc_t
672 efx_mcdi_unlink_piobuf(
674 __in uint32_t vi_index)
677 uint8_t payload[MAX(MC_CMD_UNLINK_PIOBUF_IN_LEN,
678 MC_CMD_UNLINK_PIOBUF_OUT_LEN)];
681 (void) memset(payload, 0, sizeof (payload));
682 req.emr_cmd = MC_CMD_UNLINK_PIOBUF;
683 req.emr_in_buf = payload;
684 req.emr_in_length = MC_CMD_UNLINK_PIOBUF_IN_LEN;
685 req.emr_out_buf = payload;
686 req.emr_out_length = MC_CMD_UNLINK_PIOBUF_OUT_LEN;
688 MCDI_IN_SET_DWORD(req, UNLINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
690 efx_mcdi_execute(enp, &req);
692 if (req.emr_rc != 0) {
700 EFSYS_PROBE1(fail1, efx_rc_t, rc);
706 hunt_nic_alloc_piobufs(
708 __in uint32_t max_piobuf_count)
710 efx_piobuf_handle_t *handlep;
714 EFSYS_ASSERT3U(max_piobuf_count, <=,
715 EFX_ARRAY_SIZE(enp->en_u.hunt.enu_piobuf_handle));
717 enp->en_u.hunt.enu_piobuf_count = 0;
719 for (i = 0; i < max_piobuf_count; i++) {
720 handlep = &enp->en_u.hunt.enu_piobuf_handle[i];
722 if ((rc = efx_mcdi_alloc_piobuf(enp, handlep)) != 0)
725 enp->en_u.hunt.enu_pio_alloc_map[i] = 0;
726 enp->en_u.hunt.enu_piobuf_count++;
732 for (i = 0; i < enp->en_u.hunt.enu_piobuf_count; i++) {
733 handlep = &enp->en_u.hunt.enu_piobuf_handle[i];
735 efx_mcdi_free_piobuf(enp, *handlep);
736 *handlep = EFX_PIOBUF_HANDLE_INVALID;
738 enp->en_u.hunt.enu_piobuf_count = 0;
743 hunt_nic_free_piobufs(
746 efx_piobuf_handle_t *handlep;
749 for (i = 0; i < enp->en_u.hunt.enu_piobuf_count; i++) {
750 handlep = &enp->en_u.hunt.enu_piobuf_handle[i];
752 efx_mcdi_free_piobuf(enp, *handlep);
753 *handlep = EFX_PIOBUF_HANDLE_INVALID;
755 enp->en_u.hunt.enu_piobuf_count = 0;
758 /* Sub-allocate a block from a piobuf */
759 __checkReturn efx_rc_t
761 __inout efx_nic_t *enp,
762 __out uint32_t *bufnump,
763 __out efx_piobuf_handle_t *handlep,
764 __out uint32_t *blknump,
765 __out uint32_t *offsetp,
768 efx_drv_cfg_t *edcp = &enp->en_drv_cfg;
769 uint32_t blk_per_buf;
773 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_HUNTINGTON);
774 EFSYS_ASSERT(bufnump);
775 EFSYS_ASSERT(handlep);
776 EFSYS_ASSERT(blknump);
777 EFSYS_ASSERT(offsetp);
780 if ((edcp->edc_pio_alloc_size == 0) ||
781 (enp->en_u.hunt.enu_piobuf_count == 0)) {
785 blk_per_buf = HUNT_PIOBUF_SIZE / edcp->edc_pio_alloc_size;
787 for (buf = 0; buf < enp->en_u.hunt.enu_piobuf_count; buf++) {
788 uint32_t *map = &enp->en_u.hunt.enu_pio_alloc_map[buf];
793 EFSYS_ASSERT3U(blk_per_buf, <=, (8 * sizeof (*map)));
794 for (blk = 0; blk < blk_per_buf; blk++) {
795 if ((*map & (1u << blk)) == 0) {
805 *handlep = enp->en_u.hunt.enu_piobuf_handle[buf];
808 *sizep = edcp->edc_pio_alloc_size;
809 *offsetp = blk * (*sizep);
816 EFSYS_PROBE1(fail1, efx_rc_t, rc);
821 /* Free a piobuf sub-allocated block */
822 __checkReturn efx_rc_t
824 __inout efx_nic_t *enp,
825 __in uint32_t bufnum,
826 __in uint32_t blknum)
831 if ((bufnum >= enp->en_u.hunt.enu_piobuf_count) ||
832 (blknum >= (8 * sizeof (*map)))) {
837 map = &enp->en_u.hunt.enu_pio_alloc_map[bufnum];
838 if ((*map & (1u << blknum)) == 0) {
842 *map &= ~(1u << blknum);
849 EFSYS_PROBE1(fail1, efx_rc_t, rc);
854 __checkReturn efx_rc_t
856 __inout efx_nic_t *enp,
857 __in uint32_t vi_index,
858 __in efx_piobuf_handle_t handle)
860 return (efx_mcdi_link_piobuf(enp, vi_index, handle));
863 __checkReturn efx_rc_t
865 __inout efx_nic_t *enp,
866 __in uint32_t vi_index)
868 return (efx_mcdi_unlink_piobuf(enp, vi_index));
871 static __checkReturn efx_rc_t
872 hunt_get_datapath_caps(
875 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
876 efx_dword_t datapath_capabilities;
879 if ((rc = efx_mcdi_get_capabilities(enp, &datapath_capabilities)) != 0)
883 * Huntington RXDP firmware inserts a 0 or 14 byte prefix.
884 * We only support the 14 byte prefix here.
886 if (MCDI_CMD_DWORD_FIELD(&datapath_capabilities,
887 GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14) != 1) {
891 encp->enc_rx_prefix_size = 14;
893 /* Check if the firmware supports TSO */
894 if (MCDI_CMD_DWORD_FIELD(&datapath_capabilities,
895 GET_CAPABILITIES_OUT_TX_TSO) == 1)
896 encp->enc_fw_assisted_tso_enabled = B_TRUE;
898 encp->enc_fw_assisted_tso_enabled = B_FALSE;
900 /* Check if the firmware has vadapter/vport/vswitch support */
901 if (MCDI_CMD_DWORD_FIELD(&datapath_capabilities,
902 GET_CAPABILITIES_OUT_EVB) == 1)
903 encp->enc_datapath_cap_evb = B_TRUE;
905 encp->enc_datapath_cap_evb = B_FALSE;
907 /* Check if the firmware supports VLAN insertion */
908 if (MCDI_CMD_DWORD_FIELD(&datapath_capabilities,
909 GET_CAPABILITIES_OUT_TX_VLAN_INSERTION) == 1)
910 encp->enc_hw_tx_insert_vlan_enabled = B_TRUE;
912 encp->enc_hw_tx_insert_vlan_enabled = B_FALSE;
914 /* Check if the firmware supports RX event batching */
915 if (MCDI_CMD_DWORD_FIELD(&datapath_capabilities,
916 GET_CAPABILITIES_OUT_RX_BATCHING) == 1) {
917 encp->enc_rx_batching_enabled = B_TRUE;
918 encp->enc_rx_batch_max = 16;
920 encp->enc_rx_batching_enabled = B_FALSE;
923 /* Check if the firmware supports disabling scatter on RXQs */
924 if (MCDI_CMD_DWORD_FIELD(&datapath_capabilities,
925 GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER) == 1) {
926 encp->enc_rx_disable_scatter_supported = B_TRUE;
928 encp->enc_rx_disable_scatter_supported = B_FALSE;
936 EFSYS_PROBE1(fail1, efx_rc_t, rc);
942 * The external port mapping is a one-based numbering of the external
943 * connectors on the board. It does not distinguish off-board separated
944 * outputs such as multi-headed cables.
945 * The number of ports that map to each external port connector
946 * on the board is determined by the chip family and the port modes to
947 * which the NIC can be configured. The mapping table lists modes with
948 * port numbering requirements in increasing order.
954 } __hunt_external_port_mappings[] = {
955 /* Supported modes requiring 1 output per port */
957 EFX_FAMILY_HUNTINGTON,
958 (1 << TLV_PORT_MODE_10G) |
959 (1 << TLV_PORT_MODE_10G_10G) |
960 (1 << TLV_PORT_MODE_10G_10G_10G_10G),
963 /* Supported modes requiring 2 outputs per port */
965 EFX_FAMILY_HUNTINGTON,
966 (1 << TLV_PORT_MODE_40G) |
967 (1 << TLV_PORT_MODE_40G_40G) |
968 (1 << TLV_PORT_MODE_40G_10G_10G) |
969 (1 << TLV_PORT_MODE_10G_10G_40G),
973 * NOTE: Medford modes will require 4 outputs per port:
974 * TLV_PORT_MODE_10G_10G_10G_10G_Q
975 * TLV_PORT_MODE_10G_10G_10G_10G_Q2
976 * The Q2 mode routes outputs to external port 2. Support for this
977 * will require a new field specifying the number to add after
978 * scaling by stride. This is fixed at 1 currently.
982 static __checkReturn efx_rc_t
983 hunt_external_port_mapping(
986 __out uint8_t *external_portp)
992 uint32_t stride = 1; /* default 1-1 mapping */
994 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes)) != 0) {
995 /* No port mode information available - use default mapping */
1000 * Infer the internal port -> external port mapping from
1001 * the possible port modes for this NIC.
1003 for (i = 0; i < EFX_ARRAY_SIZE(__hunt_external_port_mappings); ++i) {
1004 if (__hunt_external_port_mappings[i].family !=
1007 matches = (__hunt_external_port_mappings[i].modes_mask &
1010 stride = __hunt_external_port_mappings[i].stride;
1011 port_modes &= ~matches;
1015 if (port_modes != 0) {
1016 /* Some advertised modes are not supported */
1023 * Scale as required by last matched mode and then convert to
1024 * one-based numbering
1026 *external_portp = (uint8_t)(port / stride) + 1;
1030 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1035 static __checkReturn efx_rc_t
1037 __in efx_nic_t *enp)
1039 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
1040 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1041 uint8_t mac_addr[6];
1042 uint32_t board_type = 0;
1043 hunt_link_state_t hls;
1044 efx_port_t *epp = &(enp->en_port);
1051 uint32_t base, nvec;
1054 if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
1058 * NOTE: The MCDI protocol numbers ports from zero.
1059 * The common code MCDI interface numbers ports from one.
1061 emip->emi_port = port + 1;
1063 if ((rc = hunt_external_port_mapping(enp, port,
1064 &encp->enc_external_port)) != 0)
1068 * Get PCIe function number from firmware (used for
1069 * per-function privilege and dynamic config info).
1070 * - PCIe PF: pf = PF number, vf = 0xffff.
1071 * - PCIe VF: pf = parent PF, vf = VF number.
1073 if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
1079 /* MAC address for this function */
1080 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
1081 rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
1082 if ((rc == 0) && (mac_addr[0] & 0x02)) {
1084 * If the static config does not include a global MAC
1085 * address pool then the board may return a locally
1086 * administered MAC address (this should only happen on
1087 * incorrectly programmed boards).
1092 rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
1097 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
1099 /* Board configuration */
1100 rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
1102 /* Unprivileged functions may not be able to read board cfg */
1109 encp->enc_board_type = board_type;
1110 encp->enc_clk_mult = 1; /* not used for Huntington */
1112 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
1113 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
1116 /* Obtain the default PHY advertised capabilities */
1117 if ((rc = hunt_phy_get_link(enp, &hls)) != 0)
1119 epp->ep_default_adv_cap_mask = hls.hls_adv_cap_mask;
1120 epp->ep_adv_cap_mask = hls.hls_adv_cap_mask;
1123 * Enable firmware workarounds for hardware errata.
1124 * Expected responses are:
1126 * Success: workaround enabled or disabled as requested.
1127 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
1128 * Firmware does not support the MC_CMD_WORKAROUND request.
1129 * (assume that the workaround is not supported).
1130 * - MC_CMD_ERR_ENOENT (reported as ENOENT):
1131 * Firmware does not support the requested workaround.
1132 * - MC_CMD_ERR_EPERM (reported as EACCES):
1133 * Unprivileged function cannot enable/disable workarounds.
1135 * See efx_mcdi_request_errcode() for MCDI error translations.
1139 * If the bug35388 workaround is enabled, then use an indirect access
1140 * method to avoid unsafe EVQ writes.
1142 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG35388, B_TRUE,
1144 if ((rc == 0) || (rc == EACCES))
1145 encp->enc_bug35388_workaround = B_TRUE;
1146 else if ((rc == ENOTSUP) || (rc == ENOENT))
1147 encp->enc_bug35388_workaround = B_FALSE;
1152 * If the bug41750 workaround is enabled, then do not test interrupts,
1153 * as the test will fail (seen with Greenport controllers).
1155 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG41750, B_TRUE,
1158 encp->enc_bug41750_workaround = B_TRUE;
1159 } else if (rc == EACCES) {
1160 /* Assume a controller with 40G ports needs the workaround. */
1161 if (epp->ep_default_adv_cap_mask & EFX_PHY_CAP_40000FDX)
1162 encp->enc_bug41750_workaround = B_TRUE;
1164 encp->enc_bug41750_workaround = B_FALSE;
1165 } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
1166 encp->enc_bug41750_workaround = B_FALSE;
1170 if (EFX_PCI_FUNCTION_IS_VF(encp)) {
1171 /* Interrupt testing does not work for VFs. See bug50084. */
1172 encp->enc_bug41750_workaround = B_TRUE;
1176 * If the bug26807 workaround is enabled, then firmware has enabled
1177 * support for chained multicast filters. Firmware will reset (FLR)
1178 * functions which have filters in the hardware filter table when the
1179 * workaround is enabled/disabled.
1181 * We must recheck if the workaround is enabled after inserting the
1182 * first hardware filter, in case it has been changed since this check.
1184 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG26807,
1187 encp->enc_bug26807_workaround = B_TRUE;
1188 if (flags & (1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN)) {
1190 * Other functions had installed filters before the
1191 * workaround was enabled, and they have been reset
1194 EFSYS_PROBE(bug26807_workaround_flr_done);
1195 /* FIXME: bump MC warm boot count ? */
1197 } else if (rc == EACCES) {
1199 * Unprivileged functions cannot enable the workaround in older
1202 encp->enc_bug26807_workaround = B_FALSE;
1203 } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
1204 encp->enc_bug26807_workaround = B_FALSE;
1209 /* Get sysclk frequency (in MHz). */
1210 if ((rc = efx_mcdi_get_clock(enp, &sysclk)) != 0)
1214 * The timer quantum is 1536 sysclk cycles, documented for the
1215 * EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
1217 encp->enc_evq_timer_quantum_ns = 1536000UL / sysclk; /* 1536 cycles */
1218 if (encp->enc_bug35388_workaround) {
1219 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
1220 ERF_DD_EVQ_IND_TIMER_VAL_WIDTH) / 1000;
1222 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
1223 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
1226 /* Check capabilities of running datapath firmware */
1227 if ((rc = hunt_get_datapath_caps(enp)) != 0)
1230 /* Alignment for receive packet DMA buffers */
1231 encp->enc_rx_buf_align_start = 1;
1232 encp->enc_rx_buf_align_end = 64; /* RX DMA end padding */
1234 /* Alignment for WPTR updates */
1235 encp->enc_rx_push_align = HUNTINGTON_RX_WPTR_ALIGN;
1238 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
1239 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
1240 * resources (allocated to this PCIe function), which is zero until
1241 * after we have allocated VIs.
1243 encp->enc_evq_limit = 1024;
1244 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
1245 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
1247 encp->enc_buftbl_limit = 0xFFFFFFFF;
1249 encp->enc_piobuf_limit = HUNT_PIOBUF_NBUFS;
1250 encp->enc_piobuf_size = HUNT_PIOBUF_SIZE;
1253 * Get the current privilege mask. Note that this may be modified
1254 * dynamically, so this value is informational only. DO NOT use
1255 * the privilege mask to check for sufficient privileges, as that
1256 * can result in time-of-check/time-of-use bugs.
1258 if ((rc = efx_mcdi_privilege_mask(enp, pf, vf, &mask)) != 0) {
1262 /* Fallback for old firmware without privilege mask support */
1263 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
1264 /* Assume PF has admin privilege */
1265 mask = HUNT_LEGACY_PF_PRIVILEGE_MASK;
1267 /* VF is always unprivileged by default */
1268 mask = HUNT_LEGACY_VF_PRIVILEGE_MASK;
1272 encp->enc_privilege_mask = mask;
1274 /* Get interrupt vector limits */
1275 if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
1276 if (EFX_PCI_FUNCTION_IS_PF(encp))
1279 /* Ignore error (cannot query vector limits from a VF). */
1283 encp->enc_intr_vec_base = base;
1284 encp->enc_intr_limit = nvec;
1287 * Maximum number of bytes into the frame the TCP header can start for
1288 * firmware assisted TSO to work.
1290 encp->enc_tx_tso_tcp_header_offset_limit = 208;
1295 EFSYS_PROBE(fail14);
1297 EFSYS_PROBE(fail13);
1299 EFSYS_PROBE(fail12);
1301 EFSYS_PROBE(fail11);
1303 EFSYS_PROBE(fail10);
1321 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1327 __checkReturn efx_rc_t
1329 __in efx_nic_t *enp)
1331 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1332 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1335 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_HUNTINGTON);
1337 /* Read and clear any assertion state */
1338 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
1341 /* Exit the assertion handler */
1342 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
1346 if ((rc = efx_mcdi_drv_attach(enp, B_TRUE)) != 0)
1349 if ((rc = hunt_board_cfg(enp)) != 0)
1354 * Set default driver config limits (based on board config).
1356 * FIXME: For now allocate a fixed number of VIs which is likely to be
1357 * sufficient and small enough to allow multiple functions on the same
1360 edcp->edc_min_vi_count = edcp->edc_max_vi_count =
1361 MIN(128, MAX(encp->enc_rxq_limit, encp->enc_txq_limit));
1363 /* The client driver must configure and enable PIO buffer support */
1364 edcp->edc_max_piobuf_count = 0;
1365 edcp->edc_pio_alloc_size = 0;
1367 #if EFSYS_OPT_MAC_STATS
1368 /* Wipe the MAC statistics */
1369 if ((rc = efx_mcdi_mac_stats_clear(enp)) != 0)
1373 #if EFSYS_OPT_LOOPBACK
1374 if ((rc = efx_mcdi_get_loopback_modes(enp)) != 0)
1378 #if EFSYS_OPT_MON_STATS
1379 if ((rc = mcdi_mon_cfg_build(enp)) != 0) {
1380 /* Unprivileged functions do not have access to sensors */
1386 encp->enc_features = enp->en_features;
1390 #if EFSYS_OPT_MON_STATS
1394 #if EFSYS_OPT_LOOPBACK
1398 #if EFSYS_OPT_MAC_STATS
1409 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1414 __checkReturn efx_rc_t
1415 hunt_nic_set_drv_limits(
1416 __inout efx_nic_t *enp,
1417 __in efx_drv_limits_t *edlp)
1419 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1420 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1421 uint32_t min_evq_count, max_evq_count;
1422 uint32_t min_rxq_count, max_rxq_count;
1423 uint32_t min_txq_count, max_txq_count;
1431 /* Get minimum required and maximum usable VI limits */
1432 min_evq_count = MIN(edlp->edl_min_evq_count, encp->enc_evq_limit);
1433 min_rxq_count = MIN(edlp->edl_min_rxq_count, encp->enc_rxq_limit);
1434 min_txq_count = MIN(edlp->edl_min_txq_count, encp->enc_txq_limit);
1436 edcp->edc_min_vi_count =
1437 MAX(min_evq_count, MAX(min_rxq_count, min_txq_count));
1439 max_evq_count = MIN(edlp->edl_max_evq_count, encp->enc_evq_limit);
1440 max_rxq_count = MIN(edlp->edl_max_rxq_count, encp->enc_rxq_limit);
1441 max_txq_count = MIN(edlp->edl_max_txq_count, encp->enc_txq_limit);
1443 edcp->edc_max_vi_count =
1444 MAX(max_evq_count, MAX(max_rxq_count, max_txq_count));
1447 * Check limits for sub-allocated piobuf blocks.
1448 * PIO is optional, so don't fail if the limits are incorrect.
1450 if ((encp->enc_piobuf_size == 0) ||
1451 (encp->enc_piobuf_limit == 0) ||
1452 (edlp->edl_min_pio_alloc_size == 0) ||
1453 (edlp->edl_min_pio_alloc_size > encp->enc_piobuf_size)) {
1455 edcp->edc_max_piobuf_count = 0;
1456 edcp->edc_pio_alloc_size = 0;
1458 uint32_t blk_size, blk_count, blks_per_piobuf;
1461 MAX(edlp->edl_min_pio_alloc_size, HUNT_MIN_PIO_ALLOC_SIZE);
1463 blks_per_piobuf = encp->enc_piobuf_size / blk_size;
1464 EFSYS_ASSERT3U(blks_per_piobuf, <=, 32);
1466 blk_count = (encp->enc_piobuf_limit * blks_per_piobuf);
1468 /* A zero max pio alloc count means unlimited */
1469 if ((edlp->edl_max_pio_alloc_count > 0) &&
1470 (edlp->edl_max_pio_alloc_count < blk_count)) {
1471 blk_count = edlp->edl_max_pio_alloc_count;
1474 edcp->edc_pio_alloc_size = blk_size;
1475 edcp->edc_max_piobuf_count =
1476 (blk_count + (blks_per_piobuf - 1)) / blks_per_piobuf;
1482 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1488 __checkReturn efx_rc_t
1490 __in efx_nic_t *enp)
1493 uint8_t payload[MAX(MC_CMD_ENTITY_RESET_IN_LEN,
1494 MC_CMD_ENTITY_RESET_OUT_LEN)];
1497 /* hunt_nic_reset() is called to recover from BADASSERT failures. */
1498 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
1500 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
1503 (void) memset(payload, 0, sizeof (payload));
1504 req.emr_cmd = MC_CMD_ENTITY_RESET;
1505 req.emr_in_buf = payload;
1506 req.emr_in_length = MC_CMD_ENTITY_RESET_IN_LEN;
1507 req.emr_out_buf = payload;
1508 req.emr_out_length = MC_CMD_ENTITY_RESET_OUT_LEN;
1510 MCDI_IN_POPULATE_DWORD_1(req, ENTITY_RESET_IN_FLAG,
1511 ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET, 1);
1513 efx_mcdi_execute(enp, &req);
1515 if (req.emr_rc != 0) {
1520 /* Clear RX/TX DMA queue errors */
1521 enp->en_reset_flags &= ~(EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR);
1530 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1535 __checkReturn efx_rc_t
1537 __in efx_nic_t *enp)
1539 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1540 uint32_t min_vi_count, max_vi_count;
1541 uint32_t vi_count, vi_base;
1547 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_HUNTINGTON);
1549 /* Enable reporting of some events (e.g. link change) */
1550 if ((rc = efx_mcdi_log_ctrl(enp)) != 0)
1553 /* Allocate (optional) on-chip PIO buffers */
1554 hunt_nic_alloc_piobufs(enp, edcp->edc_max_piobuf_count);
1557 * For best performance, PIO writes should use a write-combined
1558 * (WC) memory mapping. Using a separate WC mapping for the PIO
1559 * aperture of each VI would be a burden to drivers (and not
1560 * possible if the host page size is >4Kbyte).
1562 * To avoid this we use a single uncached (UC) mapping for VI
1563 * register access, and a single WC mapping for extra VIs used
1566 * Each piobuf must be linked to a VI in the WC mapping, and to
1567 * each VI that is using a sub-allocated block from the piobuf.
1569 min_vi_count = edcp->edc_min_vi_count;
1570 max_vi_count = edcp->edc_max_vi_count + enp->en_u.hunt.enu_piobuf_count;
1572 /* Ensure that the previously attached driver's VIs are freed */
1573 if ((rc = efx_mcdi_free_vis(enp)) != 0)
1577 * Reserve VI resources (EVQ+RXQ+TXQ) for this PCIe function. If this
1578 * fails then retrying the request for fewer VI resources may succeed.
1581 if ((rc = efx_mcdi_alloc_vis(enp, min_vi_count, max_vi_count,
1582 &vi_base, &vi_count)) != 0)
1585 EFSYS_PROBE2(vi_alloc, uint32_t, vi_base, uint32_t, vi_count);
1587 if (vi_count < min_vi_count) {
1592 enp->en_u.hunt.enu_vi_base = vi_base;
1593 enp->en_u.hunt.enu_vi_count = vi_count;
1595 if (vi_count < min_vi_count + enp->en_u.hunt.enu_piobuf_count) {
1596 /* Not enough extra VIs to map piobufs */
1597 hunt_nic_free_piobufs(enp);
1600 enp->en_u.hunt.enu_pio_write_vi_base =
1601 vi_count - enp->en_u.hunt.enu_piobuf_count;
1603 /* Save UC memory mapping details */
1604 enp->en_u.hunt.enu_uc_mem_map_offset = 0;
1605 if (enp->en_u.hunt.enu_piobuf_count > 0) {
1606 enp->en_u.hunt.enu_uc_mem_map_size =
1607 (ER_DZ_TX_PIOBUF_STEP *
1608 enp->en_u.hunt.enu_pio_write_vi_base);
1610 enp->en_u.hunt.enu_uc_mem_map_size =
1611 (ER_DZ_TX_PIOBUF_STEP *
1612 enp->en_u.hunt.enu_vi_count);
1615 /* Save WC memory mapping details */
1616 enp->en_u.hunt.enu_wc_mem_map_offset =
1617 enp->en_u.hunt.enu_uc_mem_map_offset +
1618 enp->en_u.hunt.enu_uc_mem_map_size;
1620 enp->en_u.hunt.enu_wc_mem_map_size =
1621 (ER_DZ_TX_PIOBUF_STEP *
1622 enp->en_u.hunt.enu_piobuf_count);
1624 /* Link piobufs to extra VIs in WC mapping */
1625 if (enp->en_u.hunt.enu_piobuf_count > 0) {
1626 for (i = 0; i < enp->en_u.hunt.enu_piobuf_count; i++) {
1627 rc = efx_mcdi_link_piobuf(enp,
1628 enp->en_u.hunt.enu_pio_write_vi_base + i,
1629 enp->en_u.hunt.enu_piobuf_handle[i]);
1636 * Allocate a vAdaptor attached to our upstream vPort/pPort.
1638 * On a VF, this may fail with MC_CMD_ERR_NO_EVB_PORT (ENOENT) if the PF
1639 * driver has yet to bring up the EVB port. See bug 56147. In this case,
1640 * retry the request several times after waiting a while. The wait time
1641 * between retries starts small (10ms) and exponentially increases.
1642 * Total wait time is a little over two seconds. Retry logic in the
1643 * client driver may mean this whole loop is repeated if it continues to
1648 while ((rc = efx_mcdi_vadaptor_alloc(enp, EVB_PORT_ID_ASSIGNED)) != 0) {
1649 if (EFX_PCI_FUNCTION_IS_PF(&enp->en_nic_cfg) ||
1652 * Do not retry alloc for PF, or for other errors on
1658 /* VF startup before PF is ready. Retry allocation. */
1660 /* Too many attempts */
1664 EFSYS_PROBE1(mcdi_no_evb_port_retry, int, retry);
1665 EFSYS_SLEEP(delay_us);
1667 if (delay_us < 500000)
1671 enp->en_vport_id = EVB_PORT_ID_ASSIGNED;
1686 hunt_nic_free_piobufs(enp);
1689 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1694 __checkReturn efx_rc_t
1695 hunt_nic_get_vi_pool(
1696 __in efx_nic_t *enp,
1697 __out uint32_t *vi_countp)
1699 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_HUNTINGTON);
1702 * Report VIs that the client driver can use.
1703 * Do not include VIs used for PIO buffer writes.
1705 *vi_countp = enp->en_u.hunt.enu_pio_write_vi_base;
1710 __checkReturn efx_rc_t
1711 hunt_nic_get_bar_region(
1712 __in efx_nic_t *enp,
1713 __in efx_nic_region_t region,
1714 __out uint32_t *offsetp,
1715 __out size_t *sizep)
1719 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_HUNTINGTON);
1722 * TODO: Specify host memory mapping alignment and granularity
1723 * in efx_drv_limits_t so that they can be taken into account
1724 * when allocating extra VIs for PIO writes.
1728 /* UC mapped memory BAR region for VI registers */
1729 *offsetp = enp->en_u.hunt.enu_uc_mem_map_offset;
1730 *sizep = enp->en_u.hunt.enu_uc_mem_map_size;
1733 case EFX_REGION_PIO_WRITE_VI:
1734 /* WC mapped memory BAR region for piobuf writes */
1735 *offsetp = enp->en_u.hunt.enu_wc_mem_map_offset;
1736 *sizep = enp->en_u.hunt.enu_wc_mem_map_size;
1747 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1754 __in efx_nic_t *enp)
1759 (void) efx_mcdi_vadaptor_free(enp, enp->en_vport_id);
1760 enp->en_vport_id = 0;
1762 /* Unlink piobufs from extra VIs in WC mapping */
1763 if (enp->en_u.hunt.enu_piobuf_count > 0) {
1764 for (i = 0; i < enp->en_u.hunt.enu_piobuf_count; i++) {
1765 rc = efx_mcdi_unlink_piobuf(enp,
1766 enp->en_u.hunt.enu_pio_write_vi_base + i);
1772 hunt_nic_free_piobufs(enp);
1774 (void) efx_mcdi_free_vis(enp);
1775 enp->en_u.hunt.enu_vi_count = 0;
1780 __in efx_nic_t *enp)
1782 #if EFSYS_OPT_MON_STATS
1783 mcdi_mon_cfg_free(enp);
1784 #endif /* EFSYS_OPT_MON_STATS */
1785 (void) efx_mcdi_drv_attach(enp, B_FALSE);
1790 __checkReturn efx_rc_t
1791 hunt_nic_register_test(
1792 __in efx_nic_t *enp)
1797 _NOTE(ARGUNUSED(enp))
1807 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1812 #endif /* EFSYS_OPT_DIAG */
1816 #endif /* EFSYS_OPT_HUNTINGTON */