2 * Copyright 2009 Solarflare Communications Inc. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD$");
39 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
41 uint32_t rx_base, tx_base;
43 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
44 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA);
46 rx_base = encp->enc_buftbl_limit;
47 tx_base = rx_base + (encp->enc_rxq_limit * 64);
49 /* Initialize the transmit descriptor cache */
50 EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_TX_DC_BASE_ADR, tx_base);
51 EFX_BAR_WRITEO(enp, FR_AZ_SRM_TX_DC_CFG_REG, &oword);
53 EFX_POPULATE_OWORD_1(oword, FRF_AZ_TX_DC_SIZE, 1); /* 16 descriptors */
54 EFX_BAR_WRITEO(enp, FR_AZ_TX_DC_CFG_REG, &oword);
56 /* Initialize the receive descriptor cache */
57 EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_RX_DC_BASE_ADR, rx_base);
58 EFX_BAR_WRITEO(enp, FR_AZ_SRM_RX_DC_CFG_REG, &oword);
60 EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DC_SIZE, 3); /* 64 descriptors */
61 EFX_BAR_WRITEO(enp, FR_AZ_RX_DC_CFG_REG, &oword);
63 /* Set receive descriptor pre-fetch low water mark */
64 EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DC_PF_LWM, 56);
65 EFX_BAR_WRITEO(enp, FR_AZ_RX_DC_PF_WM_REG, &oword);
67 /* Set the event queue to use for SRAM updates */
68 EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_UPD_EVQ_ID, 0);
69 EFX_BAR_WRITEO(enp, FR_AZ_SRM_UPD_EVQ_REG, &oword);
77 __in efx_sram_pattern_fn_t func)
87 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA);
89 /* Reconfigure into HALF buffer table mode */
90 EFX_POPULATE_OWORD_1(oword, FRF_AZ_BUF_TBL_MODE, 0);
91 EFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_CFG_REG, &oword);
94 * Move the descriptor caches up to the top of SRAM, and test
95 * all of SRAM below them. We only miss out one row here.
97 rows = SIENA_SRAM_ROWS - 1;
98 EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_RX_DC_BASE_ADR, rows);
99 EFX_BAR_WRITEO(enp, FR_AZ_SRM_RX_DC_CFG_REG, &oword);
101 EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_TX_DC_BASE_ADR, rows + 1);
102 EFX_BAR_WRITEO(enp, FR_AZ_SRM_TX_DC_CFG_REG, &oword);
105 * Write the pattern through BUF_HALF_TBL. Write
106 * in 64 entry batches, waiting 1us in between each batch
107 * to guarantee not to overflow the SRAM fifo
109 for (wptr = 0, rptr = 0; wptr < rows; ++wptr) {
110 func(wptr, B_FALSE, &qword);
111 EFX_BAR_TBL_WRITEQ(enp, FR_AZ_BUF_HALF_TBL, wptr, &qword);
113 if ((wptr - rptr) < 64 && wptr < rows - 1)
118 for (; rptr <= wptr; ++rptr) {
119 func(rptr, B_FALSE, &qword);
120 EFX_BAR_TBL_READQ(enp, FR_AZ_BUF_HALF_TBL, rptr,
123 if (!EFX_QWORD_IS_EQUAL(verify, qword)) {
130 /* And do the same negated */
131 for (wptr = 0, rptr = 0; wptr < rows; ++wptr) {
132 func(wptr, B_TRUE, &qword);
133 EFX_BAR_TBL_WRITEQ(enp, FR_AZ_BUF_HALF_TBL, wptr, &qword);
135 if ((wptr - rptr) < 64 && wptr < rows - 1)
140 for (; rptr <= wptr; ++rptr) {
141 func(rptr, B_TRUE, &qword);
142 EFX_BAR_TBL_READQ(enp, FR_AZ_BUF_HALF_TBL, rptr,
145 if (!EFX_QWORD_IS_EQUAL(verify, qword)) {
152 /* Restore back to FULL buffer table mode */
153 EFX_POPULATE_OWORD_1(oword, FRF_AZ_BUF_TBL_MODE, 1);
154 EFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_CFG_REG, &oword);
157 * We don't need to reconfigure SRAM again because the API
158 * requires efx_nic_fini() to be called after an sram test.
165 EFSYS_PROBE1(fail1, int, rc);
167 /* Restore back to FULL buffer table mode */
168 EFX_POPULATE_OWORD_1(oword, FRF_AZ_BUF_TBL_MODE, 1);
169 EFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_CFG_REG, &oword);
174 #endif /* EFSYS_OPT_DIAG */
176 #endif /* EFSYS_OPT_SIENA */