2 * Copyright (c) 2010-2011 Solarflare Communications, Inc.
5 * This software was developed in part by Philip Paeps under contract for
6 * Solarflare Communications, Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/types.h>
34 #include <sys/limits.h>
35 #include <net/ethernet.h>
36 #include <net/if_dl.h>
38 #include "common/efx.h"
43 sfxge_mac_stat_update(struct sfxge_softc *sc)
45 struct sfxge_port *port = &sc->port;
46 efsys_mem_t *esmp = &(port->mac_stats.dma_buf);
51 mtx_lock(&port->lock);
53 if (port->init_state != SFXGE_PORT_STARTED) {
59 if (now - port->mac_stats.update_time < hz) {
64 port->mac_stats.update_time = now;
66 /* If we're unlucky enough to read statistics wduring the DMA, wait
67 * up to 10ms for it to finish (typically takes <500us) */
68 for (count = 0; count < 100; ++count) {
69 EFSYS_PROBE1(wait, unsigned int, count);
71 /* Synchronize the DMA memory for reading */
72 bus_dmamap_sync(esmp->esm_tag, esmp->esm_map,
73 BUS_DMASYNC_POSTREAD);
75 /* Try to update the cached counters */
76 if ((rc = efx_mac_stats_update(sc->enp, esmp,
77 port->mac_stats.decode_buf, NULL)) != EAGAIN)
85 mtx_unlock(&port->lock);
90 sfxge_mac_stat_handler(SYSCTL_HANDLER_ARGS)
92 struct sfxge_softc *sc = arg1;
93 unsigned int id = arg2;
96 if ((rc = sfxge_mac_stat_update(sc)) != 0)
99 return SYSCTL_OUT(req,
100 (uint64_t *)sc->port.mac_stats.decode_buf + id,
105 sfxge_mac_stat_init(struct sfxge_softc *sc)
107 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->dev);
108 struct sysctl_oid_list *stat_list;
112 stat_list = SYSCTL_CHILDREN(sc->stats_node);
114 /* Initialise the named stats */
115 for (id = 0; id < EFX_MAC_NSTATS; id++) {
116 name = efx_mac_stat_name(sc->enp, id);
119 OID_AUTO, name, CTLTYPE_U64|CTLFLAG_RD,
120 sc, id, sfxge_mac_stat_handler, "Q",
125 #ifdef SFXGE_HAVE_PAUSE_MEDIAOPTS
128 sfxge_port_wanted_fc(struct sfxge_softc *sc)
130 struct ifmedia_entry *ifm = sc->media.ifm_cur;
132 if (ifm->ifm_media == (IFM_ETHER | IFM_AUTO))
133 return EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE;
134 return ((ifm->ifm_media & IFM_ETH_RXPAUSE) ? EFX_FCNTL_RESPOND : 0) |
135 ((ifm->ifm_media & IFM_ETH_TXPAUSE) ? EFX_FCNTL_GENERATE : 0);
139 sfxge_port_link_fc_ifm(struct sfxge_softc *sc)
141 unsigned int wanted_fc, link_fc;
143 efx_mac_fcntl_get(sc->enp, &wanted_fc, &link_fc);
144 return ((link_fc & EFX_FCNTL_RESPOND) ? IFM_ETH_RXPAUSE : 0) |
145 ((link_fc & EFX_FCNTL_GENERATE) ? IFM_ETH_TXPAUSE : 0);
148 #else /* !SFXGE_HAVE_PAUSE_MEDIAOPTS */
151 sfxge_port_wanted_fc(struct sfxge_softc *sc)
153 return sc->port.wanted_fc;
157 sfxge_port_link_fc_ifm(struct sfxge_softc *sc)
163 sfxge_port_wanted_fc_handler(SYSCTL_HANDLER_ARGS)
165 struct sfxge_softc *sc;
166 struct sfxge_port *port;
173 mtx_lock(&port->lock);
176 if ((error = SYSCTL_IN(req, &fcntl, sizeof(fcntl))) != 0)
179 if (port->wanted_fc == fcntl)
182 port->wanted_fc = fcntl;
184 if (port->init_state != SFXGE_PORT_STARTED)
187 error = efx_mac_fcntl_set(sc->enp, port->wanted_fc, B_TRUE);
189 error = SYSCTL_OUT(req, &port->wanted_fc,
190 sizeof(port->wanted_fc));
194 mtx_unlock(&port->lock);
200 sfxge_port_link_fc_handler(SYSCTL_HANDLER_ARGS)
202 struct sfxge_softc *sc;
203 struct sfxge_port *port;
204 unsigned int wanted_fc, link_fc;
210 mtx_lock(&port->lock);
211 if (port->init_state == SFXGE_PORT_STARTED && SFXGE_LINK_UP(sc))
212 efx_mac_fcntl_get(sc->enp, &wanted_fc, &link_fc);
215 error = SYSCTL_OUT(req, &link_fc, sizeof(link_fc));
216 mtx_unlock(&port->lock);
221 #endif /* SFXGE_HAVE_PAUSE_MEDIAOPTS */
223 static const u_long sfxge_link_baudrate[EFX_LINK_NMODES] = {
224 [EFX_LINK_10HDX] = IF_Mbps(10),
225 [EFX_LINK_10FDX] = IF_Mbps(10),
226 [EFX_LINK_100HDX] = IF_Mbps(100),
227 [EFX_LINK_100FDX] = IF_Mbps(100),
228 [EFX_LINK_1000HDX] = IF_Gbps(1),
229 [EFX_LINK_1000FDX] = IF_Gbps(1),
230 [EFX_LINK_10000FDX] = MIN(IF_Gbps(10ULL), ULONG_MAX),
234 sfxge_mac_link_update(struct sfxge_softc *sc, efx_link_mode_t mode)
236 struct sfxge_port *port;
241 if (port->link_mode == mode)
244 port->link_mode = mode;
246 /* Push link state update to the OS */
247 link_state = (port->link_mode != EFX_LINK_DOWN ?
248 LINK_STATE_UP : LINK_STATE_DOWN);
249 sc->ifnet->if_baudrate = sfxge_link_baudrate[port->link_mode];
250 if_link_state_change(sc->ifnet, link_state);
254 sfxge_mac_poll_work(void *arg, int npending)
256 struct sfxge_softc *sc;
258 struct sfxge_port *port;
259 efx_link_mode_t mode;
261 sc = (struct sfxge_softc *)arg;
265 mtx_lock(&port->lock);
267 if (port->init_state != SFXGE_PORT_STARTED)
270 /* This may sleep waiting for MCDI completion */
271 (void)efx_port_poll(enp, &mode);
272 sfxge_mac_link_update(sc, mode);
275 mtx_unlock(&port->lock);
279 sfxge_mac_filter_set_locked(struct sfxge_softc *sc)
281 unsigned int bucket[EFX_MAC_HASH_BITS];
282 struct ifnet *ifp = sc->ifnet;
283 struct ifmultiaddr *ifma;
284 struct sockaddr_dl *sa;
285 efx_nic_t *enp = sc->enp;
289 /* Set promisc-unicast and broadcast filter bits */
290 if ((rc = efx_mac_filter_set(enp, !!(ifp->if_flags & IFF_PROMISC),
294 /* Set multicast hash filter */
295 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
296 for (index = 0; index < EFX_MAC_HASH_BITS; index++)
299 /* Broadcast frames also go through the multicast
300 * filter, and the broadcast address hashes to
305 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
306 if (ifma->ifma_addr->sa_family == AF_LINK) {
307 sa = (struct sockaddr_dl *)ifma->ifma_addr;
308 index = ether_crc32_le(LLADDR(sa), 6) & 0xff;
314 return efx_mac_hash_set(enp, bucket);
318 sfxge_mac_filter_set(struct sfxge_softc *sc)
320 struct sfxge_port *port = &sc->port;
323 KASSERT(port->init_state == SFXGE_PORT_STARTED, ("port not started"));
325 mtx_lock(&port->lock);
326 rc = sfxge_mac_filter_set_locked(sc);
327 mtx_unlock(&port->lock);
332 sfxge_port_stop(struct sfxge_softc *sc)
334 struct sfxge_port *port;
340 mtx_lock(&port->lock);
342 KASSERT(port->init_state == SFXGE_PORT_STARTED,
343 ("port not started"));
345 port->init_state = SFXGE_PORT_INITIALIZED;
347 port->mac_stats.update_time = 0;
349 /* This may call MCDI */
350 (void)efx_mac_drain(enp, B_TRUE);
352 (void)efx_mac_stats_periodic(enp, &port->mac_stats.dma_buf, 0, B_FALSE);
354 port->link_mode = EFX_LINK_UNKNOWN;
356 /* Destroy the common code port object. */
357 efx_port_fini(sc->enp);
359 mtx_unlock(&port->lock);
363 sfxge_port_start(struct sfxge_softc *sc)
365 uint8_t mac_addr[ETHER_ADDR_LEN];
366 struct ifnet *ifp = sc->ifnet;
367 struct sfxge_port *port;
375 mtx_lock(&port->lock);
377 KASSERT(port->init_state == SFXGE_PORT_INITIALIZED,
378 ("port not initialized"));
380 /* Initialize the port object in the common code. */
381 if ((rc = efx_port_init(sc->enp)) != 0)
385 pdu = EFX_MAC_PDU(ifp->if_mtu);
386 if ((rc = efx_mac_pdu_set(enp, pdu)) != 0)
389 if ((rc = efx_mac_fcntl_set(enp, sfxge_port_wanted_fc(sc), B_TRUE))
393 /* Set the unicast address */
395 bcopy(LLADDR((struct sockaddr_dl *)ifp->if_addr->ifa_addr),
396 mac_addr, sizeof(mac_addr));
398 if ((rc = efx_mac_addr_set(enp, mac_addr)) != 0)
401 sfxge_mac_filter_set_locked(sc);
403 /* Update MAC stats by DMA every second */
404 if ((rc = efx_mac_stats_periodic(enp, &port->mac_stats.dma_buf,
405 1000, B_FALSE)) != 0)
408 if ((rc = efx_mac_drain(enp, B_FALSE)) != 0)
411 if ((rc = efx_phy_adv_cap_set(sc->enp, sc->media.ifm_cur->ifm_data))
415 port->init_state = SFXGE_PORT_STARTED;
417 /* Single poll in case there were missing initial events */
418 mtx_unlock(&port->lock);
419 sfxge_mac_poll_work(sc, 0);
424 (void)efx_mac_drain(enp, B_TRUE);
426 (void)efx_mac_stats_periodic(enp, &port->mac_stats.dma_buf,
429 efx_port_fini(sc->enp);
431 mtx_unlock(&port->lock);
437 sfxge_phy_stat_update(struct sfxge_softc *sc)
439 struct sfxge_port *port = &sc->port;
440 efsys_mem_t *esmp = &port->phy_stats.dma_buf;
445 mtx_lock(&port->lock);
447 if (port->init_state != SFXGE_PORT_STARTED) {
453 if (now - port->phy_stats.update_time < hz) {
458 port->phy_stats.update_time = now;
460 /* If we're unlucky enough to read statistics wduring the DMA, wait
461 * up to 10ms for it to finish (typically takes <500us) */
462 for (count = 0; count < 100; ++count) {
463 EFSYS_PROBE1(wait, unsigned int, count);
465 /* Synchronize the DMA memory for reading */
466 bus_dmamap_sync(esmp->esm_tag, esmp->esm_map,
467 BUS_DMASYNC_POSTREAD);
469 /* Try to update the cached counters */
470 if ((rc = efx_phy_stats_update(sc->enp, esmp,
471 port->phy_stats.decode_buf)) != EAGAIN)
479 mtx_unlock(&port->lock);
484 sfxge_phy_stat_handler(SYSCTL_HANDLER_ARGS)
486 struct sfxge_softc *sc = arg1;
487 unsigned int id = arg2;
490 if ((rc = sfxge_phy_stat_update(sc)) != 0)
493 return SYSCTL_OUT(req,
494 (uint32_t *)sc->port.phy_stats.decode_buf + id,
499 sfxge_phy_stat_init(struct sfxge_softc *sc)
501 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->dev);
502 struct sysctl_oid_list *stat_list;
505 uint64_t stat_mask = efx_nic_cfg_get(sc->enp)->enc_phy_stat_mask;
507 stat_list = SYSCTL_CHILDREN(sc->stats_node);
509 /* Initialise the named stats */
510 for (id = 0; id < EFX_PHY_NSTATS; id++) {
511 if (!(stat_mask & ((uint64_t)1 << id)))
513 name = efx_phy_stat_name(sc->enp, id);
516 OID_AUTO, name, CTLTYPE_UINT|CTLFLAG_RD,
517 sc, id, sfxge_phy_stat_handler,
518 id == EFX_PHY_STAT_OUI ? "IX" : "IU",
524 sfxge_port_fini(struct sfxge_softc *sc)
526 struct sfxge_port *port;
530 esmp = &port->mac_stats.dma_buf;
532 KASSERT(port->init_state == SFXGE_PORT_INITIALIZED,
533 ("Port not initialized"));
535 port->init_state = SFXGE_PORT_UNINITIALIZED;
537 port->link_mode = EFX_LINK_UNKNOWN;
539 /* Finish with PHY DMA memory */
540 sfxge_dma_free(&port->phy_stats.dma_buf);
541 free(port->phy_stats.decode_buf, M_SFXGE);
543 sfxge_dma_free(esmp);
544 free(port->mac_stats.decode_buf, M_SFXGE);
546 mtx_destroy(&port->lock);
552 sfxge_port_init(struct sfxge_softc *sc)
554 struct sfxge_port *port;
555 struct sysctl_ctx_list *sysctl_ctx;
556 struct sysctl_oid *sysctl_tree;
557 efsys_mem_t *mac_stats_buf, *phy_stats_buf;
561 mac_stats_buf = &port->mac_stats.dma_buf;
562 phy_stats_buf = &port->phy_stats.dma_buf;
564 KASSERT(port->init_state == SFXGE_PORT_UNINITIALIZED,
565 ("Port already initialized"));
569 mtx_init(&port->lock, "sfxge_port", NULL, MTX_DEF);
571 port->phy_stats.decode_buf = malloc(EFX_PHY_NSTATS * sizeof(uint32_t),
572 M_SFXGE, M_WAITOK | M_ZERO);
573 if ((rc = sfxge_dma_alloc(sc, EFX_PHY_STATS_SIZE, phy_stats_buf)) != 0)
575 bzero(phy_stats_buf->esm_base, phy_stats_buf->esm_size);
576 sfxge_phy_stat_init(sc);
578 sysctl_ctx = device_get_sysctl_ctx(sc->dev);
579 sysctl_tree = device_get_sysctl_tree(sc->dev);
581 #ifndef SFXGE_HAVE_PAUSE_MEDIAOPTS
582 /* If flow control cannot be configured or reported through
583 * ifmedia, provide sysctls for it. */
584 port->wanted_fc = EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE;
585 SYSCTL_ADD_PROC(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), OID_AUTO,
586 "wanted_fc", CTLTYPE_UINT|CTLFLAG_RW, sc, 0,
587 sfxge_port_wanted_fc_handler, "IU", "wanted flow control mode");
588 SYSCTL_ADD_PROC(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), OID_AUTO,
589 "link_fc", CTLTYPE_UINT|CTLFLAG_RD, sc, 0,
590 sfxge_port_link_fc_handler, "IU", "link flow control mode");
593 port->mac_stats.decode_buf = malloc(EFX_MAC_NSTATS * sizeof(uint64_t),
594 M_SFXGE, M_WAITOK | M_ZERO);
595 if ((rc = sfxge_dma_alloc(sc, EFX_MAC_STATS_SIZE, mac_stats_buf)) != 0)
597 bzero(mac_stats_buf->esm_base, mac_stats_buf->esm_size);
598 sfxge_mac_stat_init(sc);
600 port->init_state = SFXGE_PORT_INITIALIZED;
605 free(port->mac_stats.decode_buf, M_SFXGE);
606 sfxge_dma_free(phy_stats_buf);
608 free(port->phy_stats.decode_buf, M_SFXGE);
609 (void)mtx_destroy(&port->lock);
614 static int sfxge_link_mode[EFX_PHY_MEDIA_NTYPES][EFX_LINK_NMODES] = {
615 [EFX_PHY_MEDIA_CX4] = {
616 [EFX_LINK_10000FDX] = IFM_ETHER | IFM_FDX | IFM_10G_CX4,
618 [EFX_PHY_MEDIA_KX4] = {
619 [EFX_LINK_10000FDX] = IFM_ETHER | IFM_FDX | IFM_10G_KX4,
621 [EFX_PHY_MEDIA_XFP] = {
622 /* Don't know the module type, but assume SR for now. */
623 [EFX_LINK_10000FDX] = IFM_ETHER | IFM_FDX | IFM_10G_SR,
625 [EFX_PHY_MEDIA_SFP_PLUS] = {
626 /* Don't know the module type, but assume SX/SR for now. */
627 [EFX_LINK_1000FDX] = IFM_ETHER | IFM_FDX | IFM_1000_SX,
628 [EFX_LINK_10000FDX] = IFM_ETHER | IFM_FDX | IFM_10G_SR,
630 [EFX_PHY_MEDIA_BASE_T] = {
631 [EFX_LINK_10HDX] = IFM_ETHER | IFM_HDX | IFM_10_T,
632 [EFX_LINK_10FDX] = IFM_ETHER | IFM_FDX | IFM_10_T,
633 [EFX_LINK_100HDX] = IFM_ETHER | IFM_HDX | IFM_100_TX,
634 [EFX_LINK_100FDX] = IFM_ETHER | IFM_FDX | IFM_100_TX,
635 [EFX_LINK_1000HDX] = IFM_ETHER | IFM_HDX | IFM_1000_T,
636 [EFX_LINK_1000FDX] = IFM_ETHER | IFM_FDX | IFM_1000_T,
637 [EFX_LINK_10000FDX] = IFM_ETHER | IFM_FDX | IFM_10G_T,
642 sfxge_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
644 struct sfxge_softc *sc;
645 efx_phy_media_type_t medium_type;
646 efx_link_mode_t mode;
649 sx_xlock(&sc->softc_lock);
651 ifmr->ifm_status = IFM_AVALID;
652 ifmr->ifm_active = IFM_ETHER;
654 if (SFXGE_RUNNING(sc) && SFXGE_LINK_UP(sc)) {
655 ifmr->ifm_status |= IFM_ACTIVE;
657 efx_phy_media_type_get(sc->enp, &medium_type);
658 mode = sc->port.link_mode;
659 ifmr->ifm_active |= sfxge_link_mode[medium_type][mode];
660 ifmr->ifm_active |= sfxge_port_link_fc_ifm(sc);
663 sx_xunlock(&sc->softc_lock);
667 sfxge_media_change(struct ifnet *ifp)
669 struct sfxge_softc *sc;
670 struct ifmedia_entry *ifm;
674 ifm = sc->media.ifm_cur;
676 sx_xlock(&sc->softc_lock);
678 if (!SFXGE_RUNNING(sc)) {
683 rc = efx_mac_fcntl_set(sc->enp, sfxge_port_wanted_fc(sc), B_TRUE);
687 rc = efx_phy_adv_cap_set(sc->enp, ifm->ifm_data);
689 sx_xunlock(&sc->softc_lock);
694 int sfxge_port_ifmedia_init(struct sfxge_softc *sc)
696 efx_phy_media_type_t medium_type;
697 uint32_t cap_mask, mode_cap_mask;
698 efx_link_mode_t mode;
699 int mode_ifm, best_mode_ifm = 0;
702 /* We need port state to initialise the ifmedia list. */
703 if ((rc = efx_nic_init(sc->enp)) != 0)
705 if ((rc = efx_port_init(sc->enp)) != 0)
709 * Register ifconfig callbacks for querying and setting the
710 * link mode and link status.
712 ifmedia_init(&sc->media, IFM_IMASK, sfxge_media_change,
716 * Map firmware medium type and capabilities to ifmedia types.
717 * ifmedia does not distinguish between forcing the link mode
718 * and disabling auto-negotiation. 1000BASE-T and 10GBASE-T
719 * require AN even if only one link mode is enabled, and for
720 * 100BASE-TX it is useful even if the link mode is forced.
721 * Therefore we never disable auto-negotiation.
723 * Also enable and advertise flow control by default.
726 efx_phy_media_type_get(sc->enp, &medium_type);
727 efx_phy_adv_cap_get(sc->enp, EFX_PHY_CAP_PERM, &cap_mask);
729 EFX_STATIC_ASSERT(EFX_LINK_10HDX == EFX_PHY_CAP_10HDX + 1);
730 EFX_STATIC_ASSERT(EFX_LINK_10FDX == EFX_PHY_CAP_10FDX + 1);
731 EFX_STATIC_ASSERT(EFX_LINK_100HDX == EFX_PHY_CAP_100HDX + 1);
732 EFX_STATIC_ASSERT(EFX_LINK_100FDX == EFX_PHY_CAP_100FDX + 1);
733 EFX_STATIC_ASSERT(EFX_LINK_1000HDX == EFX_PHY_CAP_1000HDX + 1);
734 EFX_STATIC_ASSERT(EFX_LINK_1000FDX == EFX_PHY_CAP_1000FDX + 1);
735 EFX_STATIC_ASSERT(EFX_LINK_10000FDX == EFX_PHY_CAP_10000FDX + 1);
737 for (mode = EFX_LINK_10HDX; mode <= EFX_LINK_10000FDX; mode++) {
738 mode_cap_mask = 1 << (mode - 1);
739 mode_ifm = sfxge_link_mode[medium_type][mode];
741 if ((cap_mask & mode_cap_mask) && mode_ifm) {
742 mode_cap_mask |= cap_mask & (1 << EFX_PHY_CAP_AN);
744 #ifdef SFXGE_HAVE_PAUSE_MEDIAOPTS
745 /* No flow-control */
746 ifmedia_add(&sc->media, mode_ifm, mode_cap_mask, NULL);
748 /* Respond-only. If using AN, we implicitly
749 * offer symmetric as well, but that doesn't
750 * mean we *have* to generate pause frames.
752 mode_cap_mask |= cap_mask & ((1 << EFX_PHY_CAP_PAUSE) |
753 (1 << EFX_PHY_CAP_ASYM));
754 mode_ifm |= IFM_ETH_RXPAUSE;
755 ifmedia_add(&sc->media, mode_ifm, mode_cap_mask, NULL);
758 mode_cap_mask &= ~(1 << EFX_PHY_CAP_ASYM);
759 mode_ifm |= IFM_ETH_TXPAUSE;
760 #else /* !SFXGE_HAVE_PAUSE_MEDIAOPTS */
761 mode_cap_mask |= cap_mask & (1 << EFX_PHY_CAP_PAUSE);
763 ifmedia_add(&sc->media, mode_ifm, mode_cap_mask, NULL);
765 /* Link modes are numbered in order of speed,
766 * so assume the last one available is the best.
768 best_mode_ifm = mode_ifm;
772 if (cap_mask & (1 << EFX_PHY_CAP_AN)) {
773 /* Add autoselect mode. */
774 mode_ifm = IFM_ETHER | IFM_AUTO;
775 ifmedia_add(&sc->media, mode_ifm,
776 cap_mask & ~(1 << EFX_PHY_CAP_ASYM), NULL);
777 best_mode_ifm = mode_ifm;
781 ifmedia_set(&sc->media, best_mode_ifm);
783 /* Now discard port state until interface is started. */
784 efx_port_fini(sc->enp);
786 efx_nic_fini(sc->enp);