2 * Copyright (c) 2008, 2009, 2010 Nikolay Denev <ndenev@gmail.com>
3 * Copyright (c) 2007, 2008 Alexander Pohoyda <alexander.pohoyda@gmx.net>
4 * Copyright (c) 1997, 1998, 1999
5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS''
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
25 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL AUTHORS OR
26 * THE VOICES IN THEIR HEADS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
31 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
33 * OF THE POSSIBILITY OF SUCH DAMAGE.
44 #define SIS_VENDORID 0x1039
49 #define SIS_DEVICEID_190 0x0190
50 #define SIS_DEVICEID_191 0x0191
54 #define Reserved0 0x08
59 #define Reserved1 0x18
62 #define IntrStatus 0x20
64 #define IntrControl 0x28
65 #define IntrTimer 0x2c
67 #define PMControl 0x30
68 #define Reserved2 0x34
69 #define ROMControl 0x38
70 #define ROMInterface 0x3c
71 #define StationControl 0x40
72 #define GMIIControl 0x44
74 #define GMacIOCTL 0x4c
75 #define TxMacControl 0x50
76 #define TxMacTimeLimit 0x54
77 #define RGMIIDelay 0x58
78 #define Reserved3 0x5c
79 #define RxMacControl 0x60 /* 1 WORD */
80 #define RxMacAddr 0x62 /* 6x BYTE */
81 #define RxHashTable 0x68 /* 1 LONG */
82 #define RxHashTable2 0x6c /* 1 LONG */
83 #define RxWakeOnLan 0x70
84 #define RxWakeOnLanData 0x74
85 #define RxMPSControl 0x78
86 #define Reserved4 0x7c
89 * IntrStatus Register Content
91 #define INTR_SOFT 0x40000000
92 #define INTR_TIMER 0x20000000
93 #define INTR_PAUSE_FRAME 0x00080000
94 #define INTR_MAGIC_FRAME 0x00040000
95 #define INTR_WAKE_FRAME 0x00020000
96 #define INTR_LINK 0x00010000
97 #define INTR_RX_IDLE 0x00000080
98 #define INTR_RX_DONE 0x00000040
99 #define INTR_TXQ1_IDLE 0x00000020
100 #define INTR_TXQ1_DONE 0x00000010
101 #define INTR_TX_IDLE 0x00000008
102 #define INTR_TX_DONE 0x00000004
103 #define INTR_RX_HALT 0x00000002
104 #define INTR_TX_HALT 0x00000001
107 (INTR_RX_IDLE | INTR_RX_DONE | INTR_TXQ1_IDLE | \
108 INTR_TXQ1_DONE |INTR_TX_IDLE | INTR_TX_DONE | \
109 INTR_TX_HALT | INTR_RX_HALT)
112 * RxStatusDesc Register Content
114 #define RxRES 0x00200000
115 #define RxCRC 0x00080000
116 #define RxRUNT 0x00100000
117 #define RxRWT 0x00400000
120 * RX_CTL Register Content
122 #define RX_CTL_POLL 0x00000010
123 #define RX_CTL_ENB 0x00000001
126 * TX_CTL Register Content
128 #define TX_CTL_POLL 0x00000010
129 #define TX_CTL_ENB 0x00000001
132 * RxMacControl Register Content
134 #define AcceptBroadcast 0x0800
135 #define AcceptMulticast 0x0400
136 #define AcceptMyPhys 0x0200
137 #define AcceptAllPhys 0x0100
138 #define AcceptErr 0x0020
139 #define AcceptRunt 0x0010
140 #define RXMAC_STRIP_VLAN 0x0020
141 #define RXMAC_STRIP_FCS 0x0010
142 #define RXMAC_PAD_ENB 0x0004
143 #define RXMAC_CSUM_ENB 0x0002
145 #define SGE_RX_PAD_BYTES 10
147 /* Station control register. */
148 #define SC_LOOPBACK 0x80000000
149 #define SC_RGMII 0x00008000
150 #define SC_FDX 0x00001000
151 #define SC_SPEED_MASK 0x00000c00
152 #define SC_SPEED_10 0x00000400
153 #define SC_SPEED_100 0x00000800
154 #define SC_SPEED_1000 0x00000c00
157 * Gigabit Media Independent Interface CTL register
159 #define GMI_DATA 0xffff0000
160 #define GMI_DATA_SHIFT 16
161 #define GMI_REG 0x0000f800
162 #define GMI_REG_SHIFT 11
163 #define GMI_PHY 0x000007c0
164 #define GMI_PHY_SHIFT 6
165 #define GMI_OP_WR 0x00000020
166 #define GMI_OP_RD 0x00000000
167 #define GMI_REQ 0x00000010
168 #define GMI_MDIO 0x00000008
169 #define GMI_MDDIR 0x00000004
170 #define GMI_MDC 0x00000002
171 #define GMI_MDEN 0x00000001
173 /* Tx descriptor command bits. */
174 #define TDC_OWN 0x80000000
175 #define TDC_INTR 0x40000000
176 #define TDC_THOL3 0x30000000
177 #define TDC_THOL2 0x20000000
178 #define TDC_THOL1 0x10000000
179 #define TDC_THOL0 0x00000000
180 #define TDC_LS 0x08000000
181 #define TDC_IP_CSUM 0x04000000
182 #define TDC_TCP_CSUM 0x02000000
183 #define TDC_UDP_CSUM 0x01000000
184 #define TDC_BST 0x00800000
185 #define TDC_EXT 0x00400000
186 #define TDC_DEF 0x00200000
187 #define TDC_BKF 0x00100000
188 #define TDC_CRS 0x00080000
189 #define TDC_COL 0x00040000
190 #define TDC_CRC 0x00020000
191 #define TDC_PAD 0x00010000
192 #define TDC_VLAN_MASK 0x0000FFFF
194 #define SGE_TX_INTR_FRAMES 32
197 * TX descriptor status bits.
199 #define TDS_INS_VLAN 0x80000000
200 #define TDS_OWC 0x00080000
201 #define TDS_ABT 0x00040000
202 #define TDS_FIFO 0x00020000
203 #define TDS_CRS 0x00010000
204 #define TDS_COLLS 0x0000ffff
205 #define SGE_TX_ERROR(x) ((x) & (TDS_OWC | TDS_ABT | TDS_FIFO | TDS_CRS))
206 #define TX_ERR_BITS "\20" \
207 "\21CRS\22FIFO\23ABT\24OWC"
209 /* Rx descriptor command bits. */
210 #define RDC_OWN 0x80000000
211 #define RDC_INTR 0x40000000
212 #define RDC_IP_CSUM 0x20000000
213 #define RDC_TCP_CSUM 0x10000000
214 #define RDC_UDP_CSUM 0x08000000
215 #define RDC_IP_CSUM_OK 0x04000000
216 #define RDC_TCP_CSUM_OK 0x02000000
217 #define RDC_UDP_CSUM_OK 0x01000000
218 #define RDC_WAKEUP 0x00400000
219 #define RDC_MAGIC 0x00200000
220 #define RDC_PAUSE 0x00100000
221 #define RDC_BCAST 0x000c0000
222 #define RDC_MCAST 0x00080000
223 #define RDC_UCAST 0x00040000
224 #define RDC_CRCOFF 0x00020000
225 #define RDC_PREADD 0x00010000
226 #define RDC_VLAN_MASK 0x0000FFFF
229 * RX descriptor status bits
231 #define RDS_VLAN 0x80000000
232 #define RDS_DESCS 0x3f000000
233 #define RDS_ABORT 0x00800000
234 #define RDS_SHORT 0x00400000
235 #define RDS_LIMIT 0x00200000
236 #define RDS_MIIER 0x00100000
237 #define RDS_OVRUN 0x00080000
238 #define RDS_NIBON 0x00040000
239 #define RDS_COLON 0x00020000
240 #define RDS_CRCOK 0x00010000
241 #define SGE_RX_ERROR(x) \
242 ((x) & (RDS_COLON | RDS_NIBON | RDS_OVRUN | RDS_MIIER | \
243 RDS_LIMIT | RDS_SHORT | RDS_ABORT))
244 #define SGE_RX_NSEGS(x) (((x) & RDS_DESCS) >> 24)
245 #define RX_ERR_BITS "\20" \
246 "\21CRCOK\22COLON\23NIBON\24OVRUN" \
247 "\25MIIER\26LIMIT\27SHORT\30ABORT" \
250 #define RING_END 0x80000000
251 #define SGE_RX_BYTES(x) ((x) & 0xFFFF)
252 #define SGE_INC(x, y) (x) = (((x) + 1) % y)
254 /* Taken from Solaris driver */
255 #define EI_DATA 0xffff0000
256 #define EI_DATA_SHIFT 16
257 #define EI_OFFSET 0x0000fc00
258 #define EI_OFFSET_SHIFT 10
259 #define EI_OP 0x00000300
260 #define EI_OP_SHIFT 8
261 #define EI_OP_RD (2 << EI_OP_SHIFT)
262 #define EI_OP_WR (1 << EI_OP_SHIFT)
263 #define EI_REQ 0x00000080
264 #define EI_DO 0x00000008
265 #define EI_DI 0x00000004
266 #define EI_CLK 0x00000002
267 #define EI_CS 0x00000001
272 #define EEPROMSignature 0x00
273 #define EEPROMCLK 0x01
274 #define EEPROMInfo 0x02
275 #define EEPROMMACAddr 0x03
278 uint32_t sge_sts_size;
284 #define SGE_RX_RING_CNT 256 /* [8, 1024] */
285 #define SGE_TX_RING_CNT 256 /* [8, 8192] */
286 #define SGE_DESC_ALIGN 16
287 #define SGE_MAXTXSEGS 32
288 #define SGE_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header))
289 #define SGE_TSO_MAXSEGSIZE 4096
290 #define SGE_RX_BUF_ALIGN sizeof(uint64_t)
292 #define SGE_RX_RING_SZ (SGE_RX_RING_CNT * sizeof(struct sge_desc))
293 #define SGE_TX_RING_SZ (SGE_TX_RING_CNT * sizeof(struct sge_desc))
294 #define SGE_ADDR_LO(x) ((uint64_t) (x) & 0xFFFFFFFF)
296 struct sge_list_data {
297 struct sge_desc *sge_rx_ring;
298 struct sge_desc *sge_tx_ring;
299 /* physical bus addresses of sge_rx_ring/sge_tx_ring */
300 bus_addr_t sge_rx_paddr;
301 bus_addr_t sge_tx_paddr;
306 bus_dmamap_t tx_dmamap;
312 bus_dmamap_t rx_dmamap;
315 struct sge_chain_data {
316 bus_dma_tag_t sge_tag;
317 bus_dma_tag_t sge_rx_tag;
318 bus_dma_tag_t sge_tx_tag;
319 bus_dmamap_t sge_rx_dmamap;
320 bus_dmamap_t sge_tx_dmamap;
321 bus_dma_tag_t sge_txmbuf_tag;
322 bus_dma_tag_t sge_rxmbuf_tag;
323 struct sge_txdesc sge_txdesc[SGE_TX_RING_CNT];
324 struct sge_rxdesc sge_rxdesc[SGE_RX_RING_CNT];
325 bus_dmamap_t sge_rx_spare_map;
339 struct ifnet *sge_ifp; /* interface info */
340 struct resource *sge_res;
343 struct resource *sge_irq;
348 struct sge_list_data sge_ldata;
349 struct sge_chain_data sge_cdata;
350 struct callout sge_stat_ch;
353 #define SGE_FLAG_FASTETHER 0x0001
354 #define SGE_FLAG_SIS190 0x0002
355 #define SGE_FLAG_RGMII 0x0010
356 #define SGE_FLAG_SPEED_1000 0x2000
357 #define SGE_FLAG_FDX 0x4000
358 #define SGE_FLAG_LINK 0x8000
365 #define SGE_LOCK(_sc) mtx_lock(&(_sc)->sge_mtx)
366 #define SGE_UNLOCK(_sc) mtx_unlock(&(_sc)->sge_mtx)
367 #define SGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sge_mtx, MA_OWNED)
369 #define SGE_TIMEOUT 1000
371 #endif /* _IF_SGEREG_H */