2 * Copyright (c) 2007 Bruce M. Simpson.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * TODO: implement dma translation bits (if needed for system bus)
34 #ifndef _SIBA_SIBAREG_H_
35 #define _SIBA_SIBAREG_H_
37 #define PCI_DEVICE_ID_BCM4401 0x4401
38 #define PCI_DEVICE_ID_BCM4401B0 0x4402
39 #define PCI_DEVICE_ID_BCM4401B1 0x170c
40 #define SIBA_PCIR_BAR PCIR_BAR(0)
41 #define SIBA_CCID_BCM4710 0x4710
42 #define SIBA_CCID_BCM4704 0x4704
43 #define SIBA_CCID_SENTRY5 0x5365
46 * ChipCommon registers.
48 #define SIBA_CC_CHIPID 0x0000
49 #define SIBA_CC_IDMASK 0x0000ffff
50 #define SIBA_CC_ID(id) (id & SIBA_CC_IDMASK)
51 #define SIBA_CC_REVMASK 0x000f0000
52 #define SIBA_CC_REVSHIFT 16
53 #define SIBA_CC_REV(id) \
54 ((id & SIBA_CC_REVMASK) >> SIBA_CC_REVSHIFT)
55 #define SIBA_CC_PKGMASK 0x00F00000
56 #define SIBA_CC_PKGSHIFT 20
57 #define SIBA_CC_PKG(id) \
58 ((id & SIBA_CC_PKGMASK) >> SIBA_CC_PKGSHIFT)
59 #define SIBA_CC_NCORESMASK 0x0F000000
60 #define SIBA_CC_NCORESSHIFT 24
61 #define SIBA_CC_NCORES(id) \
62 ((id & SIBA_CC_NCORESMASK) >> SIBA_CC_NCORESSHIFT)
63 #define SIBA_CC_CAPS 0x0004
64 #define SIBA_CC_CAPS_PWCTL 0x00040000
65 #define SIBA_CC_CAPS_PMU 0x10000000 /* PMU (rev >= 20) */
66 #define SIBA_CC_CHIPCTL 0x0028 /* rev >= 11 */
67 #define SIBA_CC_CHIPSTAT 0x002C /* rev >= 11 */
68 #define SIBA_CC_BCAST_ADDR 0x0050 /* Broadcast Address */
69 #define SIBA_CC_BCAST_DATA 0x0054 /* Broadcast Data */
70 #define SIBA_CC_PLLONDELAY 0x00B0 /* Rev >= 4 only */
71 #define SIBA_CC_FREFSELDELAY 0x00B4 /* Rev >= 4 only */
72 #define SIBA_CC_CLKSLOW 0x00b8 /* 6 <= Rev <= 9 only */
73 #define SIBA_CC_CLKSLOW_SRC 0x00000007
74 #define SIBA_CC_CLKSLOW_SRC_CRYSTAL 0x00000001
75 #define SIBA_CC_CLKSLOW_FSLOW 0x00000800
76 #define SIBA_CC_CLKSLOW_IPLL 0x00001000
77 #define SIBA_CC_CLKSLOW_ENXTAL 0x00002000
78 #define SIBA_CC_CLKSYSCTL 0x00C0 /* Rev >= 3 only */
79 #define SIBA_CC_CLKCTLSTATUS 0x01e0
80 #define SIBA_CC_CLKCTLSTATUS_HT 0x00010000
81 #define SIBA_CC_UART0 0x0300 /* offset of UART0 */
82 #define SIBA_CC_UART1 0x0400 /* offset of UART1 */
83 #define SIBA_CC_PMUCTL 0x0600 /* PMU control */
84 #define SIBA_CC_PMUCTL_ILP 0xffff0000 /* mask */
85 #define SIBA_CC_PMUCTL_NOILP 0x00000200
86 #define SIBA_CC_PMUCTL_XF 0x0000007c /* crystal freq */
87 #define SIBA_CC_PMUCTL_XF_VAL(id) ((id & 0x0000007c) >> 2)
88 #define SIBA_CC_PMUCAPS 0x0604
89 #define SIBA_CC_PMUCAPS_REV 0x000000ff
90 #define SIBA_CC_PMU_MINRES 0x0618
91 #define SIBA_CC_PMU_MAXRES 0x061c
92 #define SIBA_CC_PMU_TABSEL 0x0620
93 #define SIBA_CC_PMU_DEPMSK 0x0624
94 #define SIBA_CC_PMU_UPDNTM 0x0628
95 #define SIBA_CC_REGCTL_ADDR 0x0658
96 #define SIBA_CC_REGCTL_DATA 0x065c
97 #define SIBA_CC_PLLCTL_ADDR 0x0660
98 #define SIBA_CC_PLLCTL_DATA 0x0664
100 #define SIBA_CC_PMU0_PLL0 0
101 #define SIBA_CC_PMU0_PLL0_PDIV_MSK 0x00000001
102 #define SIBA_CC_PMU0_PLL0_PDIV_FREQ 25000
103 #define SIBA_CC_PMU0_PLL1 1
104 #define SIBA_CC_PMU0_PLL1_IMSK 0xf0000000
105 #define SIBA_CC_PMU0_PLL1_FMSK 0x0fffff00
106 #define SIBA_CC_PMU0_PLL1_STOPMOD 0x00000040
107 #define SIBA_CC_PMU0_PLL2 2
108 #define SIBA_CC_PMU0_PLL2_IMSKHI 0x0000000f
109 #define SIBA_CC_PMU1_PLL0 0
110 #define SIBA_CC_PMU1_PLL0_P1DIV 0x00f00000
111 #define SIBA_CC_PMU1_PLL0_P2DIV 0x0f000000
112 #define SIBA_CC_PMU1_PLL2 2
113 #define SIBA_CC_PMU1_PLL2_NDIVMODE 0x000e0000
114 #define SIBA_CC_PMU1_PLL2_NDIVINT 0x1ff00000
115 #define SIBA_CC_PMU1_PLL3 3
116 #define SIBA_CC_PMU1_PLL3_NDIVFRAC 0x00ffffff
117 #define SIBA_CC_PMU1_PLL5 5
118 #define SIBA_CC_PMU1_PLL5_CLKDRV 0xffffff00
120 #define SIBA_CC_PMU0_DEFAULT_XTALFREQ 20000
121 #define SIBA_CC_PMU1_DEFAULT_FREQ 15360
123 #define SIBA_CC_PMU1_PLLTAB_ENTRY \
125 { 12000, 1, 3, 22, 0x9, 0xffffef }, \
126 { 13000, 2, 1, 6, 0xb, 0x483483 }, \
127 { 14400, 3, 1, 10, 0xa, 0x1c71c7 }, \
128 { 15360, 4, 1, 5, 0xb, 0x755555 }, \
129 { 16200, 5, 1, 10, 0x5, 0x6e9e06 }, \
130 { 16800, 6, 1, 10, 0x5, 0x3cf3cf }, \
131 { 19200, 7, 1, 9, 0x5, 0x17b425 }, \
132 { 19800, 8, 1, 11, 0x4, 0xa57eb }, \
133 { 20000, 9, 1, 11, 0x4, 0 }, \
134 { 24000, 10, 3, 11, 0xa, 0 }, \
135 { 25000, 11, 5, 16, 0xb, 0 }, \
136 { 26000, 12, 1, 2, 0x10, 0xec4ec4 }, \
137 { 30000, 13, 3, 8, 0xb, 0 }, \
138 { 38400, 14, 1, 5, 0x4, 0x955555 }, \
139 { 40000, 15, 1, 2, 0xb, 0 } \
142 #define SIBA_CC_PMU0_PLLTAB_ENTRY \
144 { 12000, 1, 73, 349525, }, { 13000, 2, 67, 725937, }, \
145 { 14400, 3, 61, 116508, }, { 15360, 4, 57, 305834, }, \
146 { 16200, 5, 54, 336579, }, { 16800, 6, 52, 399457, }, \
147 { 19200, 7, 45, 873813, }, { 19800, 8, 44, 466033, }, \
148 { 20000, 9, 44, 0, }, { 25000, 10, 70, 419430, }, \
149 { 26000, 11, 67, 725937, }, { 30000, 12, 58, 699050, }, \
150 { 38400, 13, 45, 873813, }, { 40000, 14, 45, 0, }, \
153 #define SIBA_CC_PMU_4312_PA_REF 2
154 #define SIBA_CC_PMU_4325_BURST 1
155 #define SIBA_CC_PMU_4325_CLBURST 3
156 #define SIBA_CC_PMU_4325_LN 10
157 #define SIBA_CC_PMU_4325_CRYSTAL 13
158 #define SIBA_CC_PMU_4325_RX_PWR 15
159 #define SIBA_CC_PMU_4325_TX_PWR 16
160 #define SIBA_CC_PMU_4325_LOGEN_PWR 18
161 #define SIBA_CC_PMU_4325_AFE_PWR 19
162 #define SIBA_CC_PMU_4325_BBPLL_PWR 20
163 #define SIBA_CC_PMU_4325_HT 21
164 #define SIBA_CC_PMU_4328_EXT_SWITCH_PWM 0
165 #define SIBA_CC_PMU_4328_BB_SWITCH_PWM 1
166 #define SIBA_CC_PMU_4328_BB_SWITCH_BURST 2
167 #define SIBA_CC_PMU_4328_BB_EXT_SWITCH_BURST 3
168 #define SIBA_CC_PMU_4328_ILP_REQUEST 4
169 #define SIBA_CC_PMU_4328_RADSWITCH_PWM 5 /* radio switch */
170 #define SIBA_CC_PMU_4328_RADSWITCH_BURST 6
171 #define SIBA_CC_PMU_4328_ROM_SWITCH 7
172 #define SIBA_CC_PMU_4328_PA_REF 8
173 #define SIBA_CC_PMU_4328_RADIO 9
174 #define SIBA_CC_PMU_4328_AFE 10
175 #define SIBA_CC_PMU_4328_PLL 11
176 #define SIBA_CC_PMU_4328_BG_FILTBYP 12
177 #define SIBA_CC_PMU_4328_TX_FILTBYP 13
178 #define SIBA_CC_PMU_4328_RX_FILTBYP 14
179 #define SIBA_CC_PMU_4328_CRYSTAL_PU 15
180 #define SIBA_CC_PMU_4328_CRYSTAL_EN 16
181 #define SIBA_CC_PMU_4328_BB_PLL_FILTBYP 17
182 #define SIBA_CC_PMU_4328_RF_PLL_FILTBYP 18
183 #define SIBA_CC_PMU_4328_BB_PLL_PU 19
184 #define SIBA_CC_PMU_5354_PA_REF 8
185 #define SIBA_CC_PMU_5354_BB_PLL_PU 19
187 #define SIBA_CC_PMU_4325_RES_UPDOWN \
189 { SIBA_CC_PMU_4325_CRYSTAL, 0x1501 } \
192 #define SIBA_CC_PMU_4325_RES_DEPEND \
194 { SIBA_CC_PMU_4325_HT, SIBA_CC_PMU_DEP_ADD, \
195 ((1 << SIBA_CC_PMU_4325_RX_PWR) | \
196 (1 << SIBA_CC_PMU_4325_TX_PWR) | \
197 (1 << SIBA_CC_PMU_4325_LOGEN_PWR) | \
198 (1 << SIBA_CC_PMU_4325_AFE_PWR)) } \
201 #define SIBA_CC_PMU_4328_RES_UPDOWN \
203 { SIBA_CC_PMU_4328_EXT_SWITCH_PWM, 0x0101 }, \
204 { SIBA_CC_PMU_4328_BB_SWITCH_PWM, 0x1f01 }, \
205 { SIBA_CC_PMU_4328_BB_SWITCH_BURST, 0x010f }, \
206 { SIBA_CC_PMU_4328_BB_EXT_SWITCH_BURST, 0x0101 }, \
207 { SIBA_CC_PMU_4328_ILP_REQUEST, 0x0202 }, \
208 { SIBA_CC_PMU_4328_RADSWITCH_PWM, 0x0f01 }, \
209 { SIBA_CC_PMU_4328_RADSWITCH_BURST, 0x0f01 }, \
210 { SIBA_CC_PMU_4328_ROM_SWITCH, 0x0101 }, \
211 { SIBA_CC_PMU_4328_PA_REF, 0x0f01 }, \
212 { SIBA_CC_PMU_4328_RADIO, 0x0f01 }, \
213 { SIBA_CC_PMU_4328_AFE, 0x0f01 }, \
214 { SIBA_CC_PMU_4328_PLL, 0x0f01 }, \
215 { SIBA_CC_PMU_4328_BG_FILTBYP, 0x0101 }, \
216 { SIBA_CC_PMU_4328_TX_FILTBYP, 0x0101 }, \
217 { SIBA_CC_PMU_4328_RX_FILTBYP, 0x0101 }, \
218 { SIBA_CC_PMU_4328_CRYSTAL_PU, 0x0101 }, \
219 { SIBA_CC_PMU_4328_CRYSTAL_EN, 0xa001 }, \
220 { SIBA_CC_PMU_4328_BB_PLL_FILTBYP, 0x0101 }, \
221 { SIBA_CC_PMU_4328_RF_PLL_FILTBYP, 0x0101 }, \
222 { SIBA_CC_PMU_4328_BB_PLL_PU, 0x0701 }, \
225 #define SIBA_CC_PMU_4328_RES_DEPEND \
227 { SIBA_CC_PMU_4328_ILP_REQUEST, SIBA_CC_PMU_DEP_SET, \
228 ((1 << SIBA_CC_PMU_4328_EXT_SWITCH_PWM) | \
229 (1 << SIBA_CC_PMU_4328_BB_SWITCH_PWM)) }, \
232 #define SIBA_CC_CHST_4325_PMUTOP_2B 0x00000200
234 #define SIBA_BAR0 0x80
235 #define SIBA_IRQMASK 0x94
236 #define SIBA_GPIO_IN 0xb0
237 #define SIBA_GPIO_OUT 0xb4
238 #define SIBA_GPIO_OUT_EN 0xb8
239 #define SIBA_GPIO_CRYSTAL 0x40
240 #define SIBA_GPIO_PLL 0x80
242 #define SIBA_REGWIN(x) \
243 (SIBA_ENUM_START + ((x) * SIBA_CORE_LEN))
244 #define SIBA_CORE_LEN 0x00001000 /* Size of cfg per core */
245 #define SIBA_CFG_END 0x00010000 /* Upper bound of cfg space */
246 #define SIBA_MAX_CORES (SIBA_CFG_END/SIBA_CORE_LEN) /* #max cores */
247 #define SIBA_ENUM_START 0x18000000U
248 #define SIBA_ENUM_END 0x18010000U
250 #define SIBA_DMA_TRANSLATION_MASK 0xc0000000
252 #define SIBA_PCI_DMA 0x40000000U
253 #define SIBA_TPS 0x0f18
254 #define SIBA_TPS_BPFLAG 0x0000003f
255 #define SIBA_IAS 0x0f90 /* Initiator Agent State */
256 #define SIBA_IAS_INBAND_ERR 0x00020000
257 #define SIBA_IAS_TIMEOUT 0x00040000
258 #define SIBA_INTR_MASK 0x0f94
259 #define SIBA_TGSLOW 0x0f98
260 #define SIBA_TGSLOW_RESET 0x00000001 /* target state low */
261 #define SIBA_TGSLOW_REJECT_22 0x00000002
262 #define SIBA_TGSLOW_REJECT_23 0x00000004
263 #define SIBA_TGSLOW_CLOCK 0x00010000
264 #define SIBA_TGSLOW_FGC 0x00020000
265 #define SIBA_TGSHIGH 0x0f9c
266 #define SIBA_TGSHIGH_SERR 0x00000001
267 #define SIBA_TGSHIGH_BUSY 0x00000004
268 #define SIBA_TGSHIGH_DMA64 0x10000000
269 #define SIBA_IMCFGLO 0x0fa8
270 #define SIBA_IMCFGLO_SERTO 0x00000007
271 #define SIBA_IMCFGLO_REQTO 0x00000070
272 #define SIBA_IDLOW 0x0ff8
273 #define SIBA_IDLOW_SSBREV 0xf0000000
274 #define SIBA_IDLOW_SSBREV_22 0x00000000
275 #define SIBA_IDLOW_SSBREV_23 0x10000000
276 #define SIBA_IDLOW_SSBREV_24 0x40000000
277 #define SIBA_IDLOW_SSBREV_25 0x50000000
278 #define SIBA_IDLOW_SSBREV_26 0x60000000
279 #define SIBA_IDLOW_SSBREV_27 0x70000000
280 #define SIBA_IDHIGH 0x0ffc
281 #define SIBA_IDHIGH_CORECODEMASK 0x00008FF0 /* Core Code */
282 #define SIBA_IDHIGH_CORECODE_SHIFT 4
283 #define SIBA_IDHIGH_CORECODE(id) \
284 ((id & SIBA_IDHIGH_CORECODEMASK) >> SIBA_IDHIGH_CORECODE_SHIFT)
285 /* Revision Code (low part) */
286 #define SIBA_IDHIGH_REVLO 0x0000000f
287 /* Revision Code (high part) */
288 #define SIBA_IDHIGH_REVHI 0x00007000
289 #define SIBA_IDHIGH_REVHI_SHIFT 8
290 #define SIBA_IDHIGH_REV(id) \
291 ((id & SIBA_IDHIGH_REVLO) | ((id & SIBA_IDHIGH_REVHI) >> \
292 SIBA_IDHIGH_REVHI_SHIFT))
293 #define SIBA_IDHIGH_VENDORMASK 0xFFFF0000 /* Vendor Code */
294 #define SIBA_IDHIGH_VENDOR_SHIFT 16
295 #define SIBA_IDHIGH_VENDOR(id) \
296 ((id & SIBA_IDHIGH_VENDORMASK) >> SIBA_IDHIGH_VENDOR_SHIFT)
298 #define SIBA_SPROMSIZE_R123 64
299 #define SIBA_SPROMSIZE_R4 220
300 #define SIBA_SPROM_BASE 0x1000
301 #define SIBA_SPROM_REV_CRC 0xff00
302 #define SIBA_SPROM1_MAC_80211BG 0x1048
303 #define SIBA_SPROM1_MAC_ETH 0x104e
304 #define SIBA_SPROM1_MAC_80211A 0x1054
305 #define SIBA_SPROM1_ETHPHY 0x105a
306 #define SIBA_SPROM1_ETHPHY_MII_ETH0 0x001f
307 #define SIBA_SPROM1_ETHPHY_MII_ETH1 0x03e0
308 #define SIBA_SPROM1_ETHPHY_MDIO_ETH0 (1 << 14)
309 #define SIBA_SPROM1_ETHPHY_MDIO_ETH1 (1 << 15)
310 #define SIBA_SPROM1_BOARDINFO 0x105c
311 #define SIBA_SPROM1_BOARDINFO_BREV 0x00ff
312 #define SIBA_SPROM1_BOARDINFO_CCODE 0x0f00
313 #define SIBA_SPROM1_BOARDINFO_ANTBG 0x3000
314 #define SIBA_SPROM1_BOARDINFO_ANTA 0xc000
315 #define SIBA_SPROM1_PA0B0 0x105e
316 #define SIBA_SPROM1_PA0B1 0x1060
317 #define SIBA_SPROM1_PA0B2 0x1062
318 #define SIBA_SPROM1_GPIOA 0x1064
319 #define SIBA_SPROM1_GPIOA_P0 0x00ff
320 #define SIBA_SPROM1_GPIOA_P1 0xff00
321 #define SIBA_SPROM1_GPIOB 0x1066
322 #define SIBA_SPROM1_GPIOB_P2 0x00ff
323 #define SIBA_SPROM1_GPIOB_P3 0xff00
324 #define SIBA_SPROM1_MAXPWR 0x1068
325 #define SIBA_SPROM1_MAXPWR_BG 0x00ff
326 #define SIBA_SPROM1_MAXPWR_A 0xff00
327 #define SIBA_SPROM1_PA1B0 0x106a
328 #define SIBA_SPROM1_PA1B1 0x106c
329 #define SIBA_SPROM1_PA1B2 0x106e
330 #define SIBA_SPROM1_TSSI 0x1070
331 #define SIBA_SPROM1_TSSI_BG 0x00ff
332 #define SIBA_SPROM1_TSSI_A 0xff00
333 #define SIBA_SPROM1_BFLOW 0x1072
334 #define SIBA_SPROM1_AGAIN 0x1074
335 #define SIBA_SPROM1_AGAIN_BG 0x00ff
336 #define SIBA_SPROM1_AGAIN_A 0xff00
337 #define SIBA_SPROM2_BFHIGH 0x1038
338 #define SIBA_SPROM3_MAC_80211BG 0x104a
339 #define SIBA_SPROM4_MAC_80211BG 0x104c
340 #define SIBA_SPROM4_ETHPHY 0x105a
341 #define SIBA_SPROM4_ETHPHY_ET0A 0x001f
342 #define SIBA_SPROM4_ETHPHY_ET1A 0x03e0
343 #define SIBA_SPROM4_CCODE 0x1052
344 #define SIBA_SPROM4_ANTAVAIL 0x105d
345 #define SIBA_SPROM4_ANTAVAIL_A 0x00ff
346 #define SIBA_SPROM4_ANTAVAIL_BG 0xff00
347 #define SIBA_SPROM4_BFLOW 0x1044
348 #define SIBA_SPROM4_AGAIN01 0x105e
349 #define SIBA_SPROM4_AGAIN0 0x00ff
350 #define SIBA_SPROM4_AGAIN1 0xff00
351 #define SIBA_SPROM4_AGAIN23 0x1060
352 #define SIBA_SPROM4_AGAIN2 0x00ff
353 #define SIBA_SPROM4_AGAIN3 0xff00
354 #define SIBA_SPROM4_BFHIGH 0x1046
355 #define SIBA_SPROM4_MAXP_BG 0x1080
356 #define SIBA_SPROM4_MAXP_BG_MASK 0x00ff
357 #define SIBA_SPROM4_TSSI_BG 0xff00
358 #define SIBA_SPROM4_MAXP_A 0x108a
359 #define SIBA_SPROM4_MAXP_A_MASK 0x00ff
360 #define SIBA_SPROM4_TSSI_A 0xff00
361 #define SIBA_SPROM4_GPIOA 0x1056
362 #define SIBA_SPROM4_GPIOA_P0 0x00ff
363 #define SIBA_SPROM4_GPIOA_P1 0xff00
364 #define SIBA_SPROM4_GPIOB 0x1058
365 #define SIBA_SPROM4_GPIOB_P2 0x00ff
366 #define SIBA_SPROM4_GPIOB_P3 0xff00
367 #define SIBA_SPROM5_BFLOW 0x104a
368 #define SIBA_SPROM5_BFHIGH 0x104c
369 #define SIBA_SPROM5_MAC_80211BG 0x1052
370 #define SIBA_SPROM5_CCODE 0x1044
371 #define SIBA_SPROM5_GPIOA 0x1076
372 #define SIBA_SPROM5_GPIOA_P0 0x00ff
373 #define SIBA_SPROM5_GPIOA_P1 0xff00
374 #define SIBA_SPROM5_GPIOB 0x1078
375 #define SIBA_SPROM5_GPIOB_P2 0x00ff
376 #define SIBA_SPROM5_GPIOB_P3 0xff00
377 #define SIBA_SPROM8_BFLOW 0x1084
378 #define SIBA_SPROM8_BFHIGH 0x1086
379 #define SIBA_SPROM8_BFL2LO 0x1088
380 #define SIBA_SPROM8_BFL2HI 0x108a
381 #define SIBA_SPROM8_MAC_80211BG 0x108c
382 #define SIBA_SPROM8_CCODE 0x1092
383 #define SIBA_SPROM8_ANTAVAIL 0x109c
384 #define SIBA_SPROM8_ANTAVAIL_A 0xff00
385 #define SIBA_SPROM8_ANTAVAIL_BG 0x00ff
386 #define SIBA_SPROM8_AGAIN01 0x109e
387 #define SIBA_SPROM8_AGAIN0 0x00ff
388 #define SIBA_SPROM8_AGAIN1 0xff00
389 #define SIBA_SPROM8_GPIOA 0x1096
390 #define SIBA_SPROM8_GPIOA_P0 0x00ff
391 #define SIBA_SPROM8_GPIOA_P1 0xff00
392 #define SIBA_SPROM8_GPIOB 0x1098
393 #define SIBA_SPROM8_GPIOB_P2 0x00ff
394 #define SIBA_SPROM8_GPIOB_P3 0xff00
395 #define SIBA_SPROM8_AGAIN23 0x10a0
396 #define SIBA_SPROM8_AGAIN2 0x00ff
397 #define SIBA_SPROM8_AGAIN3 0xff00
398 #define SIBA_SPROM8_RSSIPARM2G 0x10a4
399 #define SIBA_SPROM8_RSSISMF2G 0x000f
400 #define SIBA_SPROM8_RSSISMC2G 0x00f0
401 #define SIBA_SPROM8_RSSISAV2G 0x0700 /* BITMASK */
402 #define SIBA_SPROM8_BXA2G 0x1800 /* BITMASK */
403 #define SIBA_SPROM8_RSSIPARM5G 0x10a6
404 #define SIBA_SPROM8_RSSISMF5G 0x000f
405 #define SIBA_SPROM8_RSSISMC5G 0x00f0
406 #define SIBA_SPROM8_RSSISAV5G 0x0700 /* BITMASK */
407 #define SIBA_SPROM8_BXA5G 0x1800 /* BITMASK */
408 #define SIBA_SPROM8_TRI25G 0x10a8
409 #define SIBA_SPROM8_TRI2G 0x00ff
410 #define SIBA_SPROM8_TRI5G 0xff00
411 #define SIBA_SPROM8_TRI5GHL 0x10aa
412 #define SIBA_SPROM8_TRI5GL 0x00ff
413 #define SIBA_SPROM8_TRI5GH 0xff00
414 #define SIBA_SPROM8_RXPO 0x10ac
415 #define SIBA_SPROM8_RXPO2G 0x00ff
416 #define SIBA_SPROM8_RXPO5G 0xff00
417 #define SIBA_SPROM8_MAXP_BG 0x10c0
418 #define SIBA_SPROM8_MAXP_BG_MASK 0x00ff
419 #define SIBA_SPROM8_TSSI_BG 0xff00
420 #define SIBA_SPROM8_PA0B0 0x10c2
421 #define SIBA_SPROM8_PA0B1 0x10c4
422 #define SIBA_SPROM8_PA0B2 0x10c6
423 #define SIBA_SPROM8_MAXP_A 0x10c8
424 #define SIBA_SPROM8_MAXP_A_MASK 0x00ff
425 #define SIBA_SPROM8_TSSI_A 0xff00
426 #define SIBA_SPROM8_MAXP_AHL 0x10ca
427 #define SIBA_SPROM8_MAXP_AH_MASK 0x00ff
428 #define SIBA_SPROM8_MAXP_AL_MASK 0xff00
429 #define SIBA_SPROM8_PA1B0 0x10cc
430 #define SIBA_SPROM8_PA1B1 0x10ce
431 #define SIBA_SPROM8_PA1B2 0x10d0
432 #define SIBA_SPROM8_PA1LOB0 0x10d2
433 #define SIBA_SPROM8_PA1LOB1 0x10d4
434 #define SIBA_SPROM8_PA1LOB2 0x10d6
435 #define SIBA_SPROM8_PA1HIB0 0x10d8
436 #define SIBA_SPROM8_PA1HIB1 0x10da
437 #define SIBA_SPROM8_PA1HIB2 0x10dc
438 #define SIBA_SPROM8_CCK2GPO 0x1140
439 #define SIBA_SPROM8_OFDM2GPO 0x1142
440 #define SIBA_SPROM8_OFDM5GPO 0x1146
441 #define SIBA_SPROM8_OFDM5GLPO 0x114a
442 #define SIBA_SPROM8_OFDM5GHPO 0x114e
444 #define SIBA_BOARDVENDOR_DELL 0x1028
445 #define SIBA_BOARDVENDOR_BCM 0x14e4
446 #define SIBA_BOARD_BCM4309G 0x0421
447 #define SIBA_BOARD_MP4318 0x044a
448 #define SIBA_BOARD_BU4306 0x0416
449 #define SIBA_BOARD_BU4309 0x040a
451 #define SIBA_PCICORE_BCAST_ADDR SIBA_CC_BCAST_ADDR
452 #define SIBA_PCICORE_BCAST_DATA SIBA_CC_BCAST_DATA
453 #define SIBA_PCICORE_SBTOPCI0 0x0100
454 #define SIBA_PCICORE_SBTOPCI1 0x0104
455 #define SIBA_PCICORE_SBTOPCI2 0x0108
456 #define SIBA_PCICORE_MDIO_CTL 0x0128
457 #define SIBA_PCICORE_MDIO_DATA 0x012c
458 #define SIBA_PCICORE_SBTOPCI_PREF 0x00000004
459 #define SIBA_PCICORE_SBTOPCI_BURST 0x00000008
460 #define SIBA_PCICORE_SBTOPCI_MRM 0x00000020
462 #define SIBA_CHIPPACK_BCM4712S 1 /* Small 200pin 4712 */
464 #endif /* _SIBA_SIBAREG_H_ */