2 * Copyright (c) 2005 Poul-Henning Kamp <phk@FreeBSD.org>
3 * Copyright (c) 1997, 1998, 1999
4 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
38 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are
39 * available from http://www.sis.com.tw.
41 * This driver also supports the NatSemi DP83815. Datasheets are
42 * available from http://www.national.com.
44 * Written by Bill Paul <wpaul@ee.columbia.edu>
45 * Electrical Engineering Department
46 * Columbia University, New York City
49 * The SiS 900 is a fairly simple chip. It uses bus master DMA with
50 * simple TX and RX descriptors of 3 longwords in size. The receiver
51 * has a single perfect filter entry for the station address and a
52 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based
53 * transceiver while the 7016 requires an external transceiver chip.
54 * Both chips offer the standard bit-bang MII interface as well as
55 * an enchanced PHY interface which simplifies accessing MII registers.
57 * The only downside to this chipset is that RX descriptors must be
61 #ifdef HAVE_KERNEL_OPTION_HEADERS
62 #include "opt_device_polling.h"
65 #include <sys/param.h>
66 #include <sys/systm.h>
67 #include <sys/sockio.h>
69 #include <sys/malloc.h>
70 #include <sys/kernel.h>
71 #include <sys/module.h>
72 #include <sys/socket.h>
75 #include <net/if_arp.h>
76 #include <net/ethernet.h>
77 #include <net/if_dl.h>
78 #include <net/if_media.h>
79 #include <net/if_types.h>
80 #include <net/if_vlan_var.h>
84 #include <machine/bus.h>
85 #include <machine/resource.h>
89 #include <dev/mii/mii.h>
90 #include <dev/mii/miivar.h>
92 #include <dev/pci/pcireg.h>
93 #include <dev/pci/pcivar.h>
95 #define SIS_USEIOSPACE
97 #include <dev/sis/if_sisreg.h>
99 MODULE_DEPEND(sis, pci, 1, 1, 1);
100 MODULE_DEPEND(sis, ether, 1, 1, 1);
101 MODULE_DEPEND(sis, miibus, 1, 1, 1);
103 /* "device miibus" required. See GENERIC if you get errors here. */
104 #include "miibus_if.h"
106 #define SIS_LOCK(_sc) mtx_lock(&(_sc)->sis_mtx)
107 #define SIS_UNLOCK(_sc) mtx_unlock(&(_sc)->sis_mtx)
108 #define SIS_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sis_mtx, MA_OWNED)
111 * register space access macros
113 #define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->sis_res[0], reg, val)
115 #define CSR_READ_4(sc, reg) bus_read_4(sc->sis_res[0], reg)
117 #define CSR_READ_2(sc, reg) bus_read_2(sc->sis_res[0], reg)
120 * Various supported device vendors/types and their names.
122 static struct sis_type sis_devs[] = {
123 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" },
124 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" },
125 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" },
129 static int sis_detach(device_t);
130 static void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *);
131 static int sis_ifmedia_upd(struct ifnet *);
132 static void sis_init(void *);
133 static void sis_initl(struct sis_softc *);
134 static void sis_intr(void *);
135 static int sis_ioctl(struct ifnet *, u_long, caddr_t);
136 static int sis_newbuf(struct sis_softc *, struct sis_desc *, struct mbuf *);
137 static void sis_start(struct ifnet *);
138 static void sis_startl(struct ifnet *);
139 static void sis_stop(struct sis_softc *);
140 static void sis_watchdog(struct sis_softc *);
143 static struct resource_spec sis_res_spec[] = {
144 #ifdef SIS_USEIOSPACE
145 { SYS_RES_IOPORT, SIS_PCI_LOIO, RF_ACTIVE},
147 { SYS_RES_MEMORY, SIS_PCI_LOMEM, RF_ACTIVE},
149 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE},
153 #define SIS_SETBIT(sc, reg, x) \
154 CSR_WRITE_4(sc, reg, \
155 CSR_READ_4(sc, reg) | (x))
157 #define SIS_CLRBIT(sc, reg, x) \
158 CSR_WRITE_4(sc, reg, \
159 CSR_READ_4(sc, reg) & ~(x))
162 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x)
165 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x)
168 sis_dma_map_desc_next(void *arg, bus_dma_segment_t *segs, int nseg, int error)
173 r->sis_next = segs->ds_addr;
177 sis_dma_map_desc_ptr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
182 r->sis_ptr = segs->ds_addr;
186 sis_dma_map_ring(void *arg, bus_dma_segment_t *segs, int nseg, int error)
195 * Routine to reverse the bits in a word. Stolen almost
196 * verbatim from /usr/games/fortune.
199 sis_reverse(uint16_t n)
201 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa);
202 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc);
203 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0);
204 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00);
210 sis_delay(struct sis_softc *sc)
214 for (idx = (300 / 33) + 1; idx > 0; idx--)
215 CSR_READ_4(sc, SIS_CSR);
219 sis_eeprom_idle(struct sis_softc *sc)
223 SIO_SET(SIS_EECTL_CSEL);
225 SIO_SET(SIS_EECTL_CLK);
228 for (i = 0; i < 25; i++) {
229 SIO_CLR(SIS_EECTL_CLK);
231 SIO_SET(SIS_EECTL_CLK);
235 SIO_CLR(SIS_EECTL_CLK);
237 SIO_CLR(SIS_EECTL_CSEL);
239 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000);
243 * Send a read command and address to the EEPROM, check for ACK.
246 sis_eeprom_putbyte(struct sis_softc *sc, int addr)
250 d = addr | SIS_EECMD_READ;
253 * Feed in each bit and stobe the clock.
255 for (i = 0x400; i; i >>= 1) {
257 SIO_SET(SIS_EECTL_DIN);
259 SIO_CLR(SIS_EECTL_DIN);
262 SIO_SET(SIS_EECTL_CLK);
264 SIO_CLR(SIS_EECTL_CLK);
270 * Read a word of data stored in the EEPROM at address 'addr.'
273 sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest)
278 /* Force EEPROM to idle state. */
281 /* Enter EEPROM access mode. */
283 SIO_CLR(SIS_EECTL_CLK);
285 SIO_SET(SIS_EECTL_CSEL);
289 * Send address of word we want to read.
291 sis_eeprom_putbyte(sc, addr);
294 * Start reading bits from EEPROM.
296 for (i = 0x8000; i; i >>= 1) {
297 SIO_SET(SIS_EECTL_CLK);
299 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT)
302 SIO_CLR(SIS_EECTL_CLK);
306 /* Turn off EEPROM access mode. */
313 * Read a sequence of words from the EEPROM.
316 sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap)
319 u_int16_t word = 0, *ptr;
321 for (i = 0; i < cnt; i++) {
322 sis_eeprom_getword(sc, off + i, &word);
323 ptr = (u_int16_t *)(dest + (i * 2));
331 #if defined(__i386__) || defined(__amd64__)
333 sis_find_bridge(device_t dev)
335 devclass_t pci_devclass;
336 device_t *pci_devices;
338 device_t *pci_children;
339 int pci_childcount = 0;
340 device_t *busp, *childp;
341 device_t child = NULL;
344 if ((pci_devclass = devclass_find("pci")) == NULL)
347 devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
349 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) {
350 if (device_get_children(*busp, &pci_children, &pci_childcount))
352 for (j = 0, childp = pci_children;
353 j < pci_childcount; j++, childp++) {
354 if (pci_get_vendor(*childp) == SIS_VENDORID &&
355 pci_get_device(*childp) == 0x0008) {
357 free(pci_children, M_TEMP);
361 free(pci_children, M_TEMP);
365 free(pci_devices, M_TEMP);
370 sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off, int cnt)
375 bus_space_tag_t btag;
377 bridge = sis_find_bridge(dev);
380 reg = pci_read_config(bridge, 0x48, 1);
381 pci_write_config(bridge, 0x48, reg|0x40, 1);
384 #if defined(__i386__)
385 btag = I386_BUS_SPACE_IO;
386 #elif defined(__amd64__)
387 btag = AMD64_BUS_SPACE_IO;
390 for (i = 0; i < cnt; i++) {
391 bus_space_write_1(btag, 0x0, 0x70, i + off);
392 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71);
395 pci_write_config(bridge, 0x48, reg & ~0x40, 1);
399 sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest)
401 u_int32_t filtsave, csrsave;
403 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
404 csrsave = CSR_READ_4(sc, SIS_CSR);
406 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave);
407 CSR_WRITE_4(sc, SIS_CSR, 0);
409 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE);
411 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
412 ((u_int16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA);
413 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1);
414 ((u_int16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA);
415 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
416 ((u_int16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA);
418 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
419 CSR_WRITE_4(sc, SIS_CSR, csrsave);
424 * Sync the PHYs by setting data bit and strobing the clock 32 times.
427 sis_mii_sync(struct sis_softc *sc)
431 SIO_SET(SIS_MII_DIR|SIS_MII_DATA);
433 for (i = 0; i < 32; i++) {
434 SIO_SET(SIS_MII_CLK);
436 SIO_CLR(SIS_MII_CLK);
442 * Clock a series of bits through the MII.
445 sis_mii_send(struct sis_softc *sc, uint32_t bits, int cnt)
449 SIO_CLR(SIS_MII_CLK);
451 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
453 SIO_SET(SIS_MII_DATA);
455 SIO_CLR(SIS_MII_DATA);
458 SIO_CLR(SIS_MII_CLK);
460 SIO_SET(SIS_MII_CLK);
465 * Read an PHY register through the MII.
468 sis_mii_readreg(struct sis_softc *sc, struct sis_mii_frame *frame)
473 * Set up frame for RX.
475 frame->mii_stdelim = SIS_MII_STARTDELIM;
476 frame->mii_opcode = SIS_MII_READOP;
477 frame->mii_turnaround = 0;
483 SIO_SET(SIS_MII_DIR);
488 * Send command/address info.
490 sis_mii_send(sc, frame->mii_stdelim, 2);
491 sis_mii_send(sc, frame->mii_opcode, 2);
492 sis_mii_send(sc, frame->mii_phyaddr, 5);
493 sis_mii_send(sc, frame->mii_regaddr, 5);
496 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA));
498 SIO_SET(SIS_MII_CLK);
502 SIO_CLR(SIS_MII_DIR);
505 SIO_CLR(SIS_MII_CLK);
507 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA;
508 SIO_SET(SIS_MII_CLK);
512 * Now try reading data bits. If the ack failed, we still
513 * need to clock through 16 cycles to keep the PHY(s) in sync.
516 for (i = 0; i < 16; i++) {
517 SIO_CLR(SIS_MII_CLK);
519 SIO_SET(SIS_MII_CLK);
525 for (i = 0x8000; i; i >>= 1) {
526 SIO_CLR(SIS_MII_CLK);
529 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA)
530 frame->mii_data |= i;
533 SIO_SET(SIS_MII_CLK);
539 SIO_CLR(SIS_MII_CLK);
541 SIO_SET(SIS_MII_CLK);
550 * Write to a PHY register through the MII.
553 sis_mii_writereg(struct sis_softc *sc, struct sis_mii_frame *frame)
557 * Set up frame for TX.
560 frame->mii_stdelim = SIS_MII_STARTDELIM;
561 frame->mii_opcode = SIS_MII_WRITEOP;
562 frame->mii_turnaround = SIS_MII_TURNAROUND;
565 * Turn on data output.
567 SIO_SET(SIS_MII_DIR);
571 sis_mii_send(sc, frame->mii_stdelim, 2);
572 sis_mii_send(sc, frame->mii_opcode, 2);
573 sis_mii_send(sc, frame->mii_phyaddr, 5);
574 sis_mii_send(sc, frame->mii_regaddr, 5);
575 sis_mii_send(sc, frame->mii_turnaround, 2);
576 sis_mii_send(sc, frame->mii_data, 16);
579 SIO_SET(SIS_MII_CLK);
581 SIO_CLR(SIS_MII_CLK);
587 SIO_CLR(SIS_MII_DIR);
593 sis_miibus_readreg(device_t dev, int phy, int reg)
595 struct sis_softc *sc;
596 struct sis_mii_frame frame;
598 sc = device_get_softc(dev);
600 if (sc->sis_type == SIS_TYPE_83815) {
604 * The NatSemi chip can take a while after
605 * a reset to come ready, during which the BMSR
606 * returns a value of 0. This is *never* supposed
607 * to happen: some of the BMSR bits are meant to
608 * be hardwired in the on position, and this can
609 * confuse the miibus code a bit during the probe
610 * and attach phase. So we make an effort to check
611 * for this condition and wait for it to clear.
613 if (!CSR_READ_4(sc, NS_BMSR))
615 return CSR_READ_4(sc, NS_BMCR + (reg * 4));
619 * Chipsets < SIS_635 seem not to be able to read/write
620 * through mdio. Use the enhanced PHY access register
623 if (sc->sis_type == SIS_TYPE_900 &&
624 sc->sis_rev < SIS_REV_635) {
630 CSR_WRITE_4(sc, SIS_PHYCTL,
631 (phy << 11) | (reg << 6) | SIS_PHYOP_READ);
632 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
634 for (i = 0; i < SIS_TIMEOUT; i++) {
635 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
639 if (i == SIS_TIMEOUT) {
640 device_printf(sc->sis_dev, "PHY failed to come ready\n");
644 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF;
651 bzero((char *)&frame, sizeof(frame));
653 frame.mii_phyaddr = phy;
654 frame.mii_regaddr = reg;
655 sis_mii_readreg(sc, &frame);
657 return (frame.mii_data);
662 sis_miibus_writereg(device_t dev, int phy, int reg, int data)
664 struct sis_softc *sc;
665 struct sis_mii_frame frame;
667 sc = device_get_softc(dev);
669 if (sc->sis_type == SIS_TYPE_83815) {
672 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data);
677 * Chipsets < SIS_635 seem not to be able to read/write
678 * through mdio. Use the enhanced PHY access register
681 if (sc->sis_type == SIS_TYPE_900 &&
682 sc->sis_rev < SIS_REV_635) {
688 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) |
689 (reg << 6) | SIS_PHYOP_WRITE);
690 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
692 for (i = 0; i < SIS_TIMEOUT; i++) {
693 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
697 if (i == SIS_TIMEOUT)
698 device_printf(sc->sis_dev, "PHY failed to come ready\n");
700 bzero((char *)&frame, sizeof(frame));
702 frame.mii_phyaddr = phy;
703 frame.mii_regaddr = reg;
704 frame.mii_data = data;
705 sis_mii_writereg(sc, &frame);
711 sis_miibus_statchg(device_t dev)
713 struct sis_softc *sc;
715 sc = device_get_softc(dev);
721 sis_mchash(struct sis_softc *sc, const uint8_t *addr)
725 /* Compute CRC for the address value. */
726 crc = ether_crc32_be(addr, ETHER_ADDR_LEN);
729 * return the filter bit position
731 * The NatSemi chip has a 512-bit filter, which is
732 * different than the SiS, so we special-case it.
734 if (sc->sis_type == SIS_TYPE_83815)
736 else if (sc->sis_rev >= SIS_REV_635 ||
737 sc->sis_rev == SIS_REV_900B)
744 sis_setmulti_ns(struct sis_softc *sc)
747 struct ifmultiaddr *ifma;
748 u_int32_t h = 0, i, filtsave;
753 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
754 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
755 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
760 * We have to explicitly enable the multicast hash table
761 * on the NatSemi chip if we want to use it, which we do.
763 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
764 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
766 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
768 /* first, zot all the existing hash bits */
769 for (i = 0; i < 32; i++) {
770 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2));
771 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0);
775 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
776 if (ifma->ifma_addr->sa_family != AF_LINK)
779 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
782 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index);
785 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit));
787 if_maddr_runlock(ifp);
789 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
793 sis_setmulti_sis(struct sis_softc *sc)
796 struct ifmultiaddr *ifma;
797 u_int32_t h, i, n, ctl;
798 u_int16_t hashes[16];
802 /* hash table size */
803 if (sc->sis_rev >= SIS_REV_635 ||
804 sc->sis_rev == SIS_REV_900B)
809 ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE;
811 if (ifp->if_flags & IFF_BROADCAST)
812 ctl |= SIS_RXFILTCTL_BROAD;
814 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
815 ctl |= SIS_RXFILTCTL_ALLMULTI;
816 if (ifp->if_flags & IFF_PROMISC)
817 ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS;
818 for (i = 0; i < n; i++)
821 for (i = 0; i < n; i++)
825 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
826 if (ifma->ifma_addr->sa_family != AF_LINK)
829 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
830 hashes[h >> 4] |= 1 << (h & 0xf);
833 if_maddr_runlock(ifp);
835 ctl |= SIS_RXFILTCTL_ALLMULTI;
836 for (i = 0; i < n; i++)
841 for (i = 0; i < n; i++) {
842 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16);
843 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]);
846 CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl);
850 sis_reset(struct sis_softc *sc)
854 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET);
856 for (i = 0; i < SIS_TIMEOUT; i++) {
857 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET))
861 if (i == SIS_TIMEOUT)
862 device_printf(sc->sis_dev, "reset never completed\n");
864 /* Wait a little while for the chip to get its brains in order. */
868 * If this is a NetSemi chip, make sure to clear
871 if (sc->sis_type == SIS_TYPE_83815) {
872 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS);
873 CSR_WRITE_4(sc, NS_CLKRUN, 0);
878 * Probe for an SiS chip. Check the PCI vendor and device
879 * IDs against our list and return a device name if we find a match.
882 sis_probe(device_t dev)
888 while (t->sis_name != NULL) {
889 if ((pci_get_vendor(dev) == t->sis_vid) &&
890 (pci_get_device(dev) == t->sis_did)) {
891 device_set_desc(dev, t->sis_name);
892 return (BUS_PROBE_DEFAULT);
901 * Attach the interface. Allocate softc structures, do ifmedia
902 * setup and ethernet/BPF attach.
905 sis_attach(device_t dev)
907 u_char eaddr[ETHER_ADDR_LEN];
908 struct sis_softc *sc;
910 int error = 0, waittime = 0;
913 sc = device_get_softc(dev);
917 mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
919 callout_init_mtx(&sc->sis_stat_ch, &sc->sis_mtx, 0);
921 if (pci_get_device(dev) == SIS_DEVICEID_900)
922 sc->sis_type = SIS_TYPE_900;
923 if (pci_get_device(dev) == SIS_DEVICEID_7016)
924 sc->sis_type = SIS_TYPE_7016;
925 if (pci_get_vendor(dev) == NS_VENDORID)
926 sc->sis_type = SIS_TYPE_83815;
928 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1);
930 * Map control/status registers.
932 pci_enable_busmaster(dev);
934 error = bus_alloc_resources(dev, sis_res_spec, sc->sis_res);
936 device_printf(dev, "couldn't allocate resources\n");
940 /* Reset the adapter. */
943 if (sc->sis_type == SIS_TYPE_900 &&
944 (sc->sis_rev == SIS_REV_635 ||
945 sc->sis_rev == SIS_REV_900B)) {
946 SIO_SET(SIS_CFG_RND_CNT);
947 SIO_SET(SIS_CFG_PERR_DETECT);
951 * Get station address from the EEPROM.
953 switch (pci_get_vendor(dev)) {
955 sc->sis_srr = CSR_READ_4(sc, NS_SRR);
957 /* We can't update the device description, so spew */
958 if (sc->sis_srr == NS_SRR_15C)
959 device_printf(dev, "Silicon Revision: DP83815C\n");
960 else if (sc->sis_srr == NS_SRR_15D)
961 device_printf(dev, "Silicon Revision: DP83815D\n");
962 else if (sc->sis_srr == NS_SRR_16A)
963 device_printf(dev, "Silicon Revision: DP83816A\n");
965 device_printf(dev, "Silicon Revision %x\n", sc->sis_srr);
968 * Reading the MAC address out of the EEPROM on
969 * the NatSemi chip takes a bit more work than
970 * you'd expect. The address spans 4 16-bit words,
971 * with the first word containing only a single bit.
972 * You have to shift everything over one bit to
973 * get it aligned properly. Also, the bits are
974 * stored backwards (the LSB is really the MSB,
975 * and so on) so you have to reverse them in order
976 * to get the MAC address into the form we want.
977 * Why? Who the hell knows.
982 sis_read_eeprom(sc, (caddr_t)&tmp,
983 NS_EE_NODEADDR, 4, 0);
985 /* Shift everything over one bit. */
986 tmp[3] = tmp[3] >> 1;
987 tmp[3] |= tmp[2] << 15;
988 tmp[2] = tmp[2] >> 1;
989 tmp[2] |= tmp[1] << 15;
990 tmp[1] = tmp[1] >> 1;
991 tmp[1] |= tmp[0] << 15;
993 /* Now reverse all the bits. */
994 tmp[3] = sis_reverse(tmp[3]);
995 tmp[2] = sis_reverse(tmp[2]);
996 tmp[1] = sis_reverse(tmp[1]);
998 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN);
1003 #if defined(__i386__) || defined(__amd64__)
1005 * If this is a SiS 630E chipset with an embedded
1006 * SiS 900 controller, we have to read the MAC address
1007 * from the APC CMOS RAM. Our method for doing this
1008 * is very ugly since we have to reach out and grab
1009 * ahold of hardware for which we cannot properly
1010 * allocate resources. This code is only compiled on
1011 * the i386 architecture since the SiS 630E chipset
1012 * is for x86 motherboards only. Note that there are
1013 * a lot of magic numbers in this hack. These are
1014 * taken from SiS's Linux driver. I'd like to replace
1015 * them with proper symbolic definitions, but that
1016 * requires some datasheets that I don't have access
1019 if (sc->sis_rev == SIS_REV_630S ||
1020 sc->sis_rev == SIS_REV_630E ||
1021 sc->sis_rev == SIS_REV_630EA1)
1022 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6);
1024 else if (sc->sis_rev == SIS_REV_635 ||
1025 sc->sis_rev == SIS_REV_630ET)
1026 sis_read_mac(sc, dev, (caddr_t)&eaddr);
1027 else if (sc->sis_rev == SIS_REV_96x) {
1028 /* Allow to read EEPROM from LAN. It is shared
1029 * between a 1394 controller and the NIC and each
1030 * time we access it, we need to set SIS_EECMD_REQ.
1032 SIO_SET(SIS_EECMD_REQ);
1033 for (waittime = 0; waittime < SIS_TIMEOUT;
1035 /* Force EEPROM to idle state. */
1036 sis_eeprom_idle(sc);
1037 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) {
1038 sis_read_eeprom(sc, (caddr_t)&eaddr,
1039 SIS_EE_NODEADDR, 3, 0);
1045 * Set SIS_EECTL_CLK to high, so a other master
1046 * can operate on the i2c bus.
1048 SIO_SET(SIS_EECTL_CLK);
1049 /* Refuse EEPROM access by LAN */
1050 SIO_SET(SIS_EECMD_DONE);
1053 sis_read_eeprom(sc, (caddr_t)&eaddr,
1054 SIS_EE_NODEADDR, 3, 0);
1059 * Allocate the parent bus DMA tag appropriate for PCI.
1061 #define SIS_NSEG_NEW 32
1062 error = bus_dma_tag_create(NULL, /* parent */
1063 1, 0, /* alignment, boundary */
1064 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1065 BUS_SPACE_MAXADDR, /* highaddr */
1066 NULL, NULL, /* filter, filterarg */
1067 MAXBSIZE, SIS_NSEG_NEW, /* maxsize, nsegments */
1068 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1069 BUS_DMA_ALLOCNOW, /* flags */
1070 NULL, NULL, /* lockfunc, lockarg */
1071 &sc->sis_parent_tag);
1076 * Now allocate a tag for the DMA descriptor lists and a chunk
1077 * of DMA-able memory based on the tag. Also obtain the physical
1078 * addresses of the RX and TX ring, which we'll need later.
1079 * All of our lists are allocated as a contiguous block
1082 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */
1083 1, 0, /* alignment, boundary */
1084 BUS_SPACE_MAXADDR, /* lowaddr */
1085 BUS_SPACE_MAXADDR, /* highaddr */
1086 NULL, NULL, /* filter, filterarg */
1087 SIS_RX_LIST_SZ, 1, /* maxsize,nsegments */
1088 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1090 busdma_lock_mutex, /* lockfunc */
1091 &Giant, /* lockarg */
1096 error = bus_dmamem_alloc(sc->sis_rx_tag,
1097 (void **)&sc->sis_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1098 &sc->sis_rx_dmamap);
1101 device_printf(dev, "no memory for rx list buffers!\n");
1102 bus_dma_tag_destroy(sc->sis_rx_tag);
1103 sc->sis_rx_tag = NULL;
1107 error = bus_dmamap_load(sc->sis_rx_tag,
1108 sc->sis_rx_dmamap, &(sc->sis_rx_list[0]),
1109 sizeof(struct sis_desc), sis_dma_map_ring,
1110 &sc->sis_rx_paddr, 0);
1113 device_printf(dev, "cannot get address of the rx ring!\n");
1114 bus_dmamem_free(sc->sis_rx_tag,
1115 sc->sis_rx_list, sc->sis_rx_dmamap);
1116 bus_dma_tag_destroy(sc->sis_rx_tag);
1117 sc->sis_rx_tag = NULL;
1121 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */
1122 1, 0, /* alignment, boundary */
1123 BUS_SPACE_MAXADDR, /* lowaddr */
1124 BUS_SPACE_MAXADDR, /* highaddr */
1125 NULL, NULL, /* filter, filterarg */
1126 SIS_TX_LIST_SZ, 1, /* maxsize,nsegments */
1127 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1129 busdma_lock_mutex, /* lockfunc */
1130 &Giant, /* lockarg */
1135 error = bus_dmamem_alloc(sc->sis_tx_tag,
1136 (void **)&sc->sis_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1137 &sc->sis_tx_dmamap);
1140 device_printf(dev, "no memory for tx list buffers!\n");
1141 bus_dma_tag_destroy(sc->sis_tx_tag);
1142 sc->sis_tx_tag = NULL;
1146 error = bus_dmamap_load(sc->sis_tx_tag,
1147 sc->sis_tx_dmamap, &(sc->sis_tx_list[0]),
1148 sizeof(struct sis_desc), sis_dma_map_ring,
1149 &sc->sis_tx_paddr, 0);
1152 device_printf(dev, "cannot get address of the tx ring!\n");
1153 bus_dmamem_free(sc->sis_tx_tag,
1154 sc->sis_tx_list, sc->sis_tx_dmamap);
1155 bus_dma_tag_destroy(sc->sis_tx_tag);
1156 sc->sis_tx_tag = NULL;
1160 error = bus_dma_tag_create(sc->sis_parent_tag, /* parent */
1161 1, 0, /* alignment, boundary */
1162 BUS_SPACE_MAXADDR, /* lowaddr */
1163 BUS_SPACE_MAXADDR, /* highaddr */
1164 NULL, NULL, /* filter, filterarg */
1165 MCLBYTES, 1, /* maxsize,nsegments */
1166 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1168 busdma_lock_mutex, /* lockfunc */
1169 &Giant, /* lockarg */
1175 * Obtain the physical addresses of the RX and TX
1176 * rings which we'll need later in the init routine.
1179 ifp = sc->sis_ifp = if_alloc(IFT_ETHER);
1181 device_printf(dev, "can not if_alloc()\n");
1186 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1187 ifp->if_mtu = ETHERMTU;
1188 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1189 ifp->if_ioctl = sis_ioctl;
1190 ifp->if_start = sis_start;
1191 ifp->if_init = sis_init;
1192 IFQ_SET_MAXLEN(&ifp->if_snd, SIS_TX_LIST_CNT - 1);
1193 ifp->if_snd.ifq_drv_maxlen = SIS_TX_LIST_CNT - 1;
1194 IFQ_SET_READY(&ifp->if_snd);
1199 if (mii_phy_probe(dev, &sc->sis_miibus,
1200 sis_ifmedia_upd, sis_ifmedia_sts)) {
1201 device_printf(dev, "MII without any PHY!\n");
1207 * Call MI attach routine.
1209 ether_ifattach(ifp, eaddr);
1212 * Tell the upper layer(s) we support long frames.
1214 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1215 ifp->if_capabilities |= IFCAP_VLAN_MTU;
1216 ifp->if_capenable = ifp->if_capabilities;
1217 #ifdef DEVICE_POLLING
1218 ifp->if_capabilities |= IFCAP_POLLING;
1221 /* Hook interrupt last to avoid having to lock softc */
1222 error = bus_setup_intr(dev, sc->sis_res[1], INTR_TYPE_NET | INTR_MPSAFE,
1223 NULL, sis_intr, sc, &sc->sis_intrhand);
1226 device_printf(dev, "couldn't set up irq\n");
1227 ether_ifdetach(ifp);
1239 * Shutdown hardware and free up resources. This can be called any
1240 * time after the mutex has been initialized. It is called in both
1241 * the error case in attach and the normal detach case so it needs
1242 * to be careful about only freeing resources that have actually been
1246 sis_detach(device_t dev)
1248 struct sis_softc *sc;
1251 sc = device_get_softc(dev);
1252 KASSERT(mtx_initialized(&sc->sis_mtx), ("sis mutex not initialized"));
1255 #ifdef DEVICE_POLLING
1256 if (ifp->if_capenable & IFCAP_POLLING)
1257 ether_poll_deregister(ifp);
1260 /* These should only be active if attach succeeded. */
1261 if (device_is_attached(dev)) {
1266 callout_drain(&sc->sis_stat_ch);
1267 ether_ifdetach(ifp);
1270 device_delete_child(dev, sc->sis_miibus);
1271 bus_generic_detach(dev);
1273 if (sc->sis_intrhand)
1274 bus_teardown_intr(dev, sc->sis_res[1], sc->sis_intrhand);
1275 bus_release_resources(dev, sis_res_spec, sc->sis_res);
1280 if (sc->sis_rx_tag) {
1281 bus_dmamap_unload(sc->sis_rx_tag,
1283 bus_dmamem_free(sc->sis_rx_tag,
1284 sc->sis_rx_list, sc->sis_rx_dmamap);
1285 bus_dma_tag_destroy(sc->sis_rx_tag);
1287 if (sc->sis_tx_tag) {
1288 bus_dmamap_unload(sc->sis_tx_tag,
1290 bus_dmamem_free(sc->sis_tx_tag,
1291 sc->sis_tx_list, sc->sis_tx_dmamap);
1292 bus_dma_tag_destroy(sc->sis_tx_tag);
1294 if (sc->sis_parent_tag)
1295 bus_dma_tag_destroy(sc->sis_parent_tag);
1297 bus_dma_tag_destroy(sc->sis_tag);
1299 mtx_destroy(&sc->sis_mtx);
1305 * Initialize the TX and RX descriptors and allocate mbufs for them. Note that
1306 * we arrange the descriptors in a closed ring, so that the last descriptor
1307 * points back to the first.
1310 sis_ring_init(struct sis_softc *sc)
1313 struct sis_desc *dp;
1315 dp = &sc->sis_tx_list[0];
1316 for (i = 0; i < SIS_TX_LIST_CNT; i++, dp++) {
1317 if (i == (SIS_TX_LIST_CNT - 1))
1318 dp->sis_nextdesc = &sc->sis_tx_list[0];
1320 dp->sis_nextdesc = dp + 1;
1321 bus_dmamap_load(sc->sis_tx_tag,
1323 dp->sis_nextdesc, sizeof(struct sis_desc),
1324 sis_dma_map_desc_next, dp, 0);
1325 dp->sis_mbuf = NULL;
1330 sc->sis_tx_prod = sc->sis_tx_cons = sc->sis_tx_cnt = 0;
1332 bus_dmamap_sync(sc->sis_tx_tag,
1333 sc->sis_tx_dmamap, BUS_DMASYNC_PREWRITE);
1335 dp = &sc->sis_rx_list[0];
1336 for (i = 0; i < SIS_RX_LIST_CNT; i++, dp++) {
1337 error = sis_newbuf(sc, dp, NULL);
1340 if (i == (SIS_RX_LIST_CNT - 1))
1341 dp->sis_nextdesc = &sc->sis_rx_list[0];
1343 dp->sis_nextdesc = dp + 1;
1344 bus_dmamap_load(sc->sis_rx_tag,
1346 dp->sis_nextdesc, sizeof(struct sis_desc),
1347 sis_dma_map_desc_next, dp, 0);
1350 bus_dmamap_sync(sc->sis_rx_tag,
1351 sc->sis_rx_dmamap, BUS_DMASYNC_PREWRITE);
1353 sc->sis_rx_pdsc = &sc->sis_rx_list[0];
1359 * Initialize an RX descriptor and attach an MBUF cluster.
1362 sis_newbuf(struct sis_softc *sc, struct sis_desc *c, struct mbuf *m)
1369 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1373 m->m_data = m->m_ext.ext_buf;
1376 c->sis_ctl = SIS_RXLEN;
1378 bus_dmamap_create(sc->sis_tag, 0, &c->sis_map);
1379 bus_dmamap_load(sc->sis_tag, c->sis_map,
1380 mtod(m, void *), MCLBYTES,
1381 sis_dma_map_desc_ptr, c, 0);
1382 bus_dmamap_sync(sc->sis_tag, c->sis_map, BUS_DMASYNC_PREREAD);
1388 * A frame has been uploaded: pass the resulting mbuf chain up to
1389 * the higher level protocols.
1392 sis_rxeof(struct sis_softc *sc)
1394 struct mbuf *m, *m0;
1396 struct sis_desc *cur_rx;
1397 int total_len = 0, rx_npkts = 0;
1400 SIS_LOCK_ASSERT(sc);
1404 for (cur_rx = sc->sis_rx_pdsc; SIS_OWNDESC(cur_rx);
1405 cur_rx = cur_rx->sis_nextdesc) {
1407 #ifdef DEVICE_POLLING
1408 if (ifp->if_capenable & IFCAP_POLLING) {
1409 if (sc->rxcycles <= 0)
1414 rxstat = cur_rx->sis_rxstat;
1415 bus_dmamap_sync(sc->sis_tag,
1416 cur_rx->sis_map, BUS_DMASYNC_POSTWRITE);
1417 bus_dmamap_unload(sc->sis_tag, cur_rx->sis_map);
1418 bus_dmamap_destroy(sc->sis_tag, cur_rx->sis_map);
1419 m = cur_rx->sis_mbuf;
1420 cur_rx->sis_mbuf = NULL;
1421 total_len = SIS_RXBYTES(cur_rx);
1424 * If an error occurs, update stats, clear the
1425 * status word and leave the mbuf cluster in place:
1426 * it should simply get re-used next time this descriptor
1427 * comes up in the ring.
1429 if ((ifp->if_capenable & IFCAP_VLAN_MTU) != 0 &&
1430 total_len <= (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN -
1432 rxstat &= ~SIS_RXSTAT_GIANT;
1433 if (SIS_RXSTAT_ERROR(rxstat) != 0) {
1435 if (rxstat & SIS_RXSTAT_COLL)
1436 ifp->if_collisions++;
1437 sis_newbuf(sc, cur_rx, m);
1441 /* No errors; receive the packet. */
1442 #ifdef __NO_STRICT_ALIGNMENT
1444 * On architectures without alignment problems we try to
1445 * allocate a new buffer for the receive ring, and pass up
1446 * the one where the packet is already, saving the expensive
1447 * copy done in m_devget().
1448 * If we are on an architecture with alignment problems, or
1449 * if the allocation fails, then use m_devget and leave the
1450 * existing buffer in the receive ring.
1452 if (sis_newbuf(sc, cur_rx, NULL) == 0)
1453 m->m_pkthdr.len = m->m_len = total_len;
1457 m0 = m_devget(mtod(m, char *), total_len,
1458 ETHER_ALIGN, ifp, NULL);
1459 sis_newbuf(sc, cur_rx, m);
1468 m->m_pkthdr.rcvif = ifp;
1471 (*ifp->if_input)(ifp, m);
1476 sc->sis_rx_pdsc = cur_rx;
1481 * A frame was downloaded to the chip. It's safe for us to clean up
1486 sis_txeof(struct sis_softc *sc)
1491 SIS_LOCK_ASSERT(sc);
1495 * Go through our tx list and free mbufs for those
1496 * frames that have been transmitted.
1498 for (idx = sc->sis_tx_cons; sc->sis_tx_cnt > 0;
1499 sc->sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) {
1500 struct sis_desc *cur_tx = &sc->sis_tx_list[idx];
1502 if (SIS_OWNDESC(cur_tx))
1505 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE)
1508 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) {
1510 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS)
1511 ifp->if_collisions++;
1512 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL)
1513 ifp->if_collisions++;
1516 ifp->if_collisions +=
1517 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16;
1520 if (cur_tx->sis_mbuf != NULL) {
1521 m_freem(cur_tx->sis_mbuf);
1522 cur_tx->sis_mbuf = NULL;
1523 bus_dmamap_unload(sc->sis_tag, cur_tx->sis_map);
1524 bus_dmamap_destroy(sc->sis_tag, cur_tx->sis_map);
1528 if (idx != sc->sis_tx_cons) {
1529 /* we freed up some buffers */
1530 sc->sis_tx_cons = idx;
1531 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1534 sc->sis_watchdog_timer = (sc->sis_tx_cnt == 0) ? 0 : 5;
1540 struct sis_softc *sc;
1541 struct mii_data *mii;
1545 SIS_LOCK_ASSERT(sc);
1549 mii = device_get_softc(sc->sis_miibus);
1554 if (!sc->sis_link && mii->mii_media_status & IFM_ACTIVE &&
1555 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1557 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1561 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc);
1565 #ifdef DEVICE_POLLING
1566 static poll_handler_t sis_poll;
1569 sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1571 struct sis_softc *sc = ifp->if_softc;
1575 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1581 * On the sis, reading the status register also clears it.
1582 * So before returning to intr mode we must make sure that all
1583 * possible pending sources of interrupts have been served.
1584 * In practice this means run to completion the *eof routines,
1585 * and then call the interrupt routine
1587 sc->rxcycles = count;
1588 rx_npkts = sis_rxeof(sc);
1590 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1593 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) {
1596 /* Reading the ISR register clears all interrupts. */
1597 status = CSR_READ_4(sc, SIS_ISR);
1599 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW))
1602 if (status & (SIS_ISR_RX_IDLE))
1603 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1605 if (status & SIS_ISR_SYSERR) {
1614 #endif /* DEVICE_POLLING */
1619 struct sis_softc *sc;
1626 if (sc->sis_stopped) /* Most likely shared interrupt */
1630 #ifdef DEVICE_POLLING
1631 if (ifp->if_capenable & IFCAP_POLLING) {
1637 /* Disable interrupts. */
1638 CSR_WRITE_4(sc, SIS_IER, 0);
1641 SIS_LOCK_ASSERT(sc);
1642 /* Reading the ISR register clears all interrupts. */
1643 status = CSR_READ_4(sc, SIS_ISR);
1645 if ((status & SIS_INTRS) == 0)
1649 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR |
1650 SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) )
1653 if (status & (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK |
1654 SIS_ISR_RX_ERR | SIS_ISR_RX_IDLE))
1657 if (status & SIS_ISR_RX_OFLOW)
1660 if (status & (SIS_ISR_RX_IDLE))
1661 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1663 if (status & SIS_ISR_SYSERR) {
1669 /* Re-enable interrupts. */
1670 CSR_WRITE_4(sc, SIS_IER, 1);
1672 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1679 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1680 * pointers to the fragment pointers.
1683 sis_encap(struct sis_softc *sc, struct mbuf **m_head, uint32_t *txidx)
1685 struct sis_desc *f = NULL;
1687 int frag, cur, cnt = 0, chainlen = 0;
1690 * If there's no way we can send any packets, return now.
1692 if (SIS_TX_LIST_CNT - sc->sis_tx_cnt < 2)
1696 * Count the number of frags in this chain to see if
1697 * we need to m_defrag. Since the descriptor list is shared
1698 * by all packets, we'll m_defrag long chains so that they
1699 * do not use up the entire list, even if they would fit.
1702 for (m = *m_head; m != NULL; m = m->m_next)
1705 if ((chainlen > SIS_TX_LIST_CNT / 4) ||
1706 ((SIS_TX_LIST_CNT - (chainlen + sc->sis_tx_cnt)) < 2)) {
1707 m = m_defrag(*m_head, M_DONTWAIT);
1714 * Start packing the mbufs in this chain into
1715 * the fragment pointers. Stop when we run out
1716 * of fragments or hit the end of the mbuf chain.
1718 cur = frag = *txidx;
1720 for (m = *m_head; m != NULL; m = m->m_next) {
1721 if (m->m_len != 0) {
1722 if ((SIS_TX_LIST_CNT -
1723 (sc->sis_tx_cnt + cnt)) < 2)
1725 f = &sc->sis_tx_list[frag];
1726 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len;
1727 bus_dmamap_create(sc->sis_tag, 0, &f->sis_map);
1728 bus_dmamap_load(sc->sis_tag, f->sis_map,
1729 mtod(m, void *), m->m_len,
1730 sis_dma_map_desc_ptr, f, 0);
1731 bus_dmamap_sync(sc->sis_tag,
1732 f->sis_map, BUS_DMASYNC_PREREAD);
1734 f->sis_ctl |= SIS_CMDSTS_OWN;
1736 SIS_INC(frag, SIS_TX_LIST_CNT);
1744 sc->sis_tx_list[cur].sis_mbuf = *m_head;
1745 sc->sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE;
1746 sc->sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN;
1747 sc->sis_tx_cnt += cnt;
1754 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1755 * to the mbuf data regions directly in the transmit lists. We also save a
1756 * copy of the pointers since the transmit list fragment pointers are
1757 * physical addresses.
1761 sis_start(struct ifnet *ifp)
1763 struct sis_softc *sc;
1772 sis_startl(struct ifnet *ifp)
1774 struct sis_softc *sc;
1775 struct mbuf *m_head = NULL;
1776 u_int32_t idx, queued = 0;
1780 SIS_LOCK_ASSERT(sc);
1785 idx = sc->sis_tx_prod;
1787 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
1790 while (sc->sis_tx_list[idx].sis_mbuf == NULL) {
1791 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1795 if (sis_encap(sc, &m_head, &idx)) {
1796 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1797 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1804 * If there's a BPF listener, bounce a copy of this frame
1807 BPF_MTAP(ifp, m_head);
1813 sc->sis_tx_prod = idx;
1814 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE);
1817 * Set a timeout in case the chip goes out to lunch.
1819 sc->sis_watchdog_timer = 5;
1826 struct sis_softc *sc = xsc;
1834 sis_initl(struct sis_softc *sc)
1836 struct ifnet *ifp = sc->sis_ifp;
1837 struct mii_data *mii;
1839 SIS_LOCK_ASSERT(sc);
1842 * Cancel pending I/O and free all RX/TX buffers.
1845 sc->sis_stopped = 0;
1848 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) {
1850 * Configure 400usec of interrupt holdoff. This is based
1851 * on emperical tests on a Soekris 4801.
1853 CSR_WRITE_4(sc, NS_IHR, 0x100 | 4);
1857 mii = device_get_softc(sc->sis_miibus);
1859 /* Set MAC address */
1860 if (sc->sis_type == SIS_TYPE_83815) {
1861 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0);
1862 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1863 ((u_int16_t *)IF_LLADDR(sc->sis_ifp))[0]);
1864 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1);
1865 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1866 ((u_int16_t *)IF_LLADDR(sc->sis_ifp))[1]);
1867 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2);
1868 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1869 ((u_int16_t *)IF_LLADDR(sc->sis_ifp))[2]);
1871 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
1872 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1873 ((u_int16_t *)IF_LLADDR(sc->sis_ifp))[0]);
1874 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1);
1875 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1876 ((u_int16_t *)IF_LLADDR(sc->sis_ifp))[1]);
1877 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
1878 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1879 ((u_int16_t *)IF_LLADDR(sc->sis_ifp))[2]);
1882 /* Init circular TX/RX lists. */
1883 if (sis_ring_init(sc) != 0) {
1884 device_printf(sc->sis_dev,
1885 "initialization failed: no memory for rx buffers\n");
1891 * Short Cable Receive Errors (MP21.E)
1892 * also: Page 78 of the DP83815 data sheet (september 2002 version)
1893 * recommends the following register settings "for optimum
1894 * performance." for rev 15C. Set this also for 15D parts as
1895 * they require it in practice.
1897 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr <= NS_SRR_15D) {
1898 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
1899 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C);
1900 /* set val for c2 */
1901 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000);
1903 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040);
1904 /* rais SD off, from 4 to c */
1905 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C);
1906 CSR_WRITE_4(sc, NS_PHY_PAGE, 0);
1911 * For the NatSemi chip, we have to explicitly enable the
1912 * reception of ARP frames, as well as turn on the 'perfect
1913 * match' filter where we store the station address, otherwise
1914 * we won't receive unicasts meant for this host.
1916 if (sc->sis_type == SIS_TYPE_83815) {
1917 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP);
1918 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT);
1921 /* If we want promiscuous mode, set the allframes bit. */
1922 if (ifp->if_flags & IFF_PROMISC) {
1923 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
1925 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
1929 * Set the capture broadcast bit to capture broadcast frames.
1931 if (ifp->if_flags & IFF_BROADCAST) {
1932 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD);
1934 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD);
1938 * Load the multicast filter.
1940 if (sc->sis_type == SIS_TYPE_83815)
1941 sis_setmulti_ns(sc);
1943 sis_setmulti_sis(sc);
1945 /* Turn the receive filter on */
1946 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE);
1949 * Load the address of the RX and TX lists.
1951 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_rx_paddr);
1952 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_tx_paddr);
1954 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of
1955 * the PCI bus. When this bit is set, the Max DMA Burst Size
1956 * for TX/RX DMA should be no larger than 16 double words.
1958 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) {
1959 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64);
1961 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256);
1964 /* Accept Long Packets for VLAN support */
1965 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER);
1967 /* Set TX configuration */
1968 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) {
1969 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10);
1971 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100);
1974 /* Set full/half duplex mode. */
1975 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1976 SIS_SETBIT(sc, SIS_TX_CFG,
1977 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
1978 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
1980 SIS_CLRBIT(sc, SIS_TX_CFG,
1981 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
1982 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
1985 if (sc->sis_type == SIS_TYPE_83816) {
1987 * MPII03.D: Half Duplex Excessive Collisions.
1988 * Also page 49 in 83816 manual
1990 SIS_SETBIT(sc, SIS_TX_CFG, SIS_TXCFG_MPII03D);
1993 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr < NS_SRR_16A &&
1994 IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
1998 * Short Cable Receive Errors (MP21.E)
2000 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
2001 reg = CSR_READ_4(sc, NS_PHY_DSPCFG) & 0xfff;
2002 CSR_WRITE_4(sc, NS_PHY_DSPCFG, reg | 0x1000);
2004 reg = CSR_READ_4(sc, NS_PHY_TDATA) & 0xff;
2005 if ((reg & 0x0080) == 0 || (reg > 0xd8 && reg <= 0xff)) {
2006 device_printf(sc->sis_dev,
2007 "Applying short cable fix (reg=%x)\n", reg);
2008 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8);
2009 SIS_SETBIT(sc, NS_PHY_DSPCFG, 0x20);
2011 CSR_WRITE_4(sc, NS_PHY_PAGE, 0);
2015 * Enable interrupts.
2017 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS);
2018 #ifdef DEVICE_POLLING
2020 * ... only enable interrupts if we are not polling, make sure
2021 * they are off otherwise.
2023 if (ifp->if_capenable & IFCAP_POLLING)
2024 CSR_WRITE_4(sc, SIS_IER, 0);
2027 CSR_WRITE_4(sc, SIS_IER, 1);
2029 /* Enable receiver and transmitter. */
2030 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
2031 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
2037 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2038 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2041 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc);
2045 * Set media options.
2048 sis_ifmedia_upd(struct ifnet *ifp)
2050 struct sis_softc *sc;
2051 struct mii_data *mii;
2056 mii = device_get_softc(sc->sis_miibus);
2058 if (mii->mii_instance) {
2059 struct mii_softc *miisc;
2060 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2061 mii_phy_reset(miisc);
2070 * Report current media status.
2073 sis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2075 struct sis_softc *sc;
2076 struct mii_data *mii;
2081 mii = device_get_softc(sc->sis_miibus);
2084 ifmr->ifm_active = mii->mii_media_active;
2085 ifmr->ifm_status = mii->mii_media_status;
2089 sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2091 struct sis_softc *sc = ifp->if_softc;
2092 struct ifreq *ifr = (struct ifreq *) data;
2093 struct mii_data *mii;
2099 if (ifp->if_flags & IFF_UP) {
2101 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2110 if (sc->sis_type == SIS_TYPE_83815)
2111 sis_setmulti_ns(sc);
2113 sis_setmulti_sis(sc);
2119 mii = device_get_softc(sc->sis_miibus);
2120 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2123 /* ok, disable interrupts */
2124 #ifdef DEVICE_POLLING
2125 if (ifr->ifr_reqcap & IFCAP_POLLING &&
2126 !(ifp->if_capenable & IFCAP_POLLING)) {
2127 error = ether_poll_register(sis_poll, ifp);
2131 /* Disable interrupts */
2132 CSR_WRITE_4(sc, SIS_IER, 0);
2133 ifp->if_capenable |= IFCAP_POLLING;
2138 if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
2139 ifp->if_capenable & IFCAP_POLLING) {
2140 error = ether_poll_deregister(ifp);
2141 /* Enable interrupts. */
2143 CSR_WRITE_4(sc, SIS_IER, 1);
2144 ifp->if_capenable &= ~IFCAP_POLLING;
2148 #endif /* DEVICE_POLLING */
2151 error = ether_ioctl(ifp, command, data);
2159 sis_watchdog(struct sis_softc *sc)
2162 SIS_LOCK_ASSERT(sc);
2163 if (sc->sis_stopped) {
2168 if (sc->sis_watchdog_timer == 0 || --sc->sis_watchdog_timer >0)
2171 device_printf(sc->sis_dev, "watchdog timeout\n");
2172 sc->sis_ifp->if_oerrors++;
2178 if (!IFQ_DRV_IS_EMPTY(&sc->sis_ifp->if_snd))
2179 sis_startl(sc->sis_ifp);
2183 * Stop the adapter and free any mbufs allocated to the
2187 sis_stop(struct sis_softc *sc)
2191 struct sis_desc *dp;
2193 if (sc->sis_stopped)
2195 SIS_LOCK_ASSERT(sc);
2197 sc->sis_watchdog_timer = 0;
2199 callout_stop(&sc->sis_stat_ch);
2201 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2202 CSR_WRITE_4(sc, SIS_IER, 0);
2203 CSR_WRITE_4(sc, SIS_IMR, 0);
2204 CSR_READ_4(sc, SIS_ISR); /* clear any interrupts already pending */
2205 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
2207 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0);
2208 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0);
2213 * Free data in the RX lists.
2215 dp = &sc->sis_rx_list[0];
2216 for (i = 0; i < SIS_RX_LIST_CNT; i++, dp++) {
2217 if (dp->sis_mbuf == NULL)
2219 bus_dmamap_unload(sc->sis_tag, dp->sis_map);
2220 bus_dmamap_destroy(sc->sis_tag, dp->sis_map);
2221 m_freem(dp->sis_mbuf);
2222 dp->sis_mbuf = NULL;
2224 bzero(sc->sis_rx_list, SIS_RX_LIST_SZ);
2227 * Free the TX list buffers.
2229 dp = &sc->sis_tx_list[0];
2230 for (i = 0; i < SIS_TX_LIST_CNT; i++, dp++) {
2231 if (dp->sis_mbuf == NULL)
2233 bus_dmamap_unload(sc->sis_tag, dp->sis_map);
2234 bus_dmamap_destroy(sc->sis_tag, dp->sis_map);
2235 m_freem(dp->sis_mbuf);
2236 dp->sis_mbuf = NULL;
2239 bzero(sc->sis_tx_list, SIS_TX_LIST_SZ);
2241 sc->sis_stopped = 1;
2245 * Stop all chip I/O so that the kernel's probe routines don't
2246 * get confused by errant DMAs when rebooting.
2249 sis_shutdown(device_t dev)
2251 struct sis_softc *sc;
2253 sc = device_get_softc(dev);
2261 static device_method_t sis_methods[] = {
2262 /* Device interface */
2263 DEVMETHOD(device_probe, sis_probe),
2264 DEVMETHOD(device_attach, sis_attach),
2265 DEVMETHOD(device_detach, sis_detach),
2266 DEVMETHOD(device_shutdown, sis_shutdown),
2269 DEVMETHOD(bus_print_child, bus_generic_print_child),
2270 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
2273 DEVMETHOD(miibus_readreg, sis_miibus_readreg),
2274 DEVMETHOD(miibus_writereg, sis_miibus_writereg),
2275 DEVMETHOD(miibus_statchg, sis_miibus_statchg),
2280 static driver_t sis_driver = {
2283 sizeof(struct sis_softc)
2286 static devclass_t sis_devclass;
2288 DRIVER_MODULE(sis, pci, sis_driver, sis_devclass, 0, 0);
2289 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0);