1 /* $OpenBSD: if_sk.c,v 2.33 2003/08/12 05:23:06 nate Exp $ */
4 * Copyright (c) 1997, 1998, 1999, 2000
5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
35 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
37 * Permission to use, copy, modify, and distribute this software for any
38 * purpose with or without fee is hereby granted, provided that the above
39 * copyright notice and this permission notice appear in all copies.
41 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
42 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
43 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
44 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
45 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
46 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
47 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
50 #include <sys/cdefs.h>
51 __FBSDID("$FreeBSD$");
54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports
55 * the SK-984x series adapters, both single port and dual port.
57 * The XaQti XMAC II datasheet,
58 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
59 * The SysKonnect GEnesis manual, http://www.syskonnect.com
61 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the
62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a
63 * convenience to others until Vitesse corrects this problem:
65 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
67 * Written by Bill Paul <wpaul@ee.columbia.edu>
68 * Department of Electrical Engineering
69 * Columbia University, New York City
72 * The SysKonnect gigabit ethernet adapters consist of two main
73 * components: the SysKonnect GEnesis controller chip and the XaQti Corp.
74 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC
75 * components and a PHY while the GEnesis controller provides a PCI
76 * interface with DMA support. Each card may have between 512K and
77 * 2MB of SRAM on board depending on the configuration.
79 * The SysKonnect GEnesis controller can have either one or two XMAC
80 * chips connected to it, allowing single or dual port NIC configurations.
81 * SysKonnect has the distinction of being the only vendor on the market
82 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs,
83 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the
84 * XMAC registers. This driver takes advantage of these features to allow
85 * both XMACs to operate as independent interfaces.
88 #include <sys/param.h>
89 #include <sys/systm.h>
91 #include <sys/endian.h>
93 #include <sys/malloc.h>
94 #include <sys/kernel.h>
95 #include <sys/module.h>
96 #include <sys/socket.h>
97 #include <sys/sockio.h>
98 #include <sys/queue.h>
99 #include <sys/sysctl.h>
102 #include <net/ethernet.h>
104 #include <net/if_arp.h>
105 #include <net/if_dl.h>
106 #include <net/if_media.h>
107 #include <net/if_types.h>
108 #include <net/if_vlan_var.h>
110 #include <netinet/in.h>
111 #include <netinet/in_systm.h>
112 #include <netinet/ip.h>
114 #include <machine/bus.h>
115 #include <machine/in_cksum.h>
116 #include <machine/resource.h>
117 #include <sys/rman.h>
119 #include <dev/mii/mii.h>
120 #include <dev/mii/miivar.h>
121 #include <dev/mii/brgphyreg.h>
123 #include <dev/pci/pcireg.h>
124 #include <dev/pci/pcivar.h>
127 #define SK_USEIOSPACE
130 #include <dev/sk/if_skreg.h>
131 #include <dev/sk/xmaciireg.h>
132 #include <dev/sk/yukonreg.h>
134 MODULE_DEPEND(sk, pci, 1, 1, 1);
135 MODULE_DEPEND(sk, ether, 1, 1, 1);
136 MODULE_DEPEND(sk, miibus, 1, 1, 1);
138 /* "device miibus" required. See GENERIC if you get errors here. */
139 #include "miibus_if.h"
141 static const struct sk_type sk_devs[] = {
145 "SysKonnect Gigabit Ethernet (V1.0)"
150 "SysKonnect Gigabit Ethernet (V2.0)"
155 "Marvell Gigabit Ethernet"
159 DEVICEID_BELKIN_5005,
160 "Belkin F5D5005 Gigabit Ethernet"
165 "3Com 3C940 Gigabit Ethernet"
169 DEVICEID_LINKSYS_EG1032,
170 "Linksys EG1032 Gigabit Ethernet"
174 DEVICEID_DLINK_DGE530T_A1,
175 "D-Link DGE-530T Gigabit Ethernet"
179 DEVICEID_DLINK_DGE530T_B1,
180 "D-Link DGE-530T Gigabit Ethernet"
185 static int skc_probe(device_t);
186 static int skc_attach(device_t);
187 static int skc_detach(device_t);
188 static int skc_shutdown(device_t);
189 static int skc_suspend(device_t);
190 static int skc_resume(device_t);
191 static bus_dma_tag_t skc_get_dma_tag(device_t, device_t);
192 static int sk_detach(device_t);
193 static int sk_probe(device_t);
194 static int sk_attach(device_t);
195 static void sk_tick(void *);
196 static void sk_yukon_tick(void *);
197 static void sk_intr(void *);
198 static void sk_intr_xmac(struct sk_if_softc *);
199 static void sk_intr_bcom(struct sk_if_softc *);
200 static void sk_intr_yukon(struct sk_if_softc *);
201 static __inline void sk_rxcksum(struct ifnet *, struct mbuf *, u_int32_t);
202 static __inline int sk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t);
203 static void sk_rxeof(struct sk_if_softc *);
204 static void sk_jumbo_rxeof(struct sk_if_softc *);
205 static void sk_txeof(struct sk_if_softc *);
206 static void sk_txcksum(struct ifnet *, struct mbuf *, struct sk_tx_desc *);
207 static int sk_encap(struct sk_if_softc *, struct mbuf **);
208 static void sk_start(struct ifnet *);
209 static void sk_start_locked(struct ifnet *);
210 static int sk_ioctl(struct ifnet *, u_long, caddr_t);
211 static void sk_init(void *);
212 static void sk_init_locked(struct sk_if_softc *);
213 static void sk_init_xmac(struct sk_if_softc *);
214 static void sk_init_yukon(struct sk_if_softc *);
215 static void sk_stop(struct sk_if_softc *);
216 static void sk_watchdog(void *);
217 static int sk_ifmedia_upd(struct ifnet *);
218 static void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *);
219 static void sk_reset(struct sk_softc *);
220 static __inline void sk_discard_rxbuf(struct sk_if_softc *, int);
221 static __inline void sk_discard_jumbo_rxbuf(struct sk_if_softc *, int);
222 static int sk_newbuf(struct sk_if_softc *, int);
223 static int sk_jumbo_newbuf(struct sk_if_softc *, int);
224 static void sk_dmamap_cb(void *, bus_dma_segment_t *, int, int);
225 static int sk_dma_alloc(struct sk_if_softc *);
226 static int sk_dma_jumbo_alloc(struct sk_if_softc *);
227 static void sk_dma_free(struct sk_if_softc *);
228 static void sk_dma_jumbo_free(struct sk_if_softc *);
229 static int sk_init_rx_ring(struct sk_if_softc *);
230 static int sk_init_jumbo_rx_ring(struct sk_if_softc *);
231 static void sk_init_tx_ring(struct sk_if_softc *);
232 static u_int32_t sk_win_read_4(struct sk_softc *, int);
233 static u_int16_t sk_win_read_2(struct sk_softc *, int);
234 static u_int8_t sk_win_read_1(struct sk_softc *, int);
235 static void sk_win_write_4(struct sk_softc *, int, u_int32_t);
236 static void sk_win_write_2(struct sk_softc *, int, u_int32_t);
237 static void sk_win_write_1(struct sk_softc *, int, u_int32_t);
239 static int sk_miibus_readreg(device_t, int, int);
240 static int sk_miibus_writereg(device_t, int, int, int);
241 static void sk_miibus_statchg(device_t);
243 static int sk_xmac_miibus_readreg(struct sk_if_softc *, int, int);
244 static int sk_xmac_miibus_writereg(struct sk_if_softc *, int, int,
246 static void sk_xmac_miibus_statchg(struct sk_if_softc *);
248 static int sk_marv_miibus_readreg(struct sk_if_softc *, int, int);
249 static int sk_marv_miibus_writereg(struct sk_if_softc *, int, int,
251 static void sk_marv_miibus_statchg(struct sk_if_softc *);
253 static uint32_t sk_xmchash(const uint8_t *);
254 static void sk_setfilt(struct sk_if_softc *, u_int16_t *, int);
255 static void sk_rxfilter(struct sk_if_softc *);
256 static void sk_rxfilter_genesis(struct sk_if_softc *);
257 static void sk_rxfilter_yukon(struct sk_if_softc *);
259 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high);
260 static int sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS);
263 static int jumbo_disable = 0;
264 TUNABLE_INT("hw.skc.jumbo_disable", &jumbo_disable);
267 * It seems that SK-NET GENESIS supports very simple checksum offload
268 * capability for Tx and I believe it can generate 0 checksum value for
269 * UDP packets in Tx as the hardware can't differenciate UDP packets from
270 * TCP packets. 0 chcecksum value for UDP packet is an invalid one as it
271 * means sender didn't perforam checksum computation. For the safety I
272 * disabled UDP checksum offload capability at the moment. Alternatively
273 * we can intrduce a LINK0/LINK1 flag as hme(4) did in its Tx checksum
276 #define SK_CSUM_FEATURES (CSUM_TCP)
279 * Note that we have newbus methods for both the GEnesis controller
280 * itself and the XMAC(s). The XMACs are children of the GEnesis, and
281 * the miibus code is a child of the XMACs. We need to do it this way
282 * so that the miibus drivers can access the PHY registers on the
283 * right PHY. It's not quite what I had in mind, but it's the only
284 * design that achieves the desired effect.
286 static device_method_t skc_methods[] = {
287 /* Device interface */
288 DEVMETHOD(device_probe, skc_probe),
289 DEVMETHOD(device_attach, skc_attach),
290 DEVMETHOD(device_detach, skc_detach),
291 DEVMETHOD(device_suspend, skc_suspend),
292 DEVMETHOD(device_resume, skc_resume),
293 DEVMETHOD(device_shutdown, skc_shutdown),
295 DEVMETHOD(bus_get_dma_tag, skc_get_dma_tag),
300 static driver_t skc_driver = {
303 sizeof(struct sk_softc)
306 static devclass_t skc_devclass;
308 static device_method_t sk_methods[] = {
309 /* Device interface */
310 DEVMETHOD(device_probe, sk_probe),
311 DEVMETHOD(device_attach, sk_attach),
312 DEVMETHOD(device_detach, sk_detach),
313 DEVMETHOD(device_shutdown, bus_generic_shutdown),
316 DEVMETHOD(miibus_readreg, sk_miibus_readreg),
317 DEVMETHOD(miibus_writereg, sk_miibus_writereg),
318 DEVMETHOD(miibus_statchg, sk_miibus_statchg),
323 static driver_t sk_driver = {
326 sizeof(struct sk_if_softc)
329 static devclass_t sk_devclass;
331 DRIVER_MODULE(skc, pci, skc_driver, skc_devclass, NULL, NULL);
332 DRIVER_MODULE(sk, skc, sk_driver, sk_devclass, NULL, NULL);
333 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, NULL, NULL);
335 static struct resource_spec sk_res_spec_io[] = {
336 { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE },
337 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
341 static struct resource_spec sk_res_spec_mem[] = {
342 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
343 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
347 #define SK_SETBIT(sc, reg, x) \
348 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
350 #define SK_CLRBIT(sc, reg, x) \
351 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
353 #define SK_WIN_SETBIT_4(sc, reg, x) \
354 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x)
356 #define SK_WIN_CLRBIT_4(sc, reg, x) \
357 sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x)
359 #define SK_WIN_SETBIT_2(sc, reg, x) \
360 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x)
362 #define SK_WIN_CLRBIT_2(sc, reg, x) \
363 sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x)
366 sk_win_read_4(sc, reg)
371 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
372 return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)));
374 return(CSR_READ_4(sc, reg));
379 sk_win_read_2(sc, reg)
384 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
385 return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)));
387 return(CSR_READ_2(sc, reg));
392 sk_win_read_1(sc, reg)
397 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
398 return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)));
400 return(CSR_READ_1(sc, reg));
405 sk_win_write_4(sc, reg, val)
411 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
412 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val);
414 CSR_WRITE_4(sc, reg, val);
420 sk_win_write_2(sc, reg, val)
426 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
427 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val);
429 CSR_WRITE_2(sc, reg, val);
435 sk_win_write_1(sc, reg, val)
441 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
442 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val);
444 CSR_WRITE_1(sc, reg, val);
450 sk_miibus_readreg(dev, phy, reg)
454 struct sk_if_softc *sc_if;
457 sc_if = device_get_softc(dev);
459 SK_IF_MII_LOCK(sc_if);
460 switch(sc_if->sk_softc->sk_type) {
462 v = sk_xmac_miibus_readreg(sc_if, phy, reg);
467 v = sk_marv_miibus_readreg(sc_if, phy, reg);
473 SK_IF_MII_UNLOCK(sc_if);
479 sk_miibus_writereg(dev, phy, reg, val)
483 struct sk_if_softc *sc_if;
486 sc_if = device_get_softc(dev);
488 SK_IF_MII_LOCK(sc_if);
489 switch(sc_if->sk_softc->sk_type) {
491 v = sk_xmac_miibus_writereg(sc_if, phy, reg, val);
496 v = sk_marv_miibus_writereg(sc_if, phy, reg, val);
502 SK_IF_MII_UNLOCK(sc_if);
508 sk_miibus_statchg(dev)
511 struct sk_if_softc *sc_if;
513 sc_if = device_get_softc(dev);
515 SK_IF_MII_LOCK(sc_if);
516 switch(sc_if->sk_softc->sk_type) {
518 sk_xmac_miibus_statchg(sc_if);
523 sk_marv_miibus_statchg(sc_if);
526 SK_IF_MII_UNLOCK(sc_if);
532 sk_xmac_miibus_readreg(sc_if, phy, reg)
533 struct sk_if_softc *sc_if;
538 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
539 SK_XM_READ_2(sc_if, XM_PHY_DATA);
540 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
541 for (i = 0; i < SK_TIMEOUT; i++) {
543 if (SK_XM_READ_2(sc_if, XM_MMUCMD) &
544 XM_MMUCMD_PHYDATARDY)
548 if (i == SK_TIMEOUT) {
549 if_printf(sc_if->sk_ifp, "phy failed to come ready\n");
554 i = SK_XM_READ_2(sc_if, XM_PHY_DATA);
560 sk_xmac_miibus_writereg(sc_if, phy, reg, val)
561 struct sk_if_softc *sc_if;
566 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
567 for (i = 0; i < SK_TIMEOUT; i++) {
568 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
572 if (i == SK_TIMEOUT) {
573 if_printf(sc_if->sk_ifp, "phy failed to come ready\n");
577 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val);
578 for (i = 0; i < SK_TIMEOUT; i++) {
580 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
584 if_printf(sc_if->sk_ifp, "phy write timed out\n");
590 sk_xmac_miibus_statchg(sc_if)
591 struct sk_if_softc *sc_if;
593 struct mii_data *mii;
595 mii = device_get_softc(sc_if->sk_miibus);
598 * If this is a GMII PHY, manually set the XMAC's
599 * duplex mode accordingly.
601 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
602 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
603 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
605 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
611 sk_marv_miibus_readreg(sc_if, phy, reg)
612 struct sk_if_softc *sc_if;
618 if (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER &&
619 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER) {
623 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
624 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);
626 for (i = 0; i < SK_TIMEOUT; i++) {
628 val = SK_YU_READ_2(sc_if, YUKON_SMICR);
629 if (val & YU_SMICR_READ_VALID)
633 if (i == SK_TIMEOUT) {
634 if_printf(sc_if->sk_ifp, "phy failed to come ready\n");
638 val = SK_YU_READ_2(sc_if, YUKON_SMIDR);
644 sk_marv_miibus_writereg(sc_if, phy, reg, val)
645 struct sk_if_softc *sc_if;
650 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val);
651 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
652 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);
654 for (i = 0; i < SK_TIMEOUT; i++) {
656 if ((SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) == 0)
660 if_printf(sc_if->sk_ifp, "phy write timeout\n");
666 sk_marv_miibus_statchg(sc_if)
667 struct sk_if_softc *sc_if;
680 /* Compute CRC for the address value. */
681 crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
683 return (~crc & ((1 << HASH_BITS) - 1));
687 sk_setfilt(sc_if, addr, slot)
688 struct sk_if_softc *sc_if;
694 base = XM_RXFILT_ENTRY(slot);
696 SK_XM_WRITE_2(sc_if, base, addr[0]);
697 SK_XM_WRITE_2(sc_if, base + 2, addr[1]);
698 SK_XM_WRITE_2(sc_if, base + 4, addr[2]);
705 struct sk_if_softc *sc_if;
709 SK_IF_LOCK_ASSERT(sc_if);
711 sc = sc_if->sk_softc;
712 if (sc->sk_type == SK_GENESIS)
713 sk_rxfilter_genesis(sc_if);
715 sk_rxfilter_yukon(sc_if);
719 sk_rxfilter_genesis(sc_if)
720 struct sk_if_softc *sc_if;
722 struct ifnet *ifp = sc_if->sk_ifp;
723 u_int32_t hashes[2] = { 0, 0 }, mode;
725 struct ifmultiaddr *ifma;
726 u_int16_t dummy[] = { 0, 0, 0 };
727 u_int16_t maddr[(ETHER_ADDR_LEN+1)/2];
729 SK_IF_LOCK_ASSERT(sc_if);
731 mode = SK_XM_READ_4(sc_if, XM_MODE);
732 mode &= ~(XM_MODE_RX_PROMISC | XM_MODE_RX_USE_HASH |
733 XM_MODE_RX_USE_PERFECT);
734 /* First, zot all the existing perfect filters. */
735 for (i = 1; i < XM_RXFILT_MAX; i++)
736 sk_setfilt(sc_if, dummy, i);
738 /* Now program new ones. */
739 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
740 if (ifp->if_flags & IFF_ALLMULTI)
741 mode |= XM_MODE_RX_USE_HASH;
742 if (ifp->if_flags & IFF_PROMISC)
743 mode |= XM_MODE_RX_PROMISC;
744 hashes[0] = 0xFFFFFFFF;
745 hashes[1] = 0xFFFFFFFF;
749 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead,
751 if (ifma->ifma_addr->sa_family != AF_LINK)
754 * Program the first XM_RXFILT_MAX multicast groups
755 * into the perfect filter.
757 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
758 maddr, ETHER_ADDR_LEN);
759 if (i < XM_RXFILT_MAX) {
760 sk_setfilt(sc_if, maddr, i);
761 mode |= XM_MODE_RX_USE_PERFECT;
765 h = sk_xmchash((const uint8_t *)maddr);
767 hashes[0] |= (1 << h);
769 hashes[1] |= (1 << (h - 32));
770 mode |= XM_MODE_RX_USE_HASH;
772 if_maddr_runlock(ifp);
775 SK_XM_WRITE_4(sc_if, XM_MODE, mode);
776 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]);
777 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]);
781 sk_rxfilter_yukon(sc_if)
782 struct sk_if_softc *sc_if;
785 u_int32_t crc, hashes[2] = { 0, 0 }, mode;
786 struct ifmultiaddr *ifma;
788 SK_IF_LOCK_ASSERT(sc_if);
791 mode = SK_YU_READ_2(sc_if, YUKON_RCR);
792 if (ifp->if_flags & IFF_PROMISC)
793 mode &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN);
794 else if (ifp->if_flags & IFF_ALLMULTI) {
795 mode |= YU_RCR_UFLEN | YU_RCR_MUFLEN;
796 hashes[0] = 0xFFFFFFFF;
797 hashes[1] = 0xFFFFFFFF;
799 mode |= YU_RCR_UFLEN;
801 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
802 if (ifma->ifma_addr->sa_family != AF_LINK)
804 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
805 ifma->ifma_addr), ETHER_ADDR_LEN);
806 /* Just want the 6 least significant bits. */
808 /* Set the corresponding bit in the hash table. */
809 hashes[crc >> 5] |= 1 << (crc & 0x1f);
811 if_maddr_runlock(ifp);
812 if (hashes[0] != 0 || hashes[1] != 0)
813 mode |= YU_RCR_MUFLEN;
816 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff);
817 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff);
818 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff);
819 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff);
820 SK_YU_WRITE_2(sc_if, YUKON_RCR, mode);
824 sk_init_rx_ring(sc_if)
825 struct sk_if_softc *sc_if;
827 struct sk_ring_data *rd;
829 u_int32_t csum_start;
832 sc_if->sk_cdata.sk_rx_cons = 0;
834 csum_start = (ETHER_HDR_LEN + sizeof(struct ip)) << 16 |
836 rd = &sc_if->sk_rdata;
837 bzero(rd->sk_rx_ring, sizeof(struct sk_rx_desc) * SK_RX_RING_CNT);
838 for (i = 0; i < SK_RX_RING_CNT; i++) {
839 if (sk_newbuf(sc_if, i) != 0)
841 if (i == (SK_RX_RING_CNT - 1))
842 addr = SK_RX_RING_ADDR(sc_if, 0);
844 addr = SK_RX_RING_ADDR(sc_if, i + 1);
845 rd->sk_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr));
846 rd->sk_rx_ring[i].sk_csum_start = htole32(csum_start);
849 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag,
850 sc_if->sk_cdata.sk_rx_ring_map,
851 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
857 sk_init_jumbo_rx_ring(sc_if)
858 struct sk_if_softc *sc_if;
860 struct sk_ring_data *rd;
862 u_int32_t csum_start;
865 sc_if->sk_cdata.sk_jumbo_rx_cons = 0;
867 csum_start = ((ETHER_HDR_LEN + sizeof(struct ip)) << 16) |
869 rd = &sc_if->sk_rdata;
870 bzero(rd->sk_jumbo_rx_ring,
871 sizeof(struct sk_rx_desc) * SK_JUMBO_RX_RING_CNT);
872 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
873 if (sk_jumbo_newbuf(sc_if, i) != 0)
875 if (i == (SK_JUMBO_RX_RING_CNT - 1))
876 addr = SK_JUMBO_RX_RING_ADDR(sc_if, 0);
878 addr = SK_JUMBO_RX_RING_ADDR(sc_if, i + 1);
879 rd->sk_jumbo_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr));
880 rd->sk_jumbo_rx_ring[i].sk_csum_start = htole32(csum_start);
883 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
884 sc_if->sk_cdata.sk_jumbo_rx_ring_map,
885 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
891 sk_init_tx_ring(sc_if)
892 struct sk_if_softc *sc_if;
894 struct sk_ring_data *rd;
895 struct sk_txdesc *txd;
899 STAILQ_INIT(&sc_if->sk_cdata.sk_txfreeq);
900 STAILQ_INIT(&sc_if->sk_cdata.sk_txbusyq);
902 sc_if->sk_cdata.sk_tx_prod = 0;
903 sc_if->sk_cdata.sk_tx_cons = 0;
904 sc_if->sk_cdata.sk_tx_cnt = 0;
906 rd = &sc_if->sk_rdata;
907 bzero(rd->sk_tx_ring, sizeof(struct sk_tx_desc) * SK_TX_RING_CNT);
908 for (i = 0; i < SK_TX_RING_CNT; i++) {
909 if (i == (SK_TX_RING_CNT - 1))
910 addr = SK_TX_RING_ADDR(sc_if, 0);
912 addr = SK_TX_RING_ADDR(sc_if, i + 1);
913 rd->sk_tx_ring[i].sk_next = htole32(SK_ADDR_LO(addr));
914 txd = &sc_if->sk_cdata.sk_txdesc[i];
915 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q);
918 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
919 sc_if->sk_cdata.sk_tx_ring_map,
920 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
924 sk_discard_rxbuf(sc_if, idx)
925 struct sk_if_softc *sc_if;
928 struct sk_rx_desc *r;
929 struct sk_rxdesc *rxd;
933 r = &sc_if->sk_rdata.sk_rx_ring[idx];
934 rxd = &sc_if->sk_cdata.sk_rxdesc[idx];
936 r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM);
940 sk_discard_jumbo_rxbuf(sc_if, idx)
941 struct sk_if_softc *sc_if;
944 struct sk_rx_desc *r;
945 struct sk_rxdesc *rxd;
948 r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx];
949 rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx];
951 r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM);
955 sk_newbuf(sc_if, idx)
956 struct sk_if_softc *sc_if;
959 struct sk_rx_desc *r;
960 struct sk_rxdesc *rxd;
962 bus_dma_segment_t segs[1];
966 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
969 m->m_len = m->m_pkthdr.len = MCLBYTES;
970 m_adj(m, ETHER_ALIGN);
972 if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_rx_tag,
973 sc_if->sk_cdata.sk_rx_sparemap, m, segs, &nsegs, 0) != 0) {
977 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
979 rxd = &sc_if->sk_cdata.sk_rxdesc[idx];
980 if (rxd->rx_m != NULL) {
981 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap,
982 BUS_DMASYNC_POSTREAD);
983 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap);
985 map = rxd->rx_dmamap;
986 rxd->rx_dmamap = sc_if->sk_cdata.sk_rx_sparemap;
987 sc_if->sk_cdata.sk_rx_sparemap = map;
988 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap,
989 BUS_DMASYNC_PREREAD);
991 r = &sc_if->sk_rdata.sk_rx_ring[idx];
992 r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr));
993 r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr));
994 r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM);
1000 sk_jumbo_newbuf(sc_if, idx)
1001 struct sk_if_softc *sc_if;
1004 struct sk_rx_desc *r;
1005 struct sk_rxdesc *rxd;
1007 bus_dma_segment_t segs[1];
1011 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
1014 if ((m->m_flags & M_EXT) == 0) {
1018 m->m_pkthdr.len = m->m_len = MJUM9BYTES;
1020 * Adjust alignment so packet payload begins on a
1021 * longword boundary. Mandatory for Alpha, useful on
1024 m_adj(m, ETHER_ALIGN);
1026 if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_jumbo_rx_tag,
1027 sc_if->sk_cdata.sk_jumbo_rx_sparemap, m, segs, &nsegs, 0) != 0) {
1031 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1033 rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx];
1034 if (rxd->rx_m != NULL) {
1035 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap,
1036 BUS_DMASYNC_POSTREAD);
1037 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag,
1040 map = rxd->rx_dmamap;
1041 rxd->rx_dmamap = sc_if->sk_cdata.sk_jumbo_rx_sparemap;
1042 sc_if->sk_cdata.sk_jumbo_rx_sparemap = map;
1043 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap,
1044 BUS_DMASYNC_PREREAD);
1046 r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx];
1047 r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr));
1048 r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr));
1049 r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM);
1055 * Set media options.
1061 struct sk_if_softc *sc_if = ifp->if_softc;
1062 struct mii_data *mii;
1064 mii = device_get_softc(sc_if->sk_miibus);
1072 * Report current media status.
1075 sk_ifmedia_sts(ifp, ifmr)
1077 struct ifmediareq *ifmr;
1079 struct sk_if_softc *sc_if;
1080 struct mii_data *mii;
1082 sc_if = ifp->if_softc;
1083 mii = device_get_softc(sc_if->sk_miibus);
1086 ifmr->ifm_active = mii->mii_media_active;
1087 ifmr->ifm_status = mii->mii_media_status;
1093 sk_ioctl(ifp, command, data)
1098 struct sk_if_softc *sc_if = ifp->if_softc;
1099 struct ifreq *ifr = (struct ifreq *) data;
1101 struct mii_data *mii;
1106 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > SK_JUMBO_MTU)
1108 else if (ifp->if_mtu != ifr->ifr_mtu) {
1109 if (sc_if->sk_jumbo_disable != 0 &&
1110 ifr->ifr_mtu > SK_MAX_FRAMELEN)
1114 ifp->if_mtu = ifr->ifr_mtu;
1115 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1116 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1117 sk_init_locked(sc_if);
1119 SK_IF_UNLOCK(sc_if);
1125 if (ifp->if_flags & IFF_UP) {
1126 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1127 if ((ifp->if_flags ^ sc_if->sk_if_flags)
1128 & (IFF_PROMISC | IFF_ALLMULTI))
1131 sk_init_locked(sc_if);
1133 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1136 sc_if->sk_if_flags = ifp->if_flags;
1137 SK_IF_UNLOCK(sc_if);
1142 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1144 SK_IF_UNLOCK(sc_if);
1148 mii = device_get_softc(sc_if->sk_miibus);
1149 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1153 if (sc_if->sk_softc->sk_type == SK_GENESIS) {
1154 SK_IF_UNLOCK(sc_if);
1157 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1158 if ((mask & IFCAP_TXCSUM) != 0 &&
1159 (IFCAP_TXCSUM & ifp->if_capabilities) != 0) {
1160 ifp->if_capenable ^= IFCAP_TXCSUM;
1161 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1162 ifp->if_hwassist |= SK_CSUM_FEATURES;
1164 ifp->if_hwassist &= ~SK_CSUM_FEATURES;
1166 if ((mask & IFCAP_RXCSUM) != 0 &&
1167 (IFCAP_RXCSUM & ifp->if_capabilities) != 0)
1168 ifp->if_capenable ^= IFCAP_RXCSUM;
1169 SK_IF_UNLOCK(sc_if);
1172 error = ether_ioctl(ifp, command, data);
1180 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device
1181 * IDs against our list and return a device name if we find a match.
1187 const struct sk_type *t = sk_devs;
1189 while(t->sk_name != NULL) {
1190 if ((pci_get_vendor(dev) == t->sk_vid) &&
1191 (pci_get_device(dev) == t->sk_did)) {
1193 * Only attach to rev. 2 of the Linksys EG1032 adapter.
1194 * Rev. 3 is supported by re(4).
1196 if ((t->sk_vid == VENDORID_LINKSYS) &&
1197 (t->sk_did == DEVICEID_LINKSYS_EG1032) &&
1198 (pci_get_subdevice(dev) !=
1199 SUBDEVICEID_LINKSYS_EG1032_REV2)) {
1203 device_set_desc(dev, t->sk_name);
1204 return (BUS_PROBE_DEFAULT);
1213 * Force the GEnesis into reset, then bring it out of reset.
1217 struct sk_softc *sc;
1220 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET);
1221 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET);
1222 if (SK_YUKON_FAMILY(sc->sk_type))
1223 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
1226 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET);
1228 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
1229 if (SK_YUKON_FAMILY(sc->sk_type))
1230 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);
1232 if (sc->sk_type == SK_GENESIS) {
1233 /* Configure packet arbiter */
1234 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET);
1235 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT);
1236 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT);
1237 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT);
1238 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT);
1241 /* Enable RAM interface */
1242 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET);
1245 * Configure interrupt moderation. The moderation timer
1246 * defers interrupts specified in the interrupt moderation
1247 * timer mask based on the timeout specified in the interrupt
1248 * moderation timer init register. Each bit in the timer
1249 * register represents one tick, so to specify a timeout in
1250 * microseconds, we have to multiply by the correct number of
1251 * ticks-per-microsecond.
1253 switch (sc->sk_type) {
1255 sc->sk_int_ticks = SK_IMTIMER_TICKS_GENESIS;
1258 sc->sk_int_ticks = SK_IMTIMER_TICKS_YUKON;
1262 device_printf(sc->sk_dev, "interrupt moderation is %d us\n",
1264 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod,
1266 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF|
1267 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF);
1268 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START);
1277 struct sk_softc *sc;
1279 sc = device_get_softc(device_get_parent(dev));
1282 * Not much to do here. We always know there will be
1283 * at least one XMAC present, and if there are two,
1284 * skc_attach() will create a second device instance
1287 switch (sc->sk_type) {
1289 device_set_desc(dev, "XaQti Corp. XMAC II");
1294 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon");
1298 return (BUS_PROBE_DEFAULT);
1302 * Each XMAC chip is attached as a separate logical IP interface.
1303 * Single port cards will have only one logical interface of course.
1309 struct sk_softc *sc;
1310 struct sk_if_softc *sc_if;
1313 int error, i, phy, port;
1315 u_char inv_mac[] = {0, 0, 0, 0, 0, 0};
1321 sc_if = device_get_softc(dev);
1322 sc = device_get_softc(device_get_parent(dev));
1323 port = *(int *)device_get_ivars(dev);
1325 sc_if->sk_if_dev = dev;
1326 sc_if->sk_port = port;
1327 sc_if->sk_softc = sc;
1328 sc->sk_if[port] = sc_if;
1329 if (port == SK_PORT_A)
1330 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0;
1331 if (port == SK_PORT_B)
1332 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1;
1334 callout_init_mtx(&sc_if->sk_tick_ch, &sc_if->sk_softc->sk_mtx, 0);
1335 callout_init_mtx(&sc_if->sk_watchdog_ch, &sc_if->sk_softc->sk_mtx, 0);
1337 if (sk_dma_alloc(sc_if) != 0) {
1341 sk_dma_jumbo_alloc(sc_if);
1343 ifp = sc_if->sk_ifp = if_alloc(IFT_ETHER);
1345 device_printf(sc_if->sk_if_dev, "can not if_alloc()\n");
1349 ifp->if_softc = sc_if;
1350 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1351 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1353 * SK_GENESIS has a bug in checksum offload - From linux.
1355 if (sc_if->sk_softc->sk_type != SK_GENESIS) {
1356 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_RXCSUM;
1357 ifp->if_hwassist = 0;
1359 ifp->if_capabilities = 0;
1360 ifp->if_hwassist = 0;
1362 ifp->if_capenable = ifp->if_capabilities;
1364 * Some revision of Yukon controller generates corrupted
1365 * frame when TX checksum offloading is enabled. The
1366 * frame has a valid checksum value so payload might be
1367 * modified during TX checksum calculation. Disable TX
1368 * checksum offloading but give users chance to enable it
1369 * when they know their controller works without problems
1370 * with TX checksum offloading.
1372 ifp->if_capenable &= ~IFCAP_TXCSUM;
1373 ifp->if_ioctl = sk_ioctl;
1374 ifp->if_start = sk_start;
1375 ifp->if_init = sk_init;
1376 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1);
1377 ifp->if_snd.ifq_drv_maxlen = SK_TX_RING_CNT - 1;
1378 IFQ_SET_READY(&ifp->if_snd);
1381 * Get station address for this interface. Note that
1382 * dual port cards actually come with three station
1383 * addresses: one for each port, plus an extra. The
1384 * extra one is used by the SysKonnect driver software
1385 * as a 'virtual' station address for when both ports
1386 * are operating in failover mode. Currently we don't
1387 * use this extra address.
1390 for (i = 0; i < ETHER_ADDR_LEN; i++)
1392 sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i);
1394 /* Verify whether the station address is invalid or not. */
1395 if (bcmp(eaddr, inv_mac, sizeof(inv_mac)) == 0) {
1396 device_printf(sc_if->sk_if_dev,
1397 "Generating random ethernet address\n");
1400 * Set OUI to convenient locally assigned address. 'b'
1401 * is 0x62, which has the locally assigned bit set, and
1402 * the broadcast/multicast bit clear.
1407 eaddr[3] = (r >> 16) & 0xff;
1408 eaddr[4] = (r >> 8) & 0xff;
1409 eaddr[5] = (r >> 0) & 0xff;
1412 * Set up RAM buffer addresses. The NIC will have a certain
1413 * amount of SRAM on it, somewhere between 512K and 2MB. We
1414 * need to divide this up a) between the transmitter and
1415 * receiver and b) between the two XMACs, if this is a
1416 * dual port NIC. Our algotithm is to divide up the memory
1417 * evenly so that everyone gets a fair share.
1419 * Just to be contrary, Yukon2 appears to have separate memory
1422 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) {
1423 u_int32_t chunk, val;
1425 chunk = sc->sk_ramsize / 2;
1426 val = sc->sk_rboff / sizeof(u_int64_t);
1427 sc_if->sk_rx_ramstart = val;
1428 val += (chunk / sizeof(u_int64_t));
1429 sc_if->sk_rx_ramend = val - 1;
1430 sc_if->sk_tx_ramstart = val;
1431 val += (chunk / sizeof(u_int64_t));
1432 sc_if->sk_tx_ramend = val - 1;
1434 u_int32_t chunk, val;
1436 chunk = sc->sk_ramsize / 4;
1437 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) /
1439 sc_if->sk_rx_ramstart = val;
1440 val += (chunk / sizeof(u_int64_t));
1441 sc_if->sk_rx_ramend = val - 1;
1442 sc_if->sk_tx_ramstart = val;
1443 val += (chunk / sizeof(u_int64_t));
1444 sc_if->sk_tx_ramend = val - 1;
1447 /* Read and save PHY type and set PHY address */
1448 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF;
1449 if (!SK_YUKON_FAMILY(sc->sk_type)) {
1450 switch(sc_if->sk_phytype) {
1451 case SK_PHYTYPE_XMAC:
1452 sc_if->sk_phyaddr = SK_PHYADDR_XMAC;
1454 case SK_PHYTYPE_BCOM:
1455 sc_if->sk_phyaddr = SK_PHYADDR_BCOM;
1458 device_printf(sc->sk_dev, "unsupported PHY type: %d\n",
1461 SK_IF_UNLOCK(sc_if);
1465 if (sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER &&
1466 sc->sk_pmd != 'S') {
1467 /* not initialized, punt */
1468 sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER;
1469 sc->sk_coppertype = 1;
1472 sc_if->sk_phyaddr = SK_PHYADDR_MARV;
1474 if (!(sc->sk_coppertype))
1475 sc_if->sk_phytype = SK_PHYTYPE_MARV_FIBER;
1479 * Call MI attach routine. Can't hold locks when calling into ether_*.
1481 SK_IF_UNLOCK(sc_if);
1482 ether_ifattach(ifp, eaddr);
1486 * The hardware should be ready for VLAN_MTU by default:
1487 * XMAC II has 0x8100 in VLAN Tag Level 1 register initially;
1488 * YU_SMR_MFL_VLAN is set by this driver in Yukon.
1491 ifp->if_capabilities |= IFCAP_VLAN_MTU;
1492 ifp->if_capenable |= IFCAP_VLAN_MTU;
1494 * Tell the upper layer(s) we support long frames.
1495 * Must appear after the call to ether_ifattach() because
1496 * ether_ifattach() sets ifi_hdrlen to the default value.
1498 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1504 switch (sc->sk_type) {
1506 sk_init_xmac(sc_if);
1507 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
1513 sk_init_yukon(sc_if);
1518 SK_IF_UNLOCK(sc_if);
1519 error = mii_attach(dev, &sc_if->sk_miibus, ifp, sk_ifmedia_upd,
1520 sk_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
1522 device_printf(sc_if->sk_if_dev, "attaching PHYs failed\n");
1523 ether_ifdetach(ifp);
1529 /* Access should be ok even though lock has been dropped */
1530 sc->sk_if[port] = NULL;
1538 * Attach the interface. Allocate softc structures, do ifmedia
1539 * setup and ethernet/BPF attach.
1545 struct sk_softc *sc;
1546 int error = 0, *port;
1548 const char *pname = NULL;
1551 sc = device_get_softc(dev);
1554 mtx_init(&sc->sk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1556 mtx_init(&sc->sk_mii_mtx, "sk_mii_mutex", NULL, MTX_DEF);
1558 * Map control/status registers.
1560 pci_enable_busmaster(dev);
1562 /* Allocate resources */
1563 #ifdef SK_USEIOSPACE
1564 sc->sk_res_spec = sk_res_spec_io;
1566 sc->sk_res_spec = sk_res_spec_mem;
1568 error = bus_alloc_resources(dev, sc->sk_res_spec, sc->sk_res);
1570 if (sc->sk_res_spec == sk_res_spec_mem)
1571 sc->sk_res_spec = sk_res_spec_io;
1573 sc->sk_res_spec = sk_res_spec_mem;
1574 error = bus_alloc_resources(dev, sc->sk_res_spec, sc->sk_res);
1576 device_printf(dev, "couldn't allocate %s resources\n",
1577 sc->sk_res_spec == sk_res_spec_mem ? "memory" :
1583 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER);
1584 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4) & 0xf;
1586 /* Bail out if chip is not recognized. */
1587 if (sc->sk_type != SK_GENESIS && !SK_YUKON_FAMILY(sc->sk_type)) {
1588 device_printf(dev, "unknown device: chipver=%02x, rev=%x\n",
1589 sc->sk_type, sc->sk_rev);
1594 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
1595 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1596 OID_AUTO, "int_mod", CTLTYPE_INT|CTLFLAG_RW,
1597 &sc->sk_int_mod, 0, sysctl_hw_sk_int_mod, "I",
1598 "SK interrupt moderation");
1600 /* Pull in device tunables. */
1601 sc->sk_int_mod = SK_IM_DEFAULT;
1602 error = resource_int_value(device_get_name(dev), device_get_unit(dev),
1603 "int_mod", &sc->sk_int_mod);
1605 if (sc->sk_int_mod < SK_IM_MIN ||
1606 sc->sk_int_mod > SK_IM_MAX) {
1607 device_printf(dev, "int_mod value out of range; "
1608 "using default: %d\n", SK_IM_DEFAULT);
1609 sc->sk_int_mod = SK_IM_DEFAULT;
1613 /* Reset the adapter. */
1616 skrs = sk_win_read_1(sc, SK_EPROM0);
1617 if (sc->sk_type == SK_GENESIS) {
1618 /* Read and save RAM size and RAMbuffer offset */
1620 case SK_RAMSIZE_512K_64:
1621 sc->sk_ramsize = 0x80000;
1622 sc->sk_rboff = SK_RBOFF_0;
1624 case SK_RAMSIZE_1024K_64:
1625 sc->sk_ramsize = 0x100000;
1626 sc->sk_rboff = SK_RBOFF_80000;
1628 case SK_RAMSIZE_1024K_128:
1629 sc->sk_ramsize = 0x100000;
1630 sc->sk_rboff = SK_RBOFF_0;
1632 case SK_RAMSIZE_2048K_128:
1633 sc->sk_ramsize = 0x200000;
1634 sc->sk_rboff = SK_RBOFF_0;
1637 device_printf(dev, "unknown ram size: %d\n", skrs);
1641 } else { /* SK_YUKON_FAMILY */
1643 sc->sk_ramsize = 0x20000;
1645 sc->sk_ramsize = skrs * (1<<12);
1646 sc->sk_rboff = SK_RBOFF_0;
1649 /* Read and save physical media type */
1650 sc->sk_pmd = sk_win_read_1(sc, SK_PMDTYPE);
1652 if (sc->sk_pmd == 'T' || sc->sk_pmd == '1')
1653 sc->sk_coppertype = 1;
1655 sc->sk_coppertype = 0;
1657 /* Determine whether to name it with VPD PN or just make it up.
1658 * Marvell Yukon VPD PN seems to freqently be bogus. */
1659 switch (pci_get_device(dev)) {
1660 case DEVICEID_SK_V1:
1661 case DEVICEID_BELKIN_5005:
1662 case DEVICEID_3COM_3C940:
1663 case DEVICEID_LINKSYS_EG1032:
1664 case DEVICEID_DLINK_DGE530T_A1:
1665 case DEVICEID_DLINK_DGE530T_B1:
1666 /* Stay with VPD PN. */
1667 (void) pci_get_vpd_ident(dev, &pname);
1669 case DEVICEID_SK_V2:
1670 /* YUKON VPD PN might bear no resemblance to reality. */
1671 switch (sc->sk_type) {
1673 /* Stay with VPD PN. */
1674 (void) pci_get_vpd_ident(dev, &pname);
1677 pname = "Marvell Yukon Gigabit Ethernet";
1680 pname = "Marvell Yukon Lite Gigabit Ethernet";
1683 pname = "Marvell Yukon LP Gigabit Ethernet";
1686 pname = "Marvell Yukon (Unknown) Gigabit Ethernet";
1690 /* Yukon Lite Rev. A0 needs special test. */
1691 if (sc->sk_type == SK_YUKON || sc->sk_type == SK_YUKON_LP) {
1695 /* Save flash address register before testing. */
1696 far = sk_win_read_4(sc, SK_EP_ADDR);
1698 sk_win_write_1(sc, SK_EP_ADDR+0x03, 0xff);
1699 testbyte = sk_win_read_1(sc, SK_EP_ADDR+0x03);
1701 if (testbyte != 0x00) {
1702 /* Yukon Lite Rev. A0 detected. */
1703 sc->sk_type = SK_YUKON_LITE;
1704 sc->sk_rev = SK_YUKON_LITE_REV_A0;
1705 /* Restore flash address register. */
1706 sk_win_write_4(sc, SK_EP_ADDR, far);
1711 device_printf(dev, "unknown device: vendor=%04x, device=%04x, "
1712 "chipver=%02x, rev=%x\n",
1713 pci_get_vendor(dev), pci_get_device(dev),
1714 sc->sk_type, sc->sk_rev);
1719 if (sc->sk_type == SK_YUKON_LITE) {
1720 switch (sc->sk_rev) {
1721 case SK_YUKON_LITE_REV_A0:
1724 case SK_YUKON_LITE_REV_A1:
1727 case SK_YUKON_LITE_REV_A3:
1738 /* Announce the product name and more VPD data if there. */
1740 device_printf(dev, "%s rev. %s(0x%x)\n",
1741 pname, revstr, sc->sk_rev);
1744 device_printf(dev, "chip ver = 0x%02x\n", sc->sk_type);
1745 device_printf(dev, "chip rev = 0x%02x\n", sc->sk_rev);
1746 device_printf(dev, "SK_EPROM0 = 0x%02x\n", skrs);
1747 device_printf(dev, "SRAM size = 0x%06x\n", sc->sk_ramsize);
1750 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1);
1751 if (sc->sk_devs[SK_PORT_A] == NULL) {
1752 device_printf(dev, "failed to add child for PORT_A\n");
1756 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
1758 device_printf(dev, "failed to allocate memory for "
1759 "ivars of PORT_A\n");
1764 device_set_ivars(sc->sk_devs[SK_PORT_A], port);
1766 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) {
1767 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1);
1768 if (sc->sk_devs[SK_PORT_B] == NULL) {
1769 device_printf(dev, "failed to add child for PORT_B\n");
1773 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
1775 device_printf(dev, "failed to allocate memory for "
1776 "ivars of PORT_B\n");
1781 device_set_ivars(sc->sk_devs[SK_PORT_B], port);
1784 /* Turn on the 'driver is loaded' LED. */
1785 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
1787 error = bus_generic_attach(dev);
1789 device_printf(dev, "failed to attach port(s)\n");
1793 /* Hook interrupt last to avoid having to lock softc */
1794 error = bus_setup_intr(dev, sc->sk_res[1], INTR_TYPE_NET|INTR_MPSAFE,
1795 NULL, sk_intr, sc, &sc->sk_intrhand);
1798 device_printf(dev, "couldn't set up irq\n");
1810 * Shutdown hardware and free up resources. This can be called any
1811 * time after the mutex has been initialized. It is called in both
1812 * the error case in attach and the normal detach case so it needs
1813 * to be careful about only freeing resources that have actually been
1820 struct sk_if_softc *sc_if;
1823 sc_if = device_get_softc(dev);
1824 KASSERT(mtx_initialized(&sc_if->sk_softc->sk_mtx),
1825 ("sk mutex not initialized in sk_detach"));
1828 ifp = sc_if->sk_ifp;
1829 /* These should only be active if attach_xmac succeeded */
1830 if (device_is_attached(dev)) {
1832 /* Can't hold locks while calling detach */
1833 SK_IF_UNLOCK(sc_if);
1834 callout_drain(&sc_if->sk_tick_ch);
1835 callout_drain(&sc_if->sk_watchdog_ch);
1836 ether_ifdetach(ifp);
1842 * We're generally called from skc_detach() which is using
1843 * device_delete_child() to get to here. It's already trashed
1844 * miibus for us, so don't do it here or we'll panic.
1847 if (sc_if->sk_miibus != NULL)
1848 device_delete_child(dev, sc_if->sk_miibus);
1850 bus_generic_detach(dev);
1851 sk_dma_jumbo_free(sc_if);
1853 SK_IF_UNLOCK(sc_if);
1862 struct sk_softc *sc;
1864 sc = device_get_softc(dev);
1865 KASSERT(mtx_initialized(&sc->sk_mtx), ("sk mutex not initialized"));
1867 if (device_is_alive(dev)) {
1868 if (sc->sk_devs[SK_PORT_A] != NULL) {
1869 free(device_get_ivars(sc->sk_devs[SK_PORT_A]), M_DEVBUF);
1870 device_delete_child(dev, sc->sk_devs[SK_PORT_A]);
1872 if (sc->sk_devs[SK_PORT_B] != NULL) {
1873 free(device_get_ivars(sc->sk_devs[SK_PORT_B]), M_DEVBUF);
1874 device_delete_child(dev, sc->sk_devs[SK_PORT_B]);
1876 bus_generic_detach(dev);
1879 if (sc->sk_intrhand)
1880 bus_teardown_intr(dev, sc->sk_res[1], sc->sk_intrhand);
1881 bus_release_resources(dev, sc->sk_res_spec, sc->sk_res);
1883 mtx_destroy(&sc->sk_mii_mtx);
1884 mtx_destroy(&sc->sk_mtx);
1889 static bus_dma_tag_t
1890 skc_get_dma_tag(device_t bus, device_t child __unused)
1893 return (bus_get_dma_tag(bus));
1896 struct sk_dmamap_arg {
1897 bus_addr_t sk_busaddr;
1901 sk_dmamap_cb(arg, segs, nseg, error)
1903 bus_dma_segment_t *segs;
1907 struct sk_dmamap_arg *ctx;
1913 ctx->sk_busaddr = segs[0].ds_addr;
1917 * Allocate jumbo buffer storage. The SysKonnect adapters support
1918 * "jumbograms" (9K frames), although SysKonnect doesn't currently
1919 * use them in their drivers. In order for us to use them, we need
1920 * large 9K receive buffers, however standard mbuf clusters are only
1921 * 2048 bytes in size. Consequently, we need to allocate and manage
1922 * our own jumbo buffer pool. Fortunately, this does not require an
1923 * excessive amount of additional code.
1927 struct sk_if_softc *sc_if;
1929 struct sk_dmamap_arg ctx;
1930 struct sk_txdesc *txd;
1931 struct sk_rxdesc *rxd;
1934 /* create parent tag */
1937 * This driver should use BUS_SPACE_MAXADDR for lowaddr argument
1938 * in bus_dma_tag_create(9) as the NIC would support DAC mode.
1939 * However bz@ reported that it does not work on amd64 with > 4GB
1940 * RAM. Until we have more clues of the breakage, disable DAC mode
1941 * by limiting DMA address to be in 32bit address space.
1943 error = bus_dma_tag_create(
1944 bus_get_dma_tag(sc_if->sk_if_dev),/* parent */
1945 1, 0, /* algnmnt, boundary */
1946 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1947 BUS_SPACE_MAXADDR, /* highaddr */
1948 NULL, NULL, /* filter, filterarg */
1949 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1951 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1953 NULL, NULL, /* lockfunc, lockarg */
1954 &sc_if->sk_cdata.sk_parent_tag);
1956 device_printf(sc_if->sk_if_dev,
1957 "failed to create parent DMA tag\n");
1961 /* create tag for Tx ring */
1962 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
1963 SK_RING_ALIGN, 0, /* algnmnt, boundary */
1964 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1965 BUS_SPACE_MAXADDR, /* highaddr */
1966 NULL, NULL, /* filter, filterarg */
1967 SK_TX_RING_SZ, /* maxsize */
1969 SK_TX_RING_SZ, /* maxsegsize */
1971 NULL, NULL, /* lockfunc, lockarg */
1972 &sc_if->sk_cdata.sk_tx_ring_tag);
1974 device_printf(sc_if->sk_if_dev,
1975 "failed to allocate Tx ring DMA tag\n");
1979 /* create tag for Rx ring */
1980 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
1981 SK_RING_ALIGN, 0, /* algnmnt, boundary */
1982 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1983 BUS_SPACE_MAXADDR, /* highaddr */
1984 NULL, NULL, /* filter, filterarg */
1985 SK_RX_RING_SZ, /* maxsize */
1987 SK_RX_RING_SZ, /* maxsegsize */
1989 NULL, NULL, /* lockfunc, lockarg */
1990 &sc_if->sk_cdata.sk_rx_ring_tag);
1992 device_printf(sc_if->sk_if_dev,
1993 "failed to allocate Rx ring DMA tag\n");
1997 /* create tag for Tx buffers */
1998 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
1999 1, 0, /* algnmnt, boundary */
2000 BUS_SPACE_MAXADDR, /* lowaddr */
2001 BUS_SPACE_MAXADDR, /* highaddr */
2002 NULL, NULL, /* filter, filterarg */
2003 MCLBYTES * SK_MAXTXSEGS, /* maxsize */
2004 SK_MAXTXSEGS, /* nsegments */
2005 MCLBYTES, /* maxsegsize */
2007 NULL, NULL, /* lockfunc, lockarg */
2008 &sc_if->sk_cdata.sk_tx_tag);
2010 device_printf(sc_if->sk_if_dev,
2011 "failed to allocate Tx DMA tag\n");
2015 /* create tag for Rx buffers */
2016 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2017 1, 0, /* algnmnt, boundary */
2018 BUS_SPACE_MAXADDR, /* lowaddr */
2019 BUS_SPACE_MAXADDR, /* highaddr */
2020 NULL, NULL, /* filter, filterarg */
2021 MCLBYTES, /* maxsize */
2023 MCLBYTES, /* maxsegsize */
2025 NULL, NULL, /* lockfunc, lockarg */
2026 &sc_if->sk_cdata.sk_rx_tag);
2028 device_printf(sc_if->sk_if_dev,
2029 "failed to allocate Rx DMA tag\n");
2033 /* allocate DMA'able memory and load the DMA map for Tx ring */
2034 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_tx_ring_tag,
2035 (void **)&sc_if->sk_rdata.sk_tx_ring, BUS_DMA_NOWAIT |
2036 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->sk_cdata.sk_tx_ring_map);
2038 device_printf(sc_if->sk_if_dev,
2039 "failed to allocate DMA'able memory for Tx ring\n");
2044 error = bus_dmamap_load(sc_if->sk_cdata.sk_tx_ring_tag,
2045 sc_if->sk_cdata.sk_tx_ring_map, sc_if->sk_rdata.sk_tx_ring,
2046 SK_TX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
2048 device_printf(sc_if->sk_if_dev,
2049 "failed to load DMA'able memory for Tx ring\n");
2052 sc_if->sk_rdata.sk_tx_ring_paddr = ctx.sk_busaddr;
2054 /* allocate DMA'able memory and load the DMA map for Rx ring */
2055 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_rx_ring_tag,
2056 (void **)&sc_if->sk_rdata.sk_rx_ring, BUS_DMA_NOWAIT |
2057 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->sk_cdata.sk_rx_ring_map);
2059 device_printf(sc_if->sk_if_dev,
2060 "failed to allocate DMA'able memory for Rx ring\n");
2065 error = bus_dmamap_load(sc_if->sk_cdata.sk_rx_ring_tag,
2066 sc_if->sk_cdata.sk_rx_ring_map, sc_if->sk_rdata.sk_rx_ring,
2067 SK_RX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
2069 device_printf(sc_if->sk_if_dev,
2070 "failed to load DMA'able memory for Rx ring\n");
2073 sc_if->sk_rdata.sk_rx_ring_paddr = ctx.sk_busaddr;
2075 /* create DMA maps for Tx buffers */
2076 for (i = 0; i < SK_TX_RING_CNT; i++) {
2077 txd = &sc_if->sk_cdata.sk_txdesc[i];
2079 txd->tx_dmamap = NULL;
2080 error = bus_dmamap_create(sc_if->sk_cdata.sk_tx_tag, 0,
2083 device_printf(sc_if->sk_if_dev,
2084 "failed to create Tx dmamap\n");
2089 /* create DMA maps for Rx buffers */
2090 if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0,
2091 &sc_if->sk_cdata.sk_rx_sparemap)) != 0) {
2092 device_printf(sc_if->sk_if_dev,
2093 "failed to create spare Rx dmamap\n");
2096 for (i = 0; i < SK_RX_RING_CNT; i++) {
2097 rxd = &sc_if->sk_cdata.sk_rxdesc[i];
2099 rxd->rx_dmamap = NULL;
2100 error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0,
2103 device_printf(sc_if->sk_if_dev,
2104 "failed to create Rx dmamap\n");
2114 sk_dma_jumbo_alloc(sc_if)
2115 struct sk_if_softc *sc_if;
2117 struct sk_dmamap_arg ctx;
2118 struct sk_rxdesc *jrxd;
2121 if (jumbo_disable != 0) {
2122 device_printf(sc_if->sk_if_dev, "disabling jumbo frame support\n");
2123 sc_if->sk_jumbo_disable = 1;
2126 /* create tag for jumbo Rx ring */
2127 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2128 SK_RING_ALIGN, 0, /* algnmnt, boundary */
2129 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
2130 BUS_SPACE_MAXADDR, /* highaddr */
2131 NULL, NULL, /* filter, filterarg */
2132 SK_JUMBO_RX_RING_SZ, /* maxsize */
2134 SK_JUMBO_RX_RING_SZ, /* maxsegsize */
2136 NULL, NULL, /* lockfunc, lockarg */
2137 &sc_if->sk_cdata.sk_jumbo_rx_ring_tag);
2139 device_printf(sc_if->sk_if_dev,
2140 "failed to allocate jumbo Rx ring DMA tag\n");
2144 /* create tag for jumbo Rx buffers */
2145 error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2146 1, 0, /* algnmnt, boundary */
2147 BUS_SPACE_MAXADDR, /* lowaddr */
2148 BUS_SPACE_MAXADDR, /* highaddr */
2149 NULL, NULL, /* filter, filterarg */
2150 MJUM9BYTES, /* maxsize */
2152 MJUM9BYTES, /* maxsegsize */
2154 NULL, NULL, /* lockfunc, lockarg */
2155 &sc_if->sk_cdata.sk_jumbo_rx_tag);
2157 device_printf(sc_if->sk_if_dev,
2158 "failed to allocate jumbo Rx DMA tag\n");
2162 /* allocate DMA'able memory and load the DMA map for jumbo Rx ring */
2163 error = bus_dmamem_alloc(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2164 (void **)&sc_if->sk_rdata.sk_jumbo_rx_ring, BUS_DMA_NOWAIT |
2165 BUS_DMA_COHERENT | BUS_DMA_ZERO,
2166 &sc_if->sk_cdata.sk_jumbo_rx_ring_map);
2168 device_printf(sc_if->sk_if_dev,
2169 "failed to allocate DMA'able memory for jumbo Rx ring\n");
2174 error = bus_dmamap_load(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2175 sc_if->sk_cdata.sk_jumbo_rx_ring_map,
2176 sc_if->sk_rdata.sk_jumbo_rx_ring, SK_JUMBO_RX_RING_SZ, sk_dmamap_cb,
2177 &ctx, BUS_DMA_NOWAIT);
2179 device_printf(sc_if->sk_if_dev,
2180 "failed to load DMA'able memory for jumbo Rx ring\n");
2183 sc_if->sk_rdata.sk_jumbo_rx_ring_paddr = ctx.sk_busaddr;
2185 /* create DMA maps for jumbo Rx buffers */
2186 if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0,
2187 &sc_if->sk_cdata.sk_jumbo_rx_sparemap)) != 0) {
2188 device_printf(sc_if->sk_if_dev,
2189 "failed to create spare jumbo Rx dmamap\n");
2192 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
2193 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i];
2195 jrxd->rx_dmamap = NULL;
2196 error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0,
2199 device_printf(sc_if->sk_if_dev,
2200 "failed to create jumbo Rx dmamap\n");
2208 sk_dma_jumbo_free(sc_if);
2209 device_printf(sc_if->sk_if_dev, "disabling jumbo frame support due to "
2210 "resource shortage\n");
2211 sc_if->sk_jumbo_disable = 1;
2217 struct sk_if_softc *sc_if;
2219 struct sk_txdesc *txd;
2220 struct sk_rxdesc *rxd;
2224 if (sc_if->sk_cdata.sk_tx_ring_tag) {
2225 if (sc_if->sk_cdata.sk_tx_ring_map)
2226 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_ring_tag,
2227 sc_if->sk_cdata.sk_tx_ring_map);
2228 if (sc_if->sk_cdata.sk_tx_ring_map &&
2229 sc_if->sk_rdata.sk_tx_ring)
2230 bus_dmamem_free(sc_if->sk_cdata.sk_tx_ring_tag,
2231 sc_if->sk_rdata.sk_tx_ring,
2232 sc_if->sk_cdata.sk_tx_ring_map);
2233 sc_if->sk_rdata.sk_tx_ring = NULL;
2234 sc_if->sk_cdata.sk_tx_ring_map = NULL;
2235 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_ring_tag);
2236 sc_if->sk_cdata.sk_tx_ring_tag = NULL;
2239 if (sc_if->sk_cdata.sk_rx_ring_tag) {
2240 if (sc_if->sk_cdata.sk_rx_ring_map)
2241 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_ring_tag,
2242 sc_if->sk_cdata.sk_rx_ring_map);
2243 if (sc_if->sk_cdata.sk_rx_ring_map &&
2244 sc_if->sk_rdata.sk_rx_ring)
2245 bus_dmamem_free(sc_if->sk_cdata.sk_rx_ring_tag,
2246 sc_if->sk_rdata.sk_rx_ring,
2247 sc_if->sk_cdata.sk_rx_ring_map);
2248 sc_if->sk_rdata.sk_rx_ring = NULL;
2249 sc_if->sk_cdata.sk_rx_ring_map = NULL;
2250 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_ring_tag);
2251 sc_if->sk_cdata.sk_rx_ring_tag = NULL;
2254 if (sc_if->sk_cdata.sk_tx_tag) {
2255 for (i = 0; i < SK_TX_RING_CNT; i++) {
2256 txd = &sc_if->sk_cdata.sk_txdesc[i];
2257 if (txd->tx_dmamap) {
2258 bus_dmamap_destroy(sc_if->sk_cdata.sk_tx_tag,
2260 txd->tx_dmamap = NULL;
2263 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_tag);
2264 sc_if->sk_cdata.sk_tx_tag = NULL;
2267 if (sc_if->sk_cdata.sk_rx_tag) {
2268 for (i = 0; i < SK_RX_RING_CNT; i++) {
2269 rxd = &sc_if->sk_cdata.sk_rxdesc[i];
2270 if (rxd->rx_dmamap) {
2271 bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag,
2273 rxd->rx_dmamap = NULL;
2276 if (sc_if->sk_cdata.sk_rx_sparemap) {
2277 bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag,
2278 sc_if->sk_cdata.sk_rx_sparemap);
2279 sc_if->sk_cdata.sk_rx_sparemap = NULL;
2281 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_tag);
2282 sc_if->sk_cdata.sk_rx_tag = NULL;
2285 if (sc_if->sk_cdata.sk_parent_tag) {
2286 bus_dma_tag_destroy(sc_if->sk_cdata.sk_parent_tag);
2287 sc_if->sk_cdata.sk_parent_tag = NULL;
2292 sk_dma_jumbo_free(sc_if)
2293 struct sk_if_softc *sc_if;
2295 struct sk_rxdesc *jrxd;
2299 if (sc_if->sk_cdata.sk_jumbo_rx_ring_tag) {
2300 if (sc_if->sk_cdata.sk_jumbo_rx_ring_map)
2301 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2302 sc_if->sk_cdata.sk_jumbo_rx_ring_map);
2303 if (sc_if->sk_cdata.sk_jumbo_rx_ring_map &&
2304 sc_if->sk_rdata.sk_jumbo_rx_ring)
2305 bus_dmamem_free(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2306 sc_if->sk_rdata.sk_jumbo_rx_ring,
2307 sc_if->sk_cdata.sk_jumbo_rx_ring_map);
2308 sc_if->sk_rdata.sk_jumbo_rx_ring = NULL;
2309 sc_if->sk_cdata.sk_jumbo_rx_ring_map = NULL;
2310 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_ring_tag);
2311 sc_if->sk_cdata.sk_jumbo_rx_ring_tag = NULL;
2314 /* jumbo Rx buffers */
2315 if (sc_if->sk_cdata.sk_jumbo_rx_tag) {
2316 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
2317 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i];
2318 if (jrxd->rx_dmamap) {
2320 sc_if->sk_cdata.sk_jumbo_rx_tag,
2322 jrxd->rx_dmamap = NULL;
2325 if (sc_if->sk_cdata.sk_jumbo_rx_sparemap) {
2326 bus_dmamap_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag,
2327 sc_if->sk_cdata.sk_jumbo_rx_sparemap);
2328 sc_if->sk_cdata.sk_jumbo_rx_sparemap = NULL;
2330 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag);
2331 sc_if->sk_cdata.sk_jumbo_rx_tag = NULL;
2336 sk_txcksum(ifp, m, f)
2339 struct sk_tx_desc *f;
2345 offset = sizeof(struct ip) + ETHER_HDR_LEN;
2346 for(; m && m->m_len == 0; m = m->m_next)
2348 if (m == NULL || m->m_len < ETHER_HDR_LEN) {
2349 if_printf(ifp, "%s: m_len < ETHER_HDR_LEN\n", __func__);
2350 /* checksum may be corrupted */
2353 if (m->m_len < ETHER_HDR_LEN + sizeof(u_int32_t)) {
2354 if (m->m_len != ETHER_HDR_LEN) {
2355 if_printf(ifp, "%s: m_len != ETHER_HDR_LEN\n",
2357 /* checksum may be corrupted */
2360 for(m = m->m_next; m && m->m_len == 0; m = m->m_next)
2363 offset = sizeof(struct ip) + ETHER_HDR_LEN;
2364 /* checksum may be corrupted */
2367 ip = mtod(m, struct ip *);
2369 p = mtod(m, u_int8_t *);
2371 ip = (struct ip *)p;
2373 offset = (ip->ip_hl << 2) + ETHER_HDR_LEN;
2376 f->sk_csum_startval = 0;
2377 f->sk_csum_start = htole32(((offset + m->m_pkthdr.csum_data) & 0xffff) |
2382 sk_encap(sc_if, m_head)
2383 struct sk_if_softc *sc_if;
2384 struct mbuf **m_head;
2386 struct sk_txdesc *txd;
2387 struct sk_tx_desc *f = NULL;
2389 bus_dma_segment_t txsegs[SK_MAXTXSEGS];
2390 u_int32_t cflags, frag, si, sk_ctl;
2393 SK_IF_LOCK_ASSERT(sc_if);
2395 if ((txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txfreeq)) == NULL)
2398 error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag,
2399 txd->tx_dmamap, *m_head, txsegs, &nseg, 0);
2400 if (error == EFBIG) {
2401 m = m_defrag(*m_head, M_NOWAIT);
2408 error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag,
2409 txd->tx_dmamap, *m_head, txsegs, &nseg, 0);
2415 } else if (error != 0)
2422 if (sc_if->sk_cdata.sk_tx_cnt + nseg >= SK_TX_RING_CNT) {
2423 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap);
2428 if ((m->m_pkthdr.csum_flags & sc_if->sk_ifp->if_hwassist) != 0)
2429 cflags = SK_OPCODE_CSUM;
2431 cflags = SK_OPCODE_DEFAULT;
2432 si = frag = sc_if->sk_cdata.sk_tx_prod;
2433 for (i = 0; i < nseg; i++) {
2434 f = &sc_if->sk_rdata.sk_tx_ring[frag];
2435 f->sk_data_lo = htole32(SK_ADDR_LO(txsegs[i].ds_addr));
2436 f->sk_data_hi = htole32(SK_ADDR_HI(txsegs[i].ds_addr));
2437 sk_ctl = txsegs[i].ds_len | cflags;
2439 if (cflags == SK_OPCODE_CSUM)
2440 sk_txcksum(sc_if->sk_ifp, m, f);
2441 sk_ctl |= SK_TXCTL_FIRSTFRAG;
2443 sk_ctl |= SK_TXCTL_OWN;
2444 f->sk_ctl = htole32(sk_ctl);
2445 sc_if->sk_cdata.sk_tx_cnt++;
2446 SK_INC(frag, SK_TX_RING_CNT);
2448 sc_if->sk_cdata.sk_tx_prod = frag;
2450 /* set EOF on the last desciptor */
2451 frag = (frag + SK_TX_RING_CNT - 1) % SK_TX_RING_CNT;
2452 f = &sc_if->sk_rdata.sk_tx_ring[frag];
2453 f->sk_ctl |= htole32(SK_TXCTL_LASTFRAG | SK_TXCTL_EOF_INTR);
2455 /* turn the first descriptor ownership to NIC */
2456 f = &sc_if->sk_rdata.sk_tx_ring[si];
2457 f->sk_ctl |= htole32(SK_TXCTL_OWN);
2459 STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txfreeq, tx_q);
2460 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txbusyq, txd, tx_q);
2463 /* sync descriptors */
2464 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap,
2465 BUS_DMASYNC_PREWRITE);
2466 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
2467 sc_if->sk_cdata.sk_tx_ring_map,
2468 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2477 struct sk_if_softc *sc_if;
2479 sc_if = ifp->if_softc;
2482 sk_start_locked(ifp);
2483 SK_IF_UNLOCK(sc_if);
2489 sk_start_locked(ifp)
2492 struct sk_softc *sc;
2493 struct sk_if_softc *sc_if;
2494 struct mbuf *m_head;
2497 sc_if = ifp->if_softc;
2498 sc = sc_if->sk_softc;
2500 SK_IF_LOCK_ASSERT(sc_if);
2502 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2503 sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 1; ) {
2504 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2509 * Pack the data into the transmit ring. If we
2510 * don't have room, set the OACTIVE flag and wait
2511 * for the NIC to drain the ring.
2513 if (sk_encap(sc_if, &m_head)) {
2516 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2517 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2523 * If there's a BPF listener, bounce a copy of this frame
2526 BPF_MTAP(ifp, m_head);
2531 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
2533 /* Set a timeout in case the chip goes out to lunch. */
2534 sc_if->sk_watchdog_timer = 5;
2543 struct sk_if_softc *sc_if;
2547 sc_if = ifp->if_softc;
2549 SK_IF_LOCK_ASSERT(sc_if);
2551 if (sc_if->sk_watchdog_timer == 0 || --sc_if->sk_watchdog_timer)
2555 * Reclaim first as there is a possibility of losing Tx completion
2559 if (sc_if->sk_cdata.sk_tx_cnt != 0) {
2560 if_printf(sc_if->sk_ifp, "watchdog timeout\n");
2562 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2563 sk_init_locked(sc_if);
2567 callout_reset(&sc_if->sk_watchdog_ch, hz, sk_watchdog, ifp);
2576 struct sk_softc *sc;
2578 sc = device_get_softc(dev);
2581 /* Turn off the 'driver is loaded' LED. */
2582 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
2585 * Reset the GEnesis controller. Doing this should also
2586 * assert the resets on the attached XMAC(s).
2598 struct sk_softc *sc;
2599 struct sk_if_softc *sc_if0, *sc_if1;
2600 struct ifnet *ifp0 = NULL, *ifp1 = NULL;
2602 sc = device_get_softc(dev);
2606 sc_if0 = sc->sk_if[SK_PORT_A];
2607 sc_if1 = sc->sk_if[SK_PORT_B];
2609 ifp0 = sc_if0->sk_ifp;
2611 ifp1 = sc_if1->sk_ifp;
2616 sc->sk_suspended = 1;
2627 struct sk_softc *sc;
2628 struct sk_if_softc *sc_if0, *sc_if1;
2629 struct ifnet *ifp0 = NULL, *ifp1 = NULL;
2631 sc = device_get_softc(dev);
2635 sc_if0 = sc->sk_if[SK_PORT_A];
2636 sc_if1 = sc->sk_if[SK_PORT_B];
2638 ifp0 = sc_if0->sk_ifp;
2640 ifp1 = sc_if1->sk_ifp;
2641 if (ifp0 != NULL && ifp0->if_flags & IFF_UP)
2642 sk_init_locked(sc_if0);
2643 if (ifp1 != NULL && ifp1->if_flags & IFF_UP)
2644 sk_init_locked(sc_if1);
2645 sc->sk_suspended = 0;
2653 * According to the data sheet from SK-NET GENESIS the hardware can compute
2654 * two Rx checksums at the same time(Each checksum start position is
2655 * programmed in Rx descriptors). However it seems that TCP/UDP checksum
2656 * does not work at least on my Yukon hardware. I tried every possible ways
2657 * to get correct checksum value but couldn't get correct one. So TCP/UDP
2658 * checksum offload was disabled at the moment and only IP checksum offload
2660 * As nomral IP header size is 20 bytes I can't expect it would give an
2661 * increase in throughput. However it seems it doesn't hurt performance in
2662 * my testing. If there is a more detailed information for checksum secret
2663 * of the hardware in question please contact yongari@FreeBSD.org to add
2664 * TCP/UDP checksum offload support.
2666 static __inline void
2667 sk_rxcksum(ifp, m, csum)
2672 struct ether_header *eh;
2674 int32_t hlen, len, pktlen;
2675 u_int16_t csum1, csum2, ipcsum;
2677 pktlen = m->m_pkthdr.len;
2678 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip))
2680 eh = mtod(m, struct ether_header *);
2681 if (eh->ether_type != htons(ETHERTYPE_IP))
2683 ip = (struct ip *)(eh + 1);
2684 if (ip->ip_v != IPVERSION)
2686 hlen = ip->ip_hl << 2;
2687 pktlen -= sizeof(struct ether_header);
2688 if (hlen < sizeof(struct ip))
2690 if (ntohs(ip->ip_len) < hlen)
2692 if (ntohs(ip->ip_len) != pktlen)
2695 csum1 = htons(csum & 0xffff);
2696 csum2 = htons((csum >> 16) & 0xffff);
2697 ipcsum = in_addword(csum1, ~csum2 & 0xffff);
2698 /* checksum fixup for IP options */
2699 len = hlen - sizeof(struct ip);
2702 * If the second checksum value is correct we can compute IP
2703 * checksum with simple math. Unfortunately the second checksum
2704 * value is wrong so we can't verify the checksum from the
2705 * value(It seems there is some magic here to get correct
2706 * value). If the second checksum value is correct it also
2707 * means we can get TCP/UDP checksum) here. However, it still
2708 * needs pseudo header checksum calculation due to hardware
2713 m->m_pkthdr.csum_flags = CSUM_IP_CHECKED;
2714 if (ipcsum == 0xffff)
2715 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2719 sk_rxvalid(sc, stat, len)
2720 struct sk_softc *sc;
2721 u_int32_t stat, len;
2724 if (sc->sk_type == SK_GENESIS) {
2725 if ((stat & XM_RXSTAT_ERRFRAME) == XM_RXSTAT_ERRFRAME ||
2726 XM_RXSTAT_BYTES(stat) != len)
2729 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR |
2730 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC |
2731 YU_RXSTAT_JABBER)) != 0 ||
2732 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK ||
2733 YU_RXSTAT_BYTES(stat) != len)
2742 struct sk_if_softc *sc_if;
2744 struct sk_softc *sc;
2747 struct sk_rx_desc *cur_rx;
2748 struct sk_rxdesc *rxd;
2750 u_int32_t csum, rxstat, sk_ctl;
2752 sc = sc_if->sk_softc;
2753 ifp = sc_if->sk_ifp;
2755 SK_IF_LOCK_ASSERT(sc_if);
2757 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag,
2758 sc_if->sk_cdata.sk_rx_ring_map, BUS_DMASYNC_POSTREAD);
2761 for (cons = sc_if->sk_cdata.sk_rx_cons; prog < SK_RX_RING_CNT;
2762 prog++, SK_INC(cons, SK_RX_RING_CNT)) {
2763 cur_rx = &sc_if->sk_rdata.sk_rx_ring[cons];
2764 sk_ctl = le32toh(cur_rx->sk_ctl);
2765 if ((sk_ctl & SK_RXCTL_OWN) != 0)
2767 rxd = &sc_if->sk_cdata.sk_rxdesc[cons];
2768 rxstat = le32toh(cur_rx->sk_xmac_rxstat);
2770 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG |
2771 SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID |
2772 SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) ||
2773 SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN ||
2774 SK_RXBYTES(sk_ctl) > SK_MAX_FRAMELEN ||
2775 sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) {
2777 sk_discard_rxbuf(sc_if, cons);
2782 csum = le32toh(cur_rx->sk_csum);
2783 if (sk_newbuf(sc_if, cons) != 0) {
2785 /* reuse old buffer */
2786 sk_discard_rxbuf(sc_if, cons);
2789 m->m_pkthdr.rcvif = ifp;
2790 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl);
2792 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
2793 sk_rxcksum(ifp, m, csum);
2794 SK_IF_UNLOCK(sc_if);
2795 (*ifp->if_input)(ifp, m);
2800 sc_if->sk_cdata.sk_rx_cons = cons;
2801 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag,
2802 sc_if->sk_cdata.sk_rx_ring_map,
2803 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2808 sk_jumbo_rxeof(sc_if)
2809 struct sk_if_softc *sc_if;
2811 struct sk_softc *sc;
2814 struct sk_rx_desc *cur_rx;
2815 struct sk_rxdesc *jrxd;
2817 u_int32_t csum, rxstat, sk_ctl;
2819 sc = sc_if->sk_softc;
2820 ifp = sc_if->sk_ifp;
2822 SK_IF_LOCK_ASSERT(sc_if);
2824 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2825 sc_if->sk_cdata.sk_jumbo_rx_ring_map, BUS_DMASYNC_POSTREAD);
2828 for (cons = sc_if->sk_cdata.sk_jumbo_rx_cons;
2829 prog < SK_JUMBO_RX_RING_CNT;
2830 prog++, SK_INC(cons, SK_JUMBO_RX_RING_CNT)) {
2831 cur_rx = &sc_if->sk_rdata.sk_jumbo_rx_ring[cons];
2832 sk_ctl = le32toh(cur_rx->sk_ctl);
2833 if ((sk_ctl & SK_RXCTL_OWN) != 0)
2835 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[cons];
2836 rxstat = le32toh(cur_rx->sk_xmac_rxstat);
2838 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG |
2839 SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID |
2840 SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) ||
2841 SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN ||
2842 SK_RXBYTES(sk_ctl) > SK_JUMBO_FRAMELEN ||
2843 sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) {
2845 sk_discard_jumbo_rxbuf(sc_if, cons);
2850 csum = le32toh(cur_rx->sk_csum);
2851 if (sk_jumbo_newbuf(sc_if, cons) != 0) {
2853 /* reuse old buffer */
2854 sk_discard_jumbo_rxbuf(sc_if, cons);
2857 m->m_pkthdr.rcvif = ifp;
2858 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl);
2860 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
2861 sk_rxcksum(ifp, m, csum);
2862 SK_IF_UNLOCK(sc_if);
2863 (*ifp->if_input)(ifp, m);
2868 sc_if->sk_cdata.sk_jumbo_rx_cons = cons;
2869 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2870 sc_if->sk_cdata.sk_jumbo_rx_ring_map,
2871 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2877 struct sk_if_softc *sc_if;
2879 struct sk_txdesc *txd;
2880 struct sk_tx_desc *cur_tx;
2882 u_int32_t idx, sk_ctl;
2884 ifp = sc_if->sk_ifp;
2886 txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq);
2889 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
2890 sc_if->sk_cdata.sk_tx_ring_map, BUS_DMASYNC_POSTREAD);
2892 * Go through our tx ring and free mbufs for those
2893 * frames that have been sent.
2895 for (idx = sc_if->sk_cdata.sk_tx_cons;; SK_INC(idx, SK_TX_RING_CNT)) {
2896 if (sc_if->sk_cdata.sk_tx_cnt <= 0)
2898 cur_tx = &sc_if->sk_rdata.sk_tx_ring[idx];
2899 sk_ctl = le32toh(cur_tx->sk_ctl);
2900 if (sk_ctl & SK_TXCTL_OWN)
2902 sc_if->sk_cdata.sk_tx_cnt--;
2903 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2904 if ((sk_ctl & SK_TXCTL_LASTFRAG) == 0)
2906 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap,
2907 BUS_DMASYNC_POSTWRITE);
2908 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap);
2913 STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txbusyq, tx_q);
2914 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q);
2915 txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq);
2917 sc_if->sk_cdata.sk_tx_cons = idx;
2918 sc_if->sk_watchdog_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0;
2920 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
2921 sc_if->sk_cdata.sk_tx_ring_map,
2922 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2929 struct sk_if_softc *sc_if;
2930 struct mii_data *mii;
2935 ifp = sc_if->sk_ifp;
2936 mii = device_get_softc(sc_if->sk_miibus);
2938 if (!(ifp->if_flags & IFF_UP))
2941 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2942 sk_intr_bcom(sc_if);
2947 * According to SysKonnect, the correct way to verify that
2948 * the link has come back up is to poll bit 0 of the GPIO
2949 * register three times. This pin has the signal from the
2950 * link_sync pin connected to it; if we read the same link
2951 * state 3 times in a row, we know the link is up.
2953 for (i = 0; i < 3; i++) {
2954 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET)
2959 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
2963 /* Turn the GP0 interrupt back on. */
2964 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2965 SK_XM_READ_2(sc_if, XM_ISR);
2967 callout_stop(&sc_if->sk_tick_ch);
2971 sk_yukon_tick(xsc_if)
2974 struct sk_if_softc *sc_if;
2975 struct mii_data *mii;
2978 mii = device_get_softc(sc_if->sk_miibus);
2981 callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if);
2986 struct sk_if_softc *sc_if;
2988 struct mii_data *mii;
2991 mii = device_get_softc(sc_if->sk_miibus);
2992 ifp = sc_if->sk_ifp;
2994 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2997 * Read the PHY interrupt register to make sure
2998 * we clear any pending interrupts.
3000 status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR);
3002 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3003 sk_init_xmac(sc_if);
3007 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) {
3009 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM,
3012 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) {
3014 /* Turn off the link LED. */
3015 SK_IF_WRITE_1(sc_if, 0,
3016 SK_LINKLED1_CTL, SK_LINKLED_OFF);
3018 } else if (status & BRGPHY_ISR_LNK_CHG) {
3019 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3020 BRGPHY_MII_IMR, 0xFF00);
3023 /* Turn on the link LED. */
3024 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
3025 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF|
3026 SK_LINKLED_BLINK_OFF);
3029 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
3033 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
3040 struct sk_if_softc *sc_if;
3042 struct sk_softc *sc;
3045 sc = sc_if->sk_softc;
3046 status = SK_XM_READ_2(sc_if, XM_ISR);
3049 * Link has gone down. Start MII tick timeout to
3050 * watch for link resync.
3052 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) {
3053 if (status & XM_ISR_GP0_SET) {
3054 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
3055 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
3058 if (status & XM_ISR_AUTONEG_DONE) {
3059 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
3063 if (status & XM_IMR_TX_UNDERRUN)
3064 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO);
3066 if (status & XM_IMR_RX_OVERRUN)
3067 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO);
3069 status = SK_XM_READ_2(sc_if, XM_ISR);
3075 sk_intr_yukon(sc_if)
3076 struct sk_if_softc *sc_if;
3080 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR);
3082 if ((status & SK_GMAC_INT_RX_OVER) != 0) {
3083 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
3084 SK_RFCTL_RX_FIFO_OVER);
3087 if ((status & SK_GMAC_INT_TX_UNDER) != 0) {
3088 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
3089 SK_TFCTL_TX_FIFO_UNDER);
3097 struct sk_softc *sc = xsc;
3098 struct sk_if_softc *sc_if0, *sc_if1;
3099 struct ifnet *ifp0 = NULL, *ifp1 = NULL;
3104 status = CSR_READ_4(sc, SK_ISSR);
3105 if (status == 0 || status == 0xffffffff || sc->sk_suspended)
3108 sc_if0 = sc->sk_if[SK_PORT_A];
3109 sc_if1 = sc->sk_if[SK_PORT_B];
3112 ifp0 = sc_if0->sk_ifp;
3114 ifp1 = sc_if1->sk_ifp;
3116 for (; (status &= sc->sk_intrmask) != 0;) {
3117 /* Handle receive interrupts first. */
3118 if (status & SK_ISR_RX1_EOF) {
3119 if (ifp0->if_mtu > SK_MAX_FRAMELEN)
3120 sk_jumbo_rxeof(sc_if0);
3123 CSR_WRITE_4(sc, SK_BMU_RX_CSR0,
3124 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
3126 if (status & SK_ISR_RX2_EOF) {
3127 if (ifp1->if_mtu > SK_MAX_FRAMELEN)
3128 sk_jumbo_rxeof(sc_if1);
3131 CSR_WRITE_4(sc, SK_BMU_RX_CSR1,
3132 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
3135 /* Then transmit interrupts. */
3136 if (status & SK_ISR_TX1_S_EOF) {
3138 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, SK_TXBMU_CLR_IRQ_EOF);
3140 if (status & SK_ISR_TX2_S_EOF) {
3142 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, SK_TXBMU_CLR_IRQ_EOF);
3145 /* Then MAC interrupts. */
3146 if (status & SK_ISR_MAC1 &&
3147 ifp0->if_drv_flags & IFF_DRV_RUNNING) {
3148 if (sc->sk_type == SK_GENESIS)
3149 sk_intr_xmac(sc_if0);
3151 sk_intr_yukon(sc_if0);
3154 if (status & SK_ISR_MAC2 &&
3155 ifp1->if_drv_flags & IFF_DRV_RUNNING) {
3156 if (sc->sk_type == SK_GENESIS)
3157 sk_intr_xmac(sc_if1);
3159 sk_intr_yukon(sc_if1);
3162 if (status & SK_ISR_EXTERNAL_REG) {
3164 sc_if0->sk_phytype == SK_PHYTYPE_BCOM)
3165 sk_intr_bcom(sc_if0);
3167 sc_if1->sk_phytype == SK_PHYTYPE_BCOM)
3168 sk_intr_bcom(sc_if1);
3170 status = CSR_READ_4(sc, SK_ISSR);
3173 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
3175 if (ifp0 != NULL && !IFQ_DRV_IS_EMPTY(&ifp0->if_snd))
3176 sk_start_locked(ifp0);
3177 if (ifp1 != NULL && !IFQ_DRV_IS_EMPTY(&ifp1->if_snd))
3178 sk_start_locked(ifp1);
3186 struct sk_if_softc *sc_if;
3188 struct sk_softc *sc;
3190 u_int16_t eaddr[(ETHER_ADDR_LEN+1)/2];
3191 static const struct sk_bcom_hack bhack[] = {
3192 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 },
3193 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 },
3194 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
3197 SK_IF_LOCK_ASSERT(sc_if);
3199 sc = sc_if->sk_softc;
3200 ifp = sc_if->sk_ifp;
3202 /* Unreset the XMAC. */
3203 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET);
3206 /* Reset the XMAC's internal state. */
3207 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
3209 /* Save the XMAC II revision */
3210 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID));
3213 * Perform additional initialization for external PHYs,
3214 * namely for the 1000baseTX cards that use the XMAC's
3217 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
3221 /* Take PHY out of reset. */
3222 val = sk_win_read_4(sc, SK_GPIO);
3223 if (sc_if->sk_port == SK_PORT_A)
3224 val |= SK_GPIO_DIR0|SK_GPIO_DAT0;
3226 val |= SK_GPIO_DIR2|SK_GPIO_DAT2;
3227 sk_win_write_4(sc, SK_GPIO, val);
3229 /* Enable GMII mode on the XMAC. */
3230 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE);
3232 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3233 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
3235 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3236 BRGPHY_MII_IMR, 0xFFF0);
3239 * Early versions of the BCM5400 apparently have
3240 * a bug that requires them to have their reserved
3241 * registers initialized to some magic values. I don't
3242 * know what the numbers do, I'm just the messenger.
3244 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03)
3246 while(bhack[i].reg) {
3247 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3248 bhack[i].reg, bhack[i].val);
3254 /* Set station address */
3255 bcopy(IF_LLADDR(sc_if->sk_ifp), eaddr, ETHER_ADDR_LEN);
3256 SK_XM_WRITE_2(sc_if, XM_PAR0, eaddr[0]);
3257 SK_XM_WRITE_2(sc_if, XM_PAR1, eaddr[1]);
3258 SK_XM_WRITE_2(sc_if, XM_PAR2, eaddr[2]);
3259 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION);
3261 if (ifp->if_flags & IFF_BROADCAST) {
3262 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
3264 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
3267 /* We don't need the FCS appended to the packet. */
3268 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS);
3270 /* We want short frames padded to 60 bytes. */
3271 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD);
3274 * Enable the reception of all error frames. This is is
3275 * a necessary evil due to the design of the XMAC. The
3276 * XMAC's receive FIFO is only 8K in size, however jumbo
3277 * frames can be up to 9000 bytes in length. When bad
3278 * frame filtering is enabled, the XMAC's RX FIFO operates
3279 * in 'store and forward' mode. For this to work, the
3280 * entire frame has to fit into the FIFO, but that means
3281 * that jumbo frames larger than 8192 bytes will be
3282 * truncated. Disabling all bad frame filtering causes
3283 * the RX FIFO to operate in streaming mode, in which
3284 * case the XMAC will start transfering frames out of the
3285 * RX FIFO as soon as the FIFO threshold is reached.
3287 if (ifp->if_mtu > SK_MAX_FRAMELEN) {
3288 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES|
3289 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS|
3290 XM_MODE_RX_INRANGELEN);
3291 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
3293 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
3296 * Bump up the transmit threshold. This helps hold off transmit
3297 * underruns when we're blasting traffic from both ports at once.
3299 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH);
3302 sk_rxfilter_genesis(sc_if);
3304 /* Clear and enable interrupts */
3305 SK_XM_READ_2(sc_if, XM_ISR);
3306 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
3307 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS);
3309 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
3311 /* Configure MAC arbiter */
3312 switch(sc_if->sk_xmac_rev) {
3313 case XM_XMAC_REV_B2:
3314 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2);
3315 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2);
3316 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2);
3317 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2);
3318 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2);
3319 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2);
3320 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2);
3321 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2);
3322 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
3324 case XM_XMAC_REV_C1:
3325 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1);
3326 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1);
3327 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1);
3328 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1);
3329 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1);
3330 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1);
3331 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1);
3332 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1);
3333 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
3338 sk_win_write_2(sc, SK_MACARB_CTL,
3339 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF);
3347 sk_init_yukon(sc_if)
3348 struct sk_if_softc *sc_if;
3352 struct sk_softc *sc;
3357 SK_IF_LOCK_ASSERT(sc_if);
3359 sc = sc_if->sk_softc;
3360 ifp = sc_if->sk_ifp;
3362 if (sc->sk_type == SK_YUKON_LITE &&
3363 sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
3365 * Workaround code for COMA mode, set PHY reset.
3366 * Otherwise it will not correctly take chip out of
3369 v = sk_win_read_4(sc, SK_GPIO);
3370 v |= SK_GPIO_DIR9 | SK_GPIO_DAT9;
3371 sk_win_write_4(sc, SK_GPIO, v);
3374 /* GMAC and GPHY Reset */
3375 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
3376 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
3379 if (sc->sk_type == SK_YUKON_LITE &&
3380 sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
3382 * Workaround code for COMA mode, clear PHY reset
3384 v = sk_win_read_4(sc, SK_GPIO);
3387 sk_win_write_4(sc, SK_GPIO, v);
3390 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP |
3391 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE;
3393 if (sc->sk_coppertype)
3394 phy |= SK_GPHY_COPPER;
3396 phy |= SK_GPHY_FIBER;
3398 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET);
3400 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR);
3401 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF |
3402 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR);
3404 /* unused read of the interrupt source register */
3405 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
3407 reg = SK_YU_READ_2(sc_if, YUKON_PAR);
3409 /* MIB Counter Clear Mode set */
3410 reg |= YU_PAR_MIB_CLR;
3411 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
3413 /* MIB Counter Clear Mode clear */
3414 reg &= ~YU_PAR_MIB_CLR;
3415 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
3417 /* receive control reg */
3418 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR);
3420 /* transmit parameter register */
3421 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) |
3422 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) );
3424 /* serial mode register */
3425 reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e);
3426 if (ifp->if_mtu > SK_MAX_FRAMELEN)
3427 reg |= YU_SMR_MFL_JUMBO;
3428 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg);
3430 /* Setup Yukon's station address */
3431 eaddr = IF_LLADDR(sc_if->sk_ifp);
3432 for (i = 0; i < 3; i++)
3433 SK_YU_WRITE_2(sc_if, SK_MAC0_0 + i * 4,
3434 eaddr[i * 2] | eaddr[i * 2 + 1] << 8);
3435 /* Set GMAC source address of flow control. */
3436 for (i = 0; i < 3; i++)
3437 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4,
3438 eaddr[i * 2] | eaddr[i * 2 + 1] << 8);
3439 /* Set GMAC virtual address. */
3440 for (i = 0; i < 3; i++)
3441 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4,
3442 eaddr[i * 2] | eaddr[i * 2 + 1] << 8);
3445 sk_rxfilter_yukon(sc_if);
3447 /* enable interrupt mask for counter overflows */
3448 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0);
3449 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0);
3450 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0);
3452 /* Configure RX MAC FIFO Flush Mask */
3453 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR |
3454 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT |
3456 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v);
3458 /* Disable RX MAC FIFO Flush for YUKON-Lite Rev. A0 only */
3459 if (sc->sk_type == SK_YUKON_LITE && sc->sk_rev == SK_YUKON_LITE_REV_A0)
3460 v = SK_TFCTL_OPERATION_ON;
3462 v = SK_TFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON;
3463 /* Configure RX MAC FIFO */
3464 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR);
3465 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v);
3467 /* Increase flush threshould to 64 bytes */
3468 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD,
3469 SK_RFCTL_FIFO_THRESHOLD + 1);
3471 /* Configure TX MAC FIFO */
3472 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR);
3473 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON);
3477 * Note that to properly initialize any part of the GEnesis chip,
3478 * you first have to take it out of reset mode.
3484 struct sk_if_softc *sc_if = xsc;
3487 sk_init_locked(sc_if);
3488 SK_IF_UNLOCK(sc_if);
3494 sk_init_locked(sc_if)
3495 struct sk_if_softc *sc_if;
3497 struct sk_softc *sc;
3499 struct mii_data *mii;
3504 SK_IF_LOCK_ASSERT(sc_if);
3506 ifp = sc_if->sk_ifp;
3507 sc = sc_if->sk_softc;
3508 mii = device_get_softc(sc_if->sk_miibus);
3510 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3513 /* Cancel pending I/O and free all RX/TX buffers. */
3516 if (sc->sk_type == SK_GENESIS) {
3517 /* Configure LINK_SYNC LED */
3518 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON);
3519 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
3520 SK_LINKLED_LINKSYNC_ON);
3522 /* Configure RX LED */
3523 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL,
3524 SK_RXLEDCTL_COUNTER_START);
3526 /* Configure TX LED */
3527 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL,
3528 SK_TXLEDCTL_COUNTER_START);
3532 * Configure descriptor poll timer
3534 * SK-NET GENESIS data sheet says that possibility of losing Start
3535 * transmit command due to CPU/cache related interim storage problems
3536 * under certain conditions. The document recommends a polling
3537 * mechanism to send a Start transmit command to initiate transfer
3538 * of ready descriptors regulary. To cope with this issue sk(4) now
3539 * enables descriptor poll timer to initiate descriptor processing
3540 * periodically as defined by SK_DPT_TIMER_MAX. However sk(4) still
3541 * issue SK_TXBMU_TX_START to Tx BMU to get fast execution of Tx
3542 * command instead of waiting for next descriptor polling time.
3543 * The same rule may apply to Rx side too but it seems that is not
3544 * needed at the moment.
3545 * Since sk(4) uses descriptor polling as a last resort there is no
3546 * need to set smaller polling time than maximum allowable one.
3548 SK_IF_WRITE_4(sc_if, 0, SK_DPT_INIT, SK_DPT_TIMER_MAX);
3550 /* Configure I2C registers */
3552 /* Configure XMAC(s) */
3553 switch (sc->sk_type) {
3555 sk_init_xmac(sc_if);
3560 sk_init_yukon(sc_if);
3565 if (sc->sk_type == SK_GENESIS) {
3566 /* Configure MAC FIFOs */
3567 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET);
3568 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END);
3569 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON);
3571 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET);
3572 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END);
3573 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON);
3576 /* Configure transmit arbiter(s) */
3577 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL,
3578 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON);
3580 /* Configure RAMbuffers */
3581 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET);
3582 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart);
3583 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart);
3584 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart);
3585 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend);
3586 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON);
3588 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET);
3589 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON);
3590 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart);
3591 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart);
3592 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart);
3593 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend);
3594 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON);
3596 /* Configure BMUs */
3597 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE);
3598 if (ifp->if_mtu > SK_MAX_FRAMELEN) {
3599 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
3600 SK_ADDR_LO(SK_JUMBO_RX_RING_ADDR(sc_if, 0)));
3601 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI,
3602 SK_ADDR_HI(SK_JUMBO_RX_RING_ADDR(sc_if, 0)));
3604 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
3605 SK_ADDR_LO(SK_RX_RING_ADDR(sc_if, 0)));
3606 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI,
3607 SK_ADDR_HI(SK_RX_RING_ADDR(sc_if, 0)));
3610 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE);
3611 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO,
3612 SK_ADDR_LO(SK_TX_RING_ADDR(sc_if, 0)));
3613 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI,
3614 SK_ADDR_HI(SK_TX_RING_ADDR(sc_if, 0)));
3616 /* Init descriptors */
3617 if (ifp->if_mtu > SK_MAX_FRAMELEN)
3618 error = sk_init_jumbo_rx_ring(sc_if);
3620 error = sk_init_rx_ring(sc_if);
3622 device_printf(sc_if->sk_if_dev,
3623 "initialization failed: no memory for rx buffers\n");
3627 sk_init_tx_ring(sc_if);
3629 /* Set interrupt moderation if changed via sysctl. */
3630 imr = sk_win_read_4(sc, SK_IMTIMERINIT);
3631 if (imr != SK_IM_USECS(sc->sk_int_mod, sc->sk_int_ticks)) {
3632 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod,
3635 device_printf(sc_if->sk_if_dev,
3636 "interrupt moderation is %d us.\n",
3640 /* Configure interrupt handling */
3641 CSR_READ_4(sc, SK_ISSR);
3642 if (sc_if->sk_port == SK_PORT_A)
3643 sc->sk_intrmask |= SK_INTRS1;
3645 sc->sk_intrmask |= SK_INTRS2;
3647 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG;
3649 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
3652 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START);
3654 switch(sc->sk_type) {
3656 /* Enable XMACs TX and RX state machines */
3657 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE);
3658 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
3663 reg = SK_YU_READ_2(sc_if, YUKON_GPCR);
3664 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN;
3666 /* XXX disable 100Mbps and full duplex mode? */
3667 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_DIS);
3669 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg);
3672 /* Activate descriptor polling timer */
3673 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_START);
3674 /* start transfer of Tx descriptors */
3675 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
3677 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3678 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3680 switch (sc->sk_type) {
3684 callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if);
3688 callout_reset(&sc_if->sk_watchdog_ch, hz, sk_watchdog, ifp);
3695 struct sk_if_softc *sc_if;
3698 struct sk_softc *sc;
3699 struct sk_txdesc *txd;
3700 struct sk_rxdesc *rxd;
3701 struct sk_rxdesc *jrxd;
3705 SK_IF_LOCK_ASSERT(sc_if);
3706 sc = sc_if->sk_softc;
3707 ifp = sc_if->sk_ifp;
3709 callout_stop(&sc_if->sk_tick_ch);
3710 callout_stop(&sc_if->sk_watchdog_ch);
3712 /* stop Tx descriptor polling timer */
3713 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP);
3714 /* stop transfer of Tx descriptors */
3715 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_STOP);
3716 for (i = 0; i < SK_TIMEOUT; i++) {
3717 val = CSR_READ_4(sc, sc_if->sk_tx_bmu);
3718 if ((val & SK_TXBMU_TX_STOP) == 0)
3722 if (i == SK_TIMEOUT)
3723 device_printf(sc_if->sk_if_dev,
3724 "can not stop transfer of Tx descriptor\n");
3725 /* stop transfer of Rx descriptors */
3726 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_STOP);
3727 for (i = 0; i < SK_TIMEOUT; i++) {
3728 val = SK_IF_READ_4(sc_if, 0, SK_RXQ1_BMU_CSR);
3729 if ((val & SK_RXBMU_RX_STOP) == 0)
3733 if (i == SK_TIMEOUT)
3734 device_printf(sc_if->sk_if_dev,
3735 "can not stop transfer of Rx descriptor\n");
3737 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
3738 /* Put PHY back into reset. */
3739 val = sk_win_read_4(sc, SK_GPIO);
3740 if (sc_if->sk_port == SK_PORT_A) {
3741 val |= SK_GPIO_DIR0;
3742 val &= ~SK_GPIO_DAT0;
3744 val |= SK_GPIO_DIR2;
3745 val &= ~SK_GPIO_DAT2;
3747 sk_win_write_4(sc, SK_GPIO, val);
3750 /* Turn off various components of this interface. */
3751 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
3752 switch (sc->sk_type) {
3754 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET);
3755 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET);
3760 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET);
3761 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET);
3764 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE);
3765 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
3766 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE);
3767 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
3768 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF);
3769 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
3770 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
3771 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF);
3772 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF);
3774 /* Disable interrupts */
3775 if (sc_if->sk_port == SK_PORT_A)
3776 sc->sk_intrmask &= ~SK_INTRS1;
3778 sc->sk_intrmask &= ~SK_INTRS2;
3779 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
3781 SK_XM_READ_2(sc_if, XM_ISR);
3782 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
3784 /* Free RX and TX mbufs still in the queues. */
3785 for (i = 0; i < SK_RX_RING_CNT; i++) {
3786 rxd = &sc_if->sk_cdata.sk_rxdesc[i];
3787 if (rxd->rx_m != NULL) {
3788 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag,
3789 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3790 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag,
3796 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
3797 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i];
3798 if (jrxd->rx_m != NULL) {
3799 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag,
3800 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3801 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag,
3803 m_freem(jrxd->rx_m);
3807 for (i = 0; i < SK_TX_RING_CNT; i++) {
3808 txd = &sc_if->sk_cdata.sk_txdesc[i];
3809 if (txd->tx_m != NULL) {
3810 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag,
3811 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
3812 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag,
3819 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE);
3825 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3831 value = *(int *)arg1;
3832 error = sysctl_handle_int(oidp, &value, 0, req);
3833 if (error || !req->newptr)
3835 if (value < low || value > high)
3837 *(int *)arg1 = value;
3842 sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS)
3844 return (sysctl_int_range(oidp, arg1, arg2, req, SK_IM_MIN, SK_IM_MAX));