2 * Copyright (c) 1996 Gardner Buchanan <gbuchanan@shl.com>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Gardner Buchanan.
16 * 4. The name of Gardner Buchanan may not be used to endorse or promote
17 * products derived from this software without specific prior written
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
36 * This is a driver for SMC's 9000 series of Ethernet adapters.
38 * This FreeBSD driver is derived from the smc9194 Linux driver by
39 * Erik Stahlman and is Copyright (C) 1996 by Erik Stahlman.
40 * This driver also shamelessly borrows from the FreeBSD ep driver
41 * which is Copyright (C) 1994 Herb Peyerl <hpeyerl@novatel.ca>
42 * All rights reserved.
44 * It is set up for my SMC91C92 equipped Ampro LittleBoard embedded
45 * PC. It is adapted from Erik Stahlman's Linux driver which worked
46 * with his EFA Info*Express SVC VLB adaptor. According to SMC's databook,
47 * it will work for the entire SMC 9xxx series. (Ha Ha)
49 * "Features" of the SMC chip:
50 * 4608 byte packet memory. (for the 91C92. Others have more)
51 * EEPROM for configuration
55 * Erik Stahlman erik@vt.edu
56 * Herb Peyerl hpeyerl@novatel.ca
57 * Andres Vega Garcia avega@sophia.inria.fr
58 * Serge Babkin babkin@hq.icb.chel.su
59 * Gardner Buchanan gbuchanan@shl.com
63 * o "smc9194.c:v0.10(FIXED) 02/15/96 by Erik Stahlman (erik@vt.edu)"
64 * o "if_ep.c,v 1.19 1995/01/24 20:53:45 davidg Exp"
67 * o Setting of the hardware address isn't supported.
68 * o Hardware padding isn't used.
72 * Modifications for Megahertz X-Jack Ethernet Card (XJ-10BT)
74 * Copyright (c) 1996 by Tatsumi Hosokawa <hosokawa@jp.FreeBSD.org>
75 * BSD-nomads, Tokyo, Japan.
78 * Multicast support by Kei TANAKA <kei@pal.xerox.com>
79 * Special thanks to itojun@itojun.org
82 #include <sys/param.h>
83 #include <sys/systm.h>
84 #include <sys/errno.h>
85 #include <sys/kernel.h>
86 #include <sys/sockio.h>
88 #include <sys/socket.h>
89 #include <sys/syslog.h>
91 #include <sys/module.h>
94 #include <machine/bus.h>
95 #include <machine/resource.h>
98 #include <net/ethernet.h>
100 #include <net/if_arp.h>
101 #include <net/if_dl.h>
102 #include <net/if_types.h>
103 #include <net/if_mib.h>
106 #include <netinet/in.h>
107 #include <netinet/in_systm.h>
108 #include <netinet/in_var.h>
109 #include <netinet/ip.h>
113 #include <net/bpfdesc.h>
115 #include <dev/sn/if_snreg.h>
116 #include <dev/sn/if_snvar.h>
118 /* Exported variables */
119 devclass_t sn_devclass;
121 static int snioctl(struct ifnet * ifp, u_long, caddr_t);
123 static void snresume(struct ifnet *);
125 static void snintr_locked(struct sn_softc *);
126 static void sninit_locked(void *);
127 static void snstart_locked(struct ifnet *);
129 static void sninit(void *);
130 static void snread(struct ifnet *);
131 static void snstart(struct ifnet *);
132 static void snstop(struct sn_softc *);
133 static void snwatchdog(void *);
135 static void sn_setmcast(struct sn_softc *);
136 static int sn_getmcf(struct ifnet *ifp, u_char *mcf);
138 /* I (GB) have been unlucky getting the hardware padding
143 static const char *chip_ids[15] = {
145 /* 3 */ "SMC91C90/91C92",
146 /* 4 */ "SMC91C94/91C96",
150 /* 8 */ "SMC91C100FD",
157 sn_attach(device_t dev)
159 struct sn_softc *sc = device_get_softc(dev);
168 ifp = sc->ifp = if_alloc(IFT_ETHER);
170 device_printf(dev, "can not if_alloc()\n");
175 callout_init_mtx(&sc->watchdog, &sc->sc_mtx, 0);
177 sc->pages_wanted = -1;
179 if (bootverbose || 1) {
180 SMC_SELECT_BANK(sc, 3);
181 rev = (CSR_READ_2(sc, REVISION_REG_W) >> 4) & 0xf;
183 device_printf(dev, " %s ", chip_ids[rev]);
185 device_printf(dev, " unsupported chip: rev %d ", rev);
186 SMC_SELECT_BANK(sc, 1);
187 i = CSR_READ_2(sc, CONFIG_REG_W);
188 printf("%s\n", i & CR_AUI_SELECT ? "AUI" : "UTP");
192 * Read the station address from the chip. The MAC address is bank 1,
195 SMC_SELECT_BANK(sc, 1);
196 p = (uint8_t *) eaddr;
197 for (i = 0; i < 6; i += 2) {
198 address = CSR_READ_2(sc, IAR_ADDR0_REG_W + i);
199 p[i + 1] = address >> 8;
200 p[i] = address & 0xFF;
203 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
204 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
205 ifp->if_start = snstart;
206 ifp->if_ioctl = snioctl;
207 ifp->if_init = sninit;
208 ifp->if_baudrate = 10000000;
209 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
210 ifp->if_snd.ifq_maxlen = ifqmaxlen;
211 IFQ_SET_READY(&ifp->if_snd);
213 ether_ifattach(ifp, eaddr);
216 * Activate the interrupt so we can get card interrupts. This
217 * needs to be done last so that we don't have/hold the lock
218 * during startup to avoid LORs in the network layer.
220 if ((err = bus_setup_intr(dev, sc->irq_res,
221 INTR_TYPE_NET | INTR_MPSAFE, NULL, sn_intr, sc,
222 &sc->intrhand)) != 0) {
231 sn_detach(device_t dev)
233 struct sn_softc *sc = device_get_softc(dev);
234 struct ifnet *ifp = sc->ifp;
240 callout_drain(&sc->watchdog);
250 struct sn_softc *sc = xsc;
257 * Reset and initialize the chip
260 sninit_locked(void *xsc)
262 struct sn_softc *sc = xsc;
263 struct ifnet *ifp = sc->ifp;
267 SN_ASSERT_LOCKED(sc);
270 * This resets the registers mostly to defaults, but doesn't affect
271 * EEPROM. After the reset cycle, we pause briefly for the chip to
274 SMC_SELECT_BANK(sc, 0);
275 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, RCR_SOFTRESET);
277 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, 0x0000);
281 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, 0x0000);
284 * Set the control register to automatically release succesfully
285 * transmitted packets (making the best use out of our limited
286 * memory) and to enable the EPH interrupt on certain TX errors.
288 SMC_SELECT_BANK(sc, 1);
289 CSR_WRITE_2(sc, CONTROL_REG_W, (CTR_AUTO_RELEASE | CTR_TE_ENABLE |
290 CTR_CR_ENABLE | CTR_LE_ENABLE));
292 /* Set squelch level to 240mV (default 480mV) */
293 flags = CSR_READ_2(sc, CONFIG_REG_W);
294 flags |= CR_SET_SQLCH;
295 CSR_WRITE_2(sc, CONFIG_REG_W, flags);
298 * Reset the MMU and wait for it to be un-busy.
300 SMC_SELECT_BANK(sc, 2);
301 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_RESET);
302 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
306 * Disable all interrupts
308 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00);
313 * Set the transmitter control. We want it enabled.
319 * I (GB) have been unlucky getting this to work.
321 flags |= TCR_PAD_ENABLE;
324 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, flags);
328 * Now, enable interrupts
330 SMC_SELECT_BANK(sc, 2);
337 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
338 sc->intr_mask = mask;
339 sc->pages_wanted = -1;
343 * Mark the interface running but not active.
345 ifp->if_drv_flags |= IFF_DRV_RUNNING;
346 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
347 callout_reset(&sc->watchdog, hz, snwatchdog, sc);
350 * Attempt to push out any waiting packets.
356 snstart(struct ifnet *ifp)
358 struct sn_softc *sc = ifp->if_softc;
366 snstart_locked(struct ifnet *ifp)
368 struct sn_softc *sc = ifp->if_softc;
380 SN_ASSERT_LOCKED(sc);
382 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
384 if (sc->pages_wanted != -1) {
385 if_printf(ifp, "snstart() while memory allocation pending\n");
391 * Sneak a peek at the next packet
393 m = ifp->if_snd.ifq_head;
397 * Compute the frame length and set pad to give an overall even
398 * number of bytes. Below we assume that the packet length is even.
400 for (len = 0, top = m; m; m = m->m_next)
406 * We drop packets that are too large. Perhaps we should truncate
409 if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) {
410 if_printf(ifp, "large packet discarded (A)\n");
412 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
419 * If HW padding is not turned on, then pad to ETHER_MIN_LEN.
421 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN)
422 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len;
429 * The MMU wants the number of pages to be the number of 256 byte
430 * 'pages', minus 1 (A packet can't ever have 0 pages. We also
431 * include space for the status word, byte count and control bytes in
432 * the allocation request.
434 numPages = (length + 6) >> 8;
438 * Now, try to allocate the memory
440 SMC_SELECT_BANK(sc, 2);
441 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ALLOC | numPages);
444 * Wait a short amount of time to see if the allocation request
445 * completes. Otherwise, I enable the interrupt and wait for
446 * completion asynchronously.
449 time_out = MEMORY_WAIT_TIME;
451 if (CSR_READ_1(sc, INTR_STAT_REG_B) & IM_ALLOC_INT)
453 } while (--time_out);
455 if (!time_out || junk > 10) {
458 * No memory now. Oh well, wait until the chip finds memory
459 * later. Remember how many pages we were asking for and
460 * enable the allocation completion interrupt. Also set a
461 * watchdog in case we miss the interrupt. We mark the
462 * interface active since there is no point in attempting an
463 * snstart() until after the memory is available.
465 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | IM_ALLOC_INT;
466 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
467 sc->intr_mask = mask;
470 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
471 sc->pages_wanted = numPages;
475 * The memory allocation completed. Check the results.
477 packet_no = CSR_READ_1(sc, ALLOC_RESULT_REG_B);
478 if (packet_no & ARR_FAILED) {
480 if_printf(ifp, "Memory allocation failed\n");
484 * We have a packet number, so tell the card to use it.
486 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no);
489 * Point to the beginning of the packet
491 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | 0x0000);
494 * Send the packet length (+6 for status, length and control byte)
495 * and the status word (set to zeros)
497 CSR_WRITE_2(sc, DATA_REG_W, 0);
498 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) & 0xFF);
499 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) >> 8);
502 * Get the packet from the kernel. This will include the Ethernet
503 * frame header, MAC Addresses etc.
505 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
508 * Push out the data to the card.
510 for (top = m; m != 0; m = m->m_next) {
515 CSR_WRITE_MULTI_2(sc, DATA_REG_W, mtod(m, uint16_t *),
519 * Push out remaining byte.
522 CSR_WRITE_1(sc, DATA_REG_B,
523 *(mtod(m, caddr_t) + m->m_len - 1));
530 CSR_WRITE_2(sc, DATA_REG_W, 0);
534 CSR_WRITE_1(sc, DATA_REG_B, 0);
537 * Push out control byte and unused packet byte The control byte is 0
538 * meaning the packet is even lengthed and no special CRC handling is
541 CSR_WRITE_2(sc, DATA_REG_W, 0);
544 * Enable the interrupts and let the chipset deal with it Also set a
545 * watchdog in case we miss the interrupt.
547 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT);
548 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
549 sc->intr_mask = mask;
551 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ENQUEUE);
553 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
565 * Is another packet coming in? We don't want to overflow the tiny
566 * RX FIFO. If nothing has arrived then attempt to queue another
569 if (CSR_READ_2(sc, FIFO_PORTS_REG_W) & FIFO_REMPTY)
576 /* Resume a packet transmit operation after a memory allocation
579 * This is basically a hacked up copy of snstart() which handles
580 * a completed memory allocation the same way snstart() does.
581 * It then passes control to snstart to handle any other queued
585 snresume(struct ifnet *ifp)
587 struct sn_softc *sc = ifp->if_softc;
595 uint16_t pages_wanted;
598 if (sc->pages_wanted < 0)
601 pages_wanted = sc->pages_wanted;
602 sc->pages_wanted = -1;
605 * Sneak a peek at the next packet
607 m = ifp->if_snd.ifq_head;
609 if_printf(ifp, "snresume() with nothing to send\n");
613 * Compute the frame length and set pad to give an overall even
614 * number of bytes. Below we assume that the packet length is even.
616 for (len = 0, top = m; m; m = m->m_next)
622 * We drop packets that are too large. Perhaps we should truncate
625 if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) {
626 if_printf(ifp, "large packet discarded (B)\n");
628 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
635 * If HW padding is not turned on, then pad to ETHER_MIN_LEN.
637 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN)
638 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len;
646 * The MMU wants the number of pages to be the number of 256 byte
647 * 'pages', minus 1 (A packet can't ever have 0 pages. We also
648 * include space for the status word, byte count and control bytes in
649 * the allocation request.
651 numPages = (length + 6) >> 8;
654 SMC_SELECT_BANK(sc, 2);
657 * The memory allocation completed. Check the results. If it failed,
658 * we simply set a watchdog timer and hope for the best.
660 packet_no = CSR_READ_1(sc, ALLOC_RESULT_REG_B);
661 if (packet_no & ARR_FAILED) {
662 if_printf(ifp, "Memory allocation failed. Weird.\n");
667 * We have a packet number, so tell the card to use it.
669 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no);
672 * Now, numPages should match the pages_wanted recorded when the
673 * memory allocation was initiated.
675 if (pages_wanted != numPages) {
676 if_printf(ifp, "memory allocation wrong size. Weird.\n");
678 * If the allocation was the wrong size we simply release the
679 * memory once it is granted. Wait for the MMU to be un-busy.
681 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
683 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_FREEPKT);
688 * Point to the beginning of the packet
690 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | 0x0000);
693 * Send the packet length (+6 for status, length and control byte)
694 * and the status word (set to zeros)
696 CSR_WRITE_2(sc, DATA_REG_W, 0);
697 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) & 0xFF);
698 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) >> 8);
701 * Get the packet from the kernel. This will include the Ethernet
702 * frame header, MAC Addresses etc.
704 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
707 * Push out the data to the card.
709 for (top = m; m != 0; m = m->m_next) {
714 CSR_WRITE_MULTI_2(sc, DATA_REG_W, mtod(m, uint16_t *),
717 * Push out remaining byte.
720 CSR_WRITE_1(sc, DATA_REG_B,
721 *(mtod(m, caddr_t) + m->m_len - 1));
728 CSR_WRITE_2(sc, DATA_REG_W, 0);
732 CSR_WRITE_1(sc, DATA_REG_B, 0);
735 * Push out control byte and unused packet byte The control byte is 0
736 * meaning the packet is even lengthed and no special CRC handling is
739 CSR_WRITE_2(sc, DATA_REG_W, 0);
742 * Enable the interrupts and let the chipset deal with it Also set a
743 * watchdog in case we miss the interrupt.
745 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT);
746 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
747 sc->intr_mask = mask;
748 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ENQUEUE);
758 * Now pass control to snstart() to queue any additional packets
760 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
764 * We've sent something, so we're active. Set a watchdog in case the
765 * TX_EMPTY interrupt is lost.
767 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
776 struct sn_softc *sc = (struct sn_softc *) arg;
784 snintr_locked(struct sn_softc *sc)
786 int status, interrupts;
787 struct ifnet *ifp = sc->ifp;
790 * Chip state registers
798 * Clear the watchdog.
802 SMC_SELECT_BANK(sc, 2);
805 * Obtain the current interrupt mask and clear the hardware mask
806 * while servicing interrupts.
808 mask = CSR_READ_1(sc, INTR_MASK_REG_B);
809 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00);
812 * Get the set of interrupts which occurred and eliminate any which
815 interrupts = CSR_READ_1(sc, INTR_STAT_REG_B);
816 status = interrupts & mask;
819 * Now, process each of the interrupt types.
825 if (status & IM_RX_OVRN_INT) {
827 * Acknowlege Interrupt
829 SMC_SELECT_BANK(sc, 2);
830 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_RX_OVRN_INT);
837 if (status & IM_RCV_INT) {
840 SMC_SELECT_BANK(sc, 2);
841 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W);
843 if (packet_number & FIFO_REMPTY) {
845 * we got called , but nothing was on the FIFO
847 printf("sn: Receive interrupt with nothing on FIFO\n");
853 * An on-card memory allocation came through.
855 if (status & IM_ALLOC_INT) {
857 * Disable this interrupt.
859 mask &= ~IM_ALLOC_INT;
860 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
864 * TX Completion. Handle a transmit error message. This will only be
865 * called when there is an error, because of the AUTO_RELEASE mode.
867 if (status & IM_TX_INT) {
869 * Acknowlege Interrupt
871 SMC_SELECT_BANK(sc, 2);
872 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_TX_INT);
874 packet_no = CSR_READ_2(sc, FIFO_PORTS_REG_W);
875 packet_no &= FIFO_TX_MASK;
878 * select this as the packet to read from
880 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no);
883 * Position the pointer to the first word from this packet
885 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | PTR_READ | 0x0000);
888 * Fetch the TX status word. The value found here will be a
889 * copy of the EPH_STATUS_REG_W at the time the transmit
892 tx_status = CSR_READ_2(sc, DATA_REG_W);
894 if (tx_status & EPHSR_TX_SUC) {
895 device_printf(sc->dev,
896 "Successful packet caused interrupt\n");
901 if (tx_status & EPHSR_LATCOL)
902 ++ifp->if_collisions;
905 * Some of these errors will have disabled transmit.
906 * Re-enable transmit now.
908 SMC_SELECT_BANK(sc, 0);
911 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, TCR_ENABLE);
913 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, TCR_ENABLE | TCR_PAD_ENABLE);
917 * kill the failed packet. Wait for the MMU to be un-busy.
919 SMC_SELECT_BANK(sc, 2);
920 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
922 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_FREEPKT);
925 * Attempt to queue more transmits.
927 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
931 * Transmit underrun. We use this opportunity to update transmit
932 * statistics from the card.
934 if (status & IM_TX_EMPTY_INT) {
937 * Acknowlege Interrupt
939 SMC_SELECT_BANK(sc, 2);
940 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_TX_EMPTY_INT);
943 * Disable this interrupt.
945 mask &= ~IM_TX_EMPTY_INT;
947 SMC_SELECT_BANK(sc, 0);
948 card_stats = CSR_READ_2(sc, COUNTER_REG_W);
953 ifp->if_collisions += card_stats & ECR_COLN_MASK;
956 * Multiple collisions
958 ifp->if_collisions += (card_stats & ECR_MCOLN_MASK) >> 4;
960 SMC_SELECT_BANK(sc, 2);
963 * Attempt to enqueue some more stuff.
965 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
969 * Some other error. Try to fix it by resetting the adapter.
971 if (status & IM_EPH_INT) {
978 * Handled all interrupt sources.
981 SMC_SELECT_BANK(sc, 2);
984 * Reestablish interrupts from mask which have not been deselected
985 * during this interrupt. Note that the hardware mask, which was set
986 * to 0x00 at the start of this service routine, may have been
987 * updated by one or more of the interrupt handers and we must let
988 * those new interrupts stay enabled here.
990 mask |= CSR_READ_1(sc, INTR_MASK_REG_B);
991 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask);
992 sc->intr_mask = mask;
996 snread(struct ifnet *ifp)
998 struct sn_softc *sc = ifp->if_softc;
999 struct ether_header *eh;
1003 uint16_t packet_length;
1006 SMC_SELECT_BANK(sc, 2);
1008 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W);
1010 if (packet_number & FIFO_REMPTY) {
1013 * we got called , but nothing was on the FIFO
1015 printf("sn: Receive interrupt with nothing on FIFO\n");
1022 * Start reading from the start of the packet. Since PTR_RCV is set,
1023 * packet number is found in FIFO_PORTS_REG_W, FIFO_RX_MASK.
1025 CSR_WRITE_2(sc, POINTER_REG_W, PTR_READ | PTR_RCV | PTR_AUTOINC | 0x0000);
1028 * First two words are status and packet_length
1030 status = CSR_READ_2(sc, DATA_REG_W);
1031 packet_length = CSR_READ_2(sc, DATA_REG_W) & RLEN_MASK;
1034 * The packet length contains 3 extra words: status, length, and a
1035 * extra word with the control byte.
1040 * Account for receive errors and discard.
1042 if (status & RS_ERRORS) {
1047 * A packet is received.
1051 * Adjust for odd-length packet.
1053 if (status & RS_ODDFRAME)
1057 * Allocate a header mbuf from the kernel.
1059 MGETHDR(m, M_NOWAIT, MT_DATA);
1063 m->m_pkthdr.rcvif = ifp;
1064 m->m_pkthdr.len = m->m_len = packet_length;
1067 * Attach an mbuf cluster
1069 MCLGET(m, M_NOWAIT);
1072 * Insist on getting a cluster
1074 if ((m->m_flags & M_EXT) == 0) {
1077 printf("sn: snread() kernel memory allocation problem\n");
1080 eh = mtod(m, struct ether_header *);
1083 * Get packet, including link layer address, from interface.
1085 data = (uint8_t *) eh;
1086 CSR_READ_MULTI_2(sc, DATA_REG_W, (uint16_t *) data, packet_length >> 1);
1087 if (packet_length & 1) {
1088 data += packet_length & ~1;
1089 *data = CSR_READ_1(sc, DATA_REG_B);
1094 * Remove link layer addresses and whatnot.
1096 m->m_pkthdr.len = m->m_len = packet_length;
1099 * Drop locks before calling if_input() since it may re-enter
1100 * snstart() in the netisr case. This would result in a
1101 * lock reversal. Better performance might be obtained by
1102 * chaining all packets received, dropping the lock, and then
1103 * calling if_input() on each one.
1106 (*ifp->if_input)(ifp, m);
1112 * Error or good, tell the card to get rid of this packet Wait for
1113 * the MMU to be un-busy.
1115 SMC_SELECT_BANK(sc, 2);
1116 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
1118 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_RELEASE);
1121 * Check whether another packet is ready
1123 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W);
1124 if (packet_number & FIFO_REMPTY) {
1132 * Handle IOCTLS. This function is completely stolen from if_ep.c
1133 * As with its progenitor, it does not handle hardware address
1137 snioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1139 struct sn_softc *sc = ifp->if_softc;
1145 if ((ifp->if_flags & IFF_UP) == 0 &&
1146 ifp->if_drv_flags & IFF_DRV_RUNNING) {
1149 /* reinitialize card on any parameter change */
1157 /* update multicast filter list. */
1164 error = ether_ioctl(ifp, cmd, data);
1171 snwatchdog(void *arg)
1173 struct sn_softc *sc;
1176 SN_ASSERT_LOCKED(sc);
1177 callout_reset(&sc->watchdog, hz, snwatchdog, sc);
1178 if (sc->timer == 0 || --sc->timer > 0)
1184 /* 1. zero the interrupt mask
1185 * 2. clear the enable receive flag
1186 * 3. clear the enable xmit flags
1189 snstop(struct sn_softc *sc)
1192 struct ifnet *ifp = sc->ifp;
1195 * Clear interrupt mask; disable all interrupts.
1197 SMC_SELECT_BANK(sc, 2);
1198 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00);
1201 * Disable transmitter and Receiver
1203 SMC_SELECT_BANK(sc, 0);
1204 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, 0x0000);
1205 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, 0x0000);
1211 callout_stop(&sc->watchdog);
1212 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1217 sn_activate(device_t dev)
1219 struct sn_softc *sc = device_get_softc(dev);
1222 sc->port_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->port_rid,
1223 0, ~0, SMC_IO_EXTENT, RF_ACTIVE);
1224 if (!sc->port_res) {
1226 device_printf(dev, "Cannot allocate ioport\n");
1231 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
1235 device_printf(dev, "Cannot allocate irq\n");
1243 sn_deactivate(device_t dev)
1245 struct sn_softc *sc = device_get_softc(dev);
1248 bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
1251 bus_release_resource(dev, SYS_RES_IOPORT, sc->port_rid,
1255 bus_release_resource(dev, SYS_RES_IOPORT, sc->modem_rid,
1259 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid,
1266 * Function: sn_probe(device_t dev)
1269 * Tests to see if a given ioaddr points to an SMC9xxx chip.
1270 * Tries to cause as little damage as possible if it's not a SMC chip.
1271 * Returns a 0 on success
1274 * (1) see if the high byte of BANK_SELECT is 0x33
1275 * (2) compare the ioaddr with the base register's address
1276 * (3) see if I recognize the chip ID in the appropriate register
1281 sn_probe(device_t dev)
1283 struct sn_softc *sc = device_get_softc(dev);
1285 uint16_t revision_register;
1286 uint16_t base_address_register;
1289 if ((err = sn_activate(dev)) != 0)
1293 * First, see if the high byte is 0x33
1295 bank = CSR_READ_2(sc, BANK_SELECT_REG_W);
1296 if ((bank & BSR_DETECT_MASK) != BSR_DETECT_VALUE) {
1298 device_printf(dev, "test1 failed\n");
1303 * The above MIGHT indicate a device, but I need to write to further
1304 * test this. Go to bank 0, then test that the register still
1305 * reports the high byte is 0x33.
1307 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x0000);
1308 bank = CSR_READ_2(sc, BANK_SELECT_REG_W);
1309 if ((bank & BSR_DETECT_MASK) != BSR_DETECT_VALUE) {
1311 device_printf(dev, "test2 failed\n");
1316 * well, we've already written once, so hopefully another time won't
1317 * hurt. This time, I need to switch the bank register to bank 1, so
1318 * I can access the base address register. The contents of the
1319 * BASE_ADDR_REG_W register, after some jiggery pokery, is expected
1320 * to match the I/O port address where the adapter is being probed.
1322 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x0001);
1323 base_address_register = (CSR_READ_2(sc, BASE_ADDR_REG_W) >> 3) & 0x3e0;
1325 if (rman_get_start(sc->port_res) != base_address_register) {
1328 * Well, the base address register didn't match. Must not
1329 * have been a SMC chip after all.
1332 device_printf(dev, "test3 failed ioaddr = 0x%x, "
1333 "base_address_register = 0x%x\n",
1334 rman_get_start(sc->port_res), base_address_register);
1340 * Check if the revision register is something that I recognize.
1341 * These might need to be added to later, as future revisions could
1344 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x3);
1345 revision_register = CSR_READ_2(sc, REVISION_REG_W);
1346 if (!chip_ids[(revision_register >> 4) & 0xF]) {
1349 * I don't regonize this chip, so...
1352 device_printf(dev, "test4 failed\n");
1358 * at this point I'll assume that the chip is an SMC9xxx. It might be
1359 * prudent to check a listing of MAC addresses against the hardware
1360 * address, or do some other tests.
1372 sn_setmcast(struct sn_softc *sc)
1374 struct ifnet *ifp = sc->ifp;
1378 SN_ASSERT_LOCKED(sc);
1381 * Set the receiver filter. We want receive enabled and auto strip
1382 * of CRC from received packet. If we are promiscuous then set that
1385 flags = RCR_ENABLE | RCR_STRIP_CRC;
1387 if (ifp->if_flags & IFF_PROMISC) {
1388 flags |= RCR_PROMISC | RCR_ALMUL;
1389 } else if (ifp->if_flags & IFF_ALLMULTI) {
1392 if (sn_getmcf(ifp, mcf)) {
1394 SMC_SELECT_BANK(sc, 3);
1395 CSR_WRITE_2(sc, MULTICAST1_REG_W,
1396 ((uint16_t)mcf[1] << 8) | mcf[0]);
1397 CSR_WRITE_2(sc, MULTICAST2_REG_W,
1398 ((uint16_t)mcf[3] << 8) | mcf[2]);
1399 CSR_WRITE_2(sc, MULTICAST3_REG_W,
1400 ((uint16_t)mcf[5] << 8) | mcf[4]);
1401 CSR_WRITE_2(sc, MULTICAST4_REG_W,
1402 ((uint16_t)mcf[7] << 8) | mcf[6]);
1407 SMC_SELECT_BANK(sc, 0);
1408 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, flags);
1412 sn_getmcf(struct ifnet *ifp, uint8_t *mcf)
1415 uint32_t index, index2;
1417 struct ifmultiaddr *ifma;
1421 if_maddr_rlock(ifp);
1422 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1423 if (ifma->ifma_addr->sa_family != AF_LINK) {
1424 if_maddr_runlock(ifp);
1427 index = ether_crc32_le(LLADDR((struct sockaddr_dl *)
1428 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x3f;
1430 for (i = 0; i < 6; i++) {
1432 index2 |= (index & 0x01);
1435 af[index2 >> 3] |= 1 << (index2 & 7);
1437 if_maddr_runlock(ifp);
1438 return 1; /* use multicast filter */