2 * Copyright (c) 1999 Doug Rabson
3 * Copyright (c) 1997 Luigi Rizzo
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * This file contains information and macro definitions for
32 * AD1848-compatible devices, used in the MSS/WSS compatible boards.
38 The codec part of the board is seen as a set of 4 registers mapped
39 at the base address for the board (default 0x534). Note that some
40 (early) boards implemented 4 additional registers 4 location before
41 (usually 0x530) to store configuration information. This is a source
42 of confusion in that one never knows what address to specify. The
43 (current) convention is to use the old address (0x530) in the kernel
44 configuration file and consider MSS registers start four location
52 u_int polarity:1; /* 1 means reversed */
56 typedef struct mixer_def mixer_ent;
57 typedef struct mixer_def mixer_tab[32][2];
59 #define MIX_ENT(name, reg_l, pol_l, pos_l, len_l, reg_r, pol_r, pos_r, len_r) \
60 {{reg_l, pol_l, pos_l, len_l}, {reg_r, pol_r, pos_r, len_r}}
62 #define PMIX_ENT(name, reg_l, pos_l, len_l, reg_r, pos_r, len_r) \
63 {{reg_l, 0, pos_l, len_l}, {reg_r, 0, pos_r, len_r}}
65 #define MIX_NONE(name) MIX_ENT(name, 0,0,0,0, 0,0,0,0)
68 * The four visible registers of the MSS :
72 #define MSS_INDEX (0 + 4)
73 #define MSS_IDXBUSY 0x80 /* readonly, set when busy */
74 #define MSS_MCE 0x40 /* the MCE bit. */
76 * the MCE bit must be set whenever the current mode of the
77 * codec is changed; this in particular is true for the
78 * Data Format (I8, I28) and Interface Config(I9) registers.
79 * Only exception are CEN and PEN which can be changed on the fly.
80 * The DAC output is muted when MCE is set.
82 #define MSS_TRD 0x20 /* Transfer request disable */
84 * When TRD is set, DMA transfers cease when the INT bit in
85 * the MSS status reg is set. Must be cleared for automode
88 #define MSS_IDXMASK 0x1f /* mask for indirect address */
90 #define MSS_IDATA (1 + 4)
92 * data to be transferred to the indirect register addressed
93 * by index addr. During init and sw. powerdown, cannot be
94 * written to, and is always read as 0x80 (consistent with the
98 #define MSS_STATUS (2 + 4)
100 #define IS_CUL 0x80 /* capture upper/lower */
101 #define IS_CLR 0x40 /* capture left/right */
102 #define IS_CRDY 0x20 /* capture ready for programmed i/o */
103 #define IS_SER 0x10 /* sample error (overrun/underrun) */
104 #define IS_PUL 0x08 /* playback upper/lower */
105 #define IS_PLR 0x04 /* playback left/right */
106 #define IS_PRDY 0x02 /* playback ready for programmed i/o */
107 #define IS_INT 0x01 /* int status (1 = active) */
109 * IS_INT is clreared by any write to the status register.
112 #define io_Polled_IO(d) ((d)->io_base+3+4)
114 * this register is used in case of polled i/o
119 * The MSS has a set of 16 (or 32 depending on the model) indirect
120 * registers accessible through the data port by specifying the
121 * appropriate address in the address register.
123 * The 16 low registers are uniformly handled in AD1848/CS4248 compatible
124 * mode (often called MODE1). For the upper 16 registers there are
125 * some differences among different products, mainly Crystal uses them
126 * differently from OPTi.
137 * register I9 -- interface configuration.
140 #define I9_PEN 0x01 /* playback enable */
141 #define I9_CEN 0x02 /* capture enable */
144 * values used in bd_flags
146 #define BD_F_MCE_BIT 0x0001
147 #define BD_F_IRQ_OK 0x0002
148 #define BD_F_TMR_RUN 0x0004
149 #define BD_F_MSS_OFFSET 0x0008 /* offset mss writes by -4 */
150 #define BD_F_DUPLEX 0x0010
151 #define BD_F_924PNP 0x0020 /* OPTi924 is in PNP mode */
154 * sound/ad1848_mixer.h
156 * Definitions for the mixer of AD1848 and compatible codecs.
158 * Copyright by Hannu Savolainen 1994
160 * Redistribution and use in source and binary forms, with or without
161 * modification, are permitted provided that the following conditions are
162 * met: 1. Redistributions of source code must retain the above copyright
163 * notice, this list of conditions and the following disclaimer. 2.
164 * Redistributions in binary form must reproduce the above copyright notice,
165 * this list of conditions and the following disclaimer in the documentation
166 * and/or other materials provided with the distribution.
168 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY
169 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
170 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
171 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
172 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
173 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
174 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
175 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
176 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
177 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
181 * The AD1848 codec has generic input lines called Line, Aux1 and Aux2.
182 * Soundcard manufacturers have connected actual inputs (CD, synth, line,
183 * etc) to these inputs in different order. Therefore it's difficult
184 * to assign mixer channels to to these inputs correctly. The following
185 * contains two alternative mappings. The first one is for GUS MAX and
186 * the second is just a generic one (line1, line2 and line3).
187 * (Actually this is not a mapping but rather some kind of interleaving
191 #define MSS_REC_DEVICES \
192 (SOUND_MASK_LINE | SOUND_MASK_MIC | SOUND_MASK_CD|SOUND_MASK_IMIX)
196 * Table of mixer registers. There is a default table for the
197 * AD1848/CS423x clones, one for the OPTI931 and one for the
198 * OPTi930. As more MSS clones come out, there ought to be
201 * Fields in the table are : polarity, register, offset, bits
203 * The channel numbering used by individual soundcards is not fixed.
204 * Some cards have assigned different meanings for the AUX1, AUX2
205 * and LINE inputs. Some have different features...
207 * Following there is a macro ...MIXER_DEVICES which is a bitmap
208 * of all non-zero fields in the table.
209 * MODE1_MIXER_DEVICES is the basic mixer of the 1848 in mode 1
214 mixer_ent mix_devices[32][2] = {
215 MIX_NONE(SOUND_MIXER_VOLUME),
216 MIX_NONE(SOUND_MIXER_BASS),
217 MIX_NONE(SOUND_MIXER_TREBLE),
218 #ifdef PC98 /* PC98's synth is assigned to AUX#2 */
219 MIX_ENT(SOUND_MIXER_SYNTH, 4, 1, 0, 5, 5, 1, 0, 5),
220 #else /* AT386's synth is assigned to AUX#1 */
221 MIX_ENT(SOUND_MIXER_SYNTH, 2, 1, 0, 5, 3, 1, 0, 5),
223 MIX_ENT(SOUND_MIXER_PCM, 6, 1, 0, 6, 7, 1, 0, 6),
224 MIX_ENT(SOUND_MIXER_SPEAKER, 26, 1, 0, 4, 0, 0, 0, 0),
225 MIX_ENT(SOUND_MIXER_LINE, 18, 1, 0, 5, 19, 1, 0, 5),
226 MIX_ENT(SOUND_MIXER_MIC, 0, 0, 5, 1, 1, 0, 5, 1),
227 #ifdef PC98 /* PC98's cd-audio is assigned to AUX#1 */
228 MIX_ENT(SOUND_MIXER_CD, 2, 1, 0, 5, 3, 1, 0, 5),
229 #else /* AT386's cd-audio is assigned to AUX#2 */
230 MIX_ENT(SOUND_MIXER_CD, 4, 1, 0, 5, 5, 1, 0, 5),
232 MIX_ENT(SOUND_MIXER_IMIX, 13, 1, 2, 6, 0, 0, 0, 0),
233 MIX_NONE(SOUND_MIXER_ALTPCM),
234 MIX_NONE(SOUND_MIXER_RECLEV),
235 MIX_ENT(SOUND_MIXER_IGAIN, 0, 0, 0, 4, 1, 0, 0, 4),
236 MIX_NONE(SOUND_MIXER_OGAIN),
237 MIX_NONE(SOUND_MIXER_LINE1),
238 MIX_NONE(SOUND_MIXER_LINE2),
239 MIX_NONE(SOUND_MIXER_LINE3),
242 #define MODE2_MIXER_DEVICES \
243 (SOUND_MASK_SYNTH | SOUND_MASK_PCM | SOUND_MASK_SPEAKER | \
244 SOUND_MASK_LINE | SOUND_MASK_MIC | SOUND_MASK_CD | \
245 SOUND_MASK_IMIX | SOUND_MASK_IGAIN )
247 #define MODE1_MIXER_DEVICES \
248 (SOUND_MASK_SYNTH | SOUND_MASK_PCM | SOUND_MASK_MIC | \
249 SOUND_MASK_CD | SOUND_MASK_IMIX | SOUND_MASK_IGAIN )
252 mixer_ent opti930_devices[32][2] = {
253 MIX_ENT(SOUND_MIXER_VOLUME, 22, 1, 0, 4, 23, 1, 0, 4),
254 MIX_NONE(SOUND_MIXER_BASS),
255 MIX_NONE(SOUND_MIXER_TREBLE),
256 MIX_ENT(SOUND_MIXER_SYNTH, 4, 1, 0, 4, 5, 1, 0, 4),
257 MIX_ENT(SOUND_MIXER_PCM, 6, 1, 1, 5, 7, 1, 1, 5),
258 MIX_ENT(SOUND_MIXER_LINE, 18, 1, 1, 4, 19, 1, 1, 4),
259 MIX_NONE(SOUND_MIXER_SPEAKER),
260 MIX_ENT(SOUND_MIXER_MIC, 21, 1, 0, 4, 22, 1, 0, 4),
261 MIX_ENT(SOUND_MIXER_CD, 2, 1, 1, 4, 3, 1, 1, 4),
262 MIX_NONE(SOUND_MIXER_IMIX),
263 MIX_NONE(SOUND_MIXER_ALTPCM),
264 MIX_NONE(SOUND_MIXER_RECLEV),
265 MIX_NONE(SOUND_MIXER_IGAIN),
266 MIX_NONE(SOUND_MIXER_OGAIN),
267 MIX_NONE(SOUND_MIXER_LINE1),
268 MIX_NONE(SOUND_MIXER_LINE2),
269 MIX_NONE(SOUND_MIXER_LINE3),
272 #define OPTI930_MIXER_DEVICES \
273 (SOUND_MASK_VOLUME | SOUND_MASK_SYNTH | SOUND_MASK_PCM | \
274 SOUND_MASK_LINE | SOUND_MASK_MIC | SOUND_MASK_CD )
277 * entries for the opti931...
280 mixer_ent opti931_devices[32][2] = { /* for the opti931 */
281 MIX_ENT(SOUND_MIXER_VOLUME, 22, 1, 1, 5, 23, 1, 1, 5),
282 MIX_NONE(SOUND_MIXER_BASS),
283 MIX_NONE(SOUND_MIXER_TREBLE),
284 MIX_ENT(SOUND_MIXER_SYNTH, 4, 1, 1, 4, 5, 1, 1, 4),
285 MIX_ENT(SOUND_MIXER_PCM, 6, 1, 0, 5, 7, 1, 0, 5),
286 MIX_NONE(SOUND_MIXER_SPEAKER),
287 MIX_ENT(SOUND_MIXER_LINE, 18, 1, 1, 4, 19, 1, 1, 4),
288 MIX_ENT(SOUND_MIXER_MIC, 0, 0, 5, 1, 1, 0, 5, 1),
289 MIX_ENT(SOUND_MIXER_CD, 2, 1, 1, 4, 3, 1, 1, 4),
290 MIX_NONE(SOUND_MIXER_IMIX),
291 MIX_NONE(SOUND_MIXER_ALTPCM),
292 MIX_NONE(SOUND_MIXER_RECLEV),
293 MIX_ENT(SOUND_MIXER_IGAIN, 0, 0, 0, 4, 1, 0, 0, 4),
294 MIX_NONE(SOUND_MIXER_OGAIN),
295 MIX_ENT(SOUND_MIXER_LINE1, 16, 1, 1, 4, 17, 1, 1, 4),
296 MIX_NONE(SOUND_MIXER_LINE2),
297 MIX_NONE(SOUND_MIXER_LINE3),
300 #define OPTI931_MIXER_DEVICES \
301 (SOUND_MASK_VOLUME | SOUND_MASK_SYNTH | SOUND_MASK_PCM | \
302 SOUND_MASK_LINE | SOUND_MASK_MIC | SOUND_MASK_CD | \
303 SOUND_MASK_IGAIN | SOUND_MASK_LINE1 )
306 * Register definitions for the Yamaha OPL3-SA[23x].
308 #define OPL3SAx_POWER 0x01 /* Power Management (R/W) */
309 #define OPL3SAx_POWER_PDX 0x01 /* Set to 1 to halt oscillator */
310 #define OPL3SAx_POWER_PDN 0x02 /* Set to 1 to power down */
311 #define OPL3SAx_POWER_PSV 0x04 /* Set to 1 to power save */
312 #define OPL3SAx_POWER_ADOWN 0x20 /* Analog power (?) */
314 #define OPL3SAx_SYSTEM 0x02 /* System control (R/W) */
315 #define OPL3SAx_SYSTEM_VZE 0x01 /* I2S audio routing */
316 #define OPL3SAx_SYSTEM_IDSEL 0x03 /* SB compat version select */
317 #define OPL3SAx_SYSTEM_SBHE 0x80 /* 0 for AT bus, 1 for XT bus */
319 #define OPL3SAx_IRQCONF 0x03 /* Interrupt configuration (R/W */
320 #define OPL3SAx_IRQCONF_WSSA 0x01 /* WSS interrupts through IRQA */
321 #define OPL3SAx_IRQCONF_SBA 0x02 /* WSS interrupts through IRQA */
322 #define OPL3SAx_IRQCONF_MPUA 0x04 /* WSS interrupts through IRQA */
323 #define OPL3SAx_IRQCONF_OPL3A 0x08 /* WSS interrupts through IRQA */
324 #define OPL3SAx_IRQCONF_WSSB 0x10 /* WSS interrupts through IRQB */
325 #define OPL3SAx_IRQCONF_SBB 0x20 /* WSS interrupts through IRQB */
326 #define OPL3SAx_IRQCONF_MPUB 0x40 /* WSS interrupts through IRQB */
327 #define OPL3SAx_IRQCONF_OPL3B 0x80 /* WSS interrupts through IRQB */
329 #define OPL3SAx_IRQSTATUSA 0x04 /* Interrupt (IRQ-A) Status (RO) */
330 #define OPL3SAx_IRQSTATUSB 0x05 /* Interrupt (IRQ-B) Status (RO) */
331 #define OPL3SAx_IRQSTATUS_PI 0x01 /* Playback Flag of CODEC */
332 #define OPL3SAx_IRQSTATUS_CI 0x02 /* Recording Flag of CODEC */
333 #define OPL3SAx_IRQSTATUS_TI 0x04 /* Timer Flag of CODEC */
334 #define OPL3SAx_IRQSTATUS_SB 0x08 /* SB compat Playback Interrupt Flag */
335 #define OPL3SAx_IRQSTATUS_MPU 0x10 /* MPU401 Interrupt Flag */
336 #define OPL3SAx_IRQSTATUS_OPL3 0x20 /* Internal FM Timer Flag */
337 #define OPL3SAx_IRQSTATUS_MV 0x40 /* HW Volume Interrupt Flag */
338 #define OPL3SAx_IRQSTATUS_PI 0x01 /* Playback Flag of CODEC */
339 #define OPL3SAx_IRQSTATUS_CI 0x02 /* Recording Flag of CODEC */
340 #define OPL3SAx_IRQSTATUS_TI 0x04 /* Timer Flag of CODEC */
341 #define OPL3SAx_IRQSTATUS_SB 0x08 /* SB compat Playback Interrupt Flag */
342 #define OPL3SAx_IRQSTATUS_MPU 0x10 /* MPU401 Interrupt Flag */
343 #define OPL3SAx_IRQSTATUS_OPL3 0x20 /* Internal FM Timer Flag */
344 #define OPL3SAx_IRQSTATUS_MV 0x40 /* HW Volume Interrupt Flag */
346 #define OPL3SAx_DMACONF 0x06 /* DMA configuration (R/W) */
347 #define OPL3SAx_DMACONF_WSSPA 0x01 /* WSS Playback on DMA-A */
348 #define OPL3SAx_DMACONF_WSSRA 0x02 /* WSS Recording on DMA-A */
349 #define OPL3SAx_DMACONF_SBA 0x02 /* SB Playback on DMA-A */
350 #define OPL3SAx_DMACONF_WSSPB 0x10 /* WSS Playback on DMA-A */
351 #define OPL3SAx_DMACONF_WSSRB 0x20 /* WSS Recording on DMA-A */
352 #define OPL3SAx_DMACONF_SBB 0x20 /* SB Playback on DMA-A */
354 #define OPL3SAx_VOLUMEL 0x07 /* Master Volume Left (R/W) */
355 #define OPL3SAx_VOLUMEL_MVL 0x0f /* Attenuation level */
356 #define OPL3SAx_VOLUMEL_MVLM 0x80 /* Mute */
358 #define OPL3SAx_VOLUMER 0x08 /* Master Volume Right (R/W) */
359 #define OPL3SAx_VOLUMER_MVR 0x0f /* Attenuation level */
360 #define OPL3SAx_VOLUMER_MVRM 0x80 /* Mute */
362 #define OPL3SAx_MIC 0x09 /* MIC Volume (R/W) */
363 #define OPL3SAx_VOLUMER_MCV 0x1f /* Attenuation level */
364 #define OPL3SAx_VOLUMER_MICM 0x80 /* Mute */
366 #define OPL3SAx_MISC 0x0a /* Miscellaneous */
367 #define OPL3SAx_MISC_VER 0x07 /* Version */
368 #define OPL3SAx_MISC_MODE 0x08 /* SB or WSS mode */
369 #define OPL3SAx_MISC_MCSW 0x10 /* */
370 #define OPL3SAx_MISC_VEN 0x80 /* Enable hardware volume control */
372 #define OPL3SAx_WSSDMA 0x0b /* WSS DMA Counter (RW) (4 regs) */
374 #define OPL3SAx_WSSIRQSCAN 0x0f /* WSS Interrupt Scan out/in (R/W) */
375 #define OPL3SAx_WSSIRQSCAN_SPI 0x01
376 #define OPL3SAx_WSSIRQSCAN_SCI 0x02
377 #define OPL3SAx_WSSIRQSCAN_STI 0x04
379 #define OPL3SAx_SBSTATE 0x10 /* SB compat Internal State (R/W) */
380 #define OPL3SAx_SBSTATE_SBPDR 0x01 /* SB Power Down Request */
381 #define OPL3SAx_SBSTATE_SE 0x02 /* Scan Enable */
382 #define OPL3SAx_SBSTATE_SM 0x04 /* Scan Mode */
383 #define OPL3SAx_SBSTATE_SS 0x08 /* Scan Select */
384 #define OPL3SAx_SBSTATE_SBPDA 0x80 /* SB Power Down Acknowledge */
386 #define OPL3SAx_SBDATA 0x11 /* SB compat State Scan Data (R/W) */
388 #define OPL3SAx_DIGITALPOWER 0x12 /* Digital Partial Power Down (R/W) */
389 #define OPL3SAx_DIGITALPOWER_PnP 0x01
390 #define OPL3SAx_DIGITALPOWER_SB 0x02
391 #define OPL3SAx_DIGITALPOWER_WSSP 0x04
392 #define OPL3SAx_DIGITALPOWER_WSSR 0x08
393 #define OPL3SAx_DIGITALPOWER_FM 0x10
394 #define OPL3SAx_DIGITALPOWER_MCLK0 0x20
395 #define OPL3SAx_DIGITALPOWER_MPU 0x40
396 #define OPL3SAx_DIGITALPOWER_JOY 0x80
398 #define OPL3SAx_ANALOGPOWER 0x13 /* Analog Partial Power Down (R/W) */
399 #define OPL3SAx_ANALOGPOWER_WIDE 0x01
400 #define OPL3SAx_ANALOGPOWER_SBDAC 0x02
401 #define OPL3SAx_ANALOGPOWER_DA 0x04
402 #define OPL3SAx_ANALOGPOWER_AD 0x08
403 #define OPL3SAx_ANALOGPOWER_FMDAC 0x10
405 #define OPL3SAx_WIDE 0x14 /* Enhanced control(WIDE) (R/W) */
406 #define OPL3SAx_WIDE_WIDEL 0x07 /* Wide level on Left Channel */
407 #define OPL3SAx_WIDE_WIDER 0x70 /* Wide level on Right Channel */
409 #define OPL3SAx_BASS 0x15 /* Enhanced control(BASS) (R/W) */
410 #define OPL3SAx_BASS_BASSL 0x07 /* Bass level on Left Channel */
411 #define OPL3SAx_BASS_BASSR 0x70 /* Bass level on Right Channel */
413 #define OPL3SAx_TREBLE 0x16 /* Enhanced control(TREBLE) (R/W) */
414 #define OPL3SAx_TREBLE_TREBLEL 0x07 /* Treble level on Left Channel */
415 #define OPL3SAx_TREBLE_TREBLER 0x70 /* Treble level on Right Channel */
417 #define OPL3SAx_HWVOL 0x17 /* HW Volume IRQ Configuration (R/W) */
418 #define OPL3SAx_HWVOL_IRQA 0x10 /* HW Volume IRQ on IRQ-A */
419 #define OPL3SAx_HWVOL_IRQB 0x20 /* HW Volume IRQ on IRQ-B */