sys/dev/sound/pci/hda/hdac.c

   1 /*-
   2  * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca>
   3  * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org>
   4  * Copyright (c) 2008-2012 Alexander Motin <mav@FreeBSD.org>
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 /*
  30  * Intel High Definition Audio (Controller) driver for FreeBSD.
  31  */
  32
  33 #ifdef HAVE_KERNEL_OPTION_HEADERS
  34 #include "opt_snd.h"
  35 #endif
  36
  37 #include <dev/sound/pcm/sound.h>
  38 #include <dev/pci/pcireg.h>
  39 #include <dev/pci/pcivar.h>
  40
  41 #include <sys/ctype.h>
  42 #include <sys/taskqueue.h>
  43
  44 #include <dev/sound/pci/hda/hdac_private.h>
  45 #include <dev/sound/pci/hda/hdac_reg.h>
  46 #include <dev/sound/pci/hda/hda_reg.h>
  47 #include <dev/sound/pci/hda/hdac.h>
  48
  49 #define HDA_DRV_TEST_REV        "20120126_0002"
  50
  51 SND_DECLARE_FILE("$FreeBSD$");
  52
  53 #define hdac_lock(sc)           snd_mtxlock((sc)->lock)
  54 #define hdac_unlock(sc)         snd_mtxunlock((sc)->lock)
  55 #define hdac_lockassert(sc)     snd_mtxassert((sc)->lock)
  56 #define hdac_lockowned(sc)      mtx_owned((sc)->lock)
  57
  58 #define HDAC_QUIRK_64BIT        (1 << 0)
  59 #define HDAC_QUIRK_DMAPOS       (1 << 1)
  60 #define HDAC_QUIRK_MSI          (1 << 2)
  61
  62 static const struct {
  63         char *key;
  64         uint32_t value;
  65 } hdac_quirks_tab[] = {
  66         { "64bit", HDAC_QUIRK_DMAPOS },
  67         { "dmapos", HDAC_QUIRK_DMAPOS },
  68         { "msi", HDAC_QUIRK_MSI },
  69 };
  70 #define HDAC_QUIRKS_TAB_LEN     \
  71                 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0]))
  72
  73 MALLOC_DEFINE(M_HDAC, "hdac", "HDA Controller");
  74
  75 static const struct {
  76         uint32_t        model;
  77         char            *desc;
  78         char            quirks_on;
  79         char            quirks_off;
  80 } hdac_devices[] = {
  81         { HDA_INTEL_CPT,     "Intel Cougar Point",      0, 0 },
  82         { HDA_INTEL_PATSBURG,"Intel Patsburg",  0, 0 },
  83         { HDA_INTEL_PPT1,    "Intel Panther Point",     0, 0 },
  84         { HDA_INTEL_82801F,  "Intel 82801F",    0, 0 },
  85         { HDA_INTEL_63XXESB, "Intel 631x/632xESB",      0, 0 },
  86         { HDA_INTEL_82801G,  "Intel 82801G",    0, 0 },
  87         { HDA_INTEL_82801H,  "Intel 82801H",    0, 0 },
  88         { HDA_INTEL_82801I,  "Intel 82801I",    0, 0 },
  89         { HDA_INTEL_82801JI, "Intel 82801JI",   0, 0 },
  90         { HDA_INTEL_82801JD, "Intel 82801JD",   0, 0 },
  91         { HDA_INTEL_PCH,     "Intel 5 Series/3400 Series",      0, 0 },
  92         { HDA_INTEL_PCH2,    "Intel 5 Series/3400 Series",      0, 0 },
  93         { HDA_INTEL_SCH,     "Intel SCH",       0, 0 },
  94         { HDA_NVIDIA_MCP51,  "NVIDIA MCP51",    0, HDAC_QUIRK_MSI },
  95         { HDA_NVIDIA_MCP55,  "NVIDIA MCP55",    0, HDAC_QUIRK_MSI },
  96         { HDA_NVIDIA_MCP61_1, "NVIDIA MCP61",   0, 0 },
  97         { HDA_NVIDIA_MCP61_2, "NVIDIA MCP61",   0, 0 },
  98         { HDA_NVIDIA_MCP65_1, "NVIDIA MCP65",   0, 0 },
  99         { HDA_NVIDIA_MCP65_2, "NVIDIA MCP65",   0, 0 },
 100         { HDA_NVIDIA_MCP67_1, "NVIDIA MCP67",   0, 0 },
 101         { HDA_NVIDIA_MCP67_2, "NVIDIA MCP67",   0, 0 },
 102         { HDA_NVIDIA_MCP73_1, "NVIDIA MCP73",   0, 0 },
 103         { HDA_NVIDIA_MCP73_2, "NVIDIA MCP73",   0, 0 },
 104         { HDA_NVIDIA_MCP78_1, "NVIDIA MCP78",   0, HDAC_QUIRK_64BIT },
 105         { HDA_NVIDIA_MCP78_2, "NVIDIA MCP78",   0, HDAC_QUIRK_64BIT },
 106         { HDA_NVIDIA_MCP78_3, "NVIDIA MCP78",   0, HDAC_QUIRK_64BIT },
 107         { HDA_NVIDIA_MCP78_4, "NVIDIA MCP78",   0, HDAC_QUIRK_64BIT },
 108         { HDA_NVIDIA_MCP79_1, "NVIDIA MCP79",   0, 0 },
 109         { HDA_NVIDIA_MCP79_2, "NVIDIA MCP79",   0, 0 },
 110         { HDA_NVIDIA_MCP79_3, "NVIDIA MCP79",   0, 0 },
 111         { HDA_NVIDIA_MCP79_4, "NVIDIA MCP79",   0, 0 },
 112         { HDA_NVIDIA_MCP89_1, "NVIDIA MCP89",   0, 0 },
 113         { HDA_NVIDIA_MCP89_2, "NVIDIA MCP89",   0, 0 },
 114         { HDA_NVIDIA_MCP89_3, "NVIDIA MCP89",   0, 0 },
 115         { HDA_NVIDIA_MCP89_4, "NVIDIA MCP89",   0, 0 },
 116         { HDA_NVIDIA_0BE2,   "NVIDIA (0x0be2)", 0, HDAC_QUIRK_MSI },
 117         { HDA_NVIDIA_0BE3,   "NVIDIA (0x0be3)", 0, HDAC_QUIRK_MSI },
 118         { HDA_NVIDIA_0BE4,   "NVIDIA (0x0be4)", 0, HDAC_QUIRK_MSI },
 119         { HDA_NVIDIA_GT100,  "NVIDIA GT100",    0, HDAC_QUIRK_MSI },
 120         { HDA_NVIDIA_GT104,  "NVIDIA GT104",    0, HDAC_QUIRK_MSI },
 121         { HDA_NVIDIA_GT106,  "NVIDIA GT106",    0, HDAC_QUIRK_MSI },
 122         { HDA_NVIDIA_GT108,  "NVIDIA GT108",    0, HDAC_QUIRK_MSI },
 123         { HDA_NVIDIA_GT116,  "NVIDIA GT116",    0, HDAC_QUIRK_MSI },
 124         { HDA_NVIDIA_GF119,  "NVIDIA GF119",    0, 0 },
 125         { HDA_NVIDIA_GF110_1, "NVIDIA GF110",   0, HDAC_QUIRK_MSI },
 126         { HDA_NVIDIA_GF110_2, "NVIDIA GF110",   0, HDAC_QUIRK_MSI },
 127         { HDA_ATI_SB450,     "ATI SB450",       0, 0 },
 128         { HDA_ATI_SB600,     "ATI SB600",       0, 0 },
 129         { HDA_ATI_RS600,     "ATI RS600",       0, 0 },
 130         { HDA_ATI_RS690,     "ATI RS690",       0, 0 },
 131         { HDA_ATI_RS780,     "ATI RS780",       0, 0 },
 132         { HDA_ATI_R600,      "ATI R600",        0, 0 },
 133         { HDA_ATI_RV610,     "ATI RV610",       0, 0 },
 134         { HDA_ATI_RV620,     "ATI RV620",       0, 0 },
 135         { HDA_ATI_RV630,     "ATI RV630",       0, 0 },
 136         { HDA_ATI_RV635,     "ATI RV635",       0, 0 },
 137         { HDA_ATI_RV710,     "ATI RV710",       0, 0 },
 138         { HDA_ATI_RV730,     "ATI RV730",       0, 0 },
 139         { HDA_ATI_RV740,     "ATI RV740",       0, 0 },
 140         { HDA_ATI_RV770,     "ATI RV770",       0, 0 },
 141         { HDA_RDC_M3010,     "RDC M3010",       0, 0 },
 142         { HDA_VIA_VT82XX,    "VIA VT8251/8237A",0, 0 },
 143         { HDA_SIS_966,       "SiS 966",         0, 0 },
 144         { HDA_ULI_M5461,     "ULI M5461",       0, 0 },
 145         /* Unknown */
 146         { HDA_INTEL_ALL,  "Intel",              0, 0 },
 147         { HDA_NVIDIA_ALL, "NVIDIA",             0, 0 },
 148         { HDA_ATI_ALL,    "ATI",                0, 0 },
 149         { HDA_VIA_ALL,    "VIA",                0, 0 },
 150         { HDA_SIS_ALL,    "SiS",                0, 0 },
 151         { HDA_ULI_ALL,    "ULI",                0, 0 },
 152 };
 153 #define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0]))
 154
 155 static const struct {
 156         uint16_t vendor;
 157         uint8_t reg;
 158         uint8_t mask;
 159         uint8_t enable;
 160 } hdac_pcie_snoop[] = {
 161         {  INTEL_VENDORID, 0x00, 0x00, 0x00 },
 162         {    ATI_VENDORID, 0x42, 0xf8, 0x02 },
 163         { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f },
 164 };
 165 #define HDAC_PCIESNOOP_LEN      \
 166                         (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0]))
 167
 168 /****************************************************************************
 169  * Function prototypes
 170  ****************************************************************************/
 171 static void     hdac_intr_handler(void *);
 172 static int      hdac_reset(struct hdac_softc *, int);
 173 static int      hdac_get_capabilities(struct hdac_softc *);
 174 static void     hdac_dma_cb(void *, bus_dma_segment_t *, int, int);
 175 static int      hdac_dma_alloc(struct hdac_softc *,
 176                                         struct hdac_dma *, bus_size_t);
 177 static void     hdac_dma_free(struct hdac_softc *, struct hdac_dma *);
 178 static int      hdac_mem_alloc(struct hdac_softc *);
 179 static void     hdac_mem_free(struct hdac_softc *);
 180 static int      hdac_irq_alloc(struct hdac_softc *);
 181 static void     hdac_irq_free(struct hdac_softc *);
 182 static void     hdac_corb_init(struct hdac_softc *);
 183 static void     hdac_rirb_init(struct hdac_softc *);
 184 static void     hdac_corb_start(struct hdac_softc *);
 185 static void     hdac_rirb_start(struct hdac_softc *);
 186
 187 static void     hdac_attach2(void *);
 188
 189 static uint32_t hdac_send_command(struct hdac_softc *, nid_t, uint32_t);
 190
 191 static int      hdac_probe(device_t);
 192 static int      hdac_attach(device_t);
 193 static int      hdac_detach(device_t);
 194 static int      hdac_suspend(device_t);
 195 static int      hdac_resume(device_t);
 196
 197 static int      hdac_rirb_flush(struct hdac_softc *sc);
 198 static int      hdac_unsolq_flush(struct hdac_softc *sc);
 199
 200 #define hdac_command(a1, a2, a3)        \
 201                 hdac_send_command(a1, a3, a2)
 202
 203 /* This function surely going to make its way into upper level someday. */
 204 static void
 205 hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off)
 206 {
 207         const char *res = NULL;
 208         int i = 0, j, k, len, inv;
 209
 210         if (resource_string_value(device_get_name(sc->dev),
 211             device_get_unit(sc->dev), "config", &res) != 0)
 212                 return;
 213         if (!(res != NULL && strlen(res) > 0))
 214                 return;
 215         HDA_BOOTVERBOSE(
 216                 device_printf(sc->dev, "Config options:");
 217         );
 218         for (;;) {
 219                 while (res[i] != '\0' &&
 220                     (res[i] == ',' || isspace(res[i]) != 0))
 221                         i++;
 222                 if (res[i] == '\0') {
 223                         HDA_BOOTVERBOSE(
 224                                 printf("\n");
 225                         );
 226                         return;
 227                 }
 228                 j = i;
 229                 while (res[j] != '\0' &&
 230                     !(res[j] == ',' || isspace(res[j]) != 0))
 231                         j++;
 232                 len = j - i;
 233                 if (len > 2 && strncmp(res + i, "no", 2) == 0)
 234                         inv = 2;
 235                 else
 236                         inv = 0;
 237                 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) {
 238                         if (strncmp(res + i + inv,
 239                             hdac_quirks_tab[k].key, len - inv) != 0)
 240                                 continue;
 241                         if (len - inv != strlen(hdac_quirks_tab[k].key))
 242                                 continue;
 243                         HDA_BOOTVERBOSE(
 244                                 printf(" %s%s", (inv != 0) ? "no" : "",
 245                                     hdac_quirks_tab[k].key);
 246                         );
 247                         if (inv == 0) {
 248                                 *on |= hdac_quirks_tab[k].value;
 249                                 *on &= ~hdac_quirks_tab[k].value;
 250                         } else if (inv != 0) {
 251                                 *off |= hdac_quirks_tab[k].value;
 252                                 *off &= ~hdac_quirks_tab[k].value;
 253                         }
 254                         break;
 255                 }
 256                 i = j;
 257         }
 258 }
 259
 260 /****************************************************************************
 261  * void hdac_intr_handler(void *)
 262  *
 263  * Interrupt handler. Processes interrupts received from the hdac.
 264  ****************************************************************************/
 265 static void
 266 hdac_intr_handler(void *context)
 267 {
 268         struct hdac_softc *sc;
 269         device_t dev;
 270         uint32_t intsts;
 271         uint8_t rirbsts;
 272         int i;
 273
 274         sc = (struct hdac_softc *)context;
 275         hdac_lock(sc);
 276
 277         /* Do we have anything to do? */
 278         intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS);
 279         if ((intsts & HDAC_INTSTS_GIS) == 0) {
 280                 hdac_unlock(sc);
 281                 return;
 282         }
 283
 284         /* Was this a controller interrupt? */
 285         if (intsts & HDAC_INTSTS_CIS) {
 286                 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
 287                 /* Get as many responses that we can */
 288                 while (rirbsts & HDAC_RIRBSTS_RINTFL) {
 289                         HDAC_WRITE_1(&sc->mem,
 290                             HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL);
 291                         hdac_rirb_flush(sc);
 292                         rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
 293                 }
 294                 if (sc->unsolq_rp != sc->unsolq_wp)
 295                         taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task);
 296         }
 297
 298         if (intsts & HDAC_INTSTS_SIS_MASK) {
 299                 for (i = 0; i < sc->num_ss; i++) {
 300                         if ((intsts & (1 << i)) == 0)
 301                                 continue;
 302                         HDAC_WRITE_1(&sc->mem, (i << 5) + HDAC_SDSTS,
 303                             HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS );
 304                         if ((dev = sc->streams[i].dev) != NULL) {
 305                                 HDAC_STREAM_INTR(dev,
 306                                     sc->streams[i].dir, sc->streams[i].stream);
 307                         }
 308                 }
 309         }
 310
 311         HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts);
 312         hdac_unlock(sc);
 313 }
 314
 315 static void
 316 hdac_poll_callback(void *arg)
 317 {
 318         struct hdac_softc *sc = arg;
 319
 320         if (sc == NULL)
 321                 return;
 322
 323         hdac_lock(sc);
 324         if (sc->polling == 0) {
 325                 hdac_unlock(sc);
 326                 return;
 327         }
 328         callout_reset(&sc->poll_callout, sc->poll_ival,
 329             hdac_poll_callback, sc);
 330         hdac_unlock(sc);
 331
 332         hdac_intr_handler(sc);
 333 }
 334
 335 /****************************************************************************
 336  * int hdac_reset(hdac_softc *, int)
 337  *
 338  * Reset the hdac to a quiescent and known state.
 339  ****************************************************************************/
 340 static int
 341 hdac_reset(struct hdac_softc *sc, int wakeup)
 342 {
 343         uint32_t gctl;
 344         int count, i;
 345
 346         /*
 347          * Stop all Streams DMA engine
 348          */
 349         for (i = 0; i < sc->num_iss; i++)
 350                 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0);
 351         for (i = 0; i < sc->num_oss; i++)
 352                 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0);
 353         for (i = 0; i < sc->num_bss; i++)
 354                 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0);
 355
 356         /*
 357          * Stop Control DMA engines.
 358          */
 359         HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0);
 360         HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0);
 361
 362         /*
 363          * Reset DMA position buffer.
 364          */
 365         HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0);
 366         HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0);
 367
 368         /*
 369          * Reset the controller. The reset must remain asserted for
 370          * a minimum of 100us.
 371          */
 372         gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
 373         HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST);
 374         count = 10000;
 375         do {
 376                 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
 377                 if (!(gctl & HDAC_GCTL_CRST))
 378                         break;
 379                 DELAY(10);
 380         } while (--count);
 381         if (gctl & HDAC_GCTL_CRST) {
 382                 device_printf(sc->dev, "Unable to put hdac in reset\n");
 383                 return (ENXIO);
 384         }
 385
 386         /* If wakeup is not requested - leave the controller in reset state. */
 387         if (!wakeup)
 388                 return (0);
 389
 390         DELAY(100);
 391         gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
 392         HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST);
 393         count = 10000;
 394         do {
 395                 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
 396                 if (gctl & HDAC_GCTL_CRST)
 397                         break;
 398                 DELAY(10);
 399         } while (--count);
 400         if (!(gctl & HDAC_GCTL_CRST)) {
 401                 device_printf(sc->dev, "Device stuck in reset\n");
 402                 return (ENXIO);
 403         }
 404
 405         /*
 406          * Wait for codecs to finish their own reset sequence. The delay here
 407          * should be of 250us but for some reasons, on it's not enough on my
 408          * computer. Let's use twice as much as necessary to make sure that
 409          * it's reset properly.
 410          */
 411         DELAY(1000);
 412
 413         return (0);
 414 }
 415
 416
 417 /****************************************************************************
 418  * int hdac_get_capabilities(struct hdac_softc *);
 419  *
 420  * Retreive the general capabilities of the hdac;
 421  *      Number of Input Streams
 422  *      Number of Output Streams
 423  *      Number of bidirectional Streams
 424  *      64bit ready
 425  *      CORB and RIRB sizes
 426  ****************************************************************************/
 427 static int
 428 hdac_get_capabilities(struct hdac_softc *sc)
 429 {
 430         uint16_t gcap;
 431         uint8_t corbsize, rirbsize;
 432
 433         gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP);
 434         sc->num_iss = HDAC_GCAP_ISS(gcap);
 435         sc->num_oss = HDAC_GCAP_OSS(gcap);
 436         sc->num_bss = HDAC_GCAP_BSS(gcap);
 437         sc->num_ss = sc->num_iss + sc->num_oss + sc->num_bss;
 438         sc->num_sdo = HDAC_GCAP_NSDO(gcap);
 439         sc->support_64bit = (gcap & HDAC_GCAP_64OK) != 0;
 440         if (sc->quirks_on & HDAC_QUIRK_64BIT)
 441                 sc->support_64bit = 1;
 442         else if (sc->quirks_off & HDAC_QUIRK_64BIT)
 443                 sc->support_64bit = 0;
 444
 445         corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE);
 446         if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) ==
 447             HDAC_CORBSIZE_CORBSZCAP_256)
 448                 sc->corb_size = 256;
 449         else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) ==
 450             HDAC_CORBSIZE_CORBSZCAP_16)
 451                 sc->corb_size = 16;
 452         else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) ==
 453             HDAC_CORBSIZE_CORBSZCAP_2)
 454                 sc->corb_size = 2;
 455         else {
 456                 device_printf(sc->dev, "%s: Invalid corb size (%x)\n",
 457                     __func__, corbsize);
 458                 return (ENXIO);
 459         }
 460
 461         rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE);
 462         if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) ==
 463             HDAC_RIRBSIZE_RIRBSZCAP_256)
 464                 sc->rirb_size = 256;
 465         else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) ==
 466             HDAC_RIRBSIZE_RIRBSZCAP_16)
 467                 sc->rirb_size = 16;
 468         else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) ==
 469             HDAC_RIRBSIZE_RIRBSZCAP_2)
 470                 sc->rirb_size = 2;
 471         else {
 472                 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n",
 473                     __func__, rirbsize);
 474                 return (ENXIO);
 475         }
 476
 477         HDA_BOOTVERBOSE(
 478                 device_printf(sc->dev, "Caps: OSS %d, ISS %d, BSS %d, "
 479                     "NSDO %d%s, CORB %d, RIRB %d\n",
 480                     sc->num_oss, sc->num_iss, sc->num_bss, 1 << sc->num_sdo,
 481                     sc->support_64bit ? ", 64bit" : "",
 482                     sc->corb_size, sc->rirb_size);
 483         );
 484
 485         return (0);
 486 }
 487
 488
 489 /****************************************************************************
 490  * void hdac_dma_cb
 491  *
 492  * This function is called by bus_dmamap_load when the mapping has been
 493  * established. We just record the physical address of the mapping into
 494  * the struct hdac_dma passed in.
 495  ****************************************************************************/
 496 static void
 497 hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error)
 498 {
 499         struct hdac_dma *dma;
 500
 501         if (error == 0) {
 502                 dma = (struct hdac_dma *)callback_arg;
 503                 dma->dma_paddr = segs[0].ds_addr;
 504         }
 505 }
 506
 507
 508 /****************************************************************************
 509  * int hdac_dma_alloc
 510  *
 511  * This function allocate and setup a dma region (struct hdac_dma).
 512  * It must be freed by a corresponding hdac_dma_free.
 513  ****************************************************************************/
 514 static int
 515 hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size)
 516 {
 517         bus_size_t roundsz;
 518         int result;
 519
 520         roundsz = roundup2(size, HDA_DMA_ALIGNMENT);
 521         bzero(dma, sizeof(*dma));
 522
 523         /*
 524          * Create a DMA tag
 525          */
 526         result = bus_dma_tag_create(
 527             bus_get_dma_tag(sc->dev),           /* parent */
 528             HDA_DMA_ALIGNMENT,                  /* alignment */
 529             0,                                  /* boundary */
 530             (sc->support_64bit) ? BUS_SPACE_MAXADDR :
 531                 BUS_SPACE_MAXADDR_32BIT,        /* lowaddr */
 532             BUS_SPACE_MAXADDR,                  /* highaddr */
 533             NULL,                               /* filtfunc */
 534             NULL,                               /* fistfuncarg */
 535             roundsz,                            /* maxsize */
 536             1,                                  /* nsegments */
 537             roundsz,                            /* maxsegsz */
 538             0,                                  /* flags */
 539             NULL,                               /* lockfunc */
 540             NULL,                               /* lockfuncarg */
 541             &dma->dma_tag);                     /* dmat */
 542         if (result != 0) {
 543                 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n",
 544                     __func__, result);
 545                 goto hdac_dma_alloc_fail;
 546         }
 547
 548         /*
 549          * Allocate DMA memory
 550          */
 551         result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr,
 552             BUS_DMA_NOWAIT | BUS_DMA_ZERO |
 553             ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0),
 554             &dma->dma_map);
 555         if (result != 0) {
 556                 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n",
 557                     __func__, result);
 558                 goto hdac_dma_alloc_fail;
 559         }
 560
 561         dma->dma_size = roundsz;
 562
 563         /*
 564          * Map the memory
 565          */
 566         result = bus_dmamap_load(dma->dma_tag, dma->dma_map,
 567             (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0);
 568         if (result != 0 || dma->dma_paddr == 0) {
 569                 if (result == 0)
 570                         result = ENOMEM;
 571                 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n",
 572                     __func__, result);
 573                 goto hdac_dma_alloc_fail;
 574         }
 575
 576         HDA_BOOTHVERBOSE(
 577                 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n",
 578                     __func__, (uintmax_t)size, (uintmax_t)roundsz);
 579         );
 580
 581         return (0);
 582
 583 hdac_dma_alloc_fail:
 584         hdac_dma_free(sc, dma);
 585
 586         return (result);
 587 }
 588
 589
 590 /****************************************************************************
 591  * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *)
 592  *
 593  * Free a struct dhac_dma that has been previously allocated via the
 594  * hdac_dma_alloc function.
 595  ****************************************************************************/
 596 static void
 597 hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma)
 598 {
 599         if (dma->dma_map != NULL) {
 600 #if 0
 601                 /* Flush caches */
 602                 bus_dmamap_sync(dma->dma_tag, dma->dma_map,
 603                     BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
 604 #endif
 605                 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
 606         }
 607         if (dma->dma_vaddr != NULL) {
 608                 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
 609                 dma->dma_vaddr = NULL;
 610         }
 611         dma->dma_map = NULL;
 612         if (dma->dma_tag != NULL) {
 613                 bus_dma_tag_destroy(dma->dma_tag);
 614                 dma->dma_tag = NULL;
 615         }
 616         dma->dma_size = 0;
 617 }
 618
 619 /****************************************************************************
 620  * int hdac_mem_alloc(struct hdac_softc *)
 621  *
 622  * Allocate all the bus resources necessary to speak with the physical
 623  * controller.
 624  ****************************************************************************/
 625 static int
 626 hdac_mem_alloc(struct hdac_softc *sc)
 627 {
 628         struct hdac_mem *mem;
 629
 630         mem = &sc->mem;
 631         mem->mem_rid = PCIR_BAR(0);
 632         mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
 633             &mem->mem_rid, RF_ACTIVE);
 634         if (mem->mem_res == NULL) {
 635                 device_printf(sc->dev,
 636                     "%s: Unable to allocate memory resource\n", __func__);
 637                 return (ENOMEM);
 638         }
 639         mem->mem_tag = rman_get_bustag(mem->mem_res);
 640         mem->mem_handle = rman_get_bushandle(mem->mem_res);
 641
 642         return (0);
 643 }
 644
 645 /****************************************************************************
 646  * void hdac_mem_free(struct hdac_softc *)
 647  *
 648  * Free up resources previously allocated by hdac_mem_alloc.
 649  ****************************************************************************/
 650 static void
 651 hdac_mem_free(struct hdac_softc *sc)
 652 {
 653         struct hdac_mem *mem;
 654
 655         mem = &sc->mem;
 656         if (mem->mem_res != NULL)
 657                 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid,
 658                     mem->mem_res);
 659         mem->mem_res = NULL;
 660 }
 661
 662 /****************************************************************************
 663  * int hdac_irq_alloc(struct hdac_softc *)
 664  *
 665  * Allocate and setup the resources necessary for interrupt handling.
 666  ****************************************************************************/
 667 static int
 668 hdac_irq_alloc(struct hdac_softc *sc)
 669 {
 670         struct hdac_irq *irq;
 671         int result;
 672
 673         irq = &sc->irq;
 674         irq->irq_rid = 0x0;
 675
 676         if ((sc->quirks_off & HDAC_QUIRK_MSI) == 0 &&
 677             (result = pci_msi_count(sc->dev)) == 1 &&
 678             pci_alloc_msi(sc->dev, &result) == 0)
 679                 irq->irq_rid = 0x1;
 680
 681         irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
 682             &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE);
 683         if (irq->irq_res == NULL) {
 684                 device_printf(sc->dev, "%s: Unable to allocate irq\n",
 685                     __func__);
 686                 goto hdac_irq_alloc_fail;
 687         }
 688         result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV,
 689             NULL, hdac_intr_handler, sc, &irq->irq_handle);
 690         if (result != 0) {
 691                 device_printf(sc->dev,
 692                     "%s: Unable to setup interrupt handler (%x)\n",
 693                     __func__, result);
 694                 goto hdac_irq_alloc_fail;
 695         }
 696
 697         return (0);
 698
 699 hdac_irq_alloc_fail:
 700         hdac_irq_free(sc);
 701
 702         return (ENXIO);
 703 }
 704
 705 /****************************************************************************
 706  * void hdac_irq_free(struct hdac_softc *)
 707  *
 708  * Free up resources previously allocated by hdac_irq_alloc.
 709  ****************************************************************************/
 710 static void
 711 hdac_irq_free(struct hdac_softc *sc)
 712 {
 713         struct hdac_irq *irq;
 714
 715         irq = &sc->irq;
 716         if (irq->irq_res != NULL && irq->irq_handle != NULL)
 717                 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle);
 718         if (irq->irq_res != NULL)
 719                 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid,
 720                     irq->irq_res);
 721         if (irq->irq_rid == 0x1)
 722                 pci_release_msi(sc->dev);
 723         irq->irq_handle = NULL;
 724         irq->irq_res = NULL;
 725         irq->irq_rid = 0x0;
 726 }
 727
 728 /****************************************************************************
 729  * void hdac_corb_init(struct hdac_softc *)
 730  *
 731  * Initialize the corb registers for operations but do not start it up yet.
 732  * The CORB engine must not be running when this function is called.
 733  ****************************************************************************/
 734 static void
 735 hdac_corb_init(struct hdac_softc *sc)
 736 {
 737         uint8_t corbsize;
 738         uint64_t corbpaddr;
 739
 740         /* Setup the CORB size. */
 741         switch (sc->corb_size) {
 742         case 256:
 743                 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256);
 744                 break;
 745         case 16:
 746                 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16);
 747                 break;
 748         case 2:
 749                 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2);
 750                 break;
 751         default:
 752                 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size);
 753         }
 754         HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize);
 755
 756         /* Setup the CORB Address in the hdac */
 757         corbpaddr = (uint64_t)sc->corb_dma.dma_paddr;
 758         HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr);
 759         HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32));
 760
 761         /* Set the WP and RP */
 762         sc->corb_wp = 0;
 763         HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp);
 764         HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST);
 765         /*
 766          * The HDA specification indicates that the CORBRPRST bit will always
 767          * read as zero. Unfortunately, it seems that at least the 82801G
 768          * doesn't reset the bit to zero, which stalls the corb engine.
 769          * manually reset the bit to zero before continuing.
 770          */
 771         HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0);
 772
 773         /* Enable CORB error reporting */
 774 #if 0
 775         HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE);
 776 #endif
 777 }
 778
 779 /****************************************************************************
 780  * void hdac_rirb_init(struct hdac_softc *)
 781  *
 782  * Initialize the rirb registers for operations but do not start it up yet.
 783  * The RIRB engine must not be running when this function is called.
 784  ****************************************************************************/
 785 static void
 786 hdac_rirb_init(struct hdac_softc *sc)
 787 {
 788         uint8_t rirbsize;
 789         uint64_t rirbpaddr;
 790
 791         /* Setup the RIRB size. */
 792         switch (sc->rirb_size) {
 793         case 256:
 794                 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256);
 795                 break;
 796         case 16:
 797                 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16);
 798                 break;
 799         case 2:
 800                 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2);
 801                 break;
 802         default:
 803                 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size);
 804         }
 805         HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize);
 806
 807         /* Setup the RIRB Address in the hdac */
 808         rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr;
 809         HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr);
 810         HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32));
 811
 812         /* Setup the WP and RP */
 813         sc->rirb_rp = 0;
 814         HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST);
 815
 816         /* Setup the interrupt threshold */
 817         HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2);
 818
 819         /* Enable Overrun and response received reporting */
 820 #if 0
 821         HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL,
 822             HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL);
 823 #else
 824         HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL);
 825 #endif
 826
 827 #if 0
 828         /*
 829          * Make sure that the Host CPU cache doesn't contain any dirty
 830          * cache lines that falls in the rirb. If I understood correctly, it
 831          * should be sufficient to do this only once as the rirb is purely
 832          * read-only from now on.
 833          */
 834         bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
 835             BUS_DMASYNC_PREREAD);
 836 #endif
 837 }
 838
 839 /****************************************************************************
 840  * void hdac_corb_start(hdac_softc *)
 841  *
 842  * Startup the corb DMA engine
 843  ****************************************************************************/
 844 static void
 845 hdac_corb_start(struct hdac_softc *sc)
 846 {
 847         uint32_t corbctl;
 848
 849         corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL);
 850         corbctl |= HDAC_CORBCTL_CORBRUN;
 851         HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl);
 852 }
 853
 854 /****************************************************************************
 855  * void hdac_rirb_start(hdac_softc *)
 856  *
 857  * Startup the rirb DMA engine
 858  ****************************************************************************/
 859 static void
 860 hdac_rirb_start(struct hdac_softc *sc)
 861 {
 862         uint32_t rirbctl;
 863
 864         rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL);
 865         rirbctl |= HDAC_RIRBCTL_RIRBDMAEN;
 866         HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl);
 867 }
 868
 869 static int
 870 hdac_rirb_flush(struct hdac_softc *sc)
 871 {
 872         struct hdac_rirb *rirb_base, *rirb;
 873         nid_t cad;
 874         uint32_t resp;
 875         uint8_t rirbwp;
 876         int ret;
 877
 878         rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
 879         rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP);
 880 #if 0
 881         bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
 882             BUS_DMASYNC_POSTREAD);
 883 #endif
 884
 885         ret = 0;
 886         while (sc->rirb_rp != rirbwp) {
 887                 sc->rirb_rp++;
 888                 sc->rirb_rp %= sc->rirb_size;
 889                 rirb = &rirb_base[sc->rirb_rp];
 890                 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex);
 891                 resp = rirb->response;
 892                 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) {
 893                         sc->unsolq[sc->unsolq_wp++] = resp;
 894                         sc->unsolq_wp %= HDAC_UNSOLQ_MAX;
 895                         sc->unsolq[sc->unsolq_wp++] = cad;
 896                         sc->unsolq_wp %= HDAC_UNSOLQ_MAX;
 897                 } else if (sc->codecs[cad].pending <= 0) {
 898                         device_printf(sc->dev, "Unexpected unsolicited "
 899                             "response from address %d: %08x\n", cad, resp);
 900                 } else {
 901                         sc->codecs[cad].response = resp;
 902                         sc->codecs[cad].pending--;
 903                 }
 904                 ret++;
 905         }
 906         return (ret);
 907 }
 908
 909 static int
 910 hdac_unsolq_flush(struct hdac_softc *sc)
 911 {
 912         device_t child;
 913         nid_t cad;
 914         uint32_t resp;
 915         int ret = 0;
 916
 917         if (sc->unsolq_st == HDAC_UNSOLQ_READY) {
 918                 sc->unsolq_st = HDAC_UNSOLQ_BUSY;
 919                 while (sc->unsolq_rp != sc->unsolq_wp) {
 920                         resp = sc->unsolq[sc->unsolq_rp++];
 921                         sc->unsolq_rp %= HDAC_UNSOLQ_MAX;
 922                         cad = sc->unsolq[sc->unsolq_rp++];
 923                         sc->unsolq_rp %= HDAC_UNSOLQ_MAX;
 924                         if ((child = sc->codecs[cad].dev) != NULL)
 925                                 HDAC_UNSOL_INTR(child, resp);
 926                         ret++;
 927                 }
 928                 sc->unsolq_st = HDAC_UNSOLQ_READY;
 929         }
 930
 931         return (ret);
 932 }
 933
 934 /****************************************************************************
 935  * uint32_t hdac_command_sendone_internal
 936  *
 937  * Wrapper function that sends only one command to a given codec
 938  ****************************************************************************/
 939 static uint32_t
 940 hdac_send_command(struct hdac_softc *sc, nid_t cad, uint32_t verb)
 941 {
 942         int timeout;
 943         uint32_t *corb;
 944
 945         if (!hdac_lockowned(sc))
 946                 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n");
 947         verb &= ~HDA_CMD_CAD_MASK;
 948         verb |= ((uint32_t)cad) << HDA_CMD_CAD_SHIFT;
 949         sc->codecs[cad].response = HDA_INVALID;
 950
 951         sc->codecs[cad].pending++;
 952         sc->corb_wp++;
 953         sc->corb_wp %= sc->corb_size;
 954         corb = (uint32_t *)sc->corb_dma.dma_vaddr;
 955 #if 0
 956         bus_dmamap_sync(sc->corb_dma.dma_tag,
 957             sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE);
 958 #endif
 959         corb[sc->corb_wp] = verb;
 960 #if 0
 961         bus_dmamap_sync(sc->corb_dma.dma_tag,
 962             sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE);
 963 #endif
 964         HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp);
 965
 966         timeout = 10000;
 967         do {
 968                 if (hdac_rirb_flush(sc) == 0)
 969                         DELAY(10);
 970         } while (sc->codecs[cad].pending != 0 && --timeout);
 971
 972         if (sc->codecs[cad].pending != 0) {
 973                 device_printf(sc->dev, "Command timeout on address %d\n", cad);
 974                 sc->codecs[cad].pending = 0;
 975         }
 976
 977         if (sc->unsolq_rp != sc->unsolq_wp)
 978                 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task);
 979         return (sc->codecs[cad].response);
 980 }
 981
 982 /****************************************************************************
 983  * Device Methods
 984  ****************************************************************************/
 985
 986 /****************************************************************************
 987  * int hdac_probe(device_t)
 988  *
 989  * Probe for the presence of an hdac. If none is found, check for a generic
 990  * match using the subclass of the device.
 991  ****************************************************************************/
 992 static int
 993 hdac_probe(device_t dev)
 994 {
 995         int i, result;
 996         uint32_t model;
 997         uint16_t class, subclass;
 998         char desc[64];
 999
1000         model = (uint32_t)pci_get_device(dev) << 16;
1001         model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
1002         class = pci_get_class(dev);
1003         subclass = pci_get_subclass(dev);
1004
1005         bzero(desc, sizeof(desc));
1006         result = ENXIO;
1007         for (i = 0; i < HDAC_DEVICES_LEN; i++) {
1008                 if (hdac_devices[i].model == model) {
1009                         strlcpy(desc, hdac_devices[i].desc, sizeof(desc));
1010                         result = BUS_PROBE_DEFAULT;
1011                         break;
1012                 }
1013                 if (HDA_DEV_MATCH(hdac_devices[i].model, model) &&
1014                     class == PCIC_MULTIMEDIA &&
1015                     subclass == PCIS_MULTIMEDIA_HDA) {
1016                         snprintf(desc, sizeof(desc),
1017                             "%s (0x%04x)",
1018                             hdac_devices[i].desc, pci_get_device(dev));
1019                         result = BUS_PROBE_GENERIC;
1020                         break;
1021                 }
1022         }
1023         if (result == ENXIO && class == PCIC_MULTIMEDIA &&
1024             subclass == PCIS_MULTIMEDIA_HDA) {
1025                 snprintf(desc, sizeof(desc), "Generic (0x%08x)", model);
1026                 result = BUS_PROBE_GENERIC;
1027         }
1028         if (result != ENXIO) {
1029                 strlcat(desc, " HDA Controller", sizeof(desc));
1030                 device_set_desc_copy(dev, desc);
1031         }
1032
1033         return (result);
1034 }
1035
1036 static void
1037 hdac_unsolq_task(void *context, int pending)
1038 {
1039         struct hdac_softc *sc;
1040
1041         sc = (struct hdac_softc *)context;
1042
1043         hdac_lock(sc);
1044         hdac_unsolq_flush(sc);
1045         hdac_unlock(sc);
1046 }
1047
1048 /****************************************************************************
1049  * int hdac_attach(device_t)
1050  *
1051  * Attach the device into the kernel. Interrupts usually won't be enabled
1052  * when this function is called. Setup everything that doesn't require
1053  * interrupts and defer probing of codecs until interrupts are enabled.
1054  ****************************************************************************/
1055 static int
1056 hdac_attach(device_t dev)
1057 {
1058         struct hdac_softc *sc;
1059         int result;
1060         int i, devid = -1;
1061         uint32_t model;
1062         uint16_t class, subclass;
1063         uint16_t vendor;
1064         uint8_t v;
1065
1066         sc = device_get_softc(dev);
1067         HDA_BOOTVERBOSE(
1068                 device_printf(dev, "HDA Driver Revision: %s\n",
1069                     HDA_DRV_TEST_REV);
1070         );
1071
1072         model = (uint32_t)pci_get_device(dev) << 16;
1073         model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
1074         class = pci_get_class(dev);
1075         subclass = pci_get_subclass(dev);
1076
1077         for (i = 0; i < HDAC_DEVICES_LEN; i++) {
1078                 if (hdac_devices[i].model == model) {
1079                         devid = i;
1080                         break;
1081                 }
1082                 if (HDA_DEV_MATCH(hdac_devices[i].model, model) &&
1083                     class == PCIC_MULTIMEDIA &&
1084                     subclass == PCIS_MULTIMEDIA_HDA) {
1085                         devid = i;
1086                         break;
1087                 }
1088         }
1089
1090         sc->lock = snd_mtxcreate(device_get_nameunit(dev), "HDA driver mutex");
1091         sc->dev = dev;
1092         TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc);
1093         callout_init(&sc->poll_callout, CALLOUT_MPSAFE);
1094         for (i = 0; i < HDAC_CODEC_MAX; i++)
1095                 sc->codecs[i].dev = NULL;
1096         if (devid >= 0) {
1097                 sc->quirks_on = hdac_devices[devid].quirks_on;
1098                 sc->quirks_off = hdac_devices[devid].quirks_off;
1099         } else {
1100                 sc->quirks_on = 0;
1101                 sc->quirks_off = 0;
1102         }
1103         if (resource_int_value(device_get_name(dev),
1104             device_get_unit(dev), "msi", &i) == 0) {
1105                 if (i == 0)
1106                         sc->quirks_off |= HDAC_QUIRK_MSI;
1107                 else {
1108                         sc->quirks_on |= HDAC_QUIRK_MSI;
1109                         sc->quirks_off |= ~HDAC_QUIRK_MSI;
1110                 }
1111         }
1112         hdac_config_fetch(sc, &sc->quirks_on, &sc->quirks_off);
1113         HDA_BOOTVERBOSE(
1114                 device_printf(sc->dev,
1115                     "Config options: on=0x%08x off=0x%08x\n",
1116                     sc->quirks_on, sc->quirks_off);
1117         );
1118         sc->poll_ival = hz;
1119         if (resource_int_value(device_get_name(dev),
1120             device_get_unit(dev), "polling", &i) == 0 && i != 0)
1121                 sc->polling = 1;
1122         else
1123                 sc->polling = 0;
1124
1125         pci_enable_busmaster(dev);
1126
1127         vendor = pci_get_vendor(dev);
1128         if (vendor == INTEL_VENDORID) {
1129                 /* TCSEL -> TC0 */
1130                 v = pci_read_config(dev, 0x44, 1);
1131                 pci_write_config(dev, 0x44, v & 0xf8, 1);
1132                 HDA_BOOTHVERBOSE(
1133                         device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v,
1134                             pci_read_config(dev, 0x44, 1));
1135                 );
1136         }
1137
1138 #if defined(__i386__) || defined(__amd64__)
1139         sc->flags |= HDAC_F_DMA_NOCACHE;
1140
1141         if (resource_int_value(device_get_name(dev),
1142             device_get_unit(dev), "snoop", &i) == 0 && i != 0) {
1143 #else
1144         sc->flags &= ~HDAC_F_DMA_NOCACHE;
1145 #endif
1146                 /*
1147                  * Try to enable PCIe snoop to avoid messing around with
1148                  * uncacheable DMA attribute. Since PCIe snoop register
1149                  * config is pretty much vendor specific, there are no
1150                  * general solutions on how to enable it, forcing us (even
1151                  * Microsoft) to enable uncacheable or write combined DMA
1152                  * by default.
1153                  *
1154                  * http://msdn2.microsoft.com/en-us/library/ms790324.aspx
1155                  */
1156                 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) {
1157                         if (hdac_pcie_snoop[i].vendor != vendor)
1158                                 continue;
1159                         sc->flags &= ~HDAC_F_DMA_NOCACHE;
1160                         if (hdac_pcie_snoop[i].reg == 0x00)
1161                                 break;
1162                         v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1);
1163                         if ((v & hdac_pcie_snoop[i].enable) ==
1164                             hdac_pcie_snoop[i].enable)
1165                                 break;
1166                         v &= hdac_pcie_snoop[i].mask;
1167                         v |= hdac_pcie_snoop[i].enable;
1168                         pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1);
1169                         v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1);
1170                         if ((v & hdac_pcie_snoop[i].enable) !=
1171                             hdac_pcie_snoop[i].enable) {
1172                                 HDA_BOOTVERBOSE(
1173                                         device_printf(dev,
1174                                             "WARNING: Failed to enable PCIe "
1175                                             "snoop!\n");
1176                                 );
1177 #if defined(__i386__) || defined(__amd64__)
1178                                 sc->flags |= HDAC_F_DMA_NOCACHE;
1179 #endif
1180                         }
1181                         break;
1182                 }
1183 #if defined(__i386__) || defined(__amd64__)
1184         }
1185 #endif
1186
1187         HDA_BOOTHVERBOSE(
1188                 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n",
1189                     (sc->flags & HDAC_F_DMA_NOCACHE) ?
1190                     "Uncacheable" : "PCIe snoop", vendor);
1191         );
1192
1193         /* Allocate resources */
1194         result = hdac_mem_alloc(sc);
1195         if (result != 0)
1196                 goto hdac_attach_fail;
1197         result = hdac_irq_alloc(sc);
1198         if (result != 0)
1199                 goto hdac_attach_fail;
1200
1201         /* Get Capabilities */
1202         result = hdac_get_capabilities(sc);
1203         if (result != 0)
1204                 goto hdac_attach_fail;
1205
1206         /* Allocate CORB, RIRB, POS and BDLs dma memory */
1207         result = hdac_dma_alloc(sc, &sc->corb_dma,
1208             sc->corb_size * sizeof(uint32_t));
1209         if (result != 0)
1210                 goto hdac_attach_fail;
1211         result = hdac_dma_alloc(sc, &sc->rirb_dma,
1212             sc->rirb_size * sizeof(struct hdac_rirb));
1213         if (result != 0)
1214                 goto hdac_attach_fail;
1215         sc->streams = malloc(sizeof(struct hdac_stream) * sc->num_ss,
1216             M_HDAC, M_ZERO | M_WAITOK);
1217         for (i = 0; i < sc->num_ss; i++) {
1218                 result = hdac_dma_alloc(sc, &sc->streams[i].bdl,
1219                     sizeof(struct hdac_bdle) * HDA_BDL_MAX);
1220                 if (result != 0)
1221                         goto hdac_attach_fail;
1222         }
1223         if (sc->quirks_on & HDAC_QUIRK_DMAPOS) {
1224                 if (hdac_dma_alloc(sc, &sc->pos_dma, (sc->num_ss) * 8) != 0) {
1225                         HDA_BOOTVERBOSE(
1226                                 device_printf(dev, "Failed to "
1227                                     "allocate DMA pos buffer "
1228                                     "(non-fatal)\n");
1229                         );
1230                 } else {
1231                         uint64_t addr = sc->pos_dma.dma_paddr;
1232
1233                         HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, addr >> 32);
1234                         HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE,
1235                             (addr & HDAC_DPLBASE_DPLBASE_MASK) |
1236                             HDAC_DPLBASE_DPLBASE_DMAPBE);
1237                 }
1238         }
1239
1240         result = bus_dma_tag_create(
1241             bus_get_dma_tag(sc->dev),           /* parent */
1242             HDA_DMA_ALIGNMENT,                  /* alignment */
1243             0,                                  /* boundary */
1244             (sc->support_64bit) ? BUS_SPACE_MAXADDR :
1245                 BUS_SPACE_MAXADDR_32BIT,        /* lowaddr */
1246             BUS_SPACE_MAXADDR,                  /* highaddr */
1247             NULL,                               /* filtfunc */
1248             NULL,                               /* fistfuncarg */
1249             HDA_BUFSZ_MAX,                      /* maxsize */
1250             1,                                  /* nsegments */
1251             HDA_BUFSZ_MAX,                      /* maxsegsz */
1252             0,                                  /* flags */
1253             NULL,                               /* lockfunc */
1254             NULL,                               /* lockfuncarg */
1255             &sc->chan_dmat);                    /* dmat */
1256         if (result != 0) {
1257                 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n",
1258                      __func__, result);
1259                 goto hdac_attach_fail;
1260         }
1261
1262         /* Quiesce everything */
1263         HDA_BOOTHVERBOSE(
1264                 device_printf(dev, "Reset controller...\n");
1265         );
1266         hdac_reset(sc, 1);
1267
1268         /* Initialize the CORB and RIRB */
1269         hdac_corb_init(sc);
1270         hdac_rirb_init(sc);
1271
1272         /* Defer remaining of initialization until interrupts are enabled */
1273         sc->intrhook.ich_func = hdac_attach2;
1274         sc->intrhook.ich_arg = (void *)sc;
1275         if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) {
1276                 sc->intrhook.ich_func = NULL;
1277                 hdac_attach2((void *)sc);
1278         }
1279
1280         return (0);
1281
1282 hdac_attach_fail:
1283         hdac_irq_free(sc);
1284         for (i = 0; i < sc->num_ss; i++)
1285                 hdac_dma_free(sc, &sc->streams[i].bdl);
1286         free(sc->streams, M_HDAC);
1287         hdac_dma_free(sc, &sc->rirb_dma);
1288         hdac_dma_free(sc, &sc->corb_dma);
1289         hdac_mem_free(sc);
1290         snd_mtxfree(sc->lock);
1291
1292         return (ENXIO);
1293 }
1294
1295 static int
1296 sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS)
1297 {
1298         struct hdac_softc *sc;
1299         device_t *devlist;
1300         device_t dev;
1301         int devcount, i, err, val;
1302
1303         dev = oidp->oid_arg1;
1304         sc = device_get_softc(dev);
1305         if (sc == NULL)
1306                 return (EINVAL);
1307         val = 0;
1308         err = sysctl_handle_int(oidp, &val, 0, req);
1309         if (err != 0 || req->newptr == NULL || val == 0)
1310                 return (err);
1311
1312         /* XXX: Temporary. For debugging. */
1313         if (val == 100) {
1314                 hdac_suspend(dev);
1315                 return (0);
1316         } else if (val == 101) {
1317                 hdac_resume(dev);
1318                 return (0);
1319         }
1320
1321         if ((err = device_get_children(dev, &devlist, &devcount)) != 0)
1322                 return (err);
1323         hdac_lock(sc);
1324         for (i = 0; i < devcount; i++)
1325                 HDAC_PINDUMP(devlist[i]);
1326         hdac_unlock(sc);
1327         free(devlist, M_TEMP);
1328         return (0);
1329 }
1330
1331 static int
1332 hdac_mdata_rate(uint16_t fmt)
1333 {
1334         static const int mbits[8] = { 8, 16, 32, 32, 32, 32, 32, 32 };
1335         int rate, bits;
1336
1337         if (fmt & (1 << 14))
1338                 rate = 44100;
1339         else
1340                 rate = 48000;
1341         rate *= ((fmt >> 11) & 0x07) + 1;
1342         rate /= ((fmt >> 8) & 0x07) + 1;
1343         bits = mbits[(fmt >> 4) & 0x03];
1344         bits *= (fmt & 0x0f) + 1;
1345         return (rate * bits);
1346 }
1347
1348 static int
1349 hdac_bdata_rate(uint16_t fmt, int output)
1350 {
1351         static const int bbits[8] = { 8, 16, 20, 24, 32, 32, 32, 32 };
1352         int rate, bits;
1353
1354         rate = 48000;
1355         rate *= ((fmt >> 11) & 0x07) + 1;
1356         bits = bbits[(fmt >> 4) & 0x03];
1357         bits *= (fmt & 0x0f) + 1;
1358         if (!output)
1359                 bits = ((bits + 7) & ~0x07) + 10;
1360         return (rate * bits);
1361 }
1362
1363 static void
1364 hdac_poll_reinit(struct hdac_softc *sc)
1365 {
1366         int i, pollticks, min = 1000000;
1367         struct hdac_stream *s;
1368
1369         if (sc->polling == 0)
1370                 return;
1371         if (sc->unsol_registered > 0)
1372                 min = hz / 2;
1373         for (i = 0; i < sc->num_ss; i++) {
1374                 s = &sc->streams[i];
1375                 if (s->running == 0)
1376                         continue;
1377                 pollticks = ((uint64_t)hz * s->blksz) /
1378                     (hdac_mdata_rate(s->format) / 8);
1379                 pollticks >>= 1;
1380                 if (pollticks > hz)
1381                         pollticks = hz;
1382                 if (pollticks < 1) {
1383                         HDA_BOOTVERBOSE(
1384                                 device_printf(sc->dev,
1385                                     "poll interval < 1 tick !\n");
1386                         );
1387                         pollticks = 1;
1388                 }
1389                 if (min > pollticks)
1390                         min = pollticks;
1391         }
1392         HDA_BOOTVERBOSE(
1393                 device_printf(sc->dev,
1394                     "poll interval %d -> %d ticks\n",
1395                     sc->poll_ival, min);
1396         );
1397         sc->poll_ival = min;
1398         if (min == 1000000)
1399                 callout_stop(&sc->poll_callout);
1400         else
1401                 callout_reset(&sc->poll_callout, 1, hdac_poll_callback, sc);
1402 }
1403
1404 static int
1405 sysctl_hdac_polling(SYSCTL_HANDLER_ARGS)
1406 {
1407         struct hdac_softc *sc;
1408         device_t dev;
1409         uint32_t ctl;
1410         int err, val;
1411
1412         dev = oidp->oid_arg1;
1413         sc = device_get_softc(dev);
1414         if (sc == NULL)
1415                 return (EINVAL);
1416         hdac_lock(sc);
1417         val = sc->polling;
1418         hdac_unlock(sc);
1419         err = sysctl_handle_int(oidp, &val, 0, req);
1420
1421         if (err != 0 || req->newptr == NULL)
1422                 return (err);
1423         if (val < 0 || val > 1)
1424                 return (EINVAL);
1425
1426         hdac_lock(sc);
1427         if (val != sc->polling) {
1428                 if (val == 0) {
1429                         callout_stop(&sc->poll_callout);
1430                         hdac_unlock(sc);
1431                         callout_drain(&sc->poll_callout);
1432                         hdac_lock(sc);
1433                         sc->polling = 0;
1434                         ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
1435                         ctl |= HDAC_INTCTL_GIE;
1436                         HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
1437                 } else {
1438                         ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
1439                         ctl &= ~HDAC_INTCTL_GIE;
1440                         HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
1441                         sc->polling = 1;
1442                         hdac_poll_reinit(sc);
1443                 }
1444         }
1445         hdac_unlock(sc);
1446
1447         return (err);
1448 }
1449
1450 static void
1451 hdac_attach2(void *arg)
1452 {
1453         struct hdac_softc *sc;
1454         device_t child;
1455         uint32_t vendorid, revisionid;
1456         int i;
1457         uint16_t statests;
1458
1459         sc = (struct hdac_softc *)arg;
1460
1461         hdac_lock(sc);
1462
1463         /* Remove ourselves from the config hooks */
1464         if (sc->intrhook.ich_func != NULL) {
1465                 config_intrhook_disestablish(&sc->intrhook);
1466                 sc->intrhook.ich_func = NULL;
1467         }
1468
1469         HDA_BOOTHVERBOSE(
1470                 device_printf(sc->dev, "Starting CORB Engine...\n");
1471         );
1472         hdac_corb_start(sc);
1473         HDA_BOOTHVERBOSE(
1474                 device_printf(sc->dev, "Starting RIRB Engine...\n");
1475         );
1476         hdac_rirb_start(sc);
1477         HDA_BOOTHVERBOSE(
1478                 device_printf(sc->dev,
1479                     "Enabling controller interrupt...\n");
1480         );
1481         HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) |
1482             HDAC_GCTL_UNSOL);
1483         if (sc->polling == 0) {
1484                 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL,
1485                     HDAC_INTCTL_CIE | HDAC_INTCTL_GIE);
1486         }
1487         DELAY(1000);
1488
1489         HDA_BOOTHVERBOSE(
1490                 device_printf(sc->dev, "Scanning HDA codecs ...\n");
1491         );
1492         statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS);
1493         hdac_unlock(sc);
1494         for (i = 0; i < HDAC_CODEC_MAX; i++) {
1495                 if (HDAC_STATESTS_SDIWAKE(statests, i)) {
1496                         HDA_BOOTHVERBOSE(
1497                                 device_printf(sc->dev,
1498                                     "Found CODEC at address %d\n", i);
1499                         );
1500                         hdac_lock(sc);
1501                         vendorid = hdac_send_command(sc, i,
1502                             HDA_CMD_GET_PARAMETER(0, 0x0, HDA_PARAM_VENDOR_ID));
1503                         revisionid = hdac_send_command(sc, i,
1504                             HDA_CMD_GET_PARAMETER(0, 0x0, HDA_PARAM_REVISION_ID));
1505                         hdac_unlock(sc);
1506                         if (vendorid == HDA_INVALID &&
1507                             revisionid == HDA_INVALID) {
1508                                 device_printf(sc->dev,
1509                                     "CODEC is not responding!\n");
1510                                 continue;
1511                         }
1512                         sc->codecs[i].vendor_id =
1513                             HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid);
1514                         sc->codecs[i].device_id =
1515                             HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid);
1516                         sc->codecs[i].revision_id =
1517                             HDA_PARAM_REVISION_ID_REVISION_ID(revisionid);
1518                         sc->codecs[i].stepping_id =
1519                             HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid);
1520                         child = device_add_child(sc->dev, "hdacc", -1);
1521                         if (child == NULL) {
1522                                 device_printf(sc->dev,
1523                                     "Failed to add CODEC device\n");
1524                                 continue;
1525                         }
1526                         device_set_ivars(child, (void *)(intptr_t)i);
1527                         sc->codecs[i].dev = child;
1528                 }
1529         }
1530         bus_generic_attach(sc->dev);
1531
1532         SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev),
1533             SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO,
1534             "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev),
1535             sysctl_hdac_pindump, "I", "Dump pin states/data");
1536         SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev),
1537             SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO,
1538             "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev),
1539             sysctl_hdac_polling, "I", "Enable polling mode");
1540 }
1541
1542 /****************************************************************************
1543  * int hdac_suspend(device_t)
1544  *
1545  * Suspend and power down HDA bus and codecs.
1546  ****************************************************************************/
1547 static int
1548 hdac_suspend(device_t dev)
1549 {
1550         struct hdac_softc *sc = device_get_softc(dev);
1551
1552         HDA_BOOTHVERBOSE(
1553                 device_printf(dev, "Suspend...\n");
1554         );
1555         bus_generic_suspend(dev);
1556
1557         hdac_lock(sc);
1558         HDA_BOOTHVERBOSE(
1559                 device_printf(dev, "Reset controller...\n");
1560         );
1561         hdac_reset(sc, 0);
1562         hdac_unlock(sc);
1563         taskqueue_drain(taskqueue_thread, &sc->unsolq_task);
1564         HDA_BOOTHVERBOSE(
1565                 device_printf(dev, "Suspend done\n");
1566         );
1567         return (0);
1568 }
1569
1570 /****************************************************************************
1571  * int hdac_resume(device_t)
1572  *
1573  * Powerup and restore HDA bus and codecs state.
1574  ****************************************************************************/
1575 static int
1576 hdac_resume(device_t dev)
1577 {
1578         struct hdac_softc *sc = device_get_softc(dev);
1579         int error;
1580
1581         HDA_BOOTHVERBOSE(
1582                 device_printf(dev, "Resume...\n");
1583         );
1584         hdac_lock(sc);
1585
1586         /* Quiesce everything */
1587         HDA_BOOTHVERBOSE(
1588                 device_printf(dev, "Reset controller...\n");
1589         );
1590         hdac_reset(sc, 1);
1591
1592         /* Initialize the CORB and RIRB */
1593         hdac_corb_init(sc);
1594         hdac_rirb_init(sc);
1595
1596         HDA_BOOTHVERBOSE(
1597                 device_printf(dev, "Starting CORB Engine...\n");
1598         );
1599         hdac_corb_start(sc);
1600         HDA_BOOTHVERBOSE(
1601                 device_printf(dev, "Starting RIRB Engine...\n");
1602         );
1603         hdac_rirb_start(sc);
1604         HDA_BOOTHVERBOSE(
1605                 device_printf(dev, "Enabling controller interrupt...\n");
1606         );
1607         HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) |
1608             HDAC_GCTL_UNSOL);
1609         HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, HDAC_INTCTL_CIE | HDAC_INTCTL_GIE);
1610         DELAY(1000);
1611         hdac_unlock(sc);
1612
1613         error = bus_generic_resume(dev);
1614         HDA_BOOTHVERBOSE(
1615                 device_printf(dev, "Resume done\n");
1616         );
1617         return (error);
1618 }
1619
1620 /****************************************************************************
1621  * int hdac_detach(device_t)
1622  *
1623  * Detach and free up resources utilized by the hdac device.
1624  ****************************************************************************/
1625 static int
1626 hdac_detach(device_t dev)
1627 {
1628         struct hdac_softc *sc = device_get_softc(dev);
1629         device_t *devlist;
1630         int cad, i, devcount, error;
1631
1632         if ((error = device_get_children(dev, &devlist, &devcount)) != 0)
1633                 return (error);
1634         for (i = 0; i < devcount; i++) {
1635                 cad = (intptr_t)device_get_ivars(devlist[i]);
1636                 if ((error = device_delete_child(dev, devlist[i])) != 0) {
1637                         free(devlist, M_TEMP);
1638                         return (error);
1639                 }
1640                 sc->codecs[cad].dev = NULL;
1641         }
1642         free(devlist, M_TEMP);
1643
1644         hdac_lock(sc);
1645         hdac_reset(sc, 0);
1646         hdac_unlock(sc);
1647         taskqueue_drain(taskqueue_thread, &sc->unsolq_task);
1648         hdac_irq_free(sc);
1649
1650         for (i = 0; i < sc->num_ss; i++)
1651                 hdac_dma_free(sc, &sc->streams[i].bdl);
1652         free(sc->streams, M_HDAC);
1653         hdac_dma_free(sc, &sc->pos_dma);
1654         hdac_dma_free(sc, &sc->rirb_dma);
1655         hdac_dma_free(sc, &sc->corb_dma);
1656         if (sc->chan_dmat != NULL) {
1657                 bus_dma_tag_destroy(sc->chan_dmat);
1658                 sc->chan_dmat = NULL;
1659         }
1660         hdac_mem_free(sc);
1661         snd_mtxfree(sc->lock);
1662         return (0);
1663 }
1664
1665 static bus_dma_tag_t
1666 hdac_get_dma_tag(device_t dev, device_t child)
1667 {
1668         struct hdac_softc *sc = device_get_softc(dev);
1669
1670         return (sc->chan_dmat);
1671 }
1672
1673 static int
1674 hdac_print_child(device_t dev, device_t child)
1675 {
1676         int retval;
1677
1678         retval = bus_print_child_header(dev, child);
1679         retval += printf(" at cad %d",
1680             (int)(intptr_t)device_get_ivars(child));
1681         retval += bus_print_child_footer(dev, child);
1682
1683         return (retval);
1684 }
1685
1686 static int
1687 hdac_child_location_str(device_t dev, device_t child, char *buf,
1688     size_t buflen)
1689 {
1690
1691         snprintf(buf, buflen, "cad=%d",
1692             (int)(intptr_t)device_get_ivars(child));
1693         return (0);
1694 }
1695
1696 static int
1697 hdac_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
1698     size_t buflen)
1699 {
1700         struct hdac_softc *sc = device_get_softc(dev);
1701         nid_t cad = (uintptr_t)device_get_ivars(child);
1702
1703         snprintf(buf, buflen, "vendor=0x%04x device=0x%04x revision=0x%02x "
1704             "stepping=0x%02x",
1705             sc->codecs[cad].vendor_id, sc->codecs[cad].device_id,
1706             sc->codecs[cad].revision_id, sc->codecs[cad].stepping_id);
1707         return (0);
1708 }
1709
1710 static int
1711 hdac_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1712 {
1713         struct hdac_softc *sc = device_get_softc(dev);
1714         nid_t cad = (uintptr_t)device_get_ivars(child);
1715
1716         switch (which) {
1717         case HDA_IVAR_CODEC_ID:
1718                 *result = cad;
1719                 break;
1720         case HDA_IVAR_VENDOR_ID:
1721                 *result = sc->codecs[cad].vendor_id;
1722                 break;
1723         case HDA_IVAR_DEVICE_ID:
1724                 *result = sc->codecs[cad].device_id;
1725                 break;
1726         case HDA_IVAR_REVISION_ID:
1727                 *result = sc->codecs[cad].revision_id;
1728                 break;
1729         case HDA_IVAR_STEPPING_ID:
1730                 *result = sc->codecs[cad].stepping_id;
1731                 break;
1732         case HDA_IVAR_SUBVENDOR_ID:
1733                 *result = pci_get_subvendor(dev);
1734                 break;
1735         case HDA_IVAR_SUBDEVICE_ID:
1736                 *result = pci_get_subdevice(dev);
1737                 break;
1738         case HDA_IVAR_DMA_NOCACHE:
1739                 *result = (sc->flags & HDAC_F_DMA_NOCACHE) != 0;
1740                 break;
1741         default:
1742                 return (ENOENT);
1743         }
1744         return (0);
1745 }
1746
1747 static struct mtx *
1748 hdac_get_mtx(device_t dev, device_t child)
1749 {
1750         struct hdac_softc *sc = device_get_softc(dev);
1751
1752         return (sc->lock);
1753 }
1754
1755 static uint32_t
1756 hdac_codec_command(device_t dev, device_t child, uint32_t verb)
1757 {
1758
1759         return (hdac_send_command(device_get_softc(dev),
1760             (intptr_t)device_get_ivars(child), verb));
1761 }
1762
1763 static int
1764 hdac_find_stream(struct hdac_softc *sc, int dir, int stream)
1765 {
1766         int i, ss;
1767
1768         ss = -1;
1769         /* Allocate ISS/BSS first. */
1770         if (dir == 0) {
1771                 for (i = 0; i < sc->num_iss; i++) {
1772                         if (sc->streams[i].stream == stream) {
1773                                 ss = i;
1774                                 break;
1775                         }
1776                 }
1777         } else {
1778                 for (i = 0; i < sc->num_oss; i++) {
1779                         if (sc->streams[i + sc->num_iss].stream == stream) {
1780                                 ss = i + sc->num_iss;
1781                                 break;
1782                         }
1783                 }
1784         }
1785         /* Fallback to BSS. */
1786         if (ss == -1) {
1787                 for (i = 0; i < sc->num_bss; i++) {
1788                         if (sc->streams[i + sc->num_iss + sc->num_oss].stream
1789                             == stream) {
1790                                 ss = i + sc->num_iss + sc->num_oss;
1791                                 break;
1792                         }
1793                 }
1794         }
1795         return (ss);
1796 }
1797
1798 static int
1799 hdac_stream_alloc(device_t dev, device_t child, int dir, int format, int stripe,
1800     uint32_t **dmapos)
1801 {
1802         struct hdac_softc *sc = device_get_softc(dev);
1803         nid_t cad = (uintptr_t)device_get_ivars(child);
1804         int stream, ss, bw, maxbw, prevbw;
1805
1806         /* Look for empty stream. */
1807         ss = hdac_find_stream(sc, dir, 0);
1808
1809         /* Return if found nothing. */
1810         if (ss < 0)
1811                 return (0);
1812
1813         /* Check bus bandwidth. */
1814         bw = hdac_bdata_rate(format, dir);
1815         if (dir == 1) {
1816                 bw *= 1 << (sc->num_sdo - stripe);
1817                 prevbw = sc->sdo_bw_used;
1818                 maxbw = 48000 * 960 * (1 << sc->num_sdo);
1819         } else {
1820                 prevbw = sc->codecs[cad].sdi_bw_used;
1821                 maxbw = 48000 * 464;
1822         }
1823         HDA_BOOTHVERBOSE(
1824                 device_printf(dev, "%dKbps of %dKbps bandwidth used%s\n",
1825                     (bw + prevbw) / 1000, maxbw / 1000,
1826                     bw + prevbw > maxbw ? " -- OVERFLOW!" : "");
1827         );
1828         if (bw + prevbw > maxbw)
1829                 return (0);
1830         if (dir == 1)
1831                 sc->sdo_bw_used += bw;
1832         else
1833                 sc->codecs[cad].sdi_bw_used += bw;
1834
1835         /* Allocate stream number */
1836         if (ss >= sc->num_iss + sc->num_oss)
1837                 stream = 15 - (ss - sc->num_iss + sc->num_oss);
1838         else if (ss >= sc->num_iss)
1839                 stream = ss - sc->num_iss + 1;
1840         else
1841                 stream = ss + 1;
1842
1843         sc->streams[ss].dev = child;
1844         sc->streams[ss].dir = dir;
1845         sc->streams[ss].stream = stream;
1846         sc->streams[ss].bw = bw;
1847         sc->streams[ss].format = format;
1848         sc->streams[ss].stripe = stripe;
1849         if (dmapos != NULL) {
1850                 if (sc->pos_dma.dma_vaddr != NULL)
1851                         *dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + ss * 8);
1852                 else
1853                         *dmapos = NULL;
1854         }
1855         return (stream);
1856 }
1857
1858 static void
1859 hdac_stream_free(device_t dev, device_t child, int dir, int stream)
1860 {
1861         struct hdac_softc *sc = device_get_softc(dev);
1862         nid_t cad = (uintptr_t)device_get_ivars(child);
1863         int ss;
1864
1865         ss = hdac_find_stream(sc, dir, stream);
1866         KASSERT(ss >= 0,
1867             ("Free for not allocated stream (%d/%d)\n", dir, stream));
1868         if (dir == 1)
1869                 sc->sdo_bw_used -= sc->streams[ss].bw;
1870         else
1871                 sc->codecs[cad].sdi_bw_used -= sc->streams[ss].bw;
1872         sc->streams[ss].stream = 0;
1873         sc->streams[ss].dev = NULL;
1874 }
1875
1876 static int
1877 hdac_stream_start(device_t dev, device_t child,
1878     int dir, int stream, bus_addr_t buf, int blksz, int blkcnt)
1879 {
1880         struct hdac_softc *sc = device_get_softc(dev);
1881         struct hdac_bdle *bdle;
1882         uint64_t addr;
1883         int i, ss, off;
1884         uint32_t ctl;
1885
1886         ss = hdac_find_stream(sc, dir, stream);
1887         KASSERT(ss >= 0,
1888             ("Start for not allocated stream (%d/%d)\n", dir, stream));
1889
1890         addr = (uint64_t)buf;
1891         bdle = (struct hdac_bdle *)sc->streams[ss].bdl.dma_vaddr;
1892         for (i = 0; i < blkcnt; i++, bdle++) {
1893                 bdle->addrl = (uint32_t)addr;
1894                 bdle->addrh = (uint32_t)(addr >> 32);
1895                 bdle->len = blksz;
1896                 bdle->ioc = 1;
1897                 addr += blksz;
1898         }
1899
1900         off = ss << 5;
1901         HDAC_WRITE_4(&sc->mem, off + HDAC_SDCBL, blksz * blkcnt);
1902         HDAC_WRITE_2(&sc->mem, off + HDAC_SDLVI, blkcnt - 1);
1903         addr = sc->streams[ss].bdl.dma_paddr;
1904         HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPL, (uint32_t)addr);
1905         HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPU, (uint32_t)(addr >> 32));
1906
1907         ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL2);
1908         if (dir)
1909                 ctl |= HDAC_SDCTL2_DIR;
1910         else
1911                 ctl &= ~HDAC_SDCTL2_DIR;
1912         ctl &= ~HDAC_SDCTL2_STRM_MASK;
1913         ctl |= stream << HDAC_SDCTL2_STRM_SHIFT;
1914         ctl &= ~HDAC_SDCTL2_STRIPE_MASK;
1915         ctl |= sc->streams[ss].stripe << HDAC_SDCTL2_STRIPE_SHIFT;
1916         HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL2, ctl);
1917
1918         HDAC_WRITE_2(&sc->mem, off + HDAC_SDFMT, sc->streams[ss].format);
1919
1920         ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
1921         ctl |= 1 << ss;
1922         HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
1923
1924         HDAC_WRITE_1(&sc->mem, off + HDAC_SDSTS,
1925             HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS);
1926         ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
1927         ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE |
1928             HDAC_SDCTL_RUN;
1929         HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl);
1930
1931         sc->streams[ss].blksz = blksz;
1932         sc->streams[ss].running = 1;
1933         hdac_poll_reinit(sc);
1934         return (0);
1935 }
1936
1937 static void
1938 hdac_stream_stop(device_t dev, device_t child, int dir, int stream)
1939 {
1940         struct hdac_softc *sc = device_get_softc(dev);
1941         int ss, off;
1942         uint32_t ctl;
1943
1944         ss = hdac_find_stream(sc, dir, stream);
1945         KASSERT(ss >= 0,
1946             ("Stop for not allocated stream (%d/%d)\n", dir, stream));
1947
1948         off = ss << 5;
1949         ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
1950         ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE |
1951             HDAC_SDCTL_RUN);
1952         HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl);
1953
1954         ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
1955         ctl &= ~(1 << ss);
1956         HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
1957
1958         sc->streams[ss].running = 0;
1959         hdac_poll_reinit(sc);
1960 }
1961
1962 static void
1963 hdac_stream_reset(device_t dev, device_t child, int dir, int stream)
1964 {
1965         struct hdac_softc *sc = device_get_softc(dev);
1966         int timeout = 1000;
1967         int to = timeout;
1968         int ss, off;
1969         uint32_t ctl;
1970
1971         ss = hdac_find_stream(sc, dir, stream);
1972         KASSERT(ss >= 0,
1973             ("Reset for not allocated stream (%d/%d)\n", dir, stream));
1974
1975         off = ss << 5;
1976         ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
1977         ctl |= HDAC_SDCTL_SRST;
1978         HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl);
1979         do {
1980                 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
1981                 if (ctl & HDAC_SDCTL_SRST)
1982                         break;
1983                 DELAY(10);
1984         } while (--to);
1985         if (!(ctl & HDAC_SDCTL_SRST))
1986                 device_printf(dev, "Reset setting timeout\n");
1987         ctl &= ~HDAC_SDCTL_SRST;
1988         HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl);
1989         to = timeout;
1990         do {
1991                 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
1992                 if (!(ctl & HDAC_SDCTL_SRST))
1993                         break;
1994                 DELAY(10);
1995         } while (--to);
1996         if (ctl & HDAC_SDCTL_SRST)
1997                 device_printf(dev, "Reset timeout!\n");
1998 }
1999
2000 static uint32_t
2001 hdac_stream_getptr(device_t dev, device_t child, int dir, int stream)
2002 {
2003         struct hdac_softc *sc = device_get_softc(dev);
2004         int ss, off;
2005
2006         ss = hdac_find_stream(sc, dir, stream);
2007         KASSERT(ss >= 0,
2008             ("Reset for not allocated stream (%d/%d)\n", dir, stream));
2009
2010         off = ss << 5;
2011         return (HDAC_READ_4(&sc->mem, off + HDAC_SDLPIB));
2012 }
2013
2014 static int
2015 hdac_unsol_alloc(device_t dev, device_t child, int tag)
2016 {
2017         struct hdac_softc *sc = device_get_softc(dev);
2018
2019         sc->unsol_registered++;
2020         hdac_poll_reinit(sc);
2021         return (tag);
2022 }
2023
2024 static void
2025 hdac_unsol_free(device_t dev, device_t child, int tag)
2026 {
2027         struct hdac_softc *sc = device_get_softc(dev);
2028
2029         sc->unsol_registered--;
2030         hdac_poll_reinit(sc);
2031 }
2032
2033 static device_method_t hdac_methods[] = {
2034         /* device interface */
2035         DEVMETHOD(device_probe,         hdac_probe),
2036         DEVMETHOD(device_attach,        hdac_attach),
2037         DEVMETHOD(device_detach,        hdac_detach),
2038         DEVMETHOD(device_suspend,       hdac_suspend),
2039         DEVMETHOD(device_resume,        hdac_resume),
2040         /* Bus interface */
2041         DEVMETHOD(bus_get_dma_tag,      hdac_get_dma_tag),
2042         DEVMETHOD(bus_print_child,      hdac_print_child),
2043         DEVMETHOD(bus_child_location_str, hdac_child_location_str),
2044         DEVMETHOD(bus_child_pnpinfo_str, hdac_child_pnpinfo_str_method),
2045         DEVMETHOD(bus_read_ivar,        hdac_read_ivar),
2046         DEVMETHOD(hdac_get_mtx,         hdac_get_mtx),
2047         DEVMETHOD(hdac_codec_command,   hdac_codec_command),
2048         DEVMETHOD(hdac_stream_alloc,    hdac_stream_alloc),
2049         DEVMETHOD(hdac_stream_free,     hdac_stream_free),
2050         DEVMETHOD(hdac_stream_start,    hdac_stream_start),
2051         DEVMETHOD(hdac_stream_stop,     hdac_stream_stop),
2052         DEVMETHOD(hdac_stream_reset,    hdac_stream_reset),
2053         DEVMETHOD(hdac_stream_getptr,   hdac_stream_getptr),
2054         DEVMETHOD(hdac_unsol_alloc,     hdac_unsol_alloc),
2055         DEVMETHOD(hdac_unsol_free,      hdac_unsol_free),
2056         { 0, 0 }
2057 };
2058
2059 static driver_t hdac_driver = {
2060         "hdac",
2061         hdac_methods,
2062         sizeof(struct hdac_softc),
2063 };
2064
2065 static devclass_t hdac_devclass;
2066
2067 DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, 0, 0);