2 * Copyright (c) 2001 Scott Long <scottl@freebsd.org>
3 * Copyright (c) 2001 Darrell Anderson <anderson@cs.duke.edu>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * Maestro-3/Allegro FreeBSD pcm sound driver
31 * executive status summary:
32 * (+) /dev/dsp multiple concurrent play channels.
33 * (+) /dev/dsp config (speed, mono/stereo, 8/16 bit).
34 * (+) /dev/mixer sets left/right volumes.
35 * (+) /dev/dsp recording works. Tested successfully with the cdrom channel
36 * (+) apm suspend/resume works, and works properly!.
37 * (-) hardware volme controls don't work =-(
38 * (-) setblocksize() does nothing.
40 * The real credit goes to:
42 * Zach Brown for his Linux driver core and helpful technical comments.
43 * <zab@zabbo.net>, http://www.zabbo.net/maestro3
45 * Cameron Grant created the pcm framework used here nearly verbatim.
46 * <cg@freebsd.org>, http://people.freebsd.org/~cg/template.c
48 * Taku YAMAMOTO for his Maestro-1/2 FreeBSD driver and sanity reference.
49 * <taku@cent.saitama-u.ac.jp>
51 * ESS docs explained a few magic registers and numbers.
52 * http://virgo.caltech.edu/~dmoore/maestro3.pdf.gz
55 #ifdef HAVE_KERNEL_OPTION_HEADERS
59 #include <dev/sound/pcm/sound.h>
60 #include <dev/sound/pcm/ac97.h>
62 #include <dev/pci/pcireg.h>
63 #include <dev/pci/pcivar.h>
67 #include <dev/sound/pci/allegro_reg.h>
68 #include <dev/sound/pci/allegro_code.h>
70 SND_DECLARE_FILE("$FreeBSD$");
72 /* -------------------------------------------------------------------- */
74 enum {CHANGE=0, CALL=1, INTR=2, BORING=3, NONE=-1};
75 #ifndef M3_DEBUG_LEVEL
76 #define M3_DEBUG_LEVEL NONE
78 #define M3_DEBUG(level, _msg) {if ((level) <= M3_DEBUG_LEVEL) {printf _msg;}}
80 /* -------------------------------------------------------------------- */
86 static struct m3_card_type {
87 u_int32_t pci_id; int which; int delay1; int delay2; char *name;
89 { 0x1988125d, ESS_ALLEGRO_1, 50, 800, "ESS Technology Allegro-1" },
90 { 0x1998125d, ESS_MAESTRO3, 20, 500, "ESS Technology Maestro3" },
91 { 0x199a125d, ESS_MAESTRO3, 20, 500, "ESS Technology Maestro3" },
95 #define M3_BUFSIZE_MIN 4096
96 #define M3_BUFSIZE_MAX 65536
97 #define M3_BUFSIZE_DEFAULT 4096
98 #define M3_PCHANS 4 /* create /dev/dsp0.[0-N] to use more than one */
100 #define M3_MAXADDR ((1 << 27) - 1)
101 #define M3_DEFAULT_VOL 0x6800
108 struct snd_dbuf *buffer;
109 struct pcm_channel *channel;
110 struct sc_info *parent;
122 struct snd_dbuf *buffer;
123 struct pcm_channel *channel;
124 struct sc_info *parent;
141 bus_space_handle_t sh;
142 bus_dma_tag_t parent_dmat;
144 struct resource *reg;
145 struct resource *irq;
151 struct sc_pchinfo pch[M3_PCHANS];
152 struct sc_rchinfo rch[M3_RCHANS];
162 #define M3_LOCK(_sc) snd_mtxlock((_sc)->sc_lock)
163 #define M3_UNLOCK(_sc) snd_mtxunlock((_sc)->sc_lock)
164 #define M3_LOCK_ASSERT(_sc) snd_mtxassert((_sc)->sc_lock)
166 /* -------------------------------------------------------------------- */
168 /* play channel interface */
169 static void *m3_pchan_init(kobj_t, void *, struct snd_dbuf *, struct pcm_channel *, int);
170 static int m3_pchan_free(kobj_t, void *);
171 static int m3_pchan_setformat(kobj_t, void *, u_int32_t);
172 static u_int32_t m3_pchan_setspeed(kobj_t, void *, u_int32_t);
173 static u_int32_t m3_pchan_setblocksize(kobj_t, void *, u_int32_t);
174 static int m3_pchan_trigger(kobj_t, void *, int);
175 static int m3_pchan_trigger_locked(kobj_t, void *, int);
176 static u_int32_t m3_pchan_getptr_internal(struct sc_pchinfo *);
177 static u_int32_t m3_pchan_getptr(kobj_t, void *);
178 static struct pcmchan_caps *m3_pchan_getcaps(kobj_t, void *);
180 /* record channel interface */
181 static void *m3_rchan_init(kobj_t, void *, struct snd_dbuf *, struct pcm_channel *, int);
182 static int m3_rchan_free(kobj_t, void *);
183 static int m3_rchan_setformat(kobj_t, void *, u_int32_t);
184 static u_int32_t m3_rchan_setspeed(kobj_t, void *, u_int32_t);
185 static u_int32_t m3_rchan_setblocksize(kobj_t, void *, u_int32_t);
186 static int m3_rchan_trigger(kobj_t, void *, int);
187 static int m3_rchan_trigger_locked(kobj_t, void *, int);
188 static u_int32_t m3_rchan_getptr_internal(struct sc_rchinfo *);
189 static u_int32_t m3_rchan_getptr(kobj_t, void *);
190 static struct pcmchan_caps *m3_rchan_getcaps(kobj_t, void *);
192 static int m3_chan_active(struct sc_info *);
194 /* talk to the codec - called from ac97.c */
195 static u_int32_t m3_initcd(kobj_t, void *);
196 static int m3_rdcd(kobj_t, void *, int);
197 static int m3_wrcd(kobj_t, void *, int, u_int32_t);
200 static void m3_intr(void *);
201 static int m3_power(struct sc_info *, int);
202 static int m3_init(struct sc_info *);
203 static int m3_uninit(struct sc_info *);
204 static u_int8_t m3_assp_halt(struct sc_info *);
205 static void m3_config(struct sc_info *);
206 static void m3_amp_enable(struct sc_info *);
207 static void m3_enable_ints(struct sc_info *);
208 static void m3_codec_reset(struct sc_info *);
210 /* -------------------------------------------------------------------- */
211 /* Codec descriptor */
212 static kobj_method_t m3_codec_methods[] = {
213 KOBJMETHOD(ac97_init, m3_initcd),
214 KOBJMETHOD(ac97_read, m3_rdcd),
215 KOBJMETHOD(ac97_write, m3_wrcd),
218 AC97_DECLARE(m3_codec);
220 /* -------------------------------------------------------------------- */
221 /* channel descriptors */
223 static u_int32_t m3_playfmt[] = {
224 SND_FORMAT(AFMT_U8, 1, 0),
225 SND_FORMAT(AFMT_U8, 2, 0),
226 SND_FORMAT(AFMT_S16_LE, 1, 0),
227 SND_FORMAT(AFMT_S16_LE, 2, 0),
230 static struct pcmchan_caps m3_playcaps = {8000, 48000, m3_playfmt, 0};
232 static kobj_method_t m3_pch_methods[] = {
233 KOBJMETHOD(channel_init, m3_pchan_init),
234 KOBJMETHOD(channel_setformat, m3_pchan_setformat),
235 KOBJMETHOD(channel_setspeed, m3_pchan_setspeed),
236 KOBJMETHOD(channel_setblocksize, m3_pchan_setblocksize),
237 KOBJMETHOD(channel_trigger, m3_pchan_trigger),
238 KOBJMETHOD(channel_getptr, m3_pchan_getptr),
239 KOBJMETHOD(channel_getcaps, m3_pchan_getcaps),
240 KOBJMETHOD(channel_free, m3_pchan_free),
243 CHANNEL_DECLARE(m3_pch);
245 static u_int32_t m3_recfmt[] = {
246 SND_FORMAT(AFMT_U8, 1, 0),
247 SND_FORMAT(AFMT_U8, 2, 0),
248 SND_FORMAT(AFMT_S16_LE, 1, 0),
249 SND_FORMAT(AFMT_S16_LE, 2, 0),
252 static struct pcmchan_caps m3_reccaps = {8000, 48000, m3_recfmt, 0};
254 static kobj_method_t m3_rch_methods[] = {
255 KOBJMETHOD(channel_init, m3_rchan_init),
256 KOBJMETHOD(channel_setformat, m3_rchan_setformat),
257 KOBJMETHOD(channel_setspeed, m3_rchan_setspeed),
258 KOBJMETHOD(channel_setblocksize, m3_rchan_setblocksize),
259 KOBJMETHOD(channel_trigger, m3_rchan_trigger),
260 KOBJMETHOD(channel_getptr, m3_rchan_getptr),
261 KOBJMETHOD(channel_getcaps, m3_rchan_getcaps),
262 KOBJMETHOD(channel_free, m3_rchan_free),
265 CHANNEL_DECLARE(m3_rch);
267 /* -------------------------------------------------------------------- */
268 /* some i/o convenience functions */
270 #define m3_rd_1(sc, regno) bus_space_read_1(sc->st, sc->sh, regno)
271 #define m3_rd_2(sc, regno) bus_space_read_2(sc->st, sc->sh, regno)
272 #define m3_rd_4(sc, regno) bus_space_read_4(sc->st, sc->sh, regno)
273 #define m3_wr_1(sc, regno, data) bus_space_write_1(sc->st, sc->sh, regno, data)
274 #define m3_wr_2(sc, regno, data) bus_space_write_2(sc->st, sc->sh, regno, data)
275 #define m3_wr_4(sc, regno, data) bus_space_write_4(sc->st, sc->sh, regno, data)
276 #define m3_rd_assp_code(sc, index) \
277 m3_rd_assp(sc, MEMTYPE_INTERNAL_CODE, index)
278 #define m3_wr_assp_code(sc, index, data) \
279 m3_wr_assp(sc, MEMTYPE_INTERNAL_CODE, index, data)
280 #define m3_rd_assp_data(sc, index) \
281 m3_rd_assp(sc, MEMTYPE_INTERNAL_DATA, index)
282 #define m3_wr_assp_data(sc, index, data) \
283 m3_wr_assp(sc, MEMTYPE_INTERNAL_DATA, index, data)
285 static __inline u_int16_t
286 m3_rd_assp(struct sc_info *sc, u_int16_t region, u_int16_t index)
288 m3_wr_2(sc, DSP_PORT_MEMORY_TYPE, region & MEMTYPE_MASK);
289 m3_wr_2(sc, DSP_PORT_MEMORY_INDEX, index);
290 return m3_rd_2(sc, DSP_PORT_MEMORY_DATA);
294 m3_wr_assp(struct sc_info *sc, u_int16_t region, u_int16_t index,
297 m3_wr_2(sc, DSP_PORT_MEMORY_TYPE, region & MEMTYPE_MASK);
298 m3_wr_2(sc, DSP_PORT_MEMORY_INDEX, index);
299 m3_wr_2(sc, DSP_PORT_MEMORY_DATA, data);
303 m3_wait(struct sc_info *sc)
307 for (i=0 ; i<20 ; i++) {
308 if ((m3_rd_1(sc, CODEC_STATUS) & 1) == 0) {
316 /* -------------------------------------------------------------------- */
320 m3_initcd(kobj_t kobj, void *devinfo)
322 struct sc_info *sc = (struct sc_info *)devinfo;
325 M3_DEBUG(CALL, ("m3_initcd\n"));
329 data = m3_rd_1(sc, CODEC_COMMAND);
330 return ((data & 0x1) ? 0 : 1);
334 m3_rdcd(kobj_t kobj, void *devinfo, int regno)
336 struct sc_info *sc = (struct sc_info *)devinfo;
340 device_printf(sc->dev, "m3_rdcd timed out.\n");
343 m3_wr_1(sc, CODEC_COMMAND, (regno & 0x7f) | 0x80);
344 DELAY(50); /* ac97 cycle = 20.8 usec */
346 device_printf(sc->dev, "m3_rdcd timed out.\n");
349 data = m3_rd_2(sc, CODEC_DATA);
354 m3_wrcd(kobj_t kobj, void *devinfo, int regno, u_int32_t data)
356 struct sc_info *sc = (struct sc_info *)devinfo;
358 device_printf(sc->dev, "m3_wrcd timed out.\n");
361 m3_wr_2(sc, CODEC_DATA, data);
362 m3_wr_1(sc, CODEC_COMMAND, regno & 0x7f);
363 DELAY(50); /* ac97 cycle = 20.8 usec */
367 /* -------------------------------------------------------------------- */
368 /* play channel interface */
370 #define LO(x) (((x) & 0x0000ffff) )
371 #define HI(x) (((x) & 0xffff0000) >> 16)
374 m3_pchan_init(kobj_t kobj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
376 struct sc_info *sc = devinfo;
377 struct sc_pchinfo *ch;
378 u_int32_t bus_addr, i;
379 int idx, data_bytes, dac_data;
380 int dsp_in_size, dsp_out_size, dsp_in_buf, dsp_out_buf;
385 {CDATA_LEFT_VOLUME, M3_DEFAULT_VOL},
386 {CDATA_RIGHT_VOLUME, M3_DEFAULT_VOL},
387 {SRC3_DIRECTION_OFFSET, 0} ,
388 {SRC3_DIRECTION_OFFSET + 3, 0x0000},
389 {SRC3_DIRECTION_OFFSET + 4, 0},
390 {SRC3_DIRECTION_OFFSET + 5, 0},
391 {SRC3_DIRECTION_OFFSET + 6, 0},
392 {SRC3_DIRECTION_OFFSET + 7, 0},
393 {SRC3_DIRECTION_OFFSET + 8, 0},
394 {SRC3_DIRECTION_OFFSET + 9, 0},
395 {SRC3_DIRECTION_OFFSET + 10, 0x8000},
396 {SRC3_DIRECTION_OFFSET + 11, 0xFF00},
397 {SRC3_DIRECTION_OFFSET + 13, 0},
398 {SRC3_DIRECTION_OFFSET + 14, 0},
399 {SRC3_DIRECTION_OFFSET + 15, 0},
400 {SRC3_DIRECTION_OFFSET + 16, 8},
401 {SRC3_DIRECTION_OFFSET + 17, 50*2},
402 {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1},
403 {SRC3_DIRECTION_OFFSET + 20, 0},
404 {SRC3_DIRECTION_OFFSET + 21, 0}
408 idx = sc->pch_cnt; /* dac instance number, no active reuse! */
409 M3_DEBUG(CHANGE, ("m3_pchan_init(dac=%d)\n", idx));
411 if (dir != PCMDIR_PLAY) {
413 device_printf(sc->dev, "m3_pchan_init not PCMDIR_PLAY\n");
417 data_bytes = (((MINISRC_TMP_BUFFER_SIZE & ~1) +
418 (MINISRC_IN_BUFFER_SIZE & ~1) +
419 (MINISRC_OUT_BUFFER_SIZE & ~1) + 4) + 255) &~ 255;
420 dac_data = 0x1100 + (data_bytes * idx);
422 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2);
423 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2);
424 dsp_in_buf = dac_data + (MINISRC_TMP_BUFFER_SIZE/2);
425 dsp_out_buf = dsp_in_buf + (dsp_in_size/2) + 1;
429 ch->dac_data = dac_data;
430 if (ch->dac_data + data_bytes/2 >= 0x1c00) {
432 device_printf(sc->dev, "m3_pchan_init: revb mem exhausted\n");
439 ch->fmt = SND_FORMAT(AFMT_U8, 1, 0);
440 ch->spd = DSP_DEFAULT_SPEED;
441 M3_UNLOCK(sc); /* XXX */
442 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, 0, sc->bufsz) != 0) {
443 device_printf(sc->dev, "m3_pchan_init chn_allocbuf failed\n");
447 ch->bufsize = sndbuf_getsize(ch->buffer);
449 /* host dma buffer pointers */
450 bus_addr = sndbuf_getbufaddr(ch->buffer);
452 device_printf(sc->dev, "m3_pchan_init unaligned bus_addr\n");
453 bus_addr = (bus_addr + 4) & ~3;
455 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_ADDRL, LO(bus_addr));
456 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_ADDRH, HI(bus_addr));
457 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_END_PLUS_1L,
458 LO(bus_addr + ch->bufsize));
459 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_END_PLUS_1H,
460 HI(bus_addr + ch->bufsize));
461 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTL,
463 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTH,
467 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_BEGIN, dsp_in_buf);
468 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_END_PLUS_1,
469 dsp_in_buf + dsp_in_size/2);
470 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_HEAD, dsp_in_buf);
471 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_TAIL, dsp_in_buf);
472 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_BEGIN, dsp_out_buf);
473 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_END_PLUS_1,
474 dsp_out_buf + dsp_out_size/2);
475 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_HEAD, dsp_out_buf);
476 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_TAIL, dsp_out_buf);
478 /* some per client initializers */
479 m3_wr_assp_data(sc, ch->dac_data + SRC3_DIRECTION_OFFSET + 12,
480 ch->dac_data + 40 + 8);
481 m3_wr_assp_data(sc, ch->dac_data + SRC3_DIRECTION_OFFSET + 19,
482 0x400 + MINISRC_COEF_LOC);
483 /* enable or disable low pass filter? (0xff if rate> 45000) */
484 m3_wr_assp_data(sc, ch->dac_data + SRC3_DIRECTION_OFFSET + 22, 0);
485 /* tell it which way dma is going? */
486 m3_wr_assp_data(sc, ch->dac_data + CDATA_DMA_CONTROL,
487 DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR +
488 DMAC_BLOCKF_SELECTOR);
490 /* set an armload of static initializers */
491 for(i = 0 ; i < (sizeof(pv) / sizeof(pv[0])) ; i++) {
492 m3_wr_assp_data(sc, ch->dac_data + pv[i].addr, pv[i].val);
495 /* put us in the packed task lists */
496 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC +
497 (sc->pch_cnt + sc->rch_cnt),
498 ch->dac_data >> DP_SHIFT_COUNT);
499 m3_wr_assp_data(sc, KDATA_DMA_XFER0 + (sc->pch_cnt + sc->rch_cnt),
500 ch->dac_data >> DP_SHIFT_COUNT);
501 m3_wr_assp_data(sc, KDATA_MIXER_XFER0 + sc->pch_cnt,
502 ch->dac_data >> DP_SHIFT_COUNT);
504 /* gotta start before stop */
505 m3_pchan_trigger_locked(NULL, ch, PCMTRIG_START);
506 /* silence noise on load */
507 m3_pchan_trigger_locked(NULL, ch, PCMTRIG_STOP);
516 m3_pchan_free(kobj_t kobj, void *chdata)
518 struct sc_pchinfo *ch = chdata;
519 struct sc_info *sc = ch->parent;
522 M3_DEBUG(CHANGE, ("m3_pchan_free(dac=%d)\n", ch->dac_idx));
525 * should remove this exact instance from the packed lists, but all
526 * are released at once (and in a stopped state) so this is ok.
528 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC +
529 (sc->pch_cnt - 1) + sc->rch_cnt, 0);
530 m3_wr_assp_data(sc, KDATA_DMA_XFER0 +
531 (sc->pch_cnt - 1) + sc->rch_cnt, 0);
532 m3_wr_assp_data(sc, KDATA_MIXER_XFER0 + (sc->pch_cnt-1), 0);
540 m3_pchan_setformat(kobj_t kobj, void *chdata, u_int32_t format)
542 struct sc_pchinfo *ch = chdata;
543 struct sc_info *sc = ch->parent;
548 ("m3_pchan_setformat(dac=%d, format=0x%x{%s-%s})\n",
550 format & (AFMT_U8|AFMT_S8) ? "8bit":"16bit",
551 (AFMT_CHANNEL(format) > 1) ? "STEREO":"MONO"));
554 data = (AFMT_CHANNEL(format) > 1)? 0 : 1;
555 m3_wr_assp_data(sc, ch->dac_data + SRC3_MODE_OFFSET, data);
558 data = ((format & AFMT_U8) || (format & AFMT_S8)) ? 1 : 0;
559 m3_wr_assp_data(sc, ch->dac_data + SRC3_WORD_LENGTH_OFFSET, data);
568 m3_pchan_setspeed(kobj_t kobj, void *chdata, u_int32_t speed)
570 struct sc_pchinfo *ch = chdata;
571 struct sc_info *sc = ch->parent;
575 M3_DEBUG(CHANGE, ("m3_pchan_setspeed(dac=%d, speed=%d)\n",
576 ch->dac_idx, speed));
578 if ((freq = ((speed << 15) + 24000) / 48000) != 0) {
582 m3_wr_assp_data(sc, ch->dac_data + CDATA_FREQUENCY, freq);
586 /* return closest possible speed */
591 m3_pchan_setblocksize(kobj_t kobj, void *chdata, u_int32_t blocksize)
593 struct sc_pchinfo *ch = chdata;
595 M3_DEBUG(CHANGE, ("m3_pchan_setblocksize(dac=%d, blocksize=%d)\n",
596 ch->dac_idx, blocksize));
598 return (sndbuf_getblksz(ch->buffer));
602 m3_pchan_trigger(kobj_t kobj, void *chdata, int go)
604 struct sc_pchinfo *ch = chdata;
605 struct sc_info *sc = ch->parent;
608 if (!PCMTRIG_COMMON(go))
612 ret = m3_pchan_trigger_locked(kobj, chdata, go);
619 m3_chan_active(struct sc_info *sc)
625 for (i = 0; i < sc->pch_cnt; i++)
626 ret += sc->pch[i].active;
628 for (i = 0; i < sc->rch_cnt; i++)
629 ret += sc->rch[i].active;
635 m3_pchan_trigger_locked(kobj_t kobj, void *chdata, int go)
637 struct sc_pchinfo *ch = chdata;
638 struct sc_info *sc = ch->parent;
642 M3_DEBUG(go == PCMTRIG_START ? CHANGE :
643 go == PCMTRIG_STOP ? CHANGE :
644 go == PCMTRIG_ABORT ? CHANGE :
646 ("m3_pchan_trigger(dac=%d, go=0x%x{%s})\n", ch->dac_idx, go,
647 go == PCMTRIG_START ? "PCMTRIG_START" :
648 go == PCMTRIG_STOP ? "PCMTRIG_STOP" :
649 go == PCMTRIG_ABORT ? "PCMTRIG_ABORT" : "ignore"));
659 sc->pch_active_cnt++;
661 /*[[inc_timer_users]]*/
662 if (m3_chan_active(sc) == 1) {
663 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 240);
664 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 240);
665 data = m3_rd_2(sc, HOST_INT_CTRL);
666 m3_wr_2(sc, HOST_INT_CTRL, data | CLKRUN_GEN_ENABLE);
669 m3_wr_assp_data(sc, ch->dac_data + CDATA_INSTANCE_READY, 1);
670 m3_wr_assp_data(sc, KDATA_MIXER_TASK_NUMBER,
676 if (ch->active == 0) {
680 sc->pch_active_cnt--;
682 /* XXX should the channel be drained? */
683 /*[[dec_timer_users]]*/
684 if (m3_chan_active(sc) == 0) {
685 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 0);
686 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 0);
687 data = m3_rd_2(sc, HOST_INT_CTRL);
688 m3_wr_2(sc, HOST_INT_CTRL, data & ~CLKRUN_GEN_ENABLE);
691 m3_wr_assp_data(sc, ch->dac_data + CDATA_INSTANCE_READY, 0);
692 m3_wr_assp_data(sc, KDATA_MIXER_TASK_NUMBER,
696 case PCMTRIG_EMLDMAWR:
697 /* got play irq, transfer next buffer - ignore if using dma */
698 case PCMTRIG_EMLDMARD:
699 /* got rec irq, transfer next buffer - ignore if using dma */
707 m3_pchan_getptr_internal(struct sc_pchinfo *ch)
709 struct sc_info *sc = ch->parent;
710 u_int32_t hi, lo, bus_base, bus_crnt;
712 bus_base = sndbuf_getbufaddr(ch->buffer);
713 hi = m3_rd_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTH);
714 lo = m3_rd_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTL);
715 bus_crnt = lo | (hi << 16);
717 M3_DEBUG(CALL, ("m3_pchan_getptr(dac=%d) result=%d\n",
718 ch->dac_idx, bus_crnt - bus_base));
720 return (bus_crnt - bus_base); /* current byte offset of channel */
724 m3_pchan_getptr(kobj_t kobj, void *chdata)
726 struct sc_pchinfo *ch = chdata;
727 struct sc_info *sc = ch->parent;
737 static struct pcmchan_caps *
738 m3_pchan_getcaps(kobj_t kobj, void *chdata)
740 struct sc_pchinfo *ch = chdata;
742 M3_DEBUG(CALL, ("m3_pchan_getcaps(dac=%d)\n", ch->dac_idx));
747 /* -------------------------------------------------------------------- */
748 /* rec channel interface */
751 m3_rchan_init(kobj_t kobj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
753 struct sc_info *sc = devinfo;
754 struct sc_rchinfo *ch;
755 u_int32_t bus_addr, i;
757 int idx, data_bytes, adc_data;
758 int dsp_in_size, dsp_out_size, dsp_in_buf, dsp_out_buf;
763 {CDATA_LEFT_VOLUME, M3_DEFAULT_VOL},
764 {CDATA_RIGHT_VOLUME, M3_DEFAULT_VOL},
765 {SRC3_DIRECTION_OFFSET, 1},
766 {SRC3_DIRECTION_OFFSET + 3, 0x0000},
767 {SRC3_DIRECTION_OFFSET + 4, 0},
768 {SRC3_DIRECTION_OFFSET + 5, 0},
769 {SRC3_DIRECTION_OFFSET + 6, 0},
770 {SRC3_DIRECTION_OFFSET + 7, 0},
771 {SRC3_DIRECTION_OFFSET + 8, 0},
772 {SRC3_DIRECTION_OFFSET + 9, 0},
773 {SRC3_DIRECTION_OFFSET + 10, 0x8000},
774 {SRC3_DIRECTION_OFFSET + 11, 0xFF00},
775 {SRC3_DIRECTION_OFFSET + 13, 0},
776 {SRC3_DIRECTION_OFFSET + 14, 0},
777 {SRC3_DIRECTION_OFFSET + 15, 0},
778 {SRC3_DIRECTION_OFFSET + 16, 50},
779 {SRC3_DIRECTION_OFFSET + 17, 8},
780 {SRC3_DIRECTION_OFFSET + 18, 0},
781 {SRC3_DIRECTION_OFFSET + 19, 0},
782 {SRC3_DIRECTION_OFFSET + 20, 0},
783 {SRC3_DIRECTION_OFFSET + 21, 0},
784 {SRC3_DIRECTION_OFFSET + 22, 0xff}
788 idx = sc->rch_cnt; /* adc instance number, no active reuse! */
789 M3_DEBUG(CHANGE, ("m3_rchan_init(adc=%d)\n", idx));
791 if (dir != PCMDIR_REC) {
793 device_printf(sc->dev, "m3_pchan_init not PCMDIR_REC\n");
797 data_bytes = (((MINISRC_TMP_BUFFER_SIZE & ~1) +
798 (MINISRC_IN_BUFFER_SIZE & ~1) +
799 (MINISRC_OUT_BUFFER_SIZE & ~1) + 4) + 255) &~ 255;
800 adc_data = 0x1100 + (data_bytes * idx) + data_bytes/2;
801 dsp_in_size = MINISRC_IN_BUFFER_SIZE + (0x10 * 2);
802 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2);
803 dsp_in_buf = adc_data + (MINISRC_TMP_BUFFER_SIZE / 2);
804 dsp_out_buf = dsp_in_buf + (dsp_in_size / 2) + 1;
808 ch->adc_data = adc_data;
809 if (ch->adc_data + data_bytes/2 >= 0x1c00) {
811 device_printf(sc->dev, "m3_rchan_init: revb mem exhausted\n");
818 ch->fmt = SND_FORMAT(AFMT_U8, 1, 0);
819 ch->spd = DSP_DEFAULT_SPEED;
820 M3_UNLOCK(sc); /* XXX */
821 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, 0, sc->bufsz) != 0) {
822 device_printf(sc->dev, "m3_rchan_init chn_allocbuf failed\n");
826 ch->bufsize = sndbuf_getsize(ch->buffer);
828 /* host dma buffer pointers */
829 bus_addr = sndbuf_getbufaddr(ch->buffer);
831 device_printf(sc->dev, "m3_rchan_init unaligned bus_addr\n");
832 bus_addr = (bus_addr + 4) & ~3;
834 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_ADDRL, LO(bus_addr));
835 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_ADDRH, HI(bus_addr));
836 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_END_PLUS_1L,
837 LO(bus_addr + ch->bufsize));
838 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_END_PLUS_1H,
839 HI(bus_addr + ch->bufsize));
840 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTL,
842 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTH,
846 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_BEGIN, dsp_in_buf);
847 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_END_PLUS_1,
848 dsp_in_buf + dsp_in_size/2);
849 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_HEAD, dsp_in_buf);
850 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_TAIL, dsp_in_buf);
851 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_BEGIN, dsp_out_buf);
852 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_END_PLUS_1,
853 dsp_out_buf + dsp_out_size/2);
854 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_HEAD, dsp_out_buf);
855 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_TAIL, dsp_out_buf);
857 /* some per client initializers */
858 m3_wr_assp_data(sc, ch->adc_data + SRC3_DIRECTION_OFFSET + 12,
859 ch->adc_data + 40 + 8);
860 m3_wr_assp_data(sc, ch->adc_data + CDATA_DMA_CONTROL,
861 DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT +
862 DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
864 /* set an armload of static initializers */
865 for(i = 0 ; i < (sizeof(rv) / sizeof(rv[0])) ; i++) {
866 m3_wr_assp_data(sc, ch->adc_data + rv[i].addr, rv[i].val);
869 /* put us in the packed task lists */
870 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC +
871 (sc->pch_cnt + sc->rch_cnt),
872 ch->adc_data >> DP_SHIFT_COUNT);
873 m3_wr_assp_data(sc, KDATA_DMA_XFER0 + (sc->pch_cnt + sc->rch_cnt),
874 ch->adc_data >> DP_SHIFT_COUNT);
875 m3_wr_assp_data(sc, KDATA_ADC1_XFER0 + sc->rch_cnt,
876 ch->adc_data >> DP_SHIFT_COUNT);
878 /* gotta start before stop */
879 m3_rchan_trigger_locked(NULL, ch, PCMTRIG_START);
881 m3_rchan_trigger_locked(NULL, ch, PCMTRIG_STOP);
890 m3_rchan_free(kobj_t kobj, void *chdata)
892 struct sc_rchinfo *ch = chdata;
893 struct sc_info *sc = ch->parent;
896 M3_DEBUG(CHANGE, ("m3_rchan_free(adc=%d)\n", ch->adc_idx));
899 * should remove this exact instance from the packed lists, but all
900 * are released at once (and in a stopped state) so this is ok.
902 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC +
903 (sc->rch_cnt - 1) + sc->pch_cnt, 0);
904 m3_wr_assp_data(sc, KDATA_DMA_XFER0 +
905 (sc->rch_cnt - 1) + sc->pch_cnt, 0);
906 m3_wr_assp_data(sc, KDATA_ADC1_XFER0 + (sc->rch_cnt - 1), 0);
914 m3_rchan_setformat(kobj_t kobj, void *chdata, u_int32_t format)
916 struct sc_rchinfo *ch = chdata;
917 struct sc_info *sc = ch->parent;
922 ("m3_rchan_setformat(dac=%d, format=0x%x{%s-%s})\n",
924 format & (AFMT_U8|AFMT_S8) ? "8bit":"16bit",
925 (AFMT_CHANNEL(format) > 1) ? "STEREO":"MONO"));
928 data = (AFMT_CHANNEL(format) > 1) ? 0 : 1;
929 m3_wr_assp_data(sc, ch->adc_data + SRC3_MODE_OFFSET, data);
932 data = ((format & AFMT_U8) || (format & AFMT_S8)) ? 1 : 0;
933 m3_wr_assp_data(sc, ch->adc_data + SRC3_WORD_LENGTH_OFFSET, data);
941 m3_rchan_setspeed(kobj_t kobj, void *chdata, u_int32_t speed)
943 struct sc_rchinfo *ch = chdata;
944 struct sc_info *sc = ch->parent;
948 M3_DEBUG(CHANGE, ("m3_rchan_setspeed(adc=%d, speed=%d)\n",
949 ch->adc_idx, speed));
951 if ((freq = ((speed << 15) + 24000) / 48000) != 0) {
955 m3_wr_assp_data(sc, ch->adc_data + CDATA_FREQUENCY, freq);
959 /* return closest possible speed */
964 m3_rchan_setblocksize(kobj_t kobj, void *chdata, u_int32_t blocksize)
966 struct sc_rchinfo *ch = chdata;
968 M3_DEBUG(CHANGE, ("m3_rchan_setblocksize(adc=%d, blocksize=%d)\n",
969 ch->adc_idx, blocksize));
971 return (sndbuf_getblksz(ch->buffer));
975 m3_rchan_trigger(kobj_t kobj, void *chdata, int go)
977 struct sc_rchinfo *ch = chdata;
978 struct sc_info *sc = ch->parent;
981 if (!PCMTRIG_COMMON(go))
985 ret = m3_rchan_trigger_locked(kobj, chdata, go);
992 m3_rchan_trigger_locked(kobj_t kobj, void *chdata, int go)
994 struct sc_rchinfo *ch = chdata;
995 struct sc_info *sc = ch->parent;
999 M3_DEBUG(go == PCMTRIG_START ? CHANGE :
1000 go == PCMTRIG_STOP ? CHANGE :
1001 go == PCMTRIG_ABORT ? CHANGE :
1003 ("m3_rchan_trigger(adc=%d, go=0x%x{%s})\n", ch->adc_idx, go,
1004 go == PCMTRIG_START ? "PCMTRIG_START" :
1005 go == PCMTRIG_STOP ? "PCMTRIG_STOP" :
1006 go == PCMTRIG_ABORT ? "PCMTRIG_ABORT" : "ignore"));
1017 /*[[inc_timer_users]]*/
1018 if (m3_chan_active(sc) == 1) {
1019 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 240);
1020 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 240);
1021 data = m3_rd_2(sc, HOST_INT_CTRL);
1022 m3_wr_2(sc, HOST_INT_CTRL, data | CLKRUN_GEN_ENABLE);
1025 m3_wr_assp_data(sc, KDATA_ADC1_REQUEST, 1);
1026 m3_wr_assp_data(sc, ch->adc_data + CDATA_INSTANCE_READY, 1);
1031 if (ch->active == 0) {
1036 /*[[dec_timer_users]]*/
1037 if (m3_chan_active(sc) == 0) {
1038 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 0);
1039 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 0);
1040 data = m3_rd_2(sc, HOST_INT_CTRL);
1041 m3_wr_2(sc, HOST_INT_CTRL, data & ~CLKRUN_GEN_ENABLE);
1044 m3_wr_assp_data(sc, ch->adc_data + CDATA_INSTANCE_READY, 0);
1045 m3_wr_assp_data(sc, KDATA_ADC1_REQUEST, 0);
1048 case PCMTRIG_EMLDMAWR:
1049 /* got play irq, transfer next buffer - ignore if using dma */
1050 case PCMTRIG_EMLDMARD:
1051 /* got rec irq, transfer next buffer - ignore if using dma */
1059 m3_rchan_getptr_internal(struct sc_rchinfo *ch)
1061 struct sc_info *sc = ch->parent;
1062 u_int32_t hi, lo, bus_base, bus_crnt;
1064 bus_base = sndbuf_getbufaddr(ch->buffer);
1065 hi = m3_rd_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTH);
1066 lo = m3_rd_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTL);
1067 bus_crnt = lo | (hi << 16);
1069 M3_DEBUG(CALL, ("m3_rchan_getptr(adc=%d) result=%d\n",
1070 ch->adc_idx, bus_crnt - bus_base));
1072 return (bus_crnt - bus_base); /* current byte offset of channel */
1076 m3_rchan_getptr(kobj_t kobj, void *chdata)
1078 struct sc_rchinfo *ch = chdata;
1079 struct sc_info *sc = ch->parent;
1089 static struct pcmchan_caps *
1090 m3_rchan_getcaps(kobj_t kobj, void *chdata)
1092 struct sc_rchinfo *ch = chdata;
1094 M3_DEBUG(CALL, ("m3_rchan_getcaps(adc=%d)\n", ch->adc_idx));
1099 /* -------------------------------------------------------------------- */
1100 /* The interrupt handler */
1105 struct sc_info *sc = (struct sc_info *)p;
1106 struct sc_pchinfo *pch;
1107 struct sc_rchinfo *rch;
1108 u_int32_t status, ctl, i, delta;
1110 M3_DEBUG(INTR, ("m3_intr\n"));
1113 status = m3_rd_1(sc, HOST_INT_STATUS);
1119 m3_wr_1(sc, HOST_INT_STATUS, 0xff); /* ack the int? */
1121 if (status & HV_INT_PENDING) {
1124 event = m3_rd_1(sc, HW_VOL_COUNTER_MASTER);
1127 mixer_hwvol_mute(sc->dev);
1130 mixer_hwvol_step(sc->dev, 1, 1);
1133 mixer_hwvol_step(sc->dev, -1, -1);
1138 device_printf(sc->dev, "Unknown HWVOL event\n");
1140 m3_wr_1(sc, HW_VOL_COUNTER_MASTER, 0x88);
1144 if (status & ASSP_INT_PENDING) {
1145 ctl = m3_rd_1(sc, ASSP_CONTROL_B);
1146 if (!(ctl & STOP_ASSP_CLOCK)) {
1147 ctl = m3_rd_1(sc, ASSP_HOST_INT_STATUS);
1148 if (ctl & DSP2HOST_REQ_TIMER) {
1149 m3_wr_1(sc, ASSP_HOST_INT_STATUS,
1150 DSP2HOST_REQ_TIMER);
1151 /*[[ess_update_ptr]]*/
1152 goto m3_handle_channel_intr;
1157 goto m3_handle_channel_intr_out;
1159 m3_handle_channel_intr:
1160 for (i=0 ; i<sc->pch_cnt ; i++) {
1163 pch->ptr = m3_pchan_getptr_internal(pch);
1164 delta = pch->bufsize + pch->ptr - pch->prevptr;
1165 delta %= pch->bufsize;
1166 if (delta < sndbuf_getblksz(pch->buffer))
1168 pch->prevptr = pch->ptr;
1170 chn_intr(pch->channel);
1174 for (i=0 ; i<sc->rch_cnt ; i++) {
1177 rch->ptr = m3_rchan_getptr_internal(rch);
1178 delta = rch->bufsize + rch->ptr - rch->prevptr;
1179 delta %= rch->bufsize;
1180 if (delta < sndbuf_getblksz(rch->buffer))
1182 rch->prevptr = rch->ptr;
1184 chn_intr(rch->channel);
1189 m3_handle_channel_intr_out:
1193 /* -------------------------------------------------------------------- */
1197 m3_power(struct sc_info *sc, int state)
1201 M3_DEBUG(CHANGE, ("m3_power(%d)\n", state));
1204 data = pci_read_config(sc->dev, 0x34, 1);
1205 if (pci_read_config(sc->dev, data, 1) == 1) {
1206 pci_write_config(sc->dev, data + 4, state, 1);
1213 m3_init(struct sc_info *sc)
1215 u_int32_t data, i, size;
1216 u_int8_t reset_state;
1219 M3_DEBUG(CHANGE, ("m3_init\n"));
1221 /* diable legacy emulations. */
1222 data = pci_read_config(sc->dev, PCI_LEGACY_AUDIO_CTRL, 2);
1223 data |= DISABLE_LEGACY;
1224 pci_write_config(sc->dev, PCI_LEGACY_AUDIO_CTRL, data, 2);
1228 reset_state = m3_assp_halt(sc);
1232 /* [m3_assp_init] */
1233 /* zero kernel data */
1234 size = REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA;
1235 for(i = 0 ; i < size / 2 ; i++) {
1236 m3_wr_assp_data(sc, KDATA_BASE_ADDR + i, 0);
1238 /* zero mixer data? */
1239 size = REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA;
1240 for(i = 0 ; i < size / 2 ; i++) {
1241 m3_wr_assp_data(sc, KDATA_BASE_ADDR2 + i, 0);
1243 /* init dma pointer */
1244 m3_wr_assp_data(sc, KDATA_CURRENT_DMA,
1246 /* write kernel into code memory */
1247 size = sizeof(gaw_kernel_vect_code);
1248 for(i = 0 ; i < size / 2; i++) {
1249 m3_wr_assp_code(sc, REV_B_CODE_MEMORY_BEGIN + i,
1250 gaw_kernel_vect_code[i]);
1253 * We only have this one client and we know that 0x400 is free in
1254 * our kernel's mem map, so lets just drop it there. It seems that
1255 * the minisrc doesn't need vectors, so we won't bother with them..
1257 size = sizeof(gaw_minisrc_code_0400);
1258 for(i = 0 ; i < size / 2; i++) {
1259 m3_wr_assp_code(sc, 0x400 + i, gaw_minisrc_code_0400[i]);
1261 /* write the coefficients for the low pass filter? */
1262 size = sizeof(minisrc_lpf);
1263 for(i = 0; i < size / 2 ; i++) {
1264 m3_wr_assp_code(sc,0x400 + MINISRC_COEF_LOC + i,
1267 m3_wr_assp_code(sc, 0x400 + MINISRC_COEF_LOC + size, 0x8000);
1268 /* the minisrc is the only thing on our task list */
1269 m3_wr_assp_data(sc, KDATA_TASK0, 0x400);
1270 /* init the mixer number */
1271 m3_wr_assp_data(sc, KDATA_MIXER_TASK_NUMBER, 0);
1272 /* extreme kernel master volume */
1273 m3_wr_assp_data(sc, KDATA_DAC_LEFT_VOLUME, M3_DEFAULT_VOL);
1274 m3_wr_assp_data(sc, KDATA_DAC_RIGHT_VOLUME, M3_DEFAULT_VOL);
1278 /* [m3_assp_client_init] (only one client at index 0) */
1279 for (i=0x1100 ; i<0x1c00 ; i++) {
1280 m3_wr_assp_data(sc, i, 0); /* zero entire dac/adc area */
1283 /* [m3_assp_continue] */
1284 m3_wr_1(sc, DSP_PORT_CONTROL_REG_B, reset_state | REGB_ENABLE_RESET);
1290 m3_uninit(struct sc_info *sc)
1292 M3_DEBUG(CHANGE, ("m3_uninit\n"));
1296 /* -------------------------------------------------------------------- */
1297 /* Probe and attach the card */
1300 m3_pci_probe(device_t dev)
1302 struct m3_card_type *card;
1304 M3_DEBUG(CALL, ("m3_pci_probe(0x%x)\n", pci_get_devid(dev)));
1306 for (card = m3_card_types ; card->pci_id ; card++) {
1307 if (pci_get_devid(dev) == card->pci_id) {
1308 device_set_desc(dev, card->name);
1309 return BUS_PROBE_DEFAULT;
1316 m3_pci_attach(device_t dev)
1319 struct ac97_info *codec = NULL;
1320 char status[SND_STATUSLEN];
1321 struct m3_card_type *card;
1322 int i, len, dacn, adcn;
1324 M3_DEBUG(CALL, ("m3_pci_attach\n"));
1326 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
1328 sc->type = pci_get_devid(dev);
1329 sc->sc_lock = snd_mtxcreate(device_get_nameunit(dev),
1330 "snd_maestro3 softc");
1331 for (card = m3_card_types ; card->pci_id ; card++) {
1332 if (sc->type == card->pci_id) {
1333 sc->which = card->which;
1334 sc->delay1 = card->delay1;
1335 sc->delay2 = card->delay2;
1340 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
1344 else if (i > M3_PCHANS)
1353 pci_enable_busmaster(dev);
1355 sc->regid = PCIR_BAR(0);
1356 sc->regtype = SYS_RES_MEMORY;
1357 sc->reg = bus_alloc_resource_any(dev, sc->regtype, &sc->regid,
1360 sc->regtype = SYS_RES_IOPORT;
1361 sc->reg = bus_alloc_resource_any(dev, sc->regtype, &sc->regid,
1365 device_printf(dev, "unable to allocate register space\n");
1368 sc->st = rman_get_bustag(sc->reg);
1369 sc->sh = rman_get_bushandle(sc->reg);
1372 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid,
1373 RF_ACTIVE | RF_SHAREABLE);
1375 device_printf(dev, "unable to allocate interrupt\n");
1379 if (snd_setup_intr(dev, sc->irq, INTR_MPSAFE, m3_intr, sc, &sc->ih)) {
1380 device_printf(dev, "unable to setup interrupt\n");
1384 sc->bufsz = pcm_getbuffersize(dev, M3_BUFSIZE_MIN, M3_BUFSIZE_DEFAULT,
1387 if (bus_dma_tag_create(
1388 bus_get_dma_tag(dev), /* parent */
1389 2, 0, /* alignment, boundary */
1390 M3_MAXADDR, /* lowaddr */
1391 BUS_SPACE_MAXADDR, /* highaddr */
1392 NULL, NULL, /* filtfunc, filtfuncarg */
1393 sc->bufsz, /* maxsize */
1395 0x3ffff, /* maxsegz */
1397 NULL, /* lockfunc */
1398 NULL, /* lockfuncarg */
1399 &sc->parent_dmat) != 0) {
1400 device_printf(dev, "unable to create dma tag\n");
1405 m3_power(sc, 0); /* power up */
1410 device_printf(dev, "unable to initialize the card\n");
1414 /* create/init mixer */
1415 codec = AC97_CREATE(dev, sc, m3_codec);
1416 if (codec == NULL) {
1417 device_printf(dev, "ac97_create error\n");
1420 if (mixer_init(dev, ac97_getmixerclass(), codec)) {
1421 device_printf(dev, "mixer_init error\n");
1427 if (pcm_register(dev, sc, dacn, adcn)) {
1428 device_printf(dev, "pcm_register error\n");
1431 for (i=0 ; i<dacn ; i++) {
1432 if (pcm_addchan(dev, PCMDIR_PLAY, &m3_pch_class, sc)) {
1433 device_printf(dev, "pcm_addchan (play) error\n");
1437 for (i=0 ; i<adcn ; i++) {
1438 if (pcm_addchan(dev, PCMDIR_REC, &m3_rch_class, sc)) {
1439 device_printf(dev, "pcm_addchan (rec) error\n");
1443 snprintf(status, SND_STATUSLEN, "at %s 0x%lx irq %ld %s",
1444 (sc->regtype == SYS_RES_IOPORT)? "io" : "memory",
1445 rman_get_start(sc->reg), rman_get_start(sc->irq),
1446 PCM_KLDSTRING(snd_maestro3));
1447 if (pcm_setstatus(dev, status)) {
1448 device_printf(dev, "attach: pcm_setstatus error\n");
1452 mixer_hwvol_init(dev);
1454 /* Create the buffer for saving the card state during suspend */
1455 len = sizeof(u_int16_t) * (REV_B_CODE_MEMORY_LENGTH +
1456 REV_B_DATA_MEMORY_LENGTH);
1457 sc->savemem = (u_int16_t*)malloc(len, M_DEVBUF, M_WAITOK | M_ZERO);
1463 ac97_destroy(codec);
1465 bus_teardown_intr(dev, sc->irq, sc->ih);
1467 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
1469 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg);
1470 if (sc->parent_dmat)
1471 bus_dma_tag_destroy(sc->parent_dmat);
1473 snd_mtxfree(sc->sc_lock);
1479 m3_pci_detach(device_t dev)
1481 struct sc_info *sc = pcm_getdevinfo(dev);
1484 M3_DEBUG(CALL, ("m3_pci_detach\n"));
1486 if ((r = pcm_unregister(dev)) != 0) {
1491 m3_uninit(sc); /* shutdown chip */
1492 m3_power(sc, 3); /* power off */
1495 bus_teardown_intr(dev, sc->irq, sc->ih);
1496 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
1497 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg);
1498 bus_dma_tag_destroy(sc->parent_dmat);
1500 free(sc->savemem, M_DEVBUF);
1501 snd_mtxfree(sc->sc_lock);
1507 m3_pci_suspend(device_t dev)
1509 struct sc_info *sc = pcm_getdevinfo(dev);
1512 M3_DEBUG(CHANGE, ("m3_pci_suspend\n"));
1515 for (i=0 ; i<sc->pch_cnt ; i++) {
1516 if (sc->pch[i].active) {
1517 m3_pchan_trigger_locked(NULL, &sc->pch[i],
1521 for (i=0 ; i<sc->rch_cnt ; i++) {
1522 if (sc->rch[i].active) {
1523 m3_rchan_trigger_locked(NULL, &sc->rch[i],
1527 DELAY(10 * 1000); /* give things a chance to stop */
1529 /* Disable interrupts */
1530 m3_wr_2(sc, HOST_INT_CTRL, 0);
1531 m3_wr_1(sc, ASSP_CONTROL_C, 0);
1535 /* Save the state of the ASSP */
1536 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
1537 sc->savemem[index++] = m3_rd_assp_code(sc, i);
1538 for (i = REV_B_DATA_MEMORY_BEGIN; i <= REV_B_DATA_MEMORY_END; i++)
1539 sc->savemem[index++] = m3_rd_assp_data(sc, i);
1541 /* Power down the card to D3 state */
1549 m3_pci_resume(device_t dev)
1551 struct sc_info *sc = pcm_getdevinfo(dev);
1553 u_int8_t reset_state;
1555 M3_DEBUG(CHANGE, ("m3_pci_resume\n"));
1558 /* Power the card back to D0 */
1563 reset_state = m3_assp_halt(sc);
1567 /* Restore the ASSP state */
1568 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
1569 m3_wr_assp_code(sc, i, sc->savemem[index++]);
1570 for (i = REV_B_DATA_MEMORY_BEGIN; i <= REV_B_DATA_MEMORY_END; i++)
1571 m3_wr_assp_data(sc, i, sc->savemem[index++]);
1573 /* Restart the DMA engine */
1574 m3_wr_assp_data(sc, KDATA_DMA_ACTIVE, 0);
1576 /* [m3_assp_continue] */
1577 m3_wr_1(sc, DSP_PORT_CONTROL_REG_B, reset_state | REGB_ENABLE_RESET);
1583 M3_UNLOCK(sc); /* XXX */
1584 if (mixer_reinit(dev) == -1) {
1585 device_printf(dev, "unable to reinitialize the mixer\n");
1590 /* Turn the channels back on */
1591 for (i=0 ; i<sc->pch_cnt ; i++) {
1592 if (sc->pch[i].active) {
1593 m3_pchan_trigger_locked(NULL, &sc->pch[i],
1597 for (i=0 ; i<sc->rch_cnt ; i++) {
1598 if (sc->rch[i].active) {
1599 m3_rchan_trigger_locked(NULL, &sc->rch[i],
1609 m3_pci_shutdown(device_t dev)
1611 struct sc_info *sc = pcm_getdevinfo(dev);
1613 M3_DEBUG(CALL, ("m3_pci_shutdown\n"));
1616 m3_power(sc, 3); /* power off */
1623 m3_assp_halt(struct sc_info *sc)
1625 u_int8_t data, reset_state;
1629 data = m3_rd_1(sc, DSP_PORT_CONTROL_REG_B);
1630 reset_state = data & ~REGB_STOP_CLOCK; /* remember for continue */
1632 m3_wr_1(sc, DSP_PORT_CONTROL_REG_B, reset_state & ~REGB_ENABLE_RESET);
1633 DELAY(10 * 1000); /* necessary? */
1639 m3_config(struct sc_info *sc)
1641 u_int32_t data, hv_cfg;
1648 * The volume buttons can be wired up via two different sets of pins.
1649 * This presents a problem since we can't tell which way it's
1650 * configured. Allow the user to set a hint in order to twiddle
1653 if (resource_int_value(device_get_name(sc->dev),
1654 device_get_unit(sc->dev),
1655 "hwvol_config", &hint) == 0)
1656 hv_cfg = (hint > 0) ? HV_BUTTON_FROM_GD : 0;
1658 hv_cfg = HV_BUTTON_FROM_GD;
1661 data = pci_read_config(sc->dev, PCI_ALLEGRO_CONFIG, 4);
1662 data &= ~HV_BUTTON_FROM_GD;
1663 data |= REDUCED_DEBOUNCE | HV_CTRL_ENABLE | hv_cfg;
1664 data |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING;
1665 pci_write_config(sc->dev, PCI_ALLEGRO_CONFIG, data, 4);
1667 m3_wr_1(sc, ASSP_CONTROL_B, RESET_ASSP);
1668 data = pci_read_config(sc->dev, PCI_ALLEGRO_CONFIG, 4);
1669 data &= ~INT_CLK_SELECT;
1670 if (sc->which == ESS_MAESTRO3) {
1671 data &= ~INT_CLK_MULT_ENABLE;
1672 data |= INT_CLK_SRC_NOT_PCI;
1674 data &= ~(CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2);
1675 pci_write_config(sc->dev, PCI_ALLEGRO_CONFIG, data, 4);
1677 if (sc->which == ESS_ALLEGRO_1) {
1678 data = pci_read_config(sc->dev, PCI_USER_CONFIG, 4);
1679 data |= IN_CLK_12MHZ_SELECT;
1680 pci_write_config(sc->dev, PCI_USER_CONFIG, data, 4);
1683 data = m3_rd_1(sc, ASSP_CONTROL_A);
1684 data &= ~(DSP_CLK_36MHZ_SELECT | ASSP_CLK_49MHZ_SELECT);
1685 data |= ASSP_CLK_49MHZ_SELECT; /*XXX assumes 49MHZ dsp XXX*/
1686 data |= ASSP_0_WS_ENABLE;
1687 m3_wr_1(sc, ASSP_CONTROL_A, data);
1689 m3_wr_1(sc, ASSP_CONTROL_B, RUN_ASSP);
1693 m3_enable_ints(struct sc_info *sc)
1697 m3_wr_2(sc, HOST_INT_CTRL, ASSP_INT_ENABLE | HV_INT_ENABLE);
1698 data = m3_rd_1(sc, ASSP_CONTROL_C);
1699 m3_wr_1(sc, ASSP_CONTROL_C, data | ASSP_HOST_INT_ENABLE);
1703 m3_amp_enable(struct sc_info *sc)
1705 u_int32_t gpo, polarity_port, polarity;
1710 switch (sc->which) {
1712 polarity_port = 0x1800;
1715 polarity_port = 0x1100;
1718 panic("bad sc->which");
1720 gpo = (polarity_port >> 8) & 0x0f;
1721 polarity = polarity_port >> 12;
1722 polarity = !polarity; /* enable */
1723 polarity = polarity << gpo;
1725 m3_wr_2(sc, GPIO_MASK, ~gpo);
1726 data = m3_rd_2(sc, GPIO_DIRECTION);
1727 m3_wr_2(sc, GPIO_DIRECTION, data | gpo);
1728 data = GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity;
1729 m3_wr_2(sc, GPIO_DATA, data);
1730 m3_wr_2(sc, GPIO_MASK, ~0);
1734 m3_codec_reset(struct sc_info *sc)
1736 u_int16_t data, dir;
1741 data = m3_rd_2(sc, GPIO_DIRECTION);
1742 dir = data | 0x10; /* assuming pci bus master? */
1744 /* [[remote_codec_config]] */
1745 data = m3_rd_2(sc, RING_BUS_CTRL_B);
1746 m3_wr_2(sc, RING_BUS_CTRL_B, data & ~SECOND_CODEC_ID_MASK);
1747 data = m3_rd_2(sc, SDO_OUT_DEST_CTRL);
1748 m3_wr_2(sc, SDO_OUT_DEST_CTRL, data & ~COMMAND_ADDR_OUT);
1749 data = m3_rd_2(sc, SDO_IN_DEST_CTRL);
1750 m3_wr_2(sc, SDO_IN_DEST_CTRL, data & ~STATUS_ADDR_IN);
1752 m3_wr_2(sc, RING_BUS_CTRL_A, IO_SRAM_ENABLE);
1755 m3_wr_2(sc, GPIO_DIRECTION, dir & ~GPO_PRIMARY_AC97);
1756 m3_wr_2(sc, GPIO_MASK, ~GPO_PRIMARY_AC97);
1757 m3_wr_2(sc, GPIO_DATA, 0);
1758 m3_wr_2(sc, GPIO_DIRECTION, dir | GPO_PRIMARY_AC97);
1759 DELAY(sc->delay1 * 1000); /*delay1 (ALLEGRO:50, MAESTRO3:20)*/
1760 m3_wr_2(sc, GPIO_DATA, GPO_PRIMARY_AC97);
1762 m3_wr_2(sc, RING_BUS_CTRL_A, IO_SRAM_ENABLE |
1763 SERIAL_AC_LINK_ENABLE);
1764 m3_wr_2(sc, GPIO_MASK, ~0);
1765 DELAY(sc->delay2 * 1000); /*delay2 (ALLEGRO:800, MAESTRO3:500)*/
1767 /* [[try read vendor]] */
1768 data = m3_rdcd(NULL, sc, 0x7c);
1769 if ((data == 0) || (data == 0xffff)) {
1772 device_printf(sc->dev, "Codec reset failed\n");
1775 device_printf(sc->dev, "Codec reset retry\n");
1780 static device_method_t m3_methods[] = {
1781 DEVMETHOD(device_probe, m3_pci_probe),
1782 DEVMETHOD(device_attach, m3_pci_attach),
1783 DEVMETHOD(device_detach, m3_pci_detach),
1784 DEVMETHOD(device_suspend, m3_pci_suspend),
1785 DEVMETHOD(device_resume, m3_pci_resume),
1786 DEVMETHOD(device_shutdown, m3_pci_shutdown),
1790 static driver_t m3_driver = {
1796 DRIVER_MODULE(snd_maestro3, pci, m3_driver, pcm_devclass, 0, 0);
1797 MODULE_DEPEND(snd_maestro3, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
1798 MODULE_VERSION(snd_maestro3, 1);