2 * Copyright (c) 1999 Cameron Grant <cg@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #ifndef _T4DWAVE_REG_H
30 #define _T4DWAVE_REG_H
32 #define TR_REG_CIR 0xa0
33 #define TR_CIR_MASK 0x0000003f
34 #define TR_CIR_ADDRENA 0x00001000
35 #define TR_CIR_MIDENA 0x00002000
36 #define TR_REG_MISCINT 0xb0
37 #define TR_INT_ADDR 0x00000020
38 #define TR_INT_SB 0x00000004
40 #define TR_REG_DMAR0 0x00
41 #define TR_REG_DMAR4 0x04
42 #define TR_REG_DMAR11 0x0b
43 #define TR_REG_DMAR15 0x0f
44 #define TR_REG_SBR4 0x14
45 #define TR_REG_SBR5 0x15
46 #define TR_SB_INTSTATUS 0x82
47 #define TR_REG_SBR9 0x1e
48 #define TR_REG_SBR10 0x1f
49 #define TR_REG_SBBL 0xc0
50 #define TR_REG_SBCTRL 0xc4
51 #define TR_REG_SBDELTA 0xac
53 #define TR_CDC_DATA 16
54 #define TDX_REG_CODECWR 0x40
55 #define TDX_REG_CODECRD 0x44
56 #define TDX_CDC_RWSTAT 0x00008000
57 #define TDX_REG_CODECST 0x48
58 #define TDX_CDC_SBCTRL 0x40
59 #define TDX_CDC_ACTIVE 0x20
60 #define TDX_CDC_READY 0x10
61 #define TDX_CDC_ADCON 0x08
62 #define TDX_CDC_DACON 0x02
63 #define TDX_CDC_RESET 0x01
64 #define TDX_CDC_ON (TDX_CDC_ADCON|TDX_CDC_DACON)
66 #define SPA_REG_CODECRD 0x44
67 #define SPA_REG_CODECWR 0x40
68 #define SPA_REG_CODECST 0x48
69 #define SPA_RST_OFF 0x0f0000
70 #define SPA_REG_GPIO 0x48
71 #define SPA_CDC_RWSTAT 0x00008000
73 #define TNX_REG_CODECWR 0x44
74 #define TNX_REG_CODEC1RD 0x48
75 #define TNX_REG_CODEC2RD 0x4c
76 #define TNX_CDC_RWSTAT 0x00000c00
77 #define TNX_CDC_SEC 0x00000100
78 #define TNX_REG_CODECST 0x40
79 #define TNX_CDC_READY2 0x40
80 #define TNX_CDC_ADC2ON 0x20
81 #define TNX_CDC_DAC2ON 0x10
82 #define TNX_CDC_READY1 0x08
83 #define TNX_CDC_ADC1ON 0x04
84 #define TNX_CDC_DAC1ON 0x02
85 #define TNX_CDC_RESET 0x01
86 #define TNX_CDC_ON (TNX_CDC_ADC1ON|TNX_CDC_DAC1ON)
89 #define TR_REG_STARTA 0x80
90 #define TR_REG_STOPA 0x84
91 #define TR_REG_CSPF_A 0x90
92 #define TR_REG_ADDRINTA 0x98
93 #define TR_REG_INTENA 0xa4
95 #define TR_REG_STARTB 0xb4
96 #define TR_REG_STOPB 0xb8
97 #define TR_REG_CSPF_B 0xbc
98 #define TR_REG_ADDRINTB 0xd8
99 #define TR_REG_INTENB 0xdc
101 #define TR_REG_CHNBASE 0xe0
102 #define TR_CHN_REGS 5