2 * Copyright (c) 1999 Jason L. Wright (jason@thought.net)
3 * Copyright (c) 2004 Pyun YongHyeon
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
27 * Effort sponsored in part by the Defense Advanced Research Projects
28 * Agency (DARPA) and Air Force Research Laboratory, Air Force
29 * Materiel Command, USAF, under agreement number F30602-01-2-0537.
31 * from: OpenBSD: cs4231.c,v 1.21 2003/07/03 20:36:07 jason Exp
35 * Driver for CS4231 based audio found in some sun4m systems (cs4231)
36 * based on ideas from the S/Linux project and the NetBSD project.
39 #include <sys/cdefs.h>
40 __FBSDID("$FreeBSD$");
42 #include <sys/param.h>
43 #include <sys/systm.h>
45 #include <sys/kernel.h>
46 #include <sys/resource.h>
48 #include <dev/ofw/ofw_bus.h>
49 #include <dev/ofw/openfirm.h>
50 #include <machine/bus.h>
51 #include <machine/ofw_machdep.h>
53 #ifdef HAVE_KERNEL_OPTION_HEADERS
57 #include <dev/sound/pcm/sound.h>
58 #include <dev/sound/sbus/apcdmareg.h>
59 #include <dev/sound/sbus/cs4231.h>
61 #include <sparc64/sbus/sbusvar.h>
62 #include <sparc64/ebus/ebusreg.h>
67 * The driver supports CS4231A audio chips found on Sbus/Ebus based
68 * UltraSPARCs. Though, CS4231A says it supports full-duplex mode, I
69 * doubt it due to the lack of independent sampling frequency register
70 * for playback/capture.
71 * Since I couldn't find any documentation for APCDMA programming
72 * information, I guessed the usage of APCDMA from that of OpenBSD's
73 * driver. The EBDMA information of PCIO can be obtained from
74 * http://solutions.sun.com/embedded/databook/web/microprocessors/pcio.html
75 * And CS4231A datasheet can also be obtained from
76 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/4231a.pdf
78 * Audio capture(recording) was not tested at all and may have bugs.
79 * Sorry, I don't have microphone. Don't try to use full-duplex mode.
82 #define CS_TIMEOUT 90000
84 #define CS4231_MIN_BUF_SZ (16*1024)
85 #define CS4231_DEFAULT_BUF_SZ (32*1024)
86 #define CS4231_MAX_BUF_SZ (64*1024)
87 #define CS4231_MAX_BLK_SZ (8*1024)
88 #define CS4231_MAX_APC_DMA_SZ (8*1024)
93 #define DPRINTF(x) printf x
97 #define CS4231_AUTO_CALIBRATION
101 struct cs4231_channel {
102 struct cs4231_softc *parent;
103 struct pcm_channel *channel;
104 struct snd_dbuf *buffer;
113 #define CS4231_RES_MEM_MAX 4
114 #define CS4231_RES_IRQ_MAX 2
115 struct cs4231_softc {
116 struct device *sc_dev;
117 int sc_rid[CS4231_RES_MEM_MAX];
118 struct resource *sc_res[CS4231_RES_MEM_MAX];
119 bus_space_handle_t sc_regh[CS4231_RES_MEM_MAX];
120 bus_space_tag_t sc_regt[CS4231_RES_MEM_MAX];
122 int sc_irqrid[CS4231_RES_IRQ_MAX];
123 struct resource *sc_irqres[CS4231_RES_IRQ_MAX];
124 void *sc_ih[CS4231_RES_IRQ_MAX];
125 bus_dma_tag_t sc_dmat[CS4231_RES_IRQ_MAX];
129 struct cs4231_channel sc_pch;
130 struct cs4231_channel sc_rch;
137 #define CS4231_SBUS 0x01
138 #define CS4231_EBUS 0x02
153 static int cs4231_bus_probe(device_t);
154 static int cs4231_sbus_attach(device_t);
155 static int cs4231_ebus_attach(device_t);
156 static int cs4231_attach_common(struct cs4231_softc *);
157 static int cs4231_bus_detach(device_t);
158 static int cs4231_bus_suspend(device_t);
159 static int cs4231_bus_resume(device_t);
160 static void cs4231_getversion(struct cs4231_softc *);
161 static void cs4231_free_resource(struct cs4231_softc *);
162 static void cs4231_ebdma_reset(struct cs4231_softc *);
163 static void cs4231_power_reset(struct cs4231_softc *, int);
164 static int cs4231_enable(struct cs4231_softc *, int);
165 static void cs4231_disable(struct cs4231_softc *);
166 static void cs4231_write(struct cs4231_softc *, u_int8_t, u_int8_t);
167 static u_int8_t cs4231_read(struct cs4231_softc *, u_int8_t);
168 static void cs4231_sbus_intr(void *);
169 static void cs4231_ebus_pintr(void *arg);
170 static void cs4231_ebus_cintr(void *arg);
171 static int cs4231_mixer_init(struct snd_mixer *);
172 static void cs4231_mixer_set_value(struct cs4231_softc *,
173 const struct mix_table *, u_int8_t);
174 static int cs4231_mixer_set(struct snd_mixer *, u_int32_t, u_int32_t,
176 static u_int32_t cs4231_mixer_setrecsrc(struct snd_mixer *, u_int32_t);
177 static void *cs4231_chan_init(kobj_t, void *, struct snd_dbuf *,
178 struct pcm_channel *, int);
179 static int cs4231_chan_setformat(kobj_t, void *, u_int32_t);
180 static u_int32_t cs4231_chan_setspeed(kobj_t, void *, u_int32_t);
181 static void cs4231_chan_fs(struct cs4231_softc *, int, u_int8_t);
182 static u_int32_t cs4231_chan_setblocksize(kobj_t, void *, u_int32_t);
183 static int cs4231_chan_trigger(kobj_t, void *, int);
184 static u_int32_t cs4231_chan_getptr(kobj_t, void *);
185 static struct pcmchan_caps *
186 cs4231_chan_getcaps(kobj_t, void *);
187 static void cs4231_trigger(struct cs4231_channel *);
188 static void cs4231_apcdma_trigger(struct cs4231_softc *,
189 struct cs4231_channel *);
190 static void cs4231_ebdma_trigger(struct cs4231_softc *,
191 struct cs4231_channel *);
192 static void cs4231_halt(struct cs4231_channel *);
194 #define CS4231_LOCK(sc) snd_mtxlock(sc->sc_lock)
195 #define CS4231_UNLOCK(sc) snd_mtxunlock(sc->sc_lock)
196 #define CS4231_LOCK_ASSERT(sc) snd_mtxassert(sc->sc_lock)
198 #define CS_WRITE(sc,r,v) \
199 bus_space_write_1((sc)->sc_regt[0], (sc)->sc_regh[0], (r) << 2, (v))
200 #define CS_READ(sc,r) \
201 bus_space_read_1((sc)->sc_regt[0], (sc)->sc_regh[0], (r) << 2)
203 #define APC_WRITE(sc,r,v) \
204 bus_space_write_4(sc->sc_regt[0], sc->sc_regh[0], r, v)
205 #define APC_READ(sc,r) \
206 bus_space_read_4(sc->sc_regt[0], sc->sc_regh[0], r)
208 #define EBDMA_P_WRITE(sc,r,v) \
209 bus_space_write_4((sc)->sc_regt[1], (sc)->sc_regh[1], (r), (v))
210 #define EBDMA_P_READ(sc,r) \
211 bus_space_read_4((sc)->sc_regt[1], (sc)->sc_regh[1], (r))
213 #define EBDMA_C_WRITE(sc,r,v) \
214 bus_space_write_4((sc)->sc_regt[2], (sc)->sc_regh[2], (r), (v))
215 #define EBDMA_C_READ(sc,r) \
216 bus_space_read_4((sc)->sc_regt[2], (sc)->sc_regh[2], (r))
218 #define AUXIO_CODEC 0x00
219 #define AUXIO_WRITE(sc,r,v) \
220 bus_space_write_4((sc)->sc_regt[3], (sc)->sc_regh[3], (r), (v))
221 #define AUXIO_READ(sc,r) \
222 bus_space_read_4((sc)->sc_regt[3], (sc)->sc_regh[3], (r))
224 #define CODEC_WARM_RESET 0
225 #define CODEC_COLD_RESET 1
228 static device_method_t cs4231_sbus_methods[] = {
229 DEVMETHOD(device_probe, cs4231_bus_probe),
230 DEVMETHOD(device_attach, cs4231_sbus_attach),
231 DEVMETHOD(device_detach, cs4231_bus_detach),
232 DEVMETHOD(device_suspend, cs4231_bus_suspend),
233 DEVMETHOD(device_resume, cs4231_bus_resume),
237 static driver_t cs4231_sbus_driver = {
243 DRIVER_MODULE(snd_audiocs, sbus, cs4231_sbus_driver, pcm_devclass, 0, 0);
246 static device_method_t cs4231_ebus_methods[] = {
247 DEVMETHOD(device_probe, cs4231_bus_probe),
248 DEVMETHOD(device_attach, cs4231_ebus_attach),
249 DEVMETHOD(device_detach, cs4231_bus_detach),
250 DEVMETHOD(device_suspend, cs4231_bus_suspend),
251 DEVMETHOD(device_resume, cs4231_bus_resume),
255 static driver_t cs4231_ebus_driver = {
261 DRIVER_MODULE(snd_audiocs, ebus, cs4231_ebus_driver, pcm_devclass, 0, 0);
262 MODULE_DEPEND(snd_audiocs, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
263 MODULE_VERSION(snd_audiocs, 1);
266 static u_int32_t cs4231_fmt[] = {
267 SND_FORMAT(AFMT_U8, 1, 0),
268 SND_FORMAT(AFMT_U8, 2, 0),
269 SND_FORMAT(AFMT_MU_LAW, 1, 0),
270 SND_FORMAT(AFMT_MU_LAW, 2, 0),
271 SND_FORMAT(AFMT_A_LAW, 1, 0),
272 SND_FORMAT(AFMT_A_LAW, 2, 0),
273 SND_FORMAT(AFMT_IMA_ADPCM, 1, 0),
274 SND_FORMAT(AFMT_IMA_ADPCM, 2, 0),
275 SND_FORMAT(AFMT_S16_LE, 1, 0),
276 SND_FORMAT(AFMT_S16_LE, 2, 0),
277 SND_FORMAT(AFMT_S16_BE, 1, 0),
278 SND_FORMAT(AFMT_S16_BE, 2, 0),
282 static struct pcmchan_caps cs4231_caps = {5510, 48000, cs4231_fmt, 0};
285 * sound(4) channel interface
287 static kobj_method_t cs4231_chan_methods[] = {
288 KOBJMETHOD(channel_init, cs4231_chan_init),
289 KOBJMETHOD(channel_setformat, cs4231_chan_setformat),
290 KOBJMETHOD(channel_setspeed, cs4231_chan_setspeed),
291 KOBJMETHOD(channel_setblocksize, cs4231_chan_setblocksize),
292 KOBJMETHOD(channel_trigger, cs4231_chan_trigger),
293 KOBJMETHOD(channel_getptr, cs4231_chan_getptr),
294 KOBJMETHOD(channel_getcaps, cs4231_chan_getcaps),
297 CHANNEL_DECLARE(cs4231_chan);
300 * sound(4) mixer interface
302 static kobj_method_t cs4231_mixer_methods[] = {
303 KOBJMETHOD(mixer_init, cs4231_mixer_init),
304 KOBJMETHOD(mixer_set, cs4231_mixer_set),
305 KOBJMETHOD(mixer_setrecsrc, cs4231_mixer_setrecsrc),
308 MIXER_DECLARE(cs4231_mixer);
311 cs4231_bus_probe(device_t dev)
313 const char *compat, *name;
315 compat = ofw_bus_get_compat(dev);
316 name = ofw_bus_get_name(dev);
317 if (strcmp("SUNW,CS4231", name) == 0 ||
318 (compat != NULL && strcmp("SUNW,CS4231", compat) == 0)) {
319 device_set_desc(dev, "Sun Audiocs");
320 return (BUS_PROBE_DEFAULT);
326 cs4231_sbus_attach(device_t dev)
328 struct cs4231_softc *sc;
331 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
335 * No public documentation exists on programming burst size of APCDMA.
337 burst = sbus_get_burstsz(sc->sc_dev);
338 if ((burst & SBUS_BURST_64))
340 else if ((burst & SBUS_BURST_32))
342 else if ((burst & SBUS_BURST_16))
346 sc->sc_flags = CS4231_SBUS;
349 return cs4231_attach_common(sc);
353 cs4231_ebus_attach(device_t dev)
355 struct cs4231_softc *sc;
357 sc = malloc(sizeof(struct cs4231_softc), M_DEVBUF, M_NOWAIT | M_ZERO);
359 device_printf(dev, "cannot allocate softc\n");
363 sc->sc_burst = EBDCSR_BURST_1;
364 sc->sc_nmres = CS4231_RES_MEM_MAX;
365 sc->sc_nires = CS4231_RES_IRQ_MAX;
366 sc->sc_flags = CS4231_EBUS;
367 return cs4231_attach_common(sc);
371 cs4231_attach_common(struct cs4231_softc *sc)
373 char status[SND_STATUSLEN];
374 driver_intr_t *ihandler;
377 sc->sc_lock = snd_mtxcreate(device_get_nameunit(sc->sc_dev),
380 for (i = 0; i < sc->sc_nmres; i++) {
382 if ((sc->sc_res[i] = bus_alloc_resource_any(sc->sc_dev,
383 SYS_RES_MEMORY, &sc->sc_rid[i], RF_ACTIVE)) == NULL) {
384 device_printf(sc->sc_dev,
385 "cannot map register %d\n", i);
388 sc->sc_regt[i] = rman_get_bustag(sc->sc_res[i]);
389 sc->sc_regh[i] = rman_get_bushandle(sc->sc_res[i]);
391 for (i = 0; i < sc->sc_nires; i++) {
392 sc->sc_irqrid[i] = i;
393 if ((sc->sc_irqres[i] = bus_alloc_resource_any(sc->sc_dev,
394 SYS_RES_IRQ, &sc->sc_irqrid[i], RF_SHAREABLE | RF_ACTIVE))
396 if ((sc->sc_flags & CS4231_SBUS) != 0)
397 device_printf(sc->sc_dev,
398 "cannot allocate interrupt\n");
400 device_printf(sc->sc_dev, "cannot allocate %s "
401 "interrupt\n", i == 0 ? "capture" :
407 ihandler = cs4231_sbus_intr;
408 for (i = 0; i < sc->sc_nires; i++) {
409 if ((sc->sc_flags & CS4231_EBUS) != 0) {
411 ihandler = cs4231_ebus_cintr;
413 ihandler = cs4231_ebus_pintr;
415 if (snd_setup_intr(sc->sc_dev, sc->sc_irqres[i], INTR_MPSAFE,
416 ihandler, sc, &sc->sc_ih[i])) {
417 if ((sc->sc_flags & CS4231_SBUS) != 0)
418 device_printf(sc->sc_dev,
419 "cannot set up interrupt\n");
421 device_printf(sc->sc_dev, "cannot set up %s "
422 " interrupt\n", i == 0 ? "capture" :
428 sc->sc_bufsz = pcm_getbuffersize(sc->sc_dev, CS4231_MIN_BUF_SZ,
429 CS4231_DEFAULT_BUF_SZ, CS4231_MAX_BUF_SZ);
430 for (i = 0; i < sc->sc_nires; i++) {
431 if (bus_dma_tag_create(
432 bus_get_dma_tag(sc->sc_dev),/* parent */
433 64, 0, /* alignment, boundary */
434 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
435 BUS_SPACE_MAXADDR, /* highaddr */
436 NULL, NULL, /* filtfunc, filtfuncarg */
437 sc->sc_bufsz, /* maxsize */
439 sc->sc_bufsz, /* maxsegsz */
440 BUS_DMA_ALLOCNOW, /* flags */
442 NULL, /* lockfuncarg */
444 if ((sc->sc_flags & CS4231_SBUS) != 0)
445 device_printf(sc->sc_dev,
446 "cannot allocate DMA tag\n");
448 device_printf(sc->sc_dev, "cannot allocate %s "
449 "DMA tag\n", i == 0 ? "capture" :
454 cs4231_enable(sc, CODEC_WARM_RESET);
455 cs4231_getversion(sc);
456 if (mixer_init(sc->sc_dev, &cs4231_mixer_class, sc) != 0)
458 if (pcm_register(sc->sc_dev, sc, 1, 1)) {
459 device_printf(sc->sc_dev, "cannot register to pcm\n");
462 if (pcm_addchan(sc->sc_dev, PCMDIR_REC, &cs4231_chan_class, sc) != 0)
464 if (pcm_addchan(sc->sc_dev, PCMDIR_PLAY, &cs4231_chan_class, sc) != 0)
466 if ((sc->sc_flags & CS4231_SBUS) != 0)
467 snprintf(status, SND_STATUSLEN, "at mem 0x%lx irq %ld bufsz %u",
468 rman_get_start(sc->sc_res[0]),
469 rman_get_start(sc->sc_irqres[0]), sc->sc_bufsz);
471 snprintf(status, SND_STATUSLEN, "at io 0x%lx 0x%lx 0x%lx 0x%lx "
472 "irq %ld %ld bufsz %u", rman_get_start(sc->sc_res[0]),
473 rman_get_start(sc->sc_res[1]),
474 rman_get_start(sc->sc_res[2]),
475 rman_get_start(sc->sc_res[3]),
476 rman_get_start(sc->sc_irqres[0]),
477 rman_get_start(sc->sc_irqres[1]), sc->sc_bufsz);
478 pcm_setstatus(sc->sc_dev, status);
482 pcm_unregister(sc->sc_dev);
484 cs4231_free_resource(sc);
489 cs4231_bus_detach(device_t dev)
491 struct cs4231_softc *sc;
492 struct cs4231_channel *pch, *rch;
495 sc = pcm_getdevinfo(dev);
499 if (pch->locked || rch->locked) {
504 * Since EBDMA requires valid DMA buffer to drain its FIFO, we need
505 * real DMA buffer for draining.
507 if ((sc->sc_flags & CS4231_EBUS) != 0)
508 cs4231_ebdma_reset(sc);
510 error = pcm_unregister(dev);
513 cs4231_free_resource(sc);
518 cs4231_bus_suspend(device_t dev)
525 cs4231_bus_resume(device_t dev)
532 cs4231_getversion(struct cs4231_softc *sc)
536 v = cs4231_read(sc, CS_MISC_INFO);
537 sc->sc_codecv = v & CS_CODEC_ID_MASK;
538 v = cs4231_read(sc, CS_VERSION_ID);
539 v &= (CS_VERSION_NUMBER | CS_VERSION_CHIPID);
543 device_printf(sc->sc_dev, "<CS4231 Codec Id. %d>\n",
547 device_printf(sc->sc_dev, "<CS4231A Codec Id. %d>\n",
551 device_printf(sc->sc_dev, "<CS4232 Codec Id. %d>\n",
555 device_printf(sc->sc_dev,
556 "<Unknown 0x%x Codec Id. %d\n", v, sc->sc_codecv);
562 cs4231_ebdma_reset(struct cs4231_softc *sc)
567 EBDMA_P_WRITE(sc, EBDMA_DCSR,
568 EBDMA_P_READ(sc, EBDMA_DCSR) & ~(EBDCSR_INTEN | EBDCSR_NEXTEN));
569 EBDMA_P_WRITE(sc, EBDMA_DCSR, EBDCSR_RESET);
571 i && EBDMA_P_READ(sc, EBDMA_DCSR) & EBDCSR_DRAIN; i--)
574 device_printf(sc->sc_dev,
575 "timeout waiting for playback DMA reset\n");
576 EBDMA_P_WRITE(sc, EBDMA_DCSR, sc->sc_burst);
578 EBDMA_C_WRITE(sc, EBDMA_DCSR,
579 EBDMA_C_READ(sc, EBDMA_DCSR) & ~(EBDCSR_INTEN | EBDCSR_NEXTEN));
580 EBDMA_C_WRITE(sc, EBDMA_DCSR, EBDCSR_RESET);
582 i && EBDMA_C_READ(sc, EBDMA_DCSR) & EBDCSR_DRAIN; i--)
585 device_printf(sc->sc_dev,
586 "timeout waiting for capture DMA reset\n");
587 EBDMA_C_WRITE(sc, EBDMA_DCSR, sc->sc_burst);
591 cs4231_power_reset(struct cs4231_softc *sc, int how)
596 if ((sc->sc_flags & CS4231_SBUS) != 0) {
597 APC_WRITE(sc, APC_CSR, APC_CSR_RESET);
599 APC_WRITE(sc, APC_CSR, 0);
602 APC_CSR, APC_READ(sc, APC_CSR) | APC_CSR_CODEC_RESET);
605 APC_CSR, APC_READ(sc, APC_CSR) & (~APC_CSR_CODEC_RESET));
607 v = AUXIO_READ(sc, AUXIO_CODEC);
608 if (how == CODEC_WARM_RESET && v != 0) {
609 AUXIO_WRITE(sc, AUXIO_CODEC, 0);
611 } else if (how == CODEC_COLD_RESET){
612 AUXIO_WRITE(sc, AUXIO_CODEC, 1);
614 AUXIO_WRITE(sc, AUXIO_CODEC, 0);
617 cs4231_ebdma_reset(sc);
621 i && CS_READ(sc, CS4231_IADDR) == CS_IN_INIT; i--)
624 device_printf(sc->sc_dev, "timeout waiting for reset\n");
626 /* turn on cs4231 mode */
627 cs4231_write(sc, CS_MISC_INFO,
628 cs4231_read(sc, CS_MISC_INFO) | CS_MODE2);
629 /* enable interrupts & clear CSR */
630 cs4231_write(sc, CS_PIN_CONTROL,
631 cs4231_read(sc, CS_PIN_CONTROL) | INTERRUPT_ENABLE);
632 CS_WRITE(sc, CS4231_STATUS, 0);
633 /* enable DAC output */
634 cs4231_write(sc, CS_LEFT_OUTPUT_CONTROL,
635 cs4231_read(sc, CS_LEFT_OUTPUT_CONTROL) & ~OUTPUT_MUTE);
636 cs4231_write(sc, CS_RIGHT_OUTPUT_CONTROL,
637 cs4231_read(sc, CS_RIGHT_OUTPUT_CONTROL) & ~OUTPUT_MUTE);
638 /* mute AUX1 since it generates noises */
639 cs4231_write(sc, CS_LEFT_AUX1_CONTROL,
640 cs4231_read(sc, CS_LEFT_AUX1_CONTROL) | AUX_INPUT_MUTE);
641 cs4231_write(sc, CS_RIGHT_AUX1_CONTROL,
642 cs4231_read(sc, CS_RIGHT_AUX1_CONTROL) | AUX_INPUT_MUTE);
643 /* protect buffer underrun and set output level to 0dB */
644 cs4231_write(sc, CS_ALT_FEATURE1,
645 cs4231_read(sc, CS_ALT_FEATURE1) | CS_DAC_ZERO | CS_OUTPUT_LVL);
646 /* enable high pass filter, dual xtal was disabled due to noises */
647 cs4231_write(sc, CS_ALT_FEATURE2,
648 cs4231_read(sc, CS_ALT_FEATURE2) | CS_HPF_ENABLE);
652 cs4231_enable(struct cs4231_softc *sc, int how)
654 cs4231_power_reset(sc, how);
660 cs4231_disable(struct cs4231_softc *sc)
664 CS4231_LOCK_ASSERT(sc);
666 if (sc->sc_enabled == 0)
670 cs4231_halt(&sc->sc_pch);
671 cs4231_halt(&sc->sc_rch);
673 v = cs4231_read(sc, CS_PIN_CONTROL) & ~INTERRUPT_ENABLE;
674 cs4231_write(sc, CS_PIN_CONTROL, v);
676 if ((sc->sc_flags & CS4231_SBUS) != 0) {
677 APC_WRITE(sc, APC_CSR, APC_CSR_RESET);
679 APC_WRITE(sc, APC_CSR, 0);
682 cs4231_ebdma_reset(sc);
686 cs4231_free_resource(struct cs4231_softc *sc)
693 for (i = 0; i < sc->sc_nires; i++) {
694 if (sc->sc_irqres[i]) {
696 bus_teardown_intr(sc->sc_dev, sc->sc_irqres[i],
700 bus_release_resource(sc->sc_dev, SYS_RES_IRQ,
701 sc->sc_irqrid[i], sc->sc_irqres[i]);
702 sc->sc_irqres[i] = NULL;
705 for (i = 0; i < sc->sc_nires; i++) {
707 bus_dma_tag_destroy(sc->sc_dmat[i]);
709 for (i = 0; i < sc->sc_nmres; i++) {
711 bus_release_resource(sc->sc_dev, SYS_RES_MEMORY,
712 sc->sc_rid[i], sc->sc_res[i]);
714 snd_mtxfree(sc->sc_lock);
719 cs4231_write(struct cs4231_softc *sc, u_int8_t r, u_int8_t v)
721 CS_WRITE(sc, CS4231_IADDR, r);
722 CS_WRITE(sc, CS4231_IDATA, v);
726 cs4231_read(struct cs4231_softc *sc, u_int8_t r)
728 CS_WRITE(sc, CS4231_IADDR, r);
729 return (CS_READ(sc, CS4231_IDATA));
733 cs4231_sbus_intr(void *arg)
735 struct cs4231_softc *sc;
736 struct cs4231_channel *pch, *rch;
743 csr = APC_READ(sc, APC_CSR);
744 if ((csr & APC_CSR_GI) == 0) {
748 APC_WRITE(sc, APC_CSR, csr);
750 if ((csr & APC_CSR_EIE) && (csr & APC_CSR_EI)) {
751 status = cs4231_read(sc, CS_TEST_AND_INIT);
752 device_printf(sc->sc_dev,
753 "apc error interrupt : stat = 0x%x\n", status);
757 if ((csr & APC_CSR_PMIE) && (csr & APC_CSR_PMI)) {
758 u_long nextaddr, saddr;
763 saddr = sndbuf_getbufaddr(pch->buffer);
764 nextaddr = pch->nextaddr + togo;
765 if (nextaddr >= saddr + sndbuf_getsize(pch->buffer))
767 APC_WRITE(sc, APC_PNVA, nextaddr);
768 APC_WRITE(sc, APC_PNC, togo);
769 pch->nextaddr = nextaddr;
772 if ((csr & APC_CSR_CIE) && (csr & APC_CSR_CI) && (csr & APC_CSR_CD)) {
773 u_long nextaddr, saddr;
778 saddr = sndbuf_getbufaddr(rch->buffer);
779 nextaddr = rch->nextaddr + togo;
780 if (nextaddr >= saddr + sndbuf_getsize(rch->buffer))
782 APC_WRITE(sc, APC_CNVA, nextaddr);
783 APC_WRITE(sc, APC_CNC, togo);
784 rch->nextaddr = nextaddr;
788 chn_intr(pch->channel);
790 chn_intr(rch->channel);
793 /* playback interrupt handler */
795 cs4231_ebus_pintr(void *arg)
797 struct cs4231_softc *sc;
798 struct cs4231_channel *ch;
805 csr = EBDMA_P_READ(sc, EBDMA_DCSR);
806 if ((csr & EBDCSR_INT) == 0) {
811 if ((csr & EBDCSR_ERR)) {
812 status = cs4231_read(sc, CS_TEST_AND_INIT);
813 device_printf(sc->sc_dev,
814 "ebdma error interrupt : stat = 0x%x\n", status);
816 EBDMA_P_WRITE(sc, EBDMA_DCSR, csr | EBDCSR_TC);
819 if (csr & EBDCSR_TC) {
820 u_long nextaddr, saddr;
825 saddr = sndbuf_getbufaddr(ch->buffer);
826 nextaddr = ch->nextaddr + togo;
827 if (nextaddr >= saddr + sndbuf_getsize(ch->buffer))
830 * EBDMA_DCNT is loaded automatically
831 * EBDMA_P_WRITE(sc, EBDMA_DCNT, togo);
833 EBDMA_P_WRITE(sc, EBDMA_DADDR, nextaddr);
834 ch->nextaddr = nextaddr;
838 chn_intr(ch->channel);
841 /* capture interrupt handler */
843 cs4231_ebus_cintr(void *arg)
845 struct cs4231_softc *sc;
846 struct cs4231_channel *ch;
853 csr = EBDMA_C_READ(sc, EBDMA_DCSR);
854 if ((csr & EBDCSR_INT) == 0) {
858 if ((csr & EBDCSR_ERR)) {
859 status = cs4231_read(sc, CS_TEST_AND_INIT);
860 device_printf(sc->sc_dev,
861 "dma error interrupt : stat = 0x%x\n", status);
863 EBDMA_C_WRITE(sc, EBDMA_DCSR, csr | EBDCSR_TC);
866 if (csr & EBDCSR_TC) {
867 u_long nextaddr, saddr;
872 saddr = sndbuf_getbufaddr(ch->buffer);
873 nextaddr = ch->nextaddr + togo;
874 if (nextaddr >= saddr + sndbuf_getblksz(ch->buffer))
877 * EBDMA_DCNT is loaded automatically
878 * EBDMA_C_WRITE(sc, EBDMA_DCNT, togo);
880 EBDMA_C_WRITE(sc, EBDMA_DADDR, nextaddr);
881 ch->nextaddr = nextaddr;
885 chn_intr(ch->channel);
888 static const struct mix_table cs4231_mix_table[SOUND_MIXER_NRDEVICES][2] = {
889 [SOUND_MIXER_PCM] = {
890 { CS_LEFT_OUTPUT_CONTROL, 6, OUTPUT_MUTE, 0, 1, 1, 0 },
891 { CS_RIGHT_OUTPUT_CONTROL, 6, OUTPUT_MUTE, 0, 1, 1, 0 }
893 [SOUND_MIXER_SPEAKER] = {
894 { CS_MONO_IO_CONTROL, 4, MONO_OUTPUT_MUTE, 0, 1, 1, 0 },
895 { CS_REG_NONE, 0, 0, 0, 0, 1, 0 }
897 [SOUND_MIXER_LINE] = {
898 { CS_LEFT_LINE_CONTROL, 5, LINE_INPUT_MUTE, 0, 1, 1, 1 },
899 { CS_RIGHT_LINE_CONTROL, 5, LINE_INPUT_MUTE, 0, 1, 1, 1 }
902 * AUX1 : removed intentionally since it generates noises
903 * AUX2 : Ultra1/Ultra2 has no internal CD-ROM audio in
906 { CS_LEFT_AUX2_CONTROL, 5, LINE_INPUT_MUTE, 0, 1, 1, 1 },
907 { CS_RIGHT_AUX2_CONTROL, 5, LINE_INPUT_MUTE, 0, 1, 1, 1 }
909 [SOUND_MIXER_MIC] = {
910 { CS_LEFT_INPUT_CONTROL, 4, 0, 0, 0, 1, 1 },
911 { CS_RIGHT_INPUT_CONTROL, 4, 0, 0, 0, 1, 1 }
913 [SOUND_MIXER_IGAIN] = {
914 { CS_LEFT_INPUT_CONTROL, 4, 0, 0, 1, 0 },
915 { CS_RIGHT_INPUT_CONTROL, 4, 0, 0, 1, 0 }
920 cs4231_mixer_init(struct snd_mixer *m)
926 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++)
927 if (cs4231_mix_table[i][0].avail != 0)
931 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++)
932 if (cs4231_mix_table[i][0].recdev != 0)
934 mix_setrecdevs(m, v);
939 cs4231_mixer_set_value(struct cs4231_softc *sc, const struct mix_table *mt,
943 u_int8_t old, shift, val;
945 if (mt->avail == 0 || mt->reg == CS_REG_NONE)
952 mask = (1 << mt->bits) - 1;
953 val = ((val * mask) + 50) / 100;
958 old = cs4231_read(sc, reg);
959 old &= ~(mt->mute | (mask << shift));
961 if (reg == CS_LEFT_INPUT_CONTROL || reg == CS_RIGHT_INPUT_CONTROL) {
962 if ((val & (mask << shift)) != 0)
963 val |= ADC_INPUT_GAIN_ENABLE;
965 val &= ~ADC_INPUT_GAIN_ENABLE;
967 cs4231_write(sc, reg, val);
971 cs4231_mixer_set(struct snd_mixer *m, u_int32_t dev, u_int32_t left,
974 struct cs4231_softc *sc;
976 sc = mix_getdevinfo(m);
978 cs4231_mixer_set_value(sc, &cs4231_mix_table[dev][0], left);
979 cs4231_mixer_set_value(sc, &cs4231_mix_table[dev][1], right);
982 return (left | (right << 8));
986 cs4231_mixer_setrecsrc(struct snd_mixer *m, u_int32_t src)
988 struct cs4231_softc *sc;
991 sc = mix_getdevinfo(m);
993 case SOUND_MASK_LINE:
1001 case SOUND_MASK_MIC:
1004 src = SOUND_MASK_MIC;
1008 cs4231_write(sc, CS_LEFT_INPUT_CONTROL,
1009 (cs4231_read(sc, CS_LEFT_INPUT_CONTROL) & CS_IN_MASK) | v);
1010 cs4231_write(sc, CS_RIGHT_INPUT_CONTROL,
1011 (cs4231_read(sc, CS_RIGHT_INPUT_CONTROL) & CS_IN_MASK) | v);
1018 cs4231_chan_init(kobj_t obj, void *dev, struct snd_dbuf *b,
1019 struct pcm_channel *c, int dir)
1021 struct cs4231_softc *sc;
1022 struct cs4231_channel *ch;
1026 ch = (dir == PCMDIR_PLAY) ? &sc->sc_pch : &sc->sc_rch;
1031 if ((sc->sc_flags & CS4231_SBUS) != 0)
1032 dmat = sc->sc_dmat[0];
1034 if (dir == PCMDIR_PLAY)
1035 dmat = sc->sc_dmat[1];
1037 dmat = sc->sc_dmat[0];
1039 if (sndbuf_alloc(ch->buffer, dmat, 0, sc->sc_bufsz) != 0)
1041 DPRINTF(("%s channel addr: 0x%lx\n", dir == PCMDIR_PLAY ? "playback" :
1042 "capture", sndbuf_getbufaddr(ch->buffer)));
1048 cs4231_chan_setformat(kobj_t obj, void *data, u_int32_t format)
1050 struct cs4231_softc *sc;
1051 struct cs4231_channel *ch;
1059 if (ch->format == format) {
1064 encoding = AFMT_ENCODING(format);
1071 fs = CS_AFMT_MU_LAW;
1074 fs = CS_AFMT_S16_LE;
1079 case AFMT_IMA_ADPCM:
1080 fs = CS_AFMT_IMA_ADPCM;
1083 fs = CS_AFMT_S16_BE;
1091 if (AFMT_CHANNEL(format) > 1)
1092 fs |= CS_AFMT_STEREO;
1094 DPRINTF(("FORMAT: %s : 0x%x\n", ch->dir == PCMDIR_PLAY ? "playback" :
1095 "capture", format));
1096 v = cs4231_read(sc, CS_CLOCK_DATA_FORMAT);
1097 v &= CS_CLOCK_DATA_FORMAT_MASK;
1099 cs4231_chan_fs(sc, ch->dir, fs);
1100 ch->format = format;
1107 cs4231_chan_setspeed(kobj_t obj, void *data, u_int32_t speed)
1114 const static speed_struct speed_table[] = {
1115 {5510, (0 << 1) | CLOCK_XTAL2},
1116 {5510, (0 << 1) | CLOCK_XTAL2},
1117 {6620, (7 << 1) | CLOCK_XTAL2},
1118 {8000, (0 << 1) | CLOCK_XTAL1},
1119 {9600, (7 << 1) | CLOCK_XTAL1},
1120 {11025, (1 << 1) | CLOCK_XTAL2},
1121 {16000, (1 << 1) | CLOCK_XTAL1},
1122 {18900, (2 << 1) | CLOCK_XTAL2},
1123 {22050, (3 << 1) | CLOCK_XTAL2},
1124 {27420, (2 << 1) | CLOCK_XTAL1},
1125 {32000, (3 << 1) | CLOCK_XTAL1},
1126 {33075, (6 << 1) | CLOCK_XTAL2},
1127 {33075, (4 << 1) | CLOCK_XTAL2},
1128 {44100, (5 << 1) | CLOCK_XTAL2},
1129 {48000, (6 << 1) | CLOCK_XTAL1},
1132 struct cs4231_softc *sc;
1133 struct cs4231_channel *ch;
1140 if (ch->speed == speed) {
1144 n = sizeof(speed_table) / sizeof(speed_struct);
1146 for (i = 1, sel =0; i < n - 1; i++)
1147 if (abs(speed - speed_table[i].speed) <
1148 abs(speed - speed_table[sel].speed))
1150 DPRINTF(("SPEED: %s : %dHz -> %dHz\n", ch->dir == PCMDIR_PLAY ?
1151 "playback" : "capture", speed, speed_table[sel].speed));
1152 speed = speed_table[sel].speed;
1154 fs = cs4231_read(sc, CS_CLOCK_DATA_FORMAT);
1155 fs &= ~CS_CLOCK_DATA_FORMAT_MASK;
1156 fs |= speed_table[sel].bits;
1157 cs4231_chan_fs(sc, ch->dir, fs);
1165 cs4231_chan_fs(struct cs4231_softc *sc, int dir, u_int8_t fs)
1168 #ifdef CS4231_AUTO_CALIBRATION
1172 CS4231_LOCK_ASSERT(sc);
1174 /* set autocalibration */
1176 #ifdef CS4231_AUTO_CALIBRATION
1177 v = cs4231_read(sc, CS_INTERFACE_CONFIG) | AUTO_CAL_ENABLE;
1178 CS_WRITE(sc, CS4231_IADDR, MODE_CHANGE_ENABLE);
1179 CS_WRITE(sc, CS4231_IADDR, MODE_CHANGE_ENABLE | CS_INTERFACE_CONFIG);
1180 CS_WRITE(sc, CS4231_IDATA, v);
1184 * We always need to write CS_CLOCK_DATA_FORMAT register since
1185 * the clock frequency is shared with playback/capture.
1187 CS_WRITE(sc, CS4231_IADDR, MODE_CHANGE_ENABLE | CS_CLOCK_DATA_FORMAT);
1188 CS_WRITE(sc, CS4231_IDATA, fs);
1189 CS_READ(sc, CS4231_IDATA);
1190 CS_READ(sc, CS4231_IDATA);
1191 for (i = CS_TIMEOUT;
1192 i && CS_READ(sc, CS4231_IADDR) == CS_IN_INIT; i--)
1195 device_printf(sc->sc_dev, "timeout setting playback speed\n");
1201 * cs4231 doesn't allow separate fs setup for playback/capture.
1202 * I believe this will break full-duplex operation.
1204 if (dir == PCMDIR_REC) {
1205 CS_WRITE(sc, CS4231_IADDR, MODE_CHANGE_ENABLE | CS_REC_FORMAT);
1206 CS_WRITE(sc, CS4231_IDATA, fs);
1207 CS_READ(sc, CS4231_IDATA);
1208 CS_READ(sc, CS4231_IDATA);
1209 for (i = CS_TIMEOUT;
1210 i && CS_READ(sc, CS4231_IADDR) == CS_IN_INIT; i--)
1213 device_printf(sc->sc_dev,
1214 "timeout setting capture format\n");
1219 CS_WRITE(sc, CS4231_IADDR, 0);
1220 for (i = CS_TIMEOUT;
1221 i && CS_READ(sc, CS4231_IADDR) == CS_IN_INIT; i--)
1224 device_printf(sc->sc_dev, "timeout waiting for !MCE\n");
1228 #ifdef CS4231_AUTO_CALIBRATION
1229 CS_WRITE(sc, CS4231_IADDR, CS_TEST_AND_INIT);
1230 for (i = CS_TIMEOUT;
1231 i && CS_READ(sc, CS4231_IDATA) & AUTO_CAL_IN_PROG; i--)
1234 device_printf(sc->sc_dev,
1235 "timeout waiting for autocalibration\n");
1241 * Maybe the last resort to avoid a dreadful message like
1242 * "pcm0:play:0: play interrupt timeout, channel dead" would
1243 * be hardware reset.
1245 device_printf(sc->sc_dev, "trying to hardware reset\n");
1247 cs4231_enable(sc, CODEC_COLD_RESET);
1248 CS4231_UNLOCK(sc); /* XXX */
1249 if (mixer_reinit(sc->sc_dev) != 0)
1250 device_printf(sc->sc_dev,
1251 "unable to reinitialize the mixer\n");
1257 cs4231_chan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
1259 struct cs4231_softc *sc;
1260 struct cs4231_channel *ch;
1266 if (blocksize > CS4231_MAX_BLK_SZ)
1267 blocksize = CS4231_MAX_BLK_SZ;
1268 nblks = sc->sc_bufsz / blocksize;
1269 error = sndbuf_resize(ch->buffer, nblks, blocksize);
1271 device_printf(sc->sc_dev,
1272 "unable to block size, blksz = %d, error = %d\n",
1279 cs4231_chan_trigger(kobj_t obj, void *data, int go)
1281 struct cs4231_channel *ch;
1285 case PCMTRIG_EMLDMAWR:
1286 case PCMTRIG_EMLDMARD:
1303 cs4231_chan_getptr(kobj_t obj, void *data)
1305 struct cs4231_softc *sc;
1306 struct cs4231_channel *ch;
1307 u_int32_t cur, ptr, sz;
1313 if ((sc->sc_flags & CS4231_SBUS) != 0)
1314 cur = (ch->dir == PCMDIR_PLAY) ? APC_READ(sc, APC_PVA) :
1315 APC_READ(sc, APC_CVA);
1317 cur = (ch->dir == PCMDIR_PLAY) ? EBDMA_P_READ(sc, EBDMA_DADDR) :
1318 EBDMA_C_READ(sc, EBDMA_DADDR);
1319 sz = sndbuf_getsize(ch->buffer);
1320 ptr = cur - sndbuf_getbufaddr(ch->buffer) + sz;
1327 static struct pcmchan_caps *
1328 cs4231_chan_getcaps(kobj_t obj, void *data)
1331 return (&cs4231_caps);
1335 cs4231_trigger(struct cs4231_channel *ch)
1337 struct cs4231_softc *sc;
1340 if ((sc->sc_flags & CS4231_SBUS) != 0)
1341 cs4231_apcdma_trigger(sc, ch);
1343 cs4231_ebdma_trigger(sc, ch);
1347 cs4231_apcdma_trigger(struct cs4231_softc *sc, struct cs4231_channel *ch)
1349 u_int32_t csr, togo;
1354 device_printf(sc->sc_dev, "%s channel already triggered\n",
1355 ch->dir == PCMDIR_PLAY ? "playback" : "capture");
1360 nextaddr = sndbuf_getbufaddr(ch->buffer);
1361 togo = sndbuf_getsize(ch->buffer) / 2;
1362 if (togo > CS4231_MAX_APC_DMA_SZ)
1363 togo = CS4231_MAX_APC_DMA_SZ;
1365 if (ch->dir == PCMDIR_PLAY) {
1366 DPRINTF(("TRG: PNVA = 0x%x, togo = 0x%x\n", nextaddr, togo));
1368 cs4231_read(sc, CS_TEST_AND_INIT); /* clear pending error */
1369 csr = APC_READ(sc, APC_CSR);
1370 APC_WRITE(sc, APC_PNVA, nextaddr);
1371 APC_WRITE(sc, APC_PNC, togo);
1373 if ((csr & APC_CSR_PDMA_GO) == 0 ||
1374 (csr & APC_CSR_PPAUSE) != 0) {
1375 APC_WRITE(sc, APC_CSR, APC_READ(sc, APC_CSR) &
1376 ~(APC_CSR_PIE | APC_CSR_PPAUSE));
1377 APC_WRITE(sc, APC_CSR, APC_READ(sc, APC_CSR) |
1378 APC_CSR_GIE | APC_CSR_PIE | APC_CSR_EIE |
1379 APC_CSR_EI | APC_CSR_PMIE | APC_CSR_PDMA_GO);
1380 cs4231_write(sc, CS_INTERFACE_CONFIG,
1381 cs4231_read(sc, CS_INTERFACE_CONFIG) |
1384 /* load next address */
1385 if (APC_READ(sc, APC_CSR) & APC_CSR_PD) {
1387 APC_WRITE(sc, APC_PNVA, nextaddr);
1388 APC_WRITE(sc, APC_PNC, togo);
1391 DPRINTF(("TRG: CNVA = 0x%x, togo = 0x%x\n", nextaddr, togo));
1393 cs4231_read(sc, CS_TEST_AND_INIT); /* clear pending error */
1394 APC_WRITE(sc, APC_CNVA, nextaddr);
1395 APC_WRITE(sc, APC_CNC, togo);
1396 csr = APC_READ(sc, APC_CSR);
1397 if ((csr & APC_CSR_CDMA_GO) == 0 ||
1398 (csr & APC_CSR_CPAUSE) != 0) {
1399 csr &= APC_CSR_CPAUSE;
1400 csr |= APC_CSR_GIE | APC_CSR_CMIE | APC_CSR_CIE |
1401 APC_CSR_EI | APC_CSR_CDMA_GO;
1402 APC_WRITE(sc, APC_CSR, csr);
1403 cs4231_write(sc, CS_INTERFACE_CONFIG,
1404 cs4231_read(sc, CS_INTERFACE_CONFIG) |
1407 /* load next address */
1408 if (APC_READ(sc, APC_CSR) & APC_CSR_CD) {
1410 APC_WRITE(sc, APC_CNVA, nextaddr);
1411 APC_WRITE(sc, APC_CNC, togo);
1414 ch->nextaddr = nextaddr;
1420 cs4231_ebdma_trigger(struct cs4231_softc *sc, struct cs4231_channel *ch)
1422 u_int32_t csr, togo;
1427 device_printf(sc->sc_dev, "%s channel already triggered\n",
1428 ch->dir == PCMDIR_PLAY ? "playback" : "capture");
1433 nextaddr = sndbuf_getbufaddr(ch->buffer);
1434 togo = sndbuf_getsize(ch->buffer) / 2;
1436 sc->sc_burst = EBDCSR_BURST_16;
1437 else if (togo % 32 == 0)
1438 sc->sc_burst = EBDCSR_BURST_8;
1439 else if (togo % 16 == 0)
1440 sc->sc_burst = EBDCSR_BURST_4;
1442 sc->sc_burst = EBDCSR_BURST_1;
1444 DPRINTF(("TRG: DNAR = 0x%x, togo = 0x%x\n", nextaddr, togo));
1445 if (ch->dir == PCMDIR_PLAY) {
1446 cs4231_read(sc, CS_TEST_AND_INIT); /* clear pending error */
1447 csr = EBDMA_P_READ(sc, EBDMA_DCSR);
1449 if (csr & EBDCSR_DMAEN) {
1450 EBDMA_P_WRITE(sc, EBDMA_DCNT, togo);
1451 EBDMA_P_WRITE(sc, EBDMA_DADDR, nextaddr);
1453 EBDMA_P_WRITE(sc, EBDMA_DCSR, EBDCSR_RESET);
1454 EBDMA_P_WRITE(sc, EBDMA_DCSR, sc->sc_burst);
1455 EBDMA_P_WRITE(sc, EBDMA_DCNT, togo);
1456 EBDMA_P_WRITE(sc, EBDMA_DADDR, nextaddr);
1458 EBDMA_P_WRITE(sc, EBDMA_DCSR, sc->sc_burst |
1459 EBDCSR_DMAEN | EBDCSR_INTEN | EBDCSR_CNTEN |
1461 cs4231_write(sc, CS_INTERFACE_CONFIG,
1462 cs4231_read(sc, CS_INTERFACE_CONFIG) |
1465 /* load next address */
1466 if (EBDMA_P_READ(sc, EBDMA_DCSR) & EBDCSR_A_LOADED) {
1468 EBDMA_P_WRITE(sc, EBDMA_DCNT, togo);
1469 EBDMA_P_WRITE(sc, EBDMA_DADDR, nextaddr);
1472 cs4231_read(sc, CS_TEST_AND_INIT); /* clear pending error */
1473 csr = EBDMA_C_READ(sc, EBDMA_DCSR);
1475 if (csr & EBDCSR_DMAEN) {
1476 EBDMA_C_WRITE(sc, EBDMA_DCNT, togo);
1477 EBDMA_C_WRITE(sc, EBDMA_DADDR, nextaddr);
1479 EBDMA_C_WRITE(sc, EBDMA_DCSR, EBDCSR_RESET);
1480 EBDMA_C_WRITE(sc, EBDMA_DCSR, sc->sc_burst);
1481 EBDMA_C_WRITE(sc, EBDMA_DCNT, togo);
1482 EBDMA_C_WRITE(sc, EBDMA_DADDR, nextaddr);
1484 EBDMA_C_WRITE(sc, EBDMA_DCSR, sc->sc_burst |
1485 EBDCSR_WRITE | EBDCSR_DMAEN | EBDCSR_INTEN |
1486 EBDCSR_CNTEN | EBDCSR_NEXTEN);
1487 cs4231_write(sc, CS_INTERFACE_CONFIG,
1488 cs4231_read(sc, CS_INTERFACE_CONFIG) |
1491 /* load next address */
1492 if (EBDMA_C_READ(sc, EBDMA_DCSR) & EBDCSR_A_LOADED) {
1494 EBDMA_C_WRITE(sc, EBDMA_DCNT, togo);
1495 EBDMA_C_WRITE(sc, EBDMA_DADDR, nextaddr);
1498 ch->nextaddr = nextaddr;
1504 cs4231_halt(struct cs4231_channel *ch)
1506 struct cs4231_softc *sc;
1512 if (ch->locked == 0) {
1517 if (ch->dir == PCMDIR_PLAY ) {
1518 if ((sc->sc_flags & CS4231_SBUS) != 0) {
1519 /* XXX Kills some capture bits */
1520 APC_WRITE(sc, APC_CSR, APC_READ(sc, APC_CSR) &
1521 ~(APC_CSR_EI | APC_CSR_GIE | APC_CSR_PIE |
1522 APC_CSR_EIE | APC_CSR_PDMA_GO | APC_CSR_PMIE));
1524 EBDMA_P_WRITE(sc, EBDMA_DCSR,
1525 EBDMA_P_READ(sc, EBDMA_DCSR) & ~EBDCSR_DMAEN);
1527 /* Waiting for playback FIFO to empty */
1528 status = cs4231_read(sc, CS_TEST_AND_INIT);
1529 for (i = CS_TIMEOUT;
1530 i && (status & PLAYBACK_UNDERRUN) == 0; i--) {
1532 status = cs4231_read(sc, CS_TEST_AND_INIT);
1535 device_printf(sc->sc_dev, "timeout waiting for "
1536 "playback FIFO drain\n");
1537 cs4231_write(sc, CS_INTERFACE_CONFIG,
1538 cs4231_read(sc, CS_INTERFACE_CONFIG) & (~PLAYBACK_ENABLE));
1540 if ((sc->sc_flags & CS4231_SBUS) != 0) {
1541 /* XXX Kills some playback bits */
1542 APC_WRITE(sc, APC_CSR, APC_CSR_CAPTURE_PAUSE);
1544 EBDMA_C_WRITE(sc, EBDMA_DCSR,
1545 EBDMA_C_READ(sc, EBDMA_DCSR) & ~EBDCSR_DMAEN);
1547 /* Waiting for capture FIFO to empty */
1548 status = cs4231_read(sc, CS_TEST_AND_INIT);
1549 for (i = CS_TIMEOUT;
1550 i && (status & CAPTURE_OVERRUN) == 0; i--) {
1552 status = cs4231_read(sc, CS_TEST_AND_INIT);
1555 device_printf(sc->sc_dev, "timeout waiting for "
1556 "capture FIFO drain\n");
1557 cs4231_write(sc, CS_INTERFACE_CONFIG,
1558 cs4231_read(sc, CS_INTERFACE_CONFIG) & (~CAPTURE_ENABLE));